CN109841674B - Trench gate IGBT with improved emitter structure - Google Patents
Trench gate IGBT with improved emitter structure Download PDFInfo
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- CN109841674B CN109841674B CN201711225585.7A CN201711225585A CN109841674B CN 109841674 B CN109841674 B CN 109841674B CN 201711225585 A CN201711225585 A CN 201711225585A CN 109841674 B CN109841674 B CN 109841674B
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Abstract
The invention relates to a trench gate IGBT with an improved emitter structure. The trench gate IGBT includes two parallel trenches, and a P base region and an emitter electrode located between the two trenches, where the emitter electrode is located above the P base region, and the emitter electrode includes a plurality of N + + regions and a plurality of P + + regions connected in pairs, where, when viewed from a top surface of the trench gate IGBT, each of the P + + regions is in any one of the following shapes: a circular shape inscribed to the sidewalls of the two grooves; an oval shape inscribed to the sidewalls of the two trenches; and an N-gon, N being an even number greater than or equal to 2, wherein the N-gon has only two vertices located on sidewalls of the two trenches, respectively, and is symmetrical about a straight line parallel to the trenches between the two trenches, and the N + + region is a region between the sidewalls of the two trenches except for the P + + region.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a trench gate IGBT with an improved emitter structure.
Background
Insulated Gate Bipolar Transistors (IGBT) are used in industry more and more widely, and one common IGBT is a trench Gate IGBT. In order to reduce the trench pitch and improve the latch-up resistance of the IGBT, the N + + region and the P + + region of the emitter of the trench gate IGBT are usually designed to have an alternating rectangular structure, as shown in fig. 1. Therefore, the space between the two grooves can be reduced, the parasitic base resistance of the P base region can be reduced, and the latch-up resistance of the groove gate can be improved.
However, since the channel area of the IGBT depends on the contact area of the N + + region and the gate oxide (i.e., the trench sidewalls), the emitter structure with the rectangular N + + region alternating with the rectangular P + + region sacrifices effective channel density, thereby increasing the on-state voltage drop of the IGBT.
Therefore, a new emitter structure of the trench gate IGBT is needed.
Disclosure of Invention
In order to solve the problems, the invention provides a novel emitter structure of a trench gate IGBT, which reduces the base parasitic resistance of the IGBT, improves the latch-up resistance of the IGBT and obtains a better compromise relationship between conduction voltage drop and latch-up resistance while improving the channel density of the IGBT.
According to an aspect of the present invention, there is provided a trench gate IGBT, including two parallel trenches, and a P base region and an emitter electrode located between the two trenches, wherein the emitter electrode is located above the P base region, the emitter electrode includes a plurality of N + + regions and a plurality of P + + regions connected in pairs,
wherein, when viewed from the top surface of the trench gate IGBT, each of the P + + regions has any one of the following shapes:
a circular shape inscribed to the sidewalls of the two grooves;
an oval shape inscribed to the sidewalls of the two trenches; and
an N-polygon having an even number greater than or equal to 2, wherein only two vertices of the N-polygon are respectively located on sidewalls of the two trenches, and the N-polygon is symmetrical about a straight line parallel to the trenches between the two trenches,
and the N + + region is a region between sidewalls of the two trenches except for the P + + region.
Preferably, each of said P + + zones is an ellipse, the major axis of which is parallel to said two trenches.
Preferably, each of said P + + zones is elliptical, the minor axis of the ellipse being parallel to said two trenches.
Preferably, each of the P + + regions is a diamond shape, and each of the N + + regions is a triangle shape.
Preferably, each of the N + + regions is an obtuse triangle except for four N + + regions at both ends.
Preferably, each of said N + + zones is an acute triangle, except for four N + + zones at either end.
Preferably, each of the P + + regions is a square, and each of the N + + regions is a right triangle.
Preferably, each of said P + + regions is hexagonal.
Preferably, each of the P + + zones is octagonal.
Preferably, each of said P + + zones is decagonal.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects: the emitter structure of the trench gate IGBT enlarges the contact area of the N + + region and the gate oxide layer as much as possible to enable the channel area to be as large as possible, so that the conduction voltage drop of the IGBT is reduced; and meanwhile, enough area of the P + + region is ensured, so that the latch-up resistance is improved. Thus, a better trade-off between turn-on voltage drop and latch-up resistance is obtained.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale in reality.
Fig. 1 is a schematic structural diagram of a trench gate IGBT in the prior art.
Fig. 2 is a schematic structural diagram of a trench gate IGBT according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a variation of the trench gate IGBT according to the first embodiment of the present invention.
Fig. 4 is a schematic structural diagram of another variation of the trench gate IGBT according to the first embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a trench gate IGBT according to a second embodiment of the invention.
Fig. 6 is a schematic structural diagram of a variation of the trench gate IGBT according to the second embodiment of the present invention.
Fig. 7 is a schematic structural diagram of another variation of the trench gate IGBT according to the second embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details or with other methods described herein.
Fig. 1 is a schematic structural diagram of a trench gate IGBT in the prior art. As shown in fig. 1, the trench gate IGBT includes gates 1 and 2 located in two parallel trenches, drift P regions 3 and 4 located outside the two trenches, and a P base region 5 and an emitter located between the two trenches, wherein the emitter is located above the P base region 5. Other components of the trench gate IGBT are well known to those skilled in the art and will not be described in detail herein. From the top, the emitter comprises a structure of rectangular N + + regions alternating with rectangular P + + regions. The emitter structure can reduce the space between two grooves, reduce the parasitic base resistance of the P base region and improve the latch-up resistance of the groove gate.
However, since the channel area of the IGBT depends on the contact area between the N + + region and the gate oxide layer, the emitter structure with the rectangular N + + region alternating with the rectangular P + + region sacrifices effective channel density, thereby increasing the on-state voltage drop of the IGBT.
In contrast, the invention provides a novel emitter structure of a trench gate IGBT, which enlarges the contact area of an N + + region and a gate oxide layer as much as possible to enable the channel area to be as large as possible, thereby reducing the conduction voltage drop of the IGBT; and meanwhile, enough area of the P + + region is ensured, so that the latch-up resistance is improved. Thus, a better trade-off between turn-on voltage drop and latch-up resistance is obtained.
Example one
Fig. 2 is a schematic structural diagram of a trench gate IGBT according to a first embodiment of the present invention. As shown in fig. 2, the trench gate IGBT includes gates 1 and 2 located in two parallel trenches, drift P regions 3 and 4 located outside the two trenches, and a P base region 5 and an emitter located between the two trenches, wherein the emitter is located above the P base region 5. Other components of the trench gate IGBT are well known to those skilled in the art and will not be described in detail herein.
The trench gate IGBT according to this embodiment differs from the trench gate IGBT shown in fig. 1 in that the emitter of the trench gate IGBT according to this embodiment is not in a structure in which rectangular N + + regions and rectangular P + + regions alternate, but in a structure in which a plurality of diamond-shaped P + + regions and a plurality of triangular N + + regions are combined, as viewed from the top. The two vertices of each diamond-shaped P + + region meet the trench sidewalls and each diamond-shaped P + + region is symmetric about a line (not shown) parallel to the trench between two parallel trenches. The rhombus P + + areas are connected two by two. The area between the rhombus P + + area and the side wall of the groove is a triangular N + + area.
In the embodiment of fig. 2, the remaining single N + + regions are obtuse triangles, except for the four N + + regions at the two ends, which does not limit the present invention. The single N + + region may also be designed as an acute triangle or a right triangle. Under the condition that a single N + + region is an obtuse triangle, the area of the single N + + region and the area of the single P + + region are large, and the requirement on photoetching CDs is low. Fig. 3 shows a case where a single N + + region is an acute triangle, in which case the area of the single N + + region and the single P + + region is small, so that the N + + region and the P + + region are relatively uniformly distributed as a whole. Fig. 4 shows the case where a single N + + region is a right triangle.
Through the design, the contact area of the N + + region and the gate oxide layer is maximized, so that the channel area is maximized, and the conduction voltage drop of the IGBT can be reduced; meanwhile, the area of the P + + area is larger, so that the anti-latch capability is improved. Thus, a better trade-off between turn-on voltage drop and latch-up resistance is obtained.
In one embodiment, the junction depth of the P + + region and the N + + region is approximately 0.3 μm, and the peak doping concentration is 5e19cm-3To 5e20cm-3. The junction depth of the P base region 5 is about 3 to 4 μm deeper than that of the P + + region and the N + + region, and the surface peak concentration is about 2e17cm-3. The depth of the trench is about 5 to 6 μm. The side wall of the groove is an oxide layer, and the inside of the groove is filled with polysilicon. Of course, this is not a limitation of the present invention.
Example two
Fig. 5 is a schematic structural diagram of a trench gate IGBT according to a second embodiment of the invention. As shown in fig. 5, the trench gate IGBT includes gates 1 and 2 located in two parallel trenches, drift P regions 3 and 4 located outside the two trenches, and a P base region 5 and an emitter located between the two trenches, wherein the emitter is located above the P base region 5. Other components of the trench gate IGBT are well known to those skilled in the art and will not be described in detail herein.
The trench gate IGBT of this embodiment differs from the trench gate IGBTs shown in fig. 1 and 2 in that the P + + regions of the emitter of the trench gate IGBT of this embodiment have a plurality of oval shapes which are connected two by two, and the N + + region occupies the remaining region between the two trench sidewalls, as viewed from the top surface. Each oval P + + region is inscribed in both trench sidewalls and is symmetrical about a line parallel to the trench (not shown) midway between the two parallel trenches.
In the embodiment of fig. 5, for a single elliptical P + + region, the axis parallel to the trench sidewalls is the minor axis of the ellipse, so that the area of the single ellipse is relatively small, resulting in a relatively uniform distribution of the N + + region and the P + + region as a whole. However, the present invention is not limited thereto. Fig. 6 shows another case: for a single elliptical P + + region, the axis parallel to the trench sidewalls is the major axis of the ellipse, so that the area of the single ellipse is relatively large, which places low demands on the lithographic CD. Fig. 7 shows the case where a single P + + region is circular.
In this embodiment, whether the individual P + + zones are elliptical or circular, the sum of the areas of all the P + + zones accounts for a ratio of pi/4 of the total area between the two trenches as can be seen from geometrical calculations, so that the P + + zones occupy a substantial portion of the area between the two trenches. Meanwhile, the contact area of the N + + region and the gate oxide layer is maximized, so that the channel area is maximized. Therefore, the area of the P + + region is larger while the channel density is maximized, so that the sufficient area of the P + + region is ensured while the channel density is improved, and the latch-up resistance and the channel density are improved at the same time. The improvement of the channel density can reduce the conduction voltage drop of the IGBT, so that a better compromise relation between the conduction voltage drop and the latch-up resistance is obtained.
In the second embodiment, the junction depth of the P + + region and the N + + region is approximately 0.3 μm, and the peak doping concentration is 5e19cm-3To 5e20cm-3. The junction depth of the P base region 5 is about 3 to 4 μm deeper than that of the P + + region and the N + + region, and the surface peak concentration is about 2e17cm-3. The depth of the trench is about 5 to 6 μm. The side wall of the groove is an oxide layer, and the inside of the groove is filled with polysilicon. Of course, this is not a limitation of the present invention.
Variants
Based on the above first embodiment and the second embodiment, it is obvious that the shape of the P + + region can be modified, and the object of the present invention can be achieved as well.
For example, the P + + regions are designed as two-by-two connected hexagons, where each hexagon has two and only two vertices located on the two trench sidewalls, respectively, and each hexagon is symmetric about a straight line parallel to the trench in the middle of two parallel trenches. Similarly, the P + + region is designed to be connected in pairs such as octagon and decagon, which is also suitable for the invention.
In summary, the P + + regions may be designed as N-sided polygons that are connected two by two, where N is an even number greater than or equal to 2, and each N-sided polygon has only two vertices located on the two trench sidewalls, respectively, and each N-sided polygon is symmetric about a straight line parallel to the trench between two parallel trenches.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A trench gate IGBT comprises two parallel trenches, a gate electrode positioned in the two trenches, and a P base region and an emitter electrode positioned between the two trenches, wherein the emitter electrode is positioned above the P base region, the emitter electrode comprises a plurality of N + + regions and a plurality of P + + regions which are connected in pairs,
wherein, when viewed from the top surface of the trench gate IGBT, each of the P + + regions has the same shape and is any one of:
a circle having only two points on the sidewalls of the two trenches, respectively;
an ellipse having only two points on the sidewalls of the two trenches, respectively; and
an N-polygon having an even number greater than 2, wherein only two vertices of the N-polygon are located on the sidewalls of the two trenches, respectively, and the N-polygon is symmetric about a line between the two trenches that is parallel to the trenches,
and the N + + region is a region between sidewalls of the two trenches except for the P + + region.
2. The trench gate IGBT of claim 1 wherein each of the P + + regions is an ellipse with its major axis parallel to the two trenches.
3. The trench gate IGBT of claim 1 wherein each of the P + + regions is elliptical with its minor axis parallel to the two trenches.
4. The trench gate IGBT of claim 1 wherein each of the P + + regions is diamond shaped and each of the N + + regions is triangular shaped.
5. The trench gate IGBT according to claim 4, wherein each of said N + + regions is an obtuse triangle except for four N + + regions at both ends.
6. The trench gate IGBT according to claim 4, wherein each of said N + + regions is an acute triangle except for four N + + regions at both ends.
7. The trench gate IGBT of claim 1 wherein each of the P + + regions is square and each of the N + + regions is right triangular.
8. The trench gate IGBT of claim 1 wherein each of the P + + regions is hexagonal.
9. The trench gate IGBT of claim 1 wherein each of the P + + regions is octagonal.
10. The trench gate IGBT of claim 1 wherein each of the P + + regions is decagonal.
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| CN201711225585.7A CN109841674B (en) | 2017-11-29 | 2017-11-29 | Trench gate IGBT with improved emitter structure |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0238749A2 (en) * | 1986-03-24 | 1987-09-30 | SILICONIX Incorporated | Groove gate unipolar and bipolar MOS devices and method of manufacturing the same |
| US20040084725A1 (en) * | 2002-11-01 | 2004-05-06 | Toyota Jidosha Kabushiki Kaisha | Field-effect-type semiconductor device |
| CN100514675C (en) * | 2004-05-12 | 2009-07-15 | 株式会社丰田中央研究所 | Semiconductor device |
| CN103165673A (en) * | 2011-12-16 | 2013-06-19 | 上海华虹Nec电子有限公司 | Groove type insulated gate field effect tube |
| CN107180865A (en) * | 2017-06-30 | 2017-09-19 | 东南大学 | A kind of low noise low-loss and insulating grid bipolar transistor |
-
2017
- 2017-11-29 CN CN201711225585.7A patent/CN109841674B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0238749A2 (en) * | 1986-03-24 | 1987-09-30 | SILICONIX Incorporated | Groove gate unipolar and bipolar MOS devices and method of manufacturing the same |
| US20040084725A1 (en) * | 2002-11-01 | 2004-05-06 | Toyota Jidosha Kabushiki Kaisha | Field-effect-type semiconductor device |
| CN100514675C (en) * | 2004-05-12 | 2009-07-15 | 株式会社丰田中央研究所 | Semiconductor device |
| CN103165673A (en) * | 2011-12-16 | 2013-06-19 | 上海华虹Nec电子有限公司 | Groove type insulated gate field effect tube |
| CN107180865A (en) * | 2017-06-30 | 2017-09-19 | 东南大学 | A kind of low noise low-loss and insulating grid bipolar transistor |
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Effective date of registration: 20200927 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |