CN103165673A - Groove type insulated gate field effect tube - Google Patents
Groove type insulated gate field effect tube Download PDFInfo
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- CN103165673A CN103165673A CN2011104227487A CN201110422748A CN103165673A CN 103165673 A CN103165673 A CN 103165673A CN 2011104227487 A CN2011104227487 A CN 2011104227487A CN 201110422748 A CN201110422748 A CN 201110422748A CN 103165673 A CN103165673 A CN 103165673A
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Abstract
The invention discloses a groove type insulated gate field effect tube. The groove type insulated gate field effect tube comprises an N-type epitaxial layer. A P-type injection layer is formed below the N-type epitaxial layer, a groove is formed in the upper portion of the N-type epitaxial layer, a gate oxide layer and a polysilicon gate are formed in the groove, a P-type trap and an N-type active area are formed on two sides of the groove, and the N-type active area is placed above the P-type trap. A circular hollowed-out structure is formed in the N-type active area, interlayer oxidation media are formed above the groove, the circular hollowed-out structure and the N-type active area, a P-type injection area is arranged below a contact hole, and the contact hole penetrates through the interlayer oxidation media and connects the N-type active area and the P-type injection area. The groove type insulated gate field effect tube reduces spurious base resistance (RB) of an NPN and reduces the area of an NPN emitter of a spurious thyristor at the same time, and therefore happening rates of latch-up effects of the spurious thyristor are reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of groove-shaped isolated gate FET.
Background technology
A kind of conventional groove type isolated gate FET (IGBT) structure (as shown in Figure 1 and Figure 2), the N-type active area adopts strip usually, contact hole is positioned at above P type active area and N-type active area, and contact hole below N-type active area and P type active area have the zone of coincidence.In traditional structure, because P type active area has increased the parasitic thyristor emitter area with overlapping of N-type active area, it is large that the β of parasitic thyristor becomes, thereby increased the occurrence probability of latch-up.And the consequence of breech lock to be IGBT lose the grid-control ability, device can't turn-off voluntarily, the large electric current that even forms due to positive feedback can make that IGBT is permanent to be burnt.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of groove-shaped isolated gate FET that can reduce isolated gate FET parasitic thyristor latch-up occurrence probability.
for solving the problems of the technologies described above, groove-shaped isolated gate FET of the present invention, comprise: a kind of groove-shaped isolated gate FET, comprise and be formed with P type implanted layer under the N-type epitaxial loayer, N-type epitaxial loayer top is formed with groove, be formed with gate oxide and polysilicon gate in groove, the groove both sides are formed with P type trap and N-type active area, the N-type active area is positioned at above the P trap, it is characterized in that: be formed with circular engraved structure in the N-type active area, the interlevel oxidation medium is formed at groove, above circular engraved structure and N-type active area, contact hole below has P type injection region, between the contact hole across-layer, oxide isolation connects N-type active area and P type injection region.
Described circular engraved structure diameter range is 1um to 10um.
Described circular engraved structure has p type impurity.
The gate oxide of groove and polysilicon consist of the grid of field effect transistor of the present invention; A N-type active area is arranged respectively as the source electrode of groove-shaped field effect transistor in the P type trap of groove both sides; Have a P type injection region in the N-type active area and be used for picking out of P type trap, externally be connected with source electrode; There is the implanted layer of one deck P type the below of N-type epitaxial loayer, as the drain electrode of field effect transistor of the present invention.
Because the N-type active area need to pick out by contact hole, the P trap needs to pick out by P type injection region and contact hole, so N-type active area and P type injection region must be arranged below contact hole, because sharing same version, P type injection region and contact hole in original structure make, if the P type active region area in traditional structure is enlarged merely, the N-type active area can't be picked out.After P type active area adopts circular engraved structure, can solve the problem that after P type active area is enlarged, the N-type active area can't pick out.Groove-shaped isolated gate FET of the present invention has reduced the base resistance R of parasitic NPN
B, reduced simultaneously the area of parasitic thyristor NPN emitter, thereby reduced the occurrence probability of parasitic thyristor latch-up.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is a kind of vertical view of conventional groove type isolated gate FET.
Fig. 2 is the end view of Fig. 1 section along the line A-A.
Fig. 3 is the vertical view of groove-shaped isolated gate FET the first embodiment of the present invention.
Fig. 4 is the end view of Fig. 3 section along the line B-B.
Embodiment
as Fig. 3, shown in Figure 4, groove-shaped isolated gate FET the first embodiment of the present invention comprises: be formed with P type implanted layer under the N-type epitaxial loayer, N-type epitaxial loayer top is formed with groove, be formed with gate oxide and polysilicon gate in groove, the groove both sides are formed with P type trap and N-type active area, the N-type active area is positioned at above the P trap, wherein, be formed with circular engraved structure in the N-type active area, described circular engraved structure undopes, described circular engraved structure diameter range is 1um, the interlevel oxidation medium is formed at groove, above circular engraved structure and N-type active area, contact hole below has P type injection region, between the contact hole across-layer, oxide isolation connects N-type active area and P type injection region.
In groove-shaped isolated gate FET the second embodiment of the present invention, described circular engraved structure diameter range is 10um, and described circular engraved structure has p type impurity (all the other structures are identical with the first embodiment).
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. groove-shaped isolated gate FET, comprise and be formed with P type implanted layer under the N-type epitaxial loayer, N-type epitaxial loayer top is formed with groove, be formed with gate oxide and polysilicon gate in groove, the groove both sides are formed with P type trap and N-type active area, the N-type active area is positioned at above the P trap, it is characterized in that: be formed with circular engraved structure in the N-type active area, the interlevel oxidation medium is formed at above groove, circular engraved structure and N-type active area, contact hole below has P type injection region, and between the contact hole across-layer, oxide isolation connects N-type active area and P type injection region.
2. groove-shaped isolated gate FET as claimed in claim 1, it is characterized in that: described circular engraved structure diameter range is 1um to 10um.
3. groove-shaped isolated gate FET as claimed in claim 2, it is characterized in that: described circular engraved structure has p type impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110422748.7A CN103165673B (en) | 2011-12-16 | 2011-12-16 | A kind of groove-shaped insulated-gate field-effect pipe |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110422748.7A CN103165673B (en) | 2011-12-16 | 2011-12-16 | A kind of groove-shaped insulated-gate field-effect pipe |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103165673A true CN103165673A (en) | 2013-06-19 |
| CN103165673B CN103165673B (en) | 2016-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110422748.7A Active CN103165673B (en) | 2011-12-16 | 2011-12-16 | A kind of groove-shaped insulated-gate field-effect pipe |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841674A (en) * | 2017-11-29 | 2019-06-04 | 株洲中车时代电气股份有限公司 | Trench gate IGBT with improved emitter structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124605A (en) * | 1997-08-06 | 2000-09-26 | Samsung Electronics Co., Ltd. | Insulated gate bipolar transistor with latch-up protection |
| CN1729578A (en) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| US20100117142A1 (en) * | 2008-11-10 | 2010-05-13 | Wei-Chieh Lin | Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter |
| US20100193835A1 (en) * | 2009-02-05 | 2010-08-05 | Force-Mos Technology Corporation | Trench insulated gate bipolar transistor (GBT) with improved emitter-base contacts and metal schemes |
| CN102005472A (en) * | 2009-08-31 | 2011-04-06 | 比亚迪股份有限公司 | Power semiconductor device and manufacturing method thereof |
-
2011
- 2011-12-16 CN CN201110422748.7A patent/CN103165673B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124605A (en) * | 1997-08-06 | 2000-09-26 | Samsung Electronics Co., Ltd. | Insulated gate bipolar transistor with latch-up protection |
| CN1729578A (en) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| US20100117142A1 (en) * | 2008-11-10 | 2010-05-13 | Wei-Chieh Lin | Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter |
| US20100193835A1 (en) * | 2009-02-05 | 2010-08-05 | Force-Mos Technology Corporation | Trench insulated gate bipolar transistor (GBT) with improved emitter-base contacts and metal schemes |
| CN102005472A (en) * | 2009-08-31 | 2011-04-06 | 比亚迪股份有限公司 | Power semiconductor device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841674A (en) * | 2017-11-29 | 2019-06-04 | 株洲中车时代电气股份有限公司 | Trench gate IGBT with improved emitter structure |
| CN109841674B (en) * | 2017-11-29 | 2020-08-28 | 株洲中车时代电气股份有限公司 | Trench gate IGBT with improved emitter structure |
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| CN103165673B (en) | 2016-06-08 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140115 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140115 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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