CN109841259A - Improve the method and device of NOR type storage array reading speed - Google Patents
Improve the method and device of NOR type storage array reading speed Download PDFInfo
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- CN109841259A CN109841259A CN201711230666.6A CN201711230666A CN109841259A CN 109841259 A CN109841259 A CN 109841259A CN 201711230666 A CN201711230666 A CN 201711230666A CN 109841259 A CN109841259 A CN 109841259A
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Abstract
The invention discloses a kind of method and devices for improving NOR type storage array reading speed, comprising: NOR type storage array is divided into 2nA subarray；If reading for the first time, the address and the address of selected word line for choosing bit line are determined according to first address, according to the state for distinguishing subarray marker in the address of bit line, the address of selected word line, the state of bit line address marker and bit line address marker is chosen, to 2nStorage unit in a subarray is read simultaneously；If not reading for the first time, the corresponding data of the corresponding storage unit in the address of bit line with the address of current selected word line and are currently chosen in output, and are read to the storage unit of next subarray.The technical solution of the embodiment of the present invention reads multiple storage units, every time by the way that storage array is divided into multiple subarrays to shorten the storage unit for having read selected quantity, and the temporal summation that the data of these storage units are all exported.
Description
Technical field
The present embodiments relate to non-volatile memory technologies field more particularly to a kind of raising NOR type storage arrays
The method and device of reading speed.
Background technique
In the prior art for NOR type storage array read when, the method being usually taken is: in the prior art for
When NOR type storage array is read, the method being usually taken is: it is assumed that chip interior shares x reading circuit, reading circuit
Quantity be to choose the quantity of bit line, the integral number power that x is 2, each reading circuit connects a bit line, then reading each time
Operation will read the data of x storage unit, these data will be since the corresponding storage unit of first address and by address
Constantly plus 1 Sequential output data, wherein first address is the address that chip exterior is sent into, and the corresponding output data in each address is
8bit；Since data output is according to sequence of addresses output and centre cannot have interruption, it is desirable to be deposited in the x that this reads
Before the last 8bit data of storage unit have exported, to prepare according to the data of address plus next group of x storage unit of 1 sequence
It is good；If it is just last group of 8bit data of this group of data that first address is corresponding, need exporting last group of 8bit number
According to when run through the data of next group of x storage unit, 8bit data output clock number used is fixed, then reading circuit
Primary clock number used is read to determine the clock number exported by 8bit data.
If with traditional unilateral reading of scheme second of reading will be started immediately after reading first time, at four mouthfuls
Address input and the fewer situation of the illusory clock number (dummy) that is inserted between address input and data output, read to make
4 clock cycle capable of being can only be less than the time, to be just able to satisfy second of reading unaffected.
Summary of the invention
In view of this, providing a kind of method and dress for improving NOR type storage array reading speed in the embodiment of the present invention
It sets, the method by the way that NOR type storage array to be divided into multiple subarrays reads the data of multiple storage units every time, to shorten
The storage unit of selected quantity, and the temporal summation that the data of these storage units are all exported are read.
In a first aspect, the embodiment of the invention provides a kind of methods for improving NOR type storage array reading speed, comprising:
The NOR type storage array is divided into 2nA subarray；
According to the item number m of the bit line of the NOR type storage array, bit line address mark corresponding with the bit line is determined
Position, the quantity of the bit line address marker areAnd number consecutively；
According to the item number x for choosing bit line in subarray described in each, it is determining with it is described with choosing the corresponding bit line of bit line
Location marker, the quantity for choosing bit line address label to know position are
According to the address for choosing bit line, is selected in the bit line address marker and distinguishes subarray marker,
The quantity for distinguishing subarray marker is n；
The bit line address marker include the differentiations subarray marker and it is described choose bit line address label knowledge position；
If reading for the first time, the address of bit line and the address of selected word line, the head are chosen according to first address determination
Address is the reading address that chip exterior is sent into, according to the address for choosing bit line, the address of the selected word line, institute's rheme
The state that subarray marker is distinguished described in the state of line address marker and the bit line address marker, to described 2n
Storage unit in a subarray is read simultaneously；
It is defeated according to the bit line address and wordline address of the corresponding storage unit of current output data if not reading for the first time
Out with the address of presently described selected word line and the presently described corresponding data of the corresponding storage unit in address for choosing bit line, and
The storage unit of next subarray is read；
The n is the integer more than or equal to 1, describedFor the integer more than or equal to 1, the m is greater than or waits
In x.
Optionally, when the n is 1, the NOR type storage array is divided into 2 subarrays, respectively the first subarray
With the second subarray；
The differentiation subarray marker is 1.
Optionally, if described read for the first time, the address of bit line, the ground of selected word line are chosen according to first address determination
Location, the first address be chip exterior be sent into reading address, according to the address for choosing bit line, selected word line address,
The state of subarray marker is distinguished described in the state of the bit line address marker and the bit line address marker, it is right
Described 2nStorage unit in a subarray is read step simultaneously and specifically includes:
If reading for the first time, position is known to the differentiation subarray marker packet from highest order bit line address label in the first address
Contain it is described choose the address of bit line to be all 1, then the address to selected word line described in second subarray and described choose
The corresponding storage unit in the address of bit line is read, while reading the storage unit in first subarray, described
After cyclic address change of the corresponding wordline of storage unit for selected word line described in second subarray in first subarray
The corresponding wordline in address；The corresponding bit line of storage unit in first subarray be in the bit line address marker most
The address for the bit line that high-order bit line address marker includes to the differentiation subarray marker is all 0 bit line.
Optionally, if reading for the first time, position is known to the differentiation subarray from highest order bit line address label in the first address
It include 0 in the address for choosing bit line that marker includes, and the differentiation subarray marker 1,
Then to the storage unit in second subarray through being read out, the storage unit pair that is read in the second subarray
The wordline answered is the corresponding wordline of first address, and bit line is the corresponding bit line of the first address；First son is read simultaneously
Storage unit in array, the corresponding wordline of storage unit of first subarray are that wordline address is corresponding in the first address
Wordline, the corresponding bit line of storage unit in first subarray is highest order in the first address bit line address marker
Corresponding bit line after the cyclic address change that bit line address marker includes to the differentiation subarray marker, if second son
Highest order bit line address label knowledge position includes to the differentiation subarray marker in the corresponding bit line of storage unit in array
The address for choosing bit line is all 1, then the corresponding wordline of storage unit in first subarray is second submatrix
Corresponding wordline after the corresponding wordline address of the storage unit of column adds one, otherwise, the storage unit in first subarray
Corresponding wordline is the corresponding wordline of storage unit of second subarray；
The choosing that position includes to the differentiation subarray marker is known from highest order bit line address label in the first address
Include 0 in the address of neutrality line, and the differentiation subarray marker 0, then to the storage unit in first subarray into
Row read operation, the wordline for reading storage unit in the first subarray is the corresponding wordline of the first address, reads the first submatrix
The bit line of storage unit is the corresponding bit line of the first address in column；The storage unit institute in second subarray is read simultaneously
Stating the corresponding bit line of storage unit in the first subarray is that highest order bit line address label knows position to the area in the first address
The bit line address that molecular array marker includes is to add a corresponding bit line address, the storage unit pair in second subarray
The wordline answered is the corresponding wordline of storage unit of first subarray.
Optionally, if described not read for the first time, according to the bit line address of the corresponding storage unit of current output data and
Wordline address exports and the address of presently described selected word line and the presently described corresponding storage unit pair in address for choosing bit line
The data answered, and step is read to the storage unit of next subarray and is specifically included:
If described not read for the first time, according to the bit line address of the corresponding storage unit of current output data and wordline
Location exports and the address of presently described selected word line and the presently described corresponding number of the corresponding storage unit in address for choosing bit line
According to；
And the storage unit of next subarray is read, the corresponding storage unit of the current output data
Bit line address in from highest order bit line address label know position to it is described differentiation subarray marker include bit line address in include
0, and the differentiation subarray marker 1, if highest order bit line address in the bit line of the corresponding storage unit of current output data
The address of marker to the bit line that the differentiation subarray marker includes is all 1, the storage unit of next subarray
Corresponding bit line is that highest order bit line address label knowledge position is arrived in the bit line address of the corresponding storage unit of the current output data
The bit line address that the differentiation subarray marker includes adds a corresponding bit line address, then depositing in next subarray
The corresponding wordline of storage unit is corresponding after the corresponding wordline address of the corresponding storage unit of the current output data adds one
Wordline, otherwise, the corresponding wordline of storage unit of next subarray are that the corresponding storage of the current output data is single
The corresponding wordline of member；
The bit line address of the corresponding storage unit of the current output data knows position to described from highest order bit line address label
Distinguishing includes 0 in the bit line address that subarray marker includes, and the differentiation subarray marker 0, next submatrix
The corresponding bit line of storage unit in column is highest order bit line in the bit line of the corresponding storage unit of the current output data
Location marker to it is described differentiation subarray marker include bit line address be plus a corresponding bit line address, next height
The corresponding wordline of storage unit in array is the bit line address of the corresponding storage unit of the current output data.
Second aspect, the embodiment of the invention provides a kind of devices for improving NOR type storage array reading speed, comprising:
Division module, the division module are used to the NOR type storage array being divided into 2nA subarray；
Bit line address marker determining module, the bit line address marker determining module are connected with the division module,
For the item number m according to the bit line of the NOR type storage array, bit line address marker corresponding with the bit line, institute are determined
The quantity of rheme line address marker isAnd number consecutively；
Bit line address label is chosen to know position determining module, it is described to choose bit line address label with knowing position determining module and the bit line
Location marker determining module is connected, for according to the item number x for choosing bit line in subarray described in each, determination to be chosen with described
The corresponding bit line address marker of bit line, the quantity for choosing bit line address label to know position are
Subarray marker module is distinguished, the differentiation subarray marker module chooses bit line address label to know position with described
Determining module is connected, and for choosing the address of bit line according to, selects differentiation submatrix in the bit line address marker
Column marker, the quantity for distinguishing subarray marker are n；
The bit line address marker include the differentiations subarray marker and it is described choose bit line address label knowledge position；
Read module includes reading unit and non-reading unit for the first time for the first time, and the read module is respectively with the bit line
Location marker determining module described chooses bit line address label to know position determining module and the differentiation subarray marker module phase
Even；
If the reading unit for the first time for reading for the first time, chooses address and the choosing of bit line according to first address determination
The address of middle wordline, the first address is the reading address that chip exterior is sent into, according to the address for choosing bit line, the choosing
The address of middle wordline, the bit line address marker state and the bit line address marker described in differentiation subarray mark
The state for knowing position, to described 2nStorage unit in a subarray is read simultaneously；
If the non-reading unit for the first time for not reading for the first time, if not reading for the first time, according to current output data
The bit line address and wordline address of corresponding storage unit are exported and the address of presently described selected word line and presently described are chosen
The corresponding data of the corresponding storage unit in the address of bit line, and the storage unit of next subarray is read；
The n is the integer more than or equal to 1, describedFor the integer more than or equal to 1, the m is greater than or waits
In x.
Optionally, when the n is 1, the NOR type storage array is divided into 2 subarrays, respectively the first subarray
With the second subarray；
The differentiation subarray marker is 1.
Optionally, if the reading unit for the first time is specifically used for reading for the first time, in the first address from highest order bit line
Location marker to the differentiation subarray marker include it is described choose the address of bit line to be all 1, then to second submatrix
The address of selected word line described in column and the corresponding storage unit in address for choosing bit line are read, and are read simultaneously
Storage unit in first subarray, the corresponding wordline of storage unit in first subarray are second submatrix
The corresponding wordline in address after the cyclic address change of selected word line described in column；Storage unit in first subarray is corresponding
The bit line bit line address marker in highest order bit line address label know position and to the differentiation subarray marker include
The address of bit line is all 0 bit line.
Optionally, if the reading unit for the first time is specifically also used to read for the first time, from highest order bit line in the first address
Address marker to the differentiation subarray marker include described in choose comprising 0 in the address of bit line, and differentiations is sub
Array marker 1,
Then to the storage unit in second subarray through being read out, the storage unit pair that is read in the second subarray
The wordline answered is the corresponding wordline of first address, and bit line is the corresponding bit line of the first address；First son is read simultaneously
Storage unit in array, the corresponding wordline of storage unit of first subarray are that wordline address is corresponding in the first address
Wordline, the corresponding bit line of storage unit in first subarray is highest order in the first address bit line address marker
Corresponding bit line after the cyclic address change that bit line address marker includes to the differentiation subarray marker, if second son
Highest order bit line address label knowledge position includes to the differentiation subarray marker in the corresponding bit line of storage unit in array
The address for choosing bit line is all 1, then the corresponding wordline of storage unit in first subarray is second submatrix
Corresponding wordline after the corresponding wordline address of the storage unit of column adds one, otherwise, the storage unit in first subarray
Corresponding wordline is the corresponding wordline of storage unit of second subarray；
The choosing that position includes to the differentiation subarray marker is known from highest order bit line address label in the first address
Include 0 in the address of neutrality line, and the differentiation subarray marker 0, then to the storage unit in first subarray into
Row read operation, the wordline for reading storage unit in the first subarray is the corresponding wordline of the first address, reads the first submatrix
The bit line of storage unit is the corresponding bit line of the first address in column；The storage unit institute in second subarray is read simultaneously
Stating the corresponding bit line of storage unit in the first subarray is that highest order bit line address label knows position to the area in the first address
The bit line address that molecular array marker includes is to add a corresponding bit line address, the storage unit pair in second subarray
The wordline answered is the corresponding wordline of storage unit of first subarray.
Optionally, the non-reading unit for the first time is specifically used for the bit line according to the corresponding storage unit of current output data
Address and wordline address export and the address of presently described selected word line and the presently described corresponding storage in address for choosing bit line
The corresponding data of unit, and step is read to the storage unit of next subarray and is specifically included:
If described not read for the first time, according to the bit line address of the corresponding storage unit of current output data and wordline
Location exports and the address of presently described selected word line and the presently described corresponding number of the corresponding storage unit in address for choosing bit line
According to；
And the storage unit of next subarray is read, the corresponding storage unit of the current output data
Bit line address in from highest order bit line address label know position to it is described differentiation subarray marker include bit line address in include
0, and the differentiation subarray marker 1, if highest order bit line address in the bit line of the corresponding storage unit of current output data
The address of marker to the bit line that the differentiation subarray marker includes is all 1, the storage unit of next subarray
Corresponding bit line is that highest order bit line address label knowledge position is arrived in the bit line address of the corresponding storage unit of the current output data
The bit line address that the differentiation subarray marker includes adds a corresponding bit line address, then depositing in next subarray
The corresponding wordline of storage unit is corresponding after the corresponding wordline address of the corresponding storage unit of the current output data adds one
Wordline, otherwise, the corresponding wordline of storage unit of next subarray are that the corresponding storage of the current output data is single
The corresponding wordline of member；
The bit line address of the corresponding storage unit of the current output data knows position to described from highest order bit line address label
Distinguishing includes 0 in the bit line address that subarray marker includes, and the differentiation subarray marker 0, next submatrix
The corresponding bit line of storage unit in column is highest order bit line in the bit line of the corresponding storage unit of the current output data
Location marker to it is described differentiation subarray marker include bit line address be plus a corresponding bit line address, next height
The corresponding wordline of storage unit in array is the bit line address of the corresponding storage unit of the current output data.
Provided in the embodiment of the present invention it is a kind of improve NOR type storage array reading speed method and device, pass through by
NOR type storage array is divided into the method for multiple subarrays, reads the data of multiple storage units every time, is selected with shortening to have read
The storage unit of quantity, and the temporal summation that the data of these storage units are all exported.
Detailed description of the invention
Fig. 1 is that a kind of process of the method for raising NOR type storage array reading speed that the embodiment of the present invention one provides is shown
It is intended to；
Fig. 2 is that a kind of process of method for improving NOR type storage array reading speed provided by Embodiment 2 of the present invention is shown
It is intended to；
Fig. 3 is that a kind of structure of the device for raising NOR type storage array reading speed that the embodiment of the present invention three provides is shown
It is intended to.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of process signal of method for improving NOR type storage array reading speed provided in an embodiment of the present invention
Figure, this method can be executed by a kind of square law device for improving NOR type storage array reading speed, wherein the device can be by
Hardware and/or software realize that, referring to Fig. 1, this method comprises the following steps:
NOR type storage array is divided into 2 by step 101nA subarray.N is the integer more than or equal to 1.
Step 102, the item number m according to the bit line of NOR type storage array determine that bit line address corresponding with bit line identifies
Position, the quantity of bit line address marker areAnd number consecutively.
Step 103, according to the item number x for choosing bit line in each subarray, with determining bit line corresponding with bit line is chosen
Location marker, the quantity for choosing bit line address label to know position are
It should be noted that in the present embodiment, according to total position number of lines m, corresponding 1 word of each bit line address marker
(Byte) data, i.e. 8 bit lines are saved, therefore the quantity of bit line address marker isEach each subarray is optional
Middle x root bit line, x are memory cell read circuitry number, then choose the corresponding bit line address flag bit number of bit line to beBit line address label is generally chosen to know the low order address i.e. address that position is bit line address marker
In the present embodiment, the address of bit line is usually binary coding.
Step 104, basis choose the address of bit line, know to select in position in bit line address label and distinguish subarray marker,
The quantity for distinguishing subarray marker is n.
The bit line address marker include the differentiations subarray marker and it is described choose bit line address label knowledge position；
In the present embodiment, generally distinguishing subarray marker is in the marker of address
Step 105 judges whether to read for the first time.
In the present embodiment, if reading instruction in relation to the storage unit of selected bit line and selected word line is to go out for the first time
It is existing, then being to read for the first time.
If step 106 is read for the first time, the address and the address of selected word line for choosing bit line are determined according to first address, it is first
Address is the reading address that chip exterior is sent into, according to choosing the address of bit line, the address of selected word line, bit line address marker
State and bit line address marker in distinguish subarray marker state, to 2nStorage unit in a subarray is simultaneously
It is read.
If step 107 is not read for the first time, according to the bit line address and wordline of the corresponding storage unit of current output data
The corresponding data of the corresponding storage unit in the address of bit line with the address of current selected word line and are currently chosen in address, output, and
The storage unit of next subarray is read.
The n is the integer more than or equal to 1, describedFor the integer more than or equal to 1, the m is greater than or waits
In x.
A kind of method for improving NOR type storage array reading speed is provided in the embodiment of the present invention, by depositing NOR type
Storage array is divided into the method for multiple subarrays, reads the data of multiple storage units every time, has read selected quantity to shorten
Storage unit, and the temporal summation that the data of these storage units are all exported.
Embodiment two
The embodiment of the invention provides a kind of methods for improving NOR type storage array reading speed, in above-described embodiment
On the basis of, the technical solution of the embodiment of the present invention further defines the quantity of n, and when n is 1, NOR type storage array is divided
For 2 subarrays, respectively the first subarray and the second subarray；Distinguishing subarray marker is 1.Referring to fig. 2, this method
Include the following steps:
NOR type storage array is divided into 2 subarrays by step 201.
Step 202, the item number m according to the bit line of NOR type storage array determine that bit line address corresponding with bit line identifies
Position, the quantity of bit line address marker areAnd number consecutively.
Step 203, according to the item number x for choosing bit line in each subarray, with determining bit line corresponding with bit line is chosen
Location marker, the quantity for choosing bit line address label to know position are
Step 204, basis choose the address of bit line, know to select in position in bit line address label and distinguish subarray marker,
The quantity for distinguishing subarray marker is 1.
Step 205 judges whether to read for the first time.
If step 206 is read for the first time, position is known to differentiation subarray marker packet from highest order bit line address label in first address
What is contained chooses the address of bit line to be all 1, then corresponding with the address of bit line is chosen to the address of selected word line in the second subarray
Storage unit is read, while reading the storage unit in the first subarray, the storage unit pair in the first subarray
The wordline answered is the corresponding wordline in address in the second subarray after the cyclic address change of selected word line；Depositing in the first subarray
The corresponding bit line of storage unit knows position to subarray marker is distinguished for highest order bit line address label in bit line address marker
Bit line address be all 0 bit line.
If reading for the first time, position is known from highest order bit line address label in first address and is chosen to what differentiation subarray marker included
Include 0 in the address of bit line, and distinguishes subarray marker 1, then to the storage unit in the second subarray through being read out, the
The corresponding wordline of the storage unit read in two subarrays is the corresponding wordline of first address, and bit line is the corresponding bit line of first address；
Simultaneously read the first subarray in storage unit, the corresponding wordline of the storage unit of the first subarray be first address in wordline
The corresponding wordline in location, most significant bits in the marker of bit line of address address headed by the corresponding bit line of storage unit in the first subarray
Corresponding bit line after the cyclic address change that line address marker includes to differentiation subarray marker, if depositing in the second subarray
Highest order bit line address label knows the address for choosing bit line that position includes to differentiation subarray marker in the corresponding bit line of storage unit
It is all 1, then the corresponding wordline of storage unit in the first subarray is the corresponding wordline address of storage unit of the second subarray
Corresponding wordline after adding one, otherwise, the corresponding wordline of storage unit in the first subarray are the storage list of the second subarray
The corresponding wordline of member；
The address for choosing bit line that position includes to differentiation subarray marker is known from highest order bit line address label in first address
In include 0, and distinguish subarray marker 0, then the storage unit in the first subarray is read, read first son
The wordline of storage unit is the corresponding wordline of first address in array, and the bit line for reading storage unit in the first subarray is first address
Corresponding bit line；Simultaneously headed by the corresponding bit line of storage unit in the first subarray of storage unit in the second subarray of reading
It is with adding a corresponding bit line that highest order bit line address label, which knows position to the bit line address that subarray marker includes is distinguished, in address
Location, the corresponding wordline of storage unit in the second subarray are the corresponding wordline of storage unit of the first subarray.
If step 206 is not read for the first time, according to the bit line address and wordline of the corresponding storage unit of current output data
The corresponding data of the corresponding storage unit in the address of bit line with the address of current selected word line and are currently chosen in address, output, and
The storage unit of next subarray is read.
The method of NOR type storage array reading speed provided in an embodiment of the present invention, on the basis of the above embodiments, into
One step defines the quantity of n, as example when using n being 1, further according in first address from the area highest order bit line address label Shi Weidao
What molecular array marker included chooses the address of bit line and distinguishes subarray marker, to the first subarray and the second son
Storage unit in array is read out, and reads the data of multiple storage units every time, has read depositing for selected quantity to shorten
Storage unit, and the temporal summation that the data of these storage units are all exported.
It should be noted that the quantity for distinguishing subarray marker is n when n is not 1, n differentiation subarray mark is utilized
The state of position is known to distinguish different subarrays.
Optionally, in step 206, if not reading for the first time, according to the bit line of the corresponding storage unit of current output data
Address and wordline address, output choose the corresponding storage unit in address of bit line corresponding with the address of current selected word line and currently
Data, and step is read to the storage unit of next subarray and is specifically included:
It is defeated according to the bit line address and wordline address of the corresponding storage unit of current output data if not reading for the first time
The corresponding data of the corresponding storage unit in the address of bit line are chosen with the address of current selected word line and currently out；
And the storage unit of next subarray is read, the position of the corresponding storage unit of current output data
Knowing position to distinguishing from highest order bit line address label in line address includes 0 in the bit line address that subarray marker includes, and is distinguished
Subarray marker 1, if highest order bit line address label knows position to differentiation in the bit line of the corresponding storage unit of current output data
The address for the bit line that subarray marker includes is all 1, and the corresponding bit line of the storage unit of next subarray is current output
Highest order bit line address label knows the position that position includes to differentiation subarray marker in the bit line address of the corresponding storage unit of data
The corresponding bit line address of line cyclic address change, then the corresponding wordline of storage unit in next subarray is current output data pair
Corresponding wordline after the corresponding wordline address of the storage unit answered adds one, otherwise, the storage unit of next subarray are corresponding
Wordline be the corresponding wordline of the corresponding storage unit of current output data；
The bit line address of the corresponding storage unit of current output data knows position to differentiation submatrix from highest order bit line address label
Include 0 in the bit line address that column marker includes, and distinguishes subarray marker 0, the storage unit pair in next subarray
The bit line answered is that highest order bit line address label knows position to differentiation subarray in the bit line of the corresponding storage unit of current output data
The bit line address that marker includes is to add a corresponding bit line address, and the corresponding wordline of storage unit in next subarray is
The bit line address of the corresponding storage unit of current output data.
Based on the above technical solution, it further defines and is read for the first time not, pass through current output data pair
In the bit line address for the storage unit answered with knowing the bit line that position includes to differentiation subarray marker from highest order bit line address label
Location and differentiation subarray marker, are read the storage unit of next subarray, so as to read every time multiple
The data of storage unit to shorten the storage unit for having read selected quantity, and the data of these storage units are all exported
Temporal summation.
Illustratively, it is assumed that bit line address position is A<2:0>, and each address bit corresponds to 1Byte data, so each address
Corresponding 8 bit lines, corresponding a total of 64 of the bit line of A<2:0>, defining bit line according to sequence of addresses is BL<1>~BL<8>, each
BL corresponds to 8 bit line address, as shown in table 1.
It is<2>A that highest order bit line address label, which knows position,.Distinguish address marker select A<1>, A<1>divide equally bit line BL<1>~
BL<8>is the right and left, is the corresponding bit line BL<1>of bit line on the left side, BL<2>, BL<5>, BL<6>when<1>=0 A, A<1>=
1 corresponds to bit line BL<3>, BL<4>, BL<7>, BL<8>, corresponding 8 bit lines of each BL for the bit line on the right.The right and left respectively has 16
A reading circuit, each reading circuit read a piece bit line of selection every time.
When reading for the first time: if first address A<2:1>=00, the right and left reads BL<1>, BL<2>, BL<3 simultaneously
>,BL<4>；
If first address A<2:1>=01, the right and left reads BL<3>, BL<4>, BL<5>, BL<6>simultaneously；
If first address A<2:1>=10, controls while reading BL<5>, BL<6>, BL<7>, BL<8>；
If first address A<2:1>=11, it is corresponding to read BL<7>, BL<8>and next wordline address simultaneously
BL<0>、BL<1>。
It is non-when reading for the first time, due to reading while reading the right and left for the first time, then the non-bit line address one read for the first time
It is fixed only to will appear following four kinds of situations: A<2:0>=000, A<2:0>=010, A<2:0>=100 and A<2:0>=110.
Current address A<2:0>=000, then current output data is BL<1>, BL<2>, when exporting BL<1>,<2>BL
Read the corresponding BL<3>of bit line address A<2:1>=01 and BL<4>under same root wordline；
If current address A<2:0>=010, current output data be BL<3>, BL<4>, output BL<3>, BL<
4>when, reads the corresponding BL<5>of bit line address A<2:1>=10, BL<6>under same root wordline；
If current address A<2:0>=100, current output data be BL<5>, BL<6>, output BL<5>, BL<
6>when, reads the corresponding BL<7>of bit line address A<2:1>=11, BL<8>under same root wordline；
If current address A<2:0>=110, current output data be BL<7>, BL<8>, output BL<7>, BL<
8 > when, while reading following information: selected word line is wordline current cyclic address change, i.e., puts in order according to wordline and switch to next
Wordline, bit line address are A<2:1>=00, that is, read the corresponding BL<1>of next wordline, BL<2>.
1 bit line address of table and bit line mapping table
| Bit line address A<2:0> | Corresponding bit line (bit line) |
| A<2:0>=000 | BL<1> |
| A<2:0>=001 | BL<2> |
| A<2:0>=010 | BL<3> |
| A<2:0>=011 | BL<4> |
| A<2:0>=100 | BL<5> |
| A<2:0>=101 | BL<6> |
| A<2:0>=110 | BL<7> |
| A<2:0>=111 | BL<8> |
It should be noted that the method being usually taken is when reading in the prior art for NOR type storage array:
It is assumed that chip interior shares x reading circuit, the integral number power that x is 2, each reading circuit connects a bit line, then each
Secondary read operation will read the data of x storage unit, these data will be since the corresponding storage unit of first address simultaneously
Constantly add 1 Sequential output data by address, wherein first address is the address that chip exterior is sent into, the corresponding output in each address
Data are 8bit；Due to data output be according to sequence of addresses output and centre cannot have interruption, it is desirable to this reading
X storage unit last 8bit data exported before, according to address plus the number of next group of x storage unit of 1 sequence
According to being ready to；If it is just last group of 8bit data of this group of data that first address is corresponding, need exporting last
The data of next group of x storage unit are run through when group 8bit data, 8bit data output clock number used is fixed, then
Reading circuit reads primary clock number used and determines the clock number exported by 8bit data.
If with traditional unilateral reading of scheme second of reading will be started immediately after reading first time, at four mouthfuls
The fewer situation of the illusory clock number (dummy) being inserted between address input and data output, reading enable time can only be small
It is unaffected that second of reading is just able to satisfy in 4 clock cycle, and read operation of the invention, reading point or so is read simultaneously for the first time
It takes, the corresponding all storage arrays of A<x:0>have been read into latch (latch), and for the first time and second of reading is spaced ratio
Longer, reading enable time can accomplish that 6 clock cycle are filled the read access time of storage array by wordline or bit line
The limitation such as electric discharge, circuit delay and sense amplifier (SA) recognition speed, so reading clock frequency of the invention is about to pass
System reads 1.5 times of clock frequency, and reading frequency greatly promotes, and effectively improves reading speed.
Embodiment three
On the basis of the above embodiments, the embodiment of the invention provides a kind of raising NOR type storage array reading speeds
Device, referring to Fig. 3, which includes:
Division module 310, division module are used to NOR type storage array being divided into 2nA subarray；
Bit line address marker determining module 320, bit line address marker determining module 420 are connected with division module 310,
For the item number m according to the bit line of NOR type storage array, bit line address marker corresponding with bit line, bit line address mark are determined
Know position quantity beAnd number consecutively；
It chooses bit line address label to know position determining module 330, bit line address label is chosen to know position determining module 330 and bit line address
Marker determining module 320 is connected, for determining and choosing bit line pair according to the item number x for choosing bit line in each subarray
The bit line address marker answered, the quantity for choosing bit line address label to know position are
Subarray marker module 340 is distinguished, subarray marker module 340 is distinguished and chooses bit line address label knowledge position true
Cover half block 330 is connected, for knowing to select in position in bit line address label and distinguishing subarray mark according to the address for choosing bit line
Position, the quantity for distinguishing subarray marker is n；The bit line address marker includes the differentiation subarray marker and described
Bit line address label is chosen to know position；
Read module 350 includes reading unit 3501 and non-reading unit 3502 for the first time for the first time, read module respectively with position
Line address marker determining module 320 chooses bit line address label to know position determining module 330 and distinguishes subarray marker module
340 are connected；
If reading unit 3501 for reading for the first time for the first time, is determined according to first address and choose the address of bit line and choose word
The address of line, first address is the reading address that chip exterior is sent into, according to choosing the address of bit line, the address of selected word line, position
The state that subarray marker is distinguished in the state and bit line address marker of line address marker, in 2^n subarray
Storage unit be read simultaneously；
If non-reading unit for the first time 3502 for not reading for the first time, if not reading for the first time, according to current output data
The address of the bit line address and wordline address of corresponding storage unit, output and current selected word line and the ground for currently choosing bit line
The corresponding data of the corresponding storage unit in location, and the storage unit of next subarray is read；
N is the integer more than or equal to 1,For the integer more than or equal to 1, m is greater than or equal to x.
A kind of device for improving NOR type storage array reading speed is provided in the embodiment of the present invention, by depositing NOR type
Storage array is divided into the method for multiple subarrays, reads the data of multiple storage units every time, has read selected quantity to shorten
Storage unit, and the temporal summation that the data of these storage units are all exported.
Optionally, based on the above technical solution, when n is 1, NOR type storage array is divided into 2 subarrays,
Respectively the first subarray and the second subarray；Distinguishing subarray marker is 1.
Optionally, based on the above technical solution, if reading unit 3501 is specifically used for reading for the first time for the first time, first ground
Position is known from highest order bit line address label in location and is all 1 to the subarray marker address for choosing bit line that includes is distinguished, then to the
The address of selected word line storage unit corresponding with the address of bit line is chosen is read in two subarrays, while reading the
Storage unit in one subarray, the corresponding wordline of storage unit in the first subarray are selected word line in the second subarray
The corresponding wordline in address after cyclic address change；The corresponding bit line of storage unit in first subarray is bit line address marker
Middle highest order bit line address label knows the bit line that position is all 0 to the address for distinguishing the bit line that subarray marker includes.
Optionally, based on the above technical solution, first if reading unit 3501 specifically is also used to read for the first time for the first time
Knowing position to distinguishing from highest order bit line address label in address includes 0 in the address for choosing bit line that subarray marker includes, and
Distinguish subarray marker 1, then to the storage unit in the second subarray through being read out, the storage read in the second subarray
The corresponding wordline of unit is the corresponding wordline of first address, and bit line is the corresponding bit line of first address；It reads in the first subarray simultaneously
Storage unit, the corresponding wordline of the storage unit of the first subarray be first address in the corresponding wordline of wordline address, first son
Highest order bit line address label knows position to differentiation in the marker of bit line of address address headed by the corresponding bit line of storage unit in array
Corresponding bit line after the cyclic address change that subarray marker includes, if in the corresponding bit line of storage unit in the second subarray
Highest order bit line address label knows position and is all 1 to the address for choosing bit line that subarray marker includes is distinguished, then the first subarray
In the corresponding wordline of storage unit be that the corresponding wordline address of storage unit of the second subarray adds corresponding wordline after one,
Otherwise, the corresponding wordline of storage unit in the first subarray is the corresponding wordline of storage unit of the second subarray；
The address for choosing bit line that position includes to differentiation subarray marker is known from highest order bit line address label in first address
In include 0, and distinguish subarray marker 0, then the storage unit in the first subarray is read, read first son
The wordline of storage unit is the corresponding wordline of first address in array, and the bit line for reading storage unit in the first subarray is first address
Corresponding bit line；Simultaneously headed by the corresponding bit line of storage unit in the first subarray of storage unit in the second subarray of reading
It is with adding a corresponding bit line that highest order bit line address label, which knows position to the bit line address that subarray marker includes is distinguished, in address
Location, the corresponding wordline of storage unit in the second subarray are the corresponding wordline of storage unit of the first subarray.
Optionally, based on the above technical solution, non-reading unit for the first time 4502 is specifically used for according to current output
The bit line address and wordline address of the corresponding storage unit of data, output and the address of current selected word line and current choose bit line
The corresponding data of the corresponding storage unit in address, and it is specific to be read step to the storage unit of next subarray
Include:
It is defeated according to the bit line address and wordline address of the corresponding storage unit of current output data if not reading for the first time
The corresponding data of the corresponding storage unit in the address of bit line are chosen with the address of current selected word line and currently out；
And the storage unit of next subarray is read, the position of the corresponding storage unit of current output data
Knowing position to distinguishing from highest order bit line address label in line address includes 0 in the bit line address that subarray marker includes, and is distinguished
Subarray marker 1, if highest order bit line address label knows position to differentiation in the bit line of the corresponding storage unit of current output data
The address for the bit line that subarray marker includes is all 1, and the corresponding bit line of the storage unit of next subarray is current output
Highest order bit line address label knows the position that position includes to differentiation subarray marker in the bit line address of the corresponding storage unit of data
The corresponding bit line address of line cyclic address change, then the corresponding wordline of storage unit in next subarray is current output data pair
Corresponding wordline after the corresponding wordline address of the storage unit answered adds one, otherwise, the storage unit of next subarray are corresponding
Wordline be the corresponding wordline of the corresponding storage unit of current output data；
The bit line address of the corresponding storage unit of current output data knows position to differentiation submatrix from highest order bit line address label
Include 0 in the bit line address that column marker includes, and distinguishes subarray marker 0, the storage unit pair in next subarray
The bit line answered is that highest order bit line address label knows position to differentiation subarray in the bit line of the corresponding storage unit of current output data
The bit line address that marker includes is to add a corresponding bit line address, and the corresponding wordline of storage unit in next subarray is
The bit line address of the corresponding storage unit of current output data.
The executable present invention of the device of the raising NOR type storage array reading speed provided in above-described embodiment is any to be implemented
The method that NOR type storage array reading speed is improved provided by example has and executes the corresponding functional module of this method and beneficial
Effect.The not technical detail of detailed description in the above-described embodiments, reference can be made to raising NOR provided by any embodiment of the invention
The method of type storage array reading speed.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts, be combined with each other and substitutes without departing from protection scope of the present invention.Therefore, although by above embodiments to this
Invention is described in further detail, but the present invention is not limited to the above embodiments only, is not departing from present inventive concept
In the case of, it can also include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of method for improving NOR type storage array reading speed characterized by comprising
The NOR type storage array is divided into 2nA subarray；
According to the item number m of the bit line of the NOR type storage array, bit line address marker corresponding with the bit line, institute are determined
The quantity of rheme line address marker isAnd number consecutively；
It is determining to choose the corresponding bit line address mark of bit line with described according to the item number x for choosing bit line in subarray described in each
Know position, the quantity for choosing bit line address label to know position is
According to the address for choosing bit line, is selected in the bit line address marker and distinguish subarray marker, it is described
The quantity for distinguishing subarray marker is n；
The bit line address marker include the differentiations subarray marker and it is described choose bit line address label knowledge position；
If reading for the first time, the address of bit line and the address of selected word line, the first address are chosen according to first address determination
For the reading address that chip exterior is sent into, according to the address for choosing bit line, the address of the selected word line, the bit line
The state that subarray marker is distinguished described in the state of location marker and the bit line address marker, to described 2nHeight
Storage unit in array is read simultaneously；
If not reading for the first time, according to the bit line address and wordline address of the corresponding storage unit of current output data, output with
The address of presently described selected word line and the presently described corresponding data of the corresponding storage unit in address for choosing bit line, and under
The storage unit of one subarray is read；
The n is the integer more than or equal to 1, describedFor the integer more than or equal to 1, the m is greater than or equal to x.
2. the method according to claim 1, wherein
When the n is 1, the NOR type storage array is divided into 2 subarrays, respectively the first subarray and the second submatrix
Column；
The differentiation subarray marker is 1.
3. according to the method described in claim 2, it is characterized in that,
If described read for the first time, the address of bit line, the address of selected word line, the first address are chosen according to first address determination
For chip exterior be sent into reading address, according to the address for choosing bit line, the address of selected word line, the bit line address mark
The state that subarray marker is distinguished described in the state and the bit line address marker of position is known, to described 2nA subarray
In storage unit be read step simultaneously and specifically include:
If reading for the first time, knowing position to the differentiation subarray marker from highest order bit line address label in the first address includes
The address for choosing bit line is all 1, then the address to selected word line described in second subarray and described chooses bit line
The corresponding storage unit in address be read, while reading the storage unit in first subarray, described first
The corresponding wordline of storage unit in subarray is the ground after the cyclic address change of selected word line described in second subarray
The corresponding wordline in location；The corresponding bit line of storage unit in first subarray is highest order in the bit line address marker
The address for the bit line that bit line address marker includes to the differentiation subarray marker is all 0 bit line.
4. according to the method described in claim 3, it is characterized in that,
If reading for the first time, knowing position to the differentiation subarray marker from highest order bit line address label in the first address includes
It include 0 in the address for choosing bit line, and the differentiation subarray marker 1,
Then to the storage unit in second subarray through being read out, the storage unit read in the second subarray is corresponding
The wordline is the corresponding wordline of first address, and bit line is the corresponding bit line of the first address；First subarray is read simultaneously
In storage unit, the corresponding wordline of storage unit of first subarray is the corresponding word of wordline address in the first address
Line, the corresponding bit line of storage unit in first subarray are highest order bit line in the first address bit line address marker
Corresponding bit line after the cyclic address change that address marker includes to the differentiation subarray marker, if second subarray
In the corresponding bit line of storage unit in highest order bit line address label know position to it is described distinguish subarray marker include it is described
The address of bit line is chosen to be all 1, then the corresponding wordline of storage unit in first subarray is second subarray
Corresponding wordline after the corresponding wordline address of storage unit adds one, otherwise, the storage unit in first subarray are corresponding
Wordline be second subarray the corresponding wordline of storage unit；
The selected bit that position includes to the differentiation subarray marker is known from highest order bit line address label in the first address
Include 0 in the address of line, and the differentiation subarray marker 0, then the storage unit in first subarray is read
Extract operation, the wordline for reading storage unit in the first subarray is the corresponding wordline of the first address, is read in the first subarray
The bit line of storage unit is the corresponding bit line of the first address；The is read described in storage unit in second subarray simultaneously
The corresponding bit line of storage unit in one subarray is that highest order bit line address label knows position to differentiation in the first address
The bit line address that array marker includes is to add a corresponding bit line address, and the storage unit in second subarray is corresponding
Wordline is the corresponding wordline of storage unit of first subarray.
5. according to the method described in claim 2, it is characterized in that,
If described not read for the first time, defeated according to the bit line address and wordline address of the corresponding storage unit of current output data
Out with the address of presently described selected word line and the presently described corresponding data of the corresponding storage unit in address for choosing bit line, and
Step is read to the storage unit of next subarray to specifically include:
If described not read for the first time, defeated according to the bit line address and wordline address of the corresponding storage unit of current output data
Out with the address of presently described selected word line and the presently described corresponding data of the corresponding storage unit in address for choosing bit line；
And the storage unit of next subarray is read, the position of the corresponding storage unit of the current output data
Know in the bit line address that position includes to the differentiation subarray marker from highest order bit line address label comprising 0 in line address, and
The differentiation subarray marker 1, if highest order bit line address label is known in the bit line of the corresponding storage unit of current output data
The address for the bit line that position includes to the differentiation subarray marker is all 1, and the storage unit of next subarray is corresponding
Bit line be that highest order bit line address label is known described in position arrives in the bit line address of the corresponding storage unit of the current output data
It distinguishes the bit line address that subarray marker includes and adds a corresponding bit line address, then the storage list in next subarray
The corresponding wordline of member is corresponding wordline after the corresponding wordline address of the corresponding storage unit of the current output data adds one,
Otherwise, the corresponding wordline of storage unit of next subarray is that the corresponding storage unit of the current output data is corresponding
Wordline；
The bit line address of the corresponding storage unit of the current output data knows position to the differentiation from highest order bit line address label
It include 0 in the bit line address that subarray marker includes, and the differentiation subarray marker 0, in next subarray
The corresponding bit line of storage unit be highest order bit line address label in the bit line of the corresponding storage unit of the current output data
The bit line address that position includes to the differentiation subarray marker is known to add a corresponding bit line address, next subarray
In the corresponding wordline of storage unit be the corresponding storage unit of the current output data bit line address.
6. a kind of device for improving NOR type storage array reading speed characterized by comprising
Division module, the division module are used to the NOR type storage array being divided into 2nA subarray；
Bit line address marker determining module, the bit line address marker determining module are connected with the division module, are used for
According to the item number m of the bit line of the NOR type storage array, bit line address marker corresponding with the bit line, institute's rheme are determined
The quantity of line address marker isAnd number consecutively；
Bit line address label is chosen to know position determining module, it is described that bit line address label is chosen to know position determining module and the bit line address mark
Know position determining module to be connected, for according to the item number x for choosing bit line in subarray described in each, determination to choose bit line with described
Corresponding bit line address marker, the quantity for choosing bit line address label to know position are
Subarray marker module is distinguished, the differentiation subarray marker module chooses bit line address label knowledge position to determine with described
Module is connected, and for choosing the address of bit line according to, selects in the bit line address marker and distinguishes subarray mark
Know position, the quantity for distinguishing subarray marker is n；
The bit line address marker include the differentiations subarray marker and it is described choose bit line address label knowledge position；
Read module includes reading unit and non-reading unit for the first time for the first time, the read module respectively with the bit line address mark
Know position determining module, it is described choose bit line address label know position determining module be connected with the differentiation subarray marker module；
If the reading unit for the first time for reading for the first time, chooses the address of bit line according to first address determination and chooses word
The address of line, the first address are the reading address that chip exterior is sent into, and according to the address for choosing bit line, described choose word
The address of line, the bit line address marker state and the bit line address marker described in differentiation subarray marker
State, to described 2nStorage unit in a subarray is read simultaneously；
It is corresponding according to current output data if not reading for the first time if the non-reading unit for the first time for not reading for the first time
Storage unit bit line address and wordline address, output and the address of presently described selected word line and presently described choose bit line
The corresponding data of the corresponding storage unit in address, and the storage unit of next subarray is read；
The n is the integer more than or equal to 1, describedFor the integer more than or equal to 1, the m is greater than or equal to x.
7. device according to claim 6, which is characterized in that
When the n is 1, the NOR type storage array is divided into 2 subarrays, respectively the first subarray and the second submatrix
Column；
The differentiation subarray marker is 1.
8. device according to claim 7, which is characterized in that
If the reading unit for the first time is specifically used for reading for the first time, position is known to institute from highest order bit line address label in the first address
Stating distinguish that subarray marker includes described chooses the address of bit line to be all 1, then chooses to described in second subarray
The address of wordline and the corresponding storage unit in address for choosing bit line are read, while reading first submatrix
Storage unit in column, the corresponding wordline of storage unit in first subarray are to choose described in second subarray
The corresponding wordline in address after the cyclic address change of wordline；The corresponding bit line of storage unit in first subarray is described
It is complete to the address for distinguishing the bit line that subarray marker includes to know position for highest order bit line address label in bit line address marker
For 0 bit line.
9. device according to claim 7, which is characterized in that
If the reading unit for the first time is specifically also used to read for the first time, in the first address from highest order bit line address label know position to
Described distinguish in the address for choosing bit line that subarray marker includes includes 0, and the differentiation subarray marker 1,
Then to the storage unit in second subarray through being read out, the storage unit read in the second subarray is corresponding described
Wordline is the corresponding wordline of first address, and bit line is the corresponding bit line of the first address；It reads in first subarray simultaneously
Storage unit, the corresponding wordline of storage unit of first subarray are the corresponding wordline of wordline address in the first address,
The corresponding bit line of storage unit in first subarray is for highest order bit line in the first address bit line address marker
Corresponding bit line after the cyclic address change that location marker includes to the differentiation subarray marker, if in second subarray
The corresponding bit line of storage unit in highest order bit line address label know position and distinguish the choosing that includes of subarray marker to described
The address of neutrality line is all 1, then the corresponding wordline of storage unit in first subarray is depositing for second subarray
Corresponding wordline after the corresponding wordline address of storage unit adds one, otherwise, the storage unit in first subarray is corresponding
Wordline is the corresponding wordline of storage unit of second subarray；
The selected bit that position includes to the differentiation subarray marker is known from highest order bit line address label in the first address
Include 0 in the address of line, and the differentiation subarray marker 0, then the storage unit in first subarray is read
Extract operation, the wordline for reading storage unit in the first subarray is the corresponding wordline of the first address, is read in the first subarray
The bit line of storage unit is the corresponding bit line of the first address；The is read described in storage unit in second subarray simultaneously
The corresponding bit line of storage unit in one subarray is that highest order bit line address label knows position to differentiation in the first address
The bit line address that array marker includes is to add a corresponding bit line address, and the storage unit in second subarray is corresponding
Wordline is the corresponding wordline of storage unit of first subarray.
10. device according to claim 7, which is characterized in that
The non-reading unit for the first time is specifically used for bit line address and wordline according to the corresponding storage unit of current output data
Address exports corresponding with the address of presently described selected word line and the presently described corresponding storage unit in address for choosing bit line
Data, and step is read to the storage unit of next subarray and is specifically included:
If described not read for the first time, defeated according to the bit line address and wordline address of the corresponding storage unit of current output data
Out with the address of presently described selected word line and the presently described corresponding data of the corresponding storage unit in address for choosing bit line；
And the storage unit of next subarray is read, the position of the corresponding storage unit of the current output data
Know in the bit line address that position includes to the differentiation subarray marker from highest order bit line address label comprising 0 in line address, and
The differentiation subarray marker 1, if highest order bit line address label is known in the bit line of the corresponding storage unit of current output data
The address for the bit line that position includes to the differentiation subarray marker is all 1, and the storage unit of next subarray is corresponding
Bit line be that highest order bit line address label is known described in position arrives in the bit line address of the corresponding storage unit of the current output data
It distinguishes the bit line address that subarray marker includes and adds a corresponding bit line address, then the storage list in next subarray
The corresponding wordline of member is corresponding wordline after the corresponding wordline address of the corresponding storage unit of the current output data adds one,
Otherwise, the corresponding wordline of storage unit of next subarray is that the corresponding storage unit of the current output data is corresponding
Wordline；
The bit line address of the corresponding storage unit of the current output data knows position to the differentiation from highest order bit line address label
It include 0 in the bit line address that subarray marker includes, and the differentiation subarray marker 0, in next subarray
The corresponding bit line of storage unit be highest order bit line address label in the bit line of the corresponding storage unit of the current output data
The bit line address that position includes to the differentiation subarray marker is known to add a corresponding bit line address, next subarray
In the corresponding wordline of storage unit be the corresponding storage unit of the current output data bit line address.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257304A (en) * | 2021-06-22 | 2021-08-13 | 上海亿存芯半导体有限公司 | Memory and data storage and reading method |
| US11443814B1 (en) | 2021-05-27 | 2022-09-13 | Winbond Electronics Corp. | Memory structure with marker bit and operation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7523232B2 (en) * | 2004-07-26 | 2009-04-21 | Integrated Device Technology, Inc. | Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system |
| US20090296467A1 (en) * | 2008-06-03 | 2009-12-03 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving the same |
| CN102521146A (en) * | 2011-11-08 | 2012-06-27 | 福建新大陆通信科技股份有限公司 | Data addressing storage method of flash memory block subdivision |
| US8339850B2 (en) * | 2009-05-15 | 2012-12-25 | Renesas Electronics Corporation | Semiconductor device |
| US9508423B2 (en) * | 2015-02-02 | 2016-11-29 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of reading the same |
| CN106469574A (en) * | 2015-08-19 | 2017-03-01 | 爱思开海力士有限公司 | Storage arrangement and its operational approach |
| CN106960686A (en) * | 2017-03-31 | 2017-07-18 | 中国科学院微电子研究所 | A kind of read method and flash memory devices |
-
2017
- 2017-11-29 CN CN201711230666.6A patent/CN109841259B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7523232B2 (en) * | 2004-07-26 | 2009-04-21 | Integrated Device Technology, Inc. | Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system |
| US20090296467A1 (en) * | 2008-06-03 | 2009-12-03 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving the same |
| US8339850B2 (en) * | 2009-05-15 | 2012-12-25 | Renesas Electronics Corporation | Semiconductor device |
| CN102521146A (en) * | 2011-11-08 | 2012-06-27 | 福建新大陆通信科技股份有限公司 | Data addressing storage method of flash memory block subdivision |
| US9508423B2 (en) * | 2015-02-02 | 2016-11-29 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of reading the same |
| CN106469574A (en) * | 2015-08-19 | 2017-03-01 | 爱思开海力士有限公司 | Storage arrangement and its operational approach |
| CN106960686A (en) * | 2017-03-31 | 2017-07-18 | 中国科学院微电子研究所 | A kind of read method and flash memory devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11443814B1 (en) | 2021-05-27 | 2022-09-13 | Winbond Electronics Corp. | Memory structure with marker bit and operation method thereof |
| CN113257304A (en) * | 2021-06-22 | 2021-08-13 | 上海亿存芯半导体有限公司 | Memory and data storage and reading method |
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