CN109841259B - Method and device for improving NOR type memory array reading speed - Google Patents
Method and device for improving NOR type memory array reading speed Download PDFInfo
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Abstract
The invention discloses a method and a device for improving the reading speed of a NOR type memory array, comprising the following steps: partitioning NOR-type memory arrays into 2nA sub-array; if the reading is carried out for the first time, the address of the selected bit line and the address of the selected word line are determined according to the first address, and the pair 2 is compared according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit and the state of the molecular array identification bit in the bit line address identification bitnSimultaneously reading the memory cells in the sub-arrays; and if the reading is not the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and reading the memory cell of the next sub-array. The technical scheme of the embodiment of the invention is that the storage array is divided into a plurality of sub-arrays, a plurality of storage units are read each time, so that the sum of the time for reading the selected number of storage units is shortened, and the data of the storage units are all output.
Description
Technical Field
The embodiment of the invention relates to the technical field of nonvolatile memories, in particular to a method and a device for improving the reading speed of a NOR type memory array.
Background
In the prior art, when a NOR type memory array is read, the following methods are generally adopted: in the prior art, when a NOR type memory array is read, the following methods are generally adopted: assuming that the chip has x reading circuits, the number of the reading circuits is the number of the selected bit lines, x is the integral power of 2, each reading circuit is connected with one bit line, each reading operation reads the data of x storage units, the data starts from the storage unit corresponding to the initial address and outputs data according to the sequence that the address is continuously added with 1, wherein the initial address is the address sent from the outside of the chip, and the output data corresponding to each address is 8 bits; because the data output is output according to the address sequence and the middle can not be interrupted, the data of the next group of x storage units according to the sequence of adding 1 to the address is required to be prepared before the last 8-bit data of the x storage units read at this time is output; if the head address corresponds to the last group of 8-bit data of the group of data, the data of the next group of x storage units needs to be read when the last group of 8-bit data is output, and the clock number used for outputting the 8-bit data is fixed, the clock number used for reading once by the reading circuit is determined by the clock number output by the 8-bit data.
If the traditional scheme is used for single-side reading, the second reading is started immediately after the first reading is finished, and under the condition that the dummy clock number (dummy) inserted between four-port address input and the data output is less, the read enabling time can only be less than 4 clock cycles to meet the requirement that the second reading is not influenced.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method and an apparatus for increasing a reading speed of a NOR-type memory array, in which the NOR-type memory array is divided into a plurality of sub-arrays, and data of a plurality of memory cells is read at a time, so as to reduce a sum of time for reading a selected number of memory cells and outputting all data of the memory cells.
In a first aspect, an embodiment of the present invention provides a method for increasing a reading speed of a NOR-type memory array, including:
partitioning the NOR-type memory array into 2nA sub-array;
according to the number m of the bit lines of the NOR type memory array, determining bit line address identification bits corresponding to the bit lines, wherein the number of the bit line address identification bits is
And are numbered in sequence;
determining the number of selected bit lines in each sub-array according to the number x of selected bit lines in each sub-arrayAnd determining bit line address identification bits corresponding to the selected bit lines, wherein the number of the selected bit line address identification bits is
Selecting distinguishing sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the distinguishing sub-array identification bits is n;
the bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
if the read address is read for the first time, determining the address of the selected bit line and the address of the selected word line according to a first address, wherein the first address is a read address sent from the outside of the chip, and according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit and the state of the distinguishing subarray identification bit in the bit line address identification bit, comparing the 2 bit line address with the selected word line address, the address of the selected word line, the state of the bitnSimultaneously reading the memory cells in the sub-arrays;
if the data is not read for the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data;
n is an integer greater than or equal to 1, the
Is an integer greater than or equal to 1, and m is greater than or equal to x.
Optionally, when n is 1, the NOR-type memory array is divided into 2 sub-arrays, which are a first sub-array and a second sub-array respectively;
the number of the distinguishing subarray identification bits is 1.
Optionally, if the first reading is performed, the address of the selected bit line and the address of the selected word line are determined according to a first address, where the first address is a read address sent from the outside of the chip, and the first address is determined according to the selected bit lineThe address of the selected word line, the state of the bit line address identification bit and the state of the distinguishing sub-array identification bit in the bit line address identification bit, to the 2nThe step of simultaneously reading the memory cells in the sub-array specifically comprises:
if the addresses of the selected bit lines contained from the highest bit line address identification bit to the distinguishing sub-array identification bit in the initial address are all 1 in the initial address, performing reading operation on the address of the selected word line in the second sub-array and the memory cell corresponding to the address of the selected bit line, and simultaneously reading the memory cell in the first sub-array, wherein the word line corresponding to the memory cell in the first sub-array is the word line corresponding to the address of the selected word line in the second sub-array plus one; and the bit lines corresponding to the storage units in the first sub-array are bit lines with addresses from the highest bit line address identification bit in the bit line address identification bits to bit lines contained in the distinguishing sub-array identification bits being all 0.
Optionally, if the read is performed for the first time, the address of the selected bit line from the most significant bit line address identification bit to the distinguishing sub-array identification bit in the first address includes 0, and the distinguishing sub-array identification bit is 1,
reading the memory cells in the second sub-array, wherein the word line corresponding to the memory cells read in the second sub-array is the word line corresponding to the first address, and the bit line is the bit line corresponding to the first address; simultaneously reading the memory cells in the first sub-array, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the first address, the bit line corresponding to the memory cell in the first sub-array is the bit line corresponding to the address of the highest bit line address identification bit in the first address bit line address identification bit to the address contained in the distinguishing sub-array identification bit plus one, if the addresses of the selected bit line contained in the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line corresponding to the memory cell in the second sub-array are all 1, the word line corresponding to the memory cell in the first sub-array is the corresponding word line after adding one to the word line address corresponding to the memory cell in the second sub-array, otherwise, the word lines corresponding to the memory cells in the first sub-array are the word lines corresponding to the memory cells in the second sub-array;
reading the memory cells in the first sub-array from the highest bit line address identification bit to the address of the selected bit line contained in the distinguishing sub-array identification bit, wherein the address of the selected bit line contains 0, and the distinguishing sub-array identification bit is 0, the memory cells in the first sub-array are read, the word line for reading the memory cells in the first sub-array is the word line corresponding to the head address, and the bit line for reading the memory cells in the first sub-array is the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the bit line address from the highest bit line address identification bit in the head address to the distinguishing sub-array identification bit plus one corresponding bit line address, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
Optionally, if the reading is not the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and performing the reading operation on the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data specifically includes:
if the addresses from the highest bit line address identification bit to the bit line contained in the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data all are 1, and the bit line corresponding to the memory cell of the next sub-array is the address from the highest bit line address identification bit to the bit line contained in the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data plus one, the word line corresponding to the memory cell of the next sub-array is the word line corresponding to the memory cell corresponding to the current output data plus one, otherwise, the word line corresponding to the memory cell of the next sub-array is the word line corresponding to the memory cell corresponding to the current output data A word line of (a);
the bit line address of the memory cell corresponding to the current output data includes 0 from the most significant bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the bit line address included from the most significant bit line address identification bit to the distinguishing sub-array identification bit in the bit line of the memory cell corresponding to the current output data is plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
In a second aspect, an embodiment of the present invention provides an apparatus for increasing a reading speed of a NOR-type memory array, including:
a partitioning module to partition the NOR-type memory array into 2nA sub-array;
a bit line address identification bit determining module, connected to the dividing module, for determining bit line address identification bits corresponding to the bit lines according to the number m of the bit lines of the NOR-type memory array, where the number of the bit line address identification bits is
And are numbered in sequence;
a selected bit line address identification bit determining module, connected to the bit line address identification bit determining module, for determining bit line address identification bits corresponding to selected bit lines according to the number x of the selected bit lines in each sub-array, where the number of the selected bit line address identification bits is
A sub-array identification bit distinguishing module connected with the selected bit line address identification bit determining module and used for selecting sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the sub-array identification bits is n;
the bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
the reading module comprises a first-time reading unit and a non-first-time reading unit, and is respectively connected with the bit line address identification bit determining module, the selected bit line address identification bit determining module and the distinguishing sub-array identification bit module;
the first reading unit is used for determining the address of the selected bit line and the address of the selected word line according to a first address if the first reading unit is used for reading for the first time, wherein the first address is a reading address sent from the outside of a chip, and the 2 pairs of the two sub-array identification bits are distinguished according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bits and the state of the distinguishing sub-array identification bits in the bit line address identification bitsnSimultaneously reading the memory cells in the sub-arrays;
the non-first-time reading unit is used for outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line if the reading is not the first-time reading, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data;
n is an integer greater than or equal to 1, the
Is an integer greater than or equal to 1, and m is greater than or equal to x.
Optionally, when n is 1, the NOR-type memory array is divided into 2 sub-arrays, which are a first sub-array and a second sub-array respectively;
the number of the distinguishing subarray identification bits is 1.
Optionally, the first reading unit is specifically configured to, if the first reading is performed, if all the addresses of the selected bit lines included in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit are 1, perform a reading operation on the address of the selected word line in the second sub-array and the memory cell corresponding to the address of the selected bit line, and read the memory cell in the first sub-array at the same time, where the word line corresponding to the memory cell in the first sub-array is a word line corresponding to an address of the selected word line in the second sub-array plus one; and the bit lines corresponding to the storage units in the first sub-array are bit lines with addresses from the highest bit line address identification bit in the bit line address identification bits to bit lines contained in the distinguishing sub-array identification bits being all 0.
Optionally, the first reading unit is further specifically configured to, if the first reading is performed, an address of the selected bit line included from the most significant bit line address identification bit to the distinguishing subarray identification bit in the first address includes 0, and the distinguishing subarray identification bit includes 1,
reading the memory cells in the second sub-array, wherein the word line corresponding to the memory cells read in the second sub-array is the word line corresponding to the first address, and the bit line is the bit line corresponding to the first address; simultaneously reading the memory cells in the first sub-array, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the first address, the bit line corresponding to the memory cell in the first sub-array is the bit line corresponding to the address of the highest bit line address identification bit in the first address bit line address identification bit to the address contained in the distinguishing sub-array identification bit plus one, if the addresses of the selected bit line contained in the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line corresponding to the memory cell in the second sub-array are all 1, the word line corresponding to the memory cell in the first sub-array is the corresponding word line after adding one to the word line address corresponding to the memory cell in the second sub-array, otherwise, the word lines corresponding to the memory cells in the first sub-array are the word lines corresponding to the memory cells in the second sub-array;
reading the memory cells in the first sub-array from the highest bit line address identification bit to the address of the selected bit line contained in the distinguishing sub-array identification bit, wherein the address of the selected bit line contains 0, and the distinguishing sub-array identification bit is 0, the memory cells in the first sub-array are read, the word line for reading the memory cells in the first sub-array is the word line corresponding to the head address, and the bit line for reading the memory cells in the first sub-array is the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the bit line address from the highest bit line address identification bit in the head address to the distinguishing sub-array identification bit plus one corresponding bit line address, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
Optionally, the non-primary reading unit is specifically configured to add a word line corresponding to the next sub-array to a word line corresponding to a memory cell corresponding to the current output data after adding one to the word line corresponding to the memory cell corresponding to the current output data, if the bit line address included from the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data is all 1, and the bit line corresponding to the next sub-array is the bit line address included from the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data, otherwise, the word line corresponding to the storage unit of the next sub-array is the word line corresponding to the storage unit corresponding to the current output data;
the bit line address of the memory cell corresponding to the current output data includes 0 from the most significant bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the bit line address included from the most significant bit line address identification bit to the distinguishing sub-array identification bit in the bit line of the memory cell corresponding to the current output data is plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
The embodiment of the invention provides a method and a device for improving the reading speed of a NOR-type memory array, which read data of a plurality of memory cells each time by dividing the NOR-type memory array into a plurality of sub-arrays so as to shorten the sum of the time for reading the selected number of memory cells and outputting all the data of the memory cells.
Drawings
FIG. 1 is a flow chart illustrating a method for increasing the read speed of a NOR-type memory array according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for increasing the read speed of a NOR-type memory array according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an apparatus for increasing the reading speed of a NOR-type memory array according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic flowchart of a method for increasing the reading speed of a NOR-type memory array according to an embodiment of the present invention, which may be implemented by a method apparatus for increasing the reading speed of a NOR-type memory array, wherein the apparatus may be implemented by hardware and/or software, and referring to fig. 1, the method includes the following steps:
step 101, divide NOR memory array into 2nAnd (4) sub-arrays. n is an integer greater than or equal to 1.
Step 102, determining a bit line pair according to the number m of bit lines of the NOR type memory arrayThe number of the corresponding bit line address identification bits is
And are numbered sequentially.
103, according to the number x of the selected bit lines in each sub-array, determining bit line address identification bits corresponding to the selected bit lines, wherein the number of the selected bit line address identification bits is
It should be noted that, in the present embodiment, each bit line address identification bit corresponds to 1Byte (Byte) data, i.e. 8bit lines, according to the total number m of bit lines, so the number of bit line address identification bits is equal to
Each time each sub-array can select x bit lines, wherein x is the number of reading circuits of the memory cell, and the number of bit line address flag bits corresponding to the selected bit lines is
The bit line address identification bit is selected to be the lower address of the bit line address identification bit
In this embodiment, the addresses of the bit lines are typically binary coded.
And 104, selecting distinguishing sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the distinguishing sub-array identification bits is n.
The bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
in this embodiment, the sub-array identification bits are generally distinguished as being in the address identification bits
And 105, judging whether the reading is carried out for the first time.
In this embodiment, if the memory cell read command for the selected bit line and the selected word line occurs for the first time, it is the first read.
Step 106, if the first reading is carried out, determining the address of the selected bit line and the address of the selected word line according to the first address, wherein the first address is the read address sent from the outside of the chip, and the pair 2 is compared according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit and the state of the molecular array identification bit in the bit line address identification bitnThe memory cells in the sub-arrays are read simultaneously.
And 107, if the reading is not the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data.
N is an integer greater than or equal to 1, the
Is an integer greater than or equal to 1, and m is greater than or equal to x.
The embodiment of the invention provides a method for improving the reading speed of a NOR type memory array, which is characterized in that the NOR type memory array is divided into a plurality of sub-arrays, the data of a plurality of memory cells are read each time, so that the sum of the time for reading the selected number of memory cells and outputting all the data of the memory cells is shortened.
Example two
On the basis of the embodiment, the technical scheme of the embodiment of the invention further limits the number of n, and when n is 1, the NOR type memory array is divided into 2 sub-arrays which are respectively a first sub-array and a second sub-array; the number of distinguishing sub-array identification bits is 1. Referring to fig. 2, the method comprises the steps of:
step 201, divide the NOR memory array into 2 sub-arrays.
Step 202, according to the number m of the bit lines of the NOR-type memory array, determining the bit line address identification bits corresponding to the bit lines, wherein the number of the bit line address identification bits is
And are numbered sequentially.
Step 203, according to the number x of the selected bit lines in each sub-array, determining the bit line address identification bits corresponding to the selected bit lines, wherein the number of the selected bit line address identification bits is
And 204, selecting distinguishing sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the distinguishing sub-array identification bits is 1.
Step 205, determine whether to read for the first time.
If the first reading is carried out, the address of the selected bit line contained in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit contains 0, and the distinguishing sub-array identification bit is 1, the storage unit in the second sub-array is read, the word line corresponding to the storage unit read in the second sub-array is the word line corresponding to the first address, and the bit line is the bit line corresponding to the first address; reading the memory cells in the first sub-array at the same time, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the head address, the bit line corresponding to the memory cells in the first sub-array is the bit line corresponding to the address contained from the highest bit line address identification bit in the head address bit line address identification bit to the distinguishing sub-array identification bit plus one, if the address contained from the highest bit line address identification bit in the bit line corresponding to the memory cells in the second sub-array to the selected bit line contained in the distinguishing sub-array identification bit is all 1, the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address corresponding to the memory cells in the second sub-array plus one, otherwise, the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the memory cells in the second;
the address of the selected bit line from the highest bit line address identification bit to the distinguishing sub-array identification bit in the head address contains 0, and the distinguishing sub-array identification bit is 0, then the memory unit in the first sub-array is read, the word line of the memory unit in the first sub-array is read as the word line corresponding to the head address, and the bit line of the memory unit in the first sub-array is read as the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the highest bit line address identification bit in the head address to distinguish the bit line address contained in the sub-array identification bit as the bit line address plus one, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
And step 207, if the reading is not the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data.
In the NOR-type memory array reading speed method provided by the embodiment of the invention, on the basis of the above embodiment, the number of n is further limited, taking the case that n is 1 as an example, the memory cells in the first subarray and the second subarray are further read according to the address of the selected bit line and the distinguishing subarray identification bit contained in the first address from the highest bit line address identification bit to the distinguishing subarray identification bit, and the data of a plurality of memory cells are read each time, so as to shorten the sum of the time for reading the selected number of memory cells and outputting all the data of the memory cells.
When n is not 1, the number of the discrimination sub-array identification bits is n, and different sub-arrays are discriminated by using the states of the n discrimination sub-array identification bits.
Optionally, in step 207, if the reading is not the first time, outputting data corresponding to the address of the currently selected word line and the memory cell corresponding to the address of the currently selected bit line according to the bit line address and the word line address of the memory cell corresponding to the currently output data, and performing the reading operation on the memory cell of the next sub-array specifically includes:
the bit line address from the most significant bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit of the memory cell corresponding to the currently output data includes 0, and distinguishes sub array identification bit 1, if the address from the most significant bit line address identification bit to the bit line contained in distinguishing sub array identification bit in the bit line of the memory cell corresponding to the current output data is all 1, the bit line corresponding to the memory cell of the next sub array is the sum of the most significant bit line address identification bit in the bit line address of the memory cell corresponding to the current output data and the bit line address contained in distinguishing sub array identification bit and a corresponding bit line address, if the word line corresponding to the storage unit in the next sub-array is the word line corresponding to the word line address corresponding to the storage unit corresponding to the current output data plus one, otherwise, the word line corresponding to the storage unit of the next sub-array is the word line corresponding to the storage unit corresponding to the current output data;
the bit line address of the memory cell corresponding to the current output data contains 0 from the most significant bit line address identification bit to the bit line address contained in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the most significant bit line address identification bit in the bit line of the memory cell corresponding to the current output data to the bit line address contained in the distinguishing sub-array identification bit plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
On the basis of the above technical solution, it is further limited that, when the data is not read for the first time, the reading operation is performed on the memory cell of the next sub-array through the bit line address included from the most significant bit line address identification bit to the distinguishing sub-array identification bit and the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the currently output data, so that the data of a plurality of memory cells is read each time, thereby shortening the total time of reading the selected number of memory cells and outputting all the data of the memory cells.
For example, assume that the bit line address bits are A <2:0> and each address bit corresponds to 1Byte data, so each address corresponds to 8bit lines, 64 bit lines are corresponding to A <2:0>, bit lines are defined as BL <1> to BL <8> according to the address sequence, and each BL corresponds to 8bit line addresses, as shown in Table 1.
The most significant bit line address identification bit is A <2 >. A <1> is selected as the distinguishing address identification bit, A <1> bisects bit lines BL <1> to BL <8> into the left side and the right side, when A <1> is 0, the bit lines BL <1>, BL <2>, BL <5> and BL <6> corresponding to the bit lines on the left side are used, A <1> is 1, the bit lines on the right side correspond to the bit lines BL <3>, BL <4>, BL <7> and BL <8>, and each BL corresponds to 8bit lines. The left side and the right side are respectively provided with 16 reading circuits, and each reading circuit selects one bit line for reading at a time.
At the time of first reading: if the first address A <2: when 1> is 00, the left side and the right side read BL <1>, BL <2>, BL <3> and BL <4> at the same time;
if the first address A <2: 1> is 01, then BL <3>, BL <4>, BL <5> and BL <6> are read at the same time from the left and right sides;
if the first address A <2: 1> is 10, then BL <5>, BL <6>, BL <7>, BL <8> are read simultaneously from left and right;
if the first address A <2: and 1 is equal to 11, then BL <7>, BL <8> and BL <0>, BL <1> corresponding to the next word line address are read simultaneously.
When reading for the first time, because the first reading reads the left and right sides simultaneously, the bit line address not read for the first time is only necessary to have the following four conditions: a <2:0> -000, A <2:0> 010, A <2:0> -100 and A <2:0> -110.
Current address a <2: when 0> is 000, the current output data is BL <1>, BL <2>, and when BL <1>, BL <2> are output, the lower line address A <2> of the same word line is read: BL <3> and BL <4> corresponding to 1> -01;
if the current address A <2: if 0> is 010, then the current output data is BL <3>, BL <4>, and when BL <3>, BL <4> are output, the lower line address A <2: BL <5>, BL <6> corresponding to 1> -10;
if the current address A <2: when 0> is 100, the current output data is BL <5>, BL <6>, and when BL <5>, BL <6> are output, the lower line address A <2> of the same word line is read: BL <7>, BL <8> corresponding to 1> -11;
if the current address A <2: if 0> is 110, then the current output data is BL <7>, BL <8>, and when BL <7>, BL <8> are output, the following information is read simultaneously: and (3) adding one to the current word line address by the selected word line, namely cutting the next word line according to the word line arrangement sequence, wherein the bit line address is A <2: when 1> is 00, BL <1> and BL <2> corresponding to the next word line are read.
TABLE 1 bit line Address and bit line mapping Table
| Bit line address A<2：0> | Corresponding bit line (bit line) |
| A<2:0>＝000 | BL<1> |
| A<2:0>＝001 | BL<2> |
| A<2:0>＝010 | BL<3> |
| A<2:0>＝011 | BL<4> |
| A<2:0>＝100 | BL<5> |
| A<2:0>＝101 | BL<6> |
| A<2:0>＝110 | BL<7> |
| A<2:0>＝111 | BL<8> |
It should be noted that, in the prior art, when reading a NOR-type memory array, the following approaches are generally taken: assuming that the chip has x reading circuits, x is an integral power of 2, each reading circuit is connected with a bit line, data of x storage units are read out in each reading operation, the data are output from the storage unit corresponding to a first address and the data are output according to the sequence that the addresses are continuously added by 1, wherein the first address is an address sent from the outside of the chip, and the output data corresponding to each address is 8 bits; because the data output is output according to the address sequence and the middle can not be interrupted, the data of the next group of x storage units according to the sequence of adding 1 to the address is required to be prepared before the last 8-bit data of the x storage units read at this time is output; if the head address corresponds to the last group of 8-bit data of the group of data, the data of the next group of x storage units needs to be read when the last group of 8-bit data is output, and the clock number used for outputting the 8-bit data is fixed, the clock number used for reading once by the reading circuit is determined by the clock number output by the 8-bit data.
If the traditional scheme is used for unilateral reading, the second reading is started immediately after the first reading is finished, and under the condition that the number of dummy clocks (dummy) inserted between four-port address input and data output is less, the read enabling time can only be less than 4 clock cycles to meet the requirement that the second reading is not influenced, but the reading operation of the invention is realized by simultaneously reading the first reading at the left and the right, wherein A is less than x: all the corresponding memory arrays with the reading time of 0> are already read into latches (latch), the first time reading interval and the second time reading interval are longer, the reading enabling time can be 6 clock cycles, and the reading time of the memory arrays is limited by the charging and discharging of word lines or bit lines, the circuit delay, the identification speed of a Sensitive Amplifier (SA) and the like, so that the reading clock frequency of the invention is about 1.5 times of the conventional reading clock frequency, the reading frequency is greatly improved, and the reading speed is effectively improved.
EXAMPLE III
On the basis of the above embodiments, an embodiment of the present invention provides an apparatus for increasing the reading speed of a NOR-type memory array, and referring to fig. 3, the apparatus includes:
a partitioning module 310 for partitioning a NOR type memory array into 2nA sub-array;
a bit line address identification bit determining module 320, a bit line address identification bit determining module 420 connected to the dividing module 310 for determining the bit line address identification bits corresponding to the bit lines according to the number m of the bit lines of the NOR-type memory array, the number of the bit line address identification bits being
And are numbered in sequence;
a selected bit line address identification bit determining module 330, wherein the selected bit line address identification bit determining module 330 is connected to the bit line address identification bit determining module 320, and is configured to determine bit line address identification bits corresponding to selected bit lines according to the number x of the selected bit lines in each sub-array, where the number of the selected bit line address identification bits is
A sub-array identification bit distinguishing module 340, wherein the sub-array identification bit distinguishing module 340 is connected with the selected bit line address identification bit determining module 330, and is used for selecting sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, and the number of the sub-array identification bits is n; the bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
the reading module 350 includes a first reading unit 3501 and a non-first reading unit 3502, and the reading module is respectively connected to the bit line address identification bit determining module 320, the selected bit line address identification bit determining module 330 and the sub-array distinguishing identification bit module 340;
the first reading unit 3501 is configured to, if the first reading is performed, determine an address of the selected bit line and an address of the selected word line according to the first address, where the first address is a read address sent from the outside of the chip, and perform a simultaneous reading operation on the memory cells in the 2^ n sub-arrays according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit, and the state of the sub-array identification bit in the bit line address identification bit;
the non-primary reading unit 3502 is configured to, if not performing primary reading, output data corresponding to a memory cell corresponding to an address of a currently selected word line and an address of a currently selected bit line, and perform a reading operation on a memory cell of a next sub-array according to a bit line address and a word line address of a memory cell corresponding to currently output data;
n is an integer greater than or equal to 1,
is an integer greater than or equal to 1, and m is greater than or equal to x.
The embodiment of the invention provides a device for improving the reading speed of a NOR type memory array, which reads data of a plurality of memory cells each time by a method of dividing the NOR type memory array into a plurality of sub-arrays so as to shorten the sum of time for reading a selected number of memory cells and outputting all the data of the memory cells.
Optionally, on the basis of the above technical solution, when n is 1, the NOR-type memory array is divided into 2 sub-arrays, which are respectively a first sub-array and a second sub-array; the number of distinguishing sub-array identification bits is 1.
Optionally, on the basis of the foregoing technical solution, the first reading unit 3501 is specifically configured to, if the first reading is performed, if the addresses of the selected bit lines included in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit are all 1, perform a reading operation on the address of the word line in the second sub-array and the memory cell corresponding to the address of the selected bit line, and read the memory cell in the first sub-array at the same time, where the word line corresponding to the memory cell in the first sub-array is the word line corresponding to the address of the selected word line in the second sub-array plus one; the bit lines corresponding to the memory cells in the first sub-array are bit lines with addresses from the most significant bit line address identification bit in the bit line address identification bits to the bit lines included in the distinguishing sub-array identification bits being all 0.
Optionally, on the basis of the foregoing technical solution, the first reading unit 3501 is further specifically configured to, if the first reading is performed, the address of the selected bit line included in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit includes 0, and the distinguishing sub-array identification bit 1 distinguishes that the storage unit in the second sub-array is read, the word line corresponding to the storage unit read in the second sub-array is the word line corresponding to the first address, and the bit line is the bit line corresponding to the first address; reading the memory cells in the first sub-array at the same time, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the head address, the bit line corresponding to the memory cells in the first sub-array is the bit line corresponding to the address contained from the highest bit line address identification bit in the head address bit line address identification bit to the distinguishing sub-array identification bit plus one, if the address contained from the highest bit line address identification bit in the bit line corresponding to the memory cells in the second sub-array to the selected bit line contained in the distinguishing sub-array identification bit is all 1, the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address corresponding to the memory cells in the second sub-array plus one, otherwise, the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the memory cells in the second;
the address of the selected bit line from the highest bit line address identification bit to the distinguishing sub-array identification bit in the head address contains 0, and the distinguishing sub-array identification bit is 0, then the memory unit in the first sub-array is read, the word line of the memory unit in the first sub-array is read as the word line corresponding to the head address, and the bit line of the memory unit in the first sub-array is read as the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the highest bit line address identification bit in the head address to distinguish the bit line address contained in the sub-array identification bit as the bit line address plus one, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
Optionally, on the basis of the above technical solution, the non-primary reading unit 3502 is specifically configured to use that, in bit line addresses of a storage unit corresponding to current output data, bit line addresses included from a highest bit line address identification bit to a distinguishing sub-array identification bit include 0, and the distinguishing sub-array identification bit 1, if addresses of bit lines included from the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line of the storage unit corresponding to the current output data are all 1, a bit line corresponding to a storage unit of a next sub-array is a bit line address corresponding to a sum of one bit line address included from the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line address of the storage unit corresponding to the current output data, a word line corresponding to the storage unit in the next sub-array is a word line corresponding to a sum of one bit line address corresponding to the storage unit corresponding to the current output data, otherwise, the word line corresponding to the storage unit of the next sub-array is the word line corresponding to the storage unit corresponding to the current output data;
the bit line address of the memory cell corresponding to the current output data contains 0 from the most significant bit line address identification bit to the bit line address contained in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the most significant bit line address identification bit in the bit line of the memory cell corresponding to the current output data to the bit line address contained in the distinguishing sub-array identification bit plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
The device for improving the reading speed of the NOR-type memory array provided in the above embodiments can execute the method for improving the reading speed of the NOR-type memory array provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method. The technical details not described in detail in the above embodiments can be referred to a method for increasing the reading speed of the NOR-type memory array according to any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for increasing the read speed of a NOR-type memory array, comprising:
partitioning the NOR-type memory array into 2nA sub-array;
according to the number m of bit lines of the NOR type memory array,determining bit line address identification bits corresponding to the bit lines, wherein the number of the bit line address identification bits is
And are numbered in sequence;
according to the number x of selected bit lines in each sub-array, determining bit line address identification bits corresponding to the selected bit lines, wherein the number of the selected bit line address identification bits is
Selecting distinguishing sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the distinguishing sub-array identification bits is n;
the bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
if the read address is read for the first time, determining the address of the selected bit line and the address of the selected word line according to a first address, wherein the first address is a read address sent from the outside of the chip, and according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit and the state of the distinguishing subarray identification bit in the bit line address identification bit, comparing the 2 bit line address with the selected word line address, the address of the selected word line, the state of the bitnSimultaneously reading the memory cells in the sub-arrays;
if the data is not read for the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data;
n is an integer greater than or equal to 1, the
Is an integer greater than or equal to 1, and m is greater than or equal to x.
2. The method of claim 1,
when n is 1, dividing the NOR type memory array into 2 sub-arrays which are respectively a first sub-array and a second sub-array;
the number of the distinguishing subarray identification bits is 1.
3. The method of claim 2,
if the read is carried out for the first time, the address of the selected bit line and the address of the selected word line are determined according to the initial address, the initial address is the read address sent from the outside of the chip, and the 2 pairs of the two-dimensional array are read according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bit and the state of the distinguishing sub-array identification bit in the bit line address identification bitnThe step of simultaneously reading the memory cells in the sub-array specifically comprises:
if the addresses of the selected bit lines contained from the highest bit line address identification bit to the distinguishing sub-array identification bit in the initial address are all 1 in the initial address, performing reading operation on the address of the selected word line in the second sub-array and the memory cell corresponding to the address of the selected bit line, and simultaneously reading the memory cell in the first sub-array, wherein the word line corresponding to the memory cell in the first sub-array is the word line corresponding to the address of the selected word line in the second sub-array plus one; and the bit lines corresponding to the storage units in the first sub-array are bit lines with addresses from the highest bit line address identification bit in the bit line address identification bits to bit lines contained in the distinguishing sub-array identification bits being all 0.
4. The method of claim 3,
if the read is performed for the first time, the address of the selected bit line from the highest bit line address identification bit to the distinguishing sub-array identification bit in the first address contains 0, and the distinguishing sub-array identification bit 1,
reading the memory cells in the second sub-array, wherein the word line corresponding to the memory cells read in the second sub-array is the word line corresponding to the first address, and the bit line is the bit line corresponding to the first address; simultaneously reading the memory cells in the first sub-array, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the first address, the bit line corresponding to the memory cell in the first sub-array is the bit line corresponding to the address of the highest bit line address identification bit in the first address bit line address identification bit to the address contained in the distinguishing sub-array identification bit plus one, if the addresses of the selected bit line contained in the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line corresponding to the memory cell in the second sub-array are all 1, the word line corresponding to the memory cell in the first sub-array is the corresponding word line after adding one to the word line address corresponding to the memory cell in the second sub-array, otherwise, the word lines corresponding to the memory cells in the first sub-array are the word lines corresponding to the memory cells in the second sub-array;
reading the memory cells in the first sub-array from the highest bit line address identification bit to the address of the selected bit line contained in the distinguishing sub-array identification bit, wherein the address of the selected bit line contains 0, and the distinguishing sub-array identification bit is 0, the memory cells in the first sub-array are read, the word line for reading the memory cells in the first sub-array is the word line corresponding to the head address, and the bit line for reading the memory cells in the first sub-array is the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the bit line address from the highest bit line address identification bit in the head address to the distinguishing sub-array identification bit plus one corresponding bit line address, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
5. The method of claim 2,
if the reading is not the first time, outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line, and performing the reading operation on the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data specifically comprises the following steps:
if the addresses from the highest bit line address identification bit to the bit line contained in the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data all are 1, and the bit line corresponding to the memory cell of the next sub-array is the address from the highest bit line address identification bit to the bit line contained in the distinguishing sub-array identification bit in the bit line address of the memory cell corresponding to the current output data plus one, the word line corresponding to the memory cell of the next sub-array is the word line corresponding to the memory cell corresponding to the current output data plus one, otherwise, the word line corresponding to the memory cell of the next sub-array is the word line corresponding to the memory cell corresponding to the current output data A word line of (a);
the bit line address of the memory cell corresponding to the current output data includes 0 from the most significant bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the bit line address included from the most significant bit line address identification bit to the distinguishing sub-array identification bit in the bit line of the memory cell corresponding to the current output data is plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
6. An apparatus for increasing the read speed of a NOR-type memory array, comprising:
a partitioning module to partition the NOR-type memory array into 2nA sub-array;
bit line address identification bit determination module, bit line address identification bit determination module and bit line address identification bit determination deviceThe dividing module is connected with the NOR type memory array and is used for determining bit line address identification bits corresponding to the bit lines according to the number m of the bit lines of the NOR type memory array, and the number of the bit line address identification bits is
And are numbered in sequence;
a selected bit line address identification bit determining module, connected to the bit line address identification bit determining module, for determining bit line address identification bits corresponding to selected bit lines according to the number x of the selected bit lines in each sub-array, where the number of the selected bit line address identification bits is
A sub-array identification bit distinguishing module connected with the selected bit line address identification bit determining module and used for selecting sub-array identification bits from the bit line address identification bits according to the address of the selected bit line, wherein the number of the sub-array identification bits is n;
the bit line address identification bit comprises the distinguishing subarray identification bit and the selected bit line address identification bit;
the reading module comprises a first-time reading unit and a non-first-time reading unit, and is respectively connected with the bit line address identification bit determining module, the selected bit line address identification bit determining module and the distinguishing sub-array identification bit module;
the first reading unit is used for determining the address of the selected bit line and the address of the selected word line according to a first address if the first reading unit is used for reading for the first time, wherein the first address is a reading address sent from the outside of a chip, and the 2 pairs of the two sub-array identification bits are distinguished according to the address of the selected bit line, the address of the selected word line, the state of the bit line address identification bits and the state of the distinguishing sub-array identification bits in the bit line address identification bitsnSimultaneously reading the memory cells in the sub-arrays;
the non-first-time reading unit is used for outputting data corresponding to the memory cell corresponding to the address of the currently selected word line and the address of the currently selected bit line if the reading is not the first-time reading, and reading the memory cell of the next sub-array according to the bit line address and the word line address of the memory cell corresponding to the currently output data;
n is an integer greater than or equal to 1, the
Is an integer greater than or equal to 1, and m is greater than or equal to x.
7. The apparatus of claim 6,
when n is 1, dividing the NOR type memory array into 2 sub-arrays which are respectively a first sub-array and a second sub-array;
the number of the distinguishing subarray identification bits is 1.
8. The apparatus of claim 7,
the first reading unit is specifically configured to, if the first reading is performed, if all the addresses of the selected bit lines included in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit are 1, perform a reading operation on the address of the selected word line in the second sub-array and the memory cell corresponding to the address of the selected bit line, and read the memory cell in the first sub-array at the same time, where the word line corresponding to the memory cell in the first sub-array is a word line corresponding to an address of the selected word line in the second sub-array plus one; and the bit lines corresponding to the storage units in the first sub-array are bit lines with addresses from the highest bit line address identification bit in the bit line address identification bits to bit lines contained in the distinguishing sub-array identification bits being all 0.
9. The apparatus of claim 7,
the first reading unit is further specifically configured to, if the first reading is performed, the address of the selected bit line included in the first address from the highest bit line address identification bit to the distinguishing sub-array identification bit includes 0, and the distinguishing sub-array identification bit 1 reads the memory cell in the second sub-array, where the word line corresponding to the memory cell read in the second sub-array is a word line corresponding to the first address, and the bit line is a bit line corresponding to the first address; simultaneously reading the memory cells in the first sub-array, wherein the word line corresponding to the memory cells in the first sub-array is the word line corresponding to the word line address in the first address, the bit line corresponding to the memory cell in the first sub-array is the bit line corresponding to the address of the highest bit line address identification bit in the first address bit line address identification bit to the address contained in the distinguishing sub-array identification bit plus one, if the addresses of the selected bit line contained in the highest bit line address identification bit to the distinguishing sub-array identification bit in the bit line corresponding to the memory cell in the second sub-array are all 1, the word line corresponding to the memory cell in the first sub-array is the corresponding word line after adding one to the word line address corresponding to the memory cell in the second sub-array, otherwise, the word lines corresponding to the memory cells in the first sub-array are the word lines corresponding to the memory cells in the second sub-array;
reading the memory cells in the first sub-array from the highest bit line address identification bit to the address of the selected bit line contained in the distinguishing sub-array identification bit, wherein the address of the selected bit line contains 0, and the distinguishing sub-array identification bit is 0, the memory cells in the first sub-array are read, the word line for reading the memory cells in the first sub-array is the word line corresponding to the head address, and the bit line for reading the memory cells in the first sub-array is the bit line corresponding to the head address; and simultaneously reading the bit line corresponding to the memory cell in the first sub-array of the memory cells in the second sub-array as the bit line address from the highest bit line address identification bit in the head address to the distinguishing sub-array identification bit plus one corresponding bit line address, wherein the word line corresponding to the memory cell in the second sub-array is the word line corresponding to the memory cell in the first sub-array.
10. The apparatus of claim 7,
the non-primary reading unit is specifically configured to use that, in the bit line addresses of the storage unit corresponding to the current output data, the bit line addresses from the highest bit line address identification bit to the distinguishing sub-array identification bit include 0, and the distinguishing sub-array identification bit is 1, if the addresses from the highest bit line address identification bit to the bit line included in the distinguishing sub-array identification bit in the bit line of the storage unit corresponding to the current output data are all 1, the bit line corresponding to the storage unit of the next sub-array is a bit line address corresponding to the sum of one from the highest bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit in the bit line address of the storage unit corresponding to the current output data, and then the word line corresponding to the storage unit in the next sub-array is a word line corresponding to the word line address corresponding to the storage unit corresponding to the current output data after the sum of one, otherwise, the word line corresponding to the storage unit of the next sub-array is the word line corresponding to the storage unit corresponding to the current output data;
the bit line address of the memory cell corresponding to the current output data includes 0 from the most significant bit line address identification bit to the bit line address included in the distinguishing sub-array identification bit, and the distinguishing sub-array identification bit is 0, the bit line corresponding to the memory cell in the next sub-array is the bit line address included from the most significant bit line address identification bit to the distinguishing sub-array identification bit in the bit line of the memory cell corresponding to the current output data is plus one corresponding bit line address, and the word line corresponding to the memory cell in the next sub-array is the bit line address of the memory cell corresponding to the current output data.
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |