CN106960686A - Reading method and flash memory device - Google Patents
Reading method and flash memory device Download PDFInfo
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- CN106960686A CN106960686A CN201710208361.9A CN201710208361A CN106960686A CN 106960686 A CN106960686 A CN 106960686A CN 201710208361 A CN201710208361 A CN 201710208361A CN 106960686 A CN106960686 A CN 106960686A
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- 238000003860 storage Methods 0.000 claims description 9
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The invention discloses a reading method and a flash memory device, wherein the reading method is applied to the flash memory device, the flash memory device comprises a nonvolatile semiconductor memory cell array, and the reading method comprises the following steps: judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation. According to the technical scheme provided by the invention, the flash memory device can be read through two induction operations, so that the noise of the common source line is reduced, and the high accuracy of the reading operation is ensured.
Description
Technical field
The present invention relates to memory technology field, more specifically, it is related to a kind of read method and flash memories dress
Put.
Background technology
NAND-type flash memory, due to the high characteristic of its integrated level, has become Large Copacity as a kind of nonvolatile memory
The important key components of storage arrangement.But because NAND-type flash memory memory, it constitutes non-volatile memory cells
The earth terminal of all memory cell of array is finally all connected together by common source line, so with the expansion of memory cell array
Greatly, when being read using full bit line read method, the influence of noise of common source line is just increasing, or even causes to read behaviour
Make mistake, thus, when being read, reduction common source line noise just becomes particularly important.
The content of the invention
In view of this, the invention provides a kind of read method and flash memory devices, first to whole memory cell
First time inductive operation is carried out, then to being determined as that the memory cell of OFF state carries out second of inductive operation, by sensing twice
Operation is read out to flash memory devices, to reduce the noise of common source line, it is ensured that the accuracy rate of read operation is high.
To achieve the above object, the technical scheme that the present invention is provided is as follows：
A kind of read method, applied to flash memory devices, the flash memory devices are partly led including non-volatile
Body memory cell array, including：
Judge whether to read whole memory cell of the non-volatile semiconductor memory cell array, if so, then to institute
State whole memory cell respective words and apply voltage, to carry out first time inductive operation；
Second of inductive operation is carried out to the memory cell for after the first time inductive operation, being determined as OFF state, wherein,
The difference of the voltage applied when the voltage applied in the first time inductive operation in wordline and second of inductive operation in wordline
It is worth within a preset range, and, second of inductive operation correspondence sensitive time is felt not less than first time inductive operation correspondence
Between seasonable.
Optionally, when the voltage applied in the first time inductive operation in wordline and second of inductive operation in wordline
The voltage of application is identical；
And, the first time inductive operation correspondence sensitive time is less than second of inductive operation correspondence sensitive time.Can
Choosing, judging that it is not whole memory cell to read the non-volatile semiconductor memory cell array, and be judged as reading
When taking the memory cell of predetermined number, then voltage is applied to the memory cell respective word, and the predetermined number is deposited
Storage unit carries out the operation of predetermined inductive, wherein, the voltage that applies when the predetermined inductive operate in wordline and described the
The voltage applied when inductive operation is with second of inductive operation in wordline is identical, and predetermined inductive operation correspondence sensing
Not less than the second inductive operation correspondence sensitive time of time.
Optionally, the memory cell of the predetermined number is the half of whole memory cell, wherein, the default sense
The correspondence sensitive time should be operated identical with second of inductive operation corresponding sensitive time.
Optionally, the memory cell of the predetermined number is a quarter of whole memory cell, wherein, it is described pre-
If not less than the second inductive operation correspondence sensitive time of inductive operation correspondence sensitive time.
Accordingly, present invention also offers a kind of flash memory devices, including non-volatile semiconductor memory cell battle array
Row, also include：
Judging unit, the judging unit is used to judge whether to read the non-volatile semiconductor memory cell array
Whole memory cell；
And, processing unit is judging whole memory cell of the reading non-volatile semiconductor memory cell array
When, the processing unit is used to apply voltage to whole memory cell respective words, to carry out first time inductive operation；It is right
After the first time inductive operation, it is determined as that the memory cell of OFF state carries out second of inductive operation, wherein, described first
The difference of the voltage applied when the voltage applied during secondary inductive operation in wordline and second of inductive operation in wordline is in default model
In enclosing, and, second of inductive operation correspondence sensitive time is not less than the first time inductive operation correspondence sensitive time.
Optionally, when the voltage applied in the first time inductive operation in wordline and second of inductive operation in wordline
The voltage of application is identical.
Optionally, judging that it is not whole memory cell to read the non-volatile semiconductor memory cell array,
And when being judged as reading the memory cell of predetermined number, the processing unit is used to apply electricity to the memory cell respective word
Pressure, and a predetermined inductive operation is carried out to the memory cell of the predetermined number, wherein, the word when the predetermined inductive is operated
The voltage applied when the voltage applied on line is with the first time inductive operation and second of inductive operation in wordline is identical, and institute
State not less than the second inductive operation correspondence sensitive time of predetermined inductive operation correspondence sensitive time.
Optionally, the memory cell of the predetermined number is the half of whole memory cell, wherein, the default sense
The correspondence sensitive time should be operated identical with second of inductive operation corresponding sensitive time；
And, the first time inductive operation correspondence sensitive time is less than second of inductive operation correspondence sensitive time.
Optionally, the memory cell of the predetermined number is a quarter of whole memory cell, wherein, it is described pre-
If not less than the second inductive operation correspondence sensitive time of inductive operation correspondence sensitive time.
Compared to prior art, the technical scheme that the present invention is provided at least has advantages below：
The invention provides a kind of read method and flash memory devices, read method is filled applied to flash memories
Put, the flash memory devices include non-volatile semiconductor memory cell array, including：Judge whether that reading is described non-easy
Whole memory cell of the property lost semiconductor memory cell array, if so, then applying electricity to whole memory cell respective words
Pressure, to carry out first time inductive operation；Second is carried out to the memory cell for after the first time inductive operation, being determined as OFF state
Secondary inductive operation, wherein, the wordline when voltage applied in the first time inductive operation in wordline and second of inductive operation
The difference of the voltage of upper application within a preset range, and, second of inductive operation correspondence sensitive time is not less than first
The secondary inductive operation correspondence sensitive time.
As shown in the above, the technical scheme that the present invention is provided, enters for non-volatile semiconductor memory cell array
Whole memory cell are carried out first time inductive operation by row inductive operation twice first, then to being determined as the storage list of OFF state
Member carries out second of inductive operation, wherein, inductive operation time first time is less than second of inductive operation time.Because first time is felt
Short between seasonable, so the only larger memory cell of ON state current can be judged as ON state, and remaining ON state current is less deposits
Storage unit is then judged as OFF state, then to being determined as that the memory cell of OFF state carries out second of inductive operation, due to second
In secondary inductive operation, the larger memory cell of ON state current is no longer participate in the number of memory cells reduction, it is necessary to sense, total stream
The conducting electric current for crossing array is reduced, and common source line noise reduces, and second of sensitive time than the first vice-minister, and in prescribed limit
It is interior, it is possible to induce remaining ON state memory cell.So, the technical scheme that the present invention is provided can be by sensing twice
Operation is read out to flash memory devices, to reduce the noise of common source line, it is ensured that the accuracy rate of read operation is high.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
A kind of flow chart for read method that Fig. 1 provides for the embodiment of the present application；
A kind of LSB read operations schematic diagram that Fig. 2 a provide for the embodiment of the present application；
A kind of MSB read operations schematic diagram that Fig. 2 b provide for the embodiment of the present application；
The flow chart for another read method that Fig. 3 provides for the embodiment of the present application；
A kind of structural representation for flash memory devices that Fig. 4 provides for the embodiment of the present application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As described in background, because NAND-type flash memory memory, it constitutes the institute of array of non-volatile memory cells
The earth terminal for having memory cell is finally all connected together by common source line, so with the expansion of memory cell array, adopting
When being read with full bit line read method, the influence of noise of common source line is just increasing, or even causes read operation mistake,
Thus, when being read, reduction common source line noise just becomes particularly important.
Based on this, the embodiment of the present application provides a kind of read method and flash memory devices, first to whole storages
Unit carries out first time inductive operation, then to being determined as that the memory cell of OFF state carries out second of inductive operation, by twice
Inductive operation is read out to flash memory devices, to reduce the noise of common source line, it is ensured that the accuracy rate of read operation is high.For
Above-mentioned purpose is realized, the technical scheme that the embodiment of the present application is provided is as follows, specifically with reference to shown in Fig. 1 to Fig. 4, and the application is implemented
The technical scheme that example is provided is described in detail.
With reference to shown in Fig. 1, a kind of flow chart for the read method for implementing to provide for the application, wherein, read method application
In flash memory devices, the flash memory devices include non-volatile semiconductor memory cell array, read method bag
Include：
S1, judge whether to read whole memory cell of the non-volatile semiconductor memory cell array；
S2, if so, then applying voltages to the whole memory cell respective words, to carry out first time inductive operation；
S3, memory cell second of inductive operation of progress to after the first time inductive operation, being determined as OFF state, its
In, the voltage applied when the voltage applied in the first time inductive operation in wordline and second of inductive operation in wordline
Difference within a preset range, and, second of inductive operation correspondence sensitive time is not less than first time inductive operation correspondingly
Sensitive time.
As shown in the above, the technical scheme that the embodiment of the present application is provided, for non-volatile semiconductor memory cell
Array carries out inductive operation twice, first time inductive operation is carried out to whole memory cell first, then to being determined as OFF state
Memory cell carries out second of inductive operation, wherein, inductive operation time first time is less than second of inductive operation time.Because of the
Sensitive time is short, so the only larger memory cell of ON state current can be judged as ON state, and remaining ON state current compared with
Small memory cell is then judged as OFF state, then to being determined as that the memory cell of OFF state carries out second of inductive operation, due to
In second of inductive operation, the larger memory cell of ON state current is no longer participate in the number of memory cells reduction, it is necessary to sense,
Total conducting electric current for flowing through array is reduced, and common source line noise reduces.And second of sensitive time than the first vice-minister, and regulation
In the range of, it is possible to remaining ON state memory cell is induced, whole read operation is completed.So, the embodiment of the present application is provided
Technical scheme flash memory devices can be read out by inductive operation twice, to reduce the noise of common source line, protect
The accuracy rate for demonstrate,proving read operation is high.
The voltage applied in the embodiment of the application one in the first time inductive operation in wordline and second of sensing
The voltage applied during operation in wordline is identical.
And, when the first time inductive operation correspondence sensitive time preferably is less than second of inductive operation correspondence sensing
Between, it is ensured that final sensing is more accurate.
Shown in lower mask body combination Fig. 2 a and Fig. 2 b, detailed retouch is carried out to the read method that the embodiment of the present application is provided
State.It should be noted that a read operation all includes bit line preliminary filling, sensing on bit line, latches three parts, its corresponding time
Tpre, Tdev, Tsense are corresponded to respectively, it is same as the prior art to this, therefore unnecessary repeat is not done.
With reference to shown in Fig. 2 a, a kind of LSB read operations schematic diagram provided for the embodiment of the present application, first time inductive operation
Correspondence bit line preliminary filling, sensing, the time latched correspond to Tpre1, Tdev1, Tsense1 respectively, and, second of inductive operation
Correspondence bit line preliminary filling, sensing, the time latched correspond to Tpre2, Tdev2, Tsense2 respectively.Wherein, to the word of memory cell
Apply voltage Vrd2 on line WL, it is first time inductive operation and that once complete LSB read operations, which include inductive operation twice,
Secondary inductive operation.Wherein, the sensitive time Tdev1 of first time inductive operation is less than the sensitive time of second of inductive operation
Tdev2.Because than second sensitive time of sensitive time first time is short, so the only larger memory cell of ON state current can be judged to
It is set to ON state.And sense for the second time, will be on the basis of first time, it is ON state memory cell to read remaining storage state.And
And, because the bit line that preliminary filling is needed when to second of inductive operation is reduced, so, during the bit line preliminary filling of second inductive operation
Between Tpre2 be less than first time inductive operation bit line pre-charging time Tpre1.
With reference to shown in Fig. 2 b, a kind of MSB read operations schematic diagram provided for the embodiment of the present application reads for MSB and grasped
Work is divided into twi-read, and reads include inductive operation twice every time, i.e. read for the first time include first time inductive operation with
Second of inductive operation, wherein, first time inductive operation correspondence bit line preliminary filling, sensing, the time point latched in reading for the first time
Tpre3, Tdev3, Tsense3 are not corresponded to, and, second inductive operation correspondence bit line preliminary filling, sensing, the time point latched
Tpre4, Tdev4, Tsense4 are not corresponded to；And, second read in first time inductive operation correspondence bit line preliminary filling, sensing,
The time of latch corresponds to Tpre3 ', Tdev3 ', Tsense3 ' respectively, and, second inductive operation correspondence bit line preliminary filling, sense
The time that should, latch corresponds to Tpre4 ', Tdev4 ', Tsense4 ' respectively.Wherein, when reading first time to being applied on wordline WL
Making alive Vrd1, and, when reading for second to applying voltage Vrd3 on wordline WL, wherein, feel for the first time in reading every time
The sensitive time that should be operated is less than the sensitive time of second of inductive operation, because sensitive time first time is short, so only ON state
The larger memory cell of electric current can be judged as ON state.And sense for the second time, on the basis of sensing in first time, read remaining
Storage state be ON state memory cell.Specifically, with reference to shown in Fig. 3, another reading side provided for the embodiment of the present application
The flow chart of method, wherein, judging that it is not whole memory cell to read the non-volatile semiconductor memory cell array,
And when being judged as reading the memory cell of predetermined number, S4, voltage then is applied to the memory cell respective word, and to described
The memory cell of predetermined number carries out a predetermined inductive operation and (wherein, passes through memory cell of the control bit line to predetermined number
Carry out inductive operation), wherein, the voltage that applies when the predetermined inductive operate in wordline and the first time inductive operation and
The voltage applied during second of inductive operation in wordline is identical, and the predetermined inductive operation correspondence sensitive time is not less than second
The secondary inductive operation correspondence sensitive time.
Wherein, partial memory cell can be the memory cell of 1/2 quantity, i.e. the memory cell of the predetermined number is
The half of whole memory cell, wherein, the predetermined inductive operation correspondence sensitive time is corresponding with second of inductive operation
Sensitive time is identical.
In addition, partial memory cell can also be the memory cell of 1/4 quantity, i.e. the memory cell of the predetermined number
For a quarter of whole memory cell, wherein, the predetermined inductive operation correspondence sensitive time is felt not less than second
The correspondence sensitive time should be operated.
It should be noted that partial memory cell can also be the memory cell of other quantity, this application is not done and had
Body is limited, it is necessary to specific design be carried out according to practical application, by operating the setting of correspondence sensitive time to be not less than predetermined inductive
It is second of inductive operation correspondence sensitive time, low with the noise for ensureing common source line, it is ensured that to read accuracy rate high.
Accordingly, the embodiment of the present application additionally provides a kind of flash memory devices, with reference to shown in Fig. 4, is that the application is real
A kind of structural representation of flash memory devices of example offer is provided, wherein, flash memory devices are partly led including non-volatile
Body memory cell array, also includes：
Judging unit 100, the judging unit 100 is used to judge whether to read the non-volatile semiconductor memory cell
Whole memory cell of array；
And, processing unit 200 is judging that the whole storages for reading the non-volatile semiconductor memory cell array are single
When first, the processing unit 200 is used to apply voltage to whole memory cell respective words, is grasped with carrying out sensing for the first time
Make；Second of inductive operation is carried out to the memory cell for after the first time inductive operation, being determined as OFF state, wherein, in institute
The difference of the voltage applied when the voltage applied when stating first time inductive operation in wordline and second of inductive operation in wordline exists
In preset range, and, when second of inductive operation correspondence sensitive time senses not less than first time inductive operation correspondence
Between.
Wherein, WL<0>~WL<m>For the wordline of flash memory devices, S1~S4 is bit line, and SSL is to be connected to bit line
Switching tube grid end control line, GSL is the grid end control line for the switching tube for being connected to common source line GL, and, every bit line connects
It is connected to bit line sensing circuit.
The voltage applied in the embodiment of the application one in the first time inductive operation in wordline and second of sensing
The voltage applied during operation in wordline is identical.
And, when the first time inductive operation correspondence sensitive time preferably is less than second of inductive operation correspondence sensing
Between, it is ensured that final sensing is more accurate.
In the embodiment of the application one, partial memory cell can also be read.Specifically, judging that reading is described non-volatile
Property semiconductor memory cell array be not whole memory cell, and be judged as read predetermined number memory cell when, institute
Stating processing unit 200 is used to apply voltage to the memory cell respective word, and the memory cell of the predetermined number is entered
Predetermined inductive operation of row, wherein, the voltage applied when the predetermined inductive is operated in wordline senses with the first time
Operate the voltage applied during with second of inductive operation in wordline identical, and the predetermined inductive operation correspondence sensitive time is not small
In second of inductive operation correspondence sensitive time.
Wherein, partial memory cell can be the memory cell of 1/2 quantity, i.e. the memory cell of the predetermined number is
The half of whole memory cell, wherein, the predetermined inductive operation correspondence sensitive time is corresponding with second of inductive operation
Sensitive time is identical.
In addition, partial memory cell can also be the memory cell of 1/4 quantity, the memory cell of the predetermined number is institute
The a quarter of whole memory cell is stated, wherein, described not less than second sensing behaviour of predetermined inductive operation correspondence sensitive time
Make the correspondence sensitive time.
It should be noted that partial memory cell can also be the memory cell of other quantity, this application is not done and had
Body is limited, it is necessary to specific design be carried out according to practical application, by operating the setting of correspondence sensitive time to be not less than predetermined inductive
It is second of inductive operation correspondence sensitive time, low with the noise for ensureing common source line, it is ensured that to read accuracy rate high.
The embodiment of the present application provides a kind of read method and flash memory devices, and read method is applied to flash memory storage
Device device, the flash memory devices include non-volatile semiconductor memory cell array, including：Judge whether that reading is described
Whole memory cell of non-volatile semiconductor memory cell array, if so, then being applied to whole memory cell respective words
Making alive, to carry out first time inductive operation；The memory cell for after the first time inductive operation, being determined as OFF state is carried out
Second of inductive operation, wherein, when the voltage applied in the first time inductive operation in wordline and second of inductive operation
The difference of the voltage applied in wordline within a preset range, and, second of inductive operation correspondence sensitive time is not less than
The first time inductive operation correspondence sensitive time.
As shown in the above, the technical scheme that the embodiment of the present application is provided, for non-volatile semiconductor memory cell
Array carries out inductive operation twice, first time inductive operation is carried out to whole memory cell first, then to being determined as OFF state
Memory cell carries out second of inductive operation, wherein, it is less than second of inductive operation time in inductive operation time first time.Cause
Sensitive time first time is short, so the only larger memory cell of ON state current can be judged as ON state, and remaining ON state current
Less memory cell is then judged as OFF state, then to being determined as that the memory cell of OFF state carries out second of inductive operation, by
In in second of inductive operation, the larger memory cell of ON state current is no longer participate in, it is necessary to which the number of memory cells sensed subtracts
Few, total conducting electric current for flowing through array is reduced, and common source line noise reduces, and second of sensitive time is long, it is possible to will be surplus
The remaining memory cell for being stored as ON state is smoothly read.So, the technical scheme that the embodiment of the present application is provided can be by twice
Inductive operation is read out to flash memory devices, to reduce the noise of common source line, it is ensured that the accuracy rate of read operation is high.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
1. a kind of read method, applied to flash memory devices, the flash memory devices include nonvolatile semiconductor
Memory cell array, it is characterised in that including：
Judge whether to read whole memory cell of the non-volatile semiconductor memory cell array, if so, then to described complete
Portion's memory cell respective word applies voltage, to carry out first time inductive operation；
Second of inductive operation is carried out to the memory cell for after the first time inductive operation, being determined as OFF state, wherein, in institute
The difference of the voltage applied when the voltage applied when stating first time inductive operation in wordline and second of inductive operation in wordline exists
In preset range, and, when second of inductive operation correspondence sensitive time senses not less than first time inductive operation correspondence
Between.
2. read method according to claim 1, it is characterised in that apply in the first time inductive operation in wordline
Voltage and the voltage that applies in wordline during second of inductive operation it is identical；
And, the first time inductive operation correspondence sensitive time is less than second of inductive operation correspondence sensitive time.
3. read method according to claim 2, it is characterised in that judging to read the non-volatile semiconductor storage
Cell array is not whole memory cell, and when being judged as reading the memory cell of predetermined number, then it is single to the storage
First respective word applies voltage, and carries out a predetermined inductive operation to the memory cell of the predetermined number, wherein, described
Applied when the voltage applied when predetermined inductive is operated in wordline is with the first time inductive operation and second of inductive operation in wordline
Plus voltage it is identical, and the predetermined inductive operation correspondence sensitive time is not less than second inductive operation correspondence sensitive time.
4. read method according to claim 3, it is characterised in that the memory cell of the predetermined number is the whole
The half of memory cell, wherein, the predetermined inductive operation correspondence sensitive time corresponding with second of inductive operation sensitive time
It is identical.
5. read method according to claim 3, it is characterised in that the memory cell of the predetermined number is the whole
The a quarter of memory cell, wherein, described not less than second inductive operation correspondence of predetermined inductive operation correspondence sensitive time
Sensitive time.
6. a kind of flash memory devices, including non-volatile semiconductor memory cell array, it is characterised in that also include：
Judging unit, the judging unit is used to judge whether to read the whole of the non-volatile semiconductor memory cell array
Memory cell；
And, processing unit, when judging to read whole memory cell of the non-volatile semiconductor memory cell array, institute
Stating processing unit is used to apply voltage to whole memory cell respective words, to carry out first time inductive operation；To institute
State after first time inductive operation, be determined as that the memory cell of OFF state carries out second of inductive operation, wherein, in first time sense
The difference of the voltage applied when the voltage applied when should operate in wordline and second of inductive operation in wordline within a preset range,
And, second of inductive operation correspondence sensitive time is not less than the first time inductive operation correspondence sensitive time.
7. flash memory devices according to claim 6, it is characterised in that the wordline in the first time inductive operation
The voltage applied when the voltage of upper application and second of inductive operation in wordline is identical；
And, the first time inductive operation correspondence sensitive time is less than second of inductive operation correspondence sensitive time.
8. flash memory devices according to claim 7, it is characterised in that judging to read described non-volatile partly lead
Body memory cell array is not whole memory cell, and when being judged as reading the memory cell of predetermined number, the processing
Unit is used to apply voltage to the memory cell respective word, and the memory cell of the predetermined number is once preset
Inductive operation, wherein, the voltage applied when the predetermined inductive is operated in wordline and the first time inductive operation and second
The voltage applied during secondary inductive operation in wordline is identical, and the predetermined inductive operation correspondence sensitive time is felt not less than second
The correspondence sensitive time should be operated.
9. flash memory devices according to claim 8, it is characterised in that the memory cell of the predetermined number is institute
The half of whole memory cell is stated, wherein, the predetermined inductive operation correspondence sensitive time sense corresponding with second of inductive operation
It is identical between seasonable.
10. flash memory devices according to claim 8, it is characterised in that the memory cell of the predetermined number is
The a quarter of whole memory cell, wherein, the predetermined inductive operation correspondence sensitive time senses not less than second
The operation correspondence sensitive time.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109841259A (en) * | 2017-11-29 | 2019-06-04 | 北京兆易创新科技股份有限公司 | Improve the method and device of NOR type storage array reading speed |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841259A (en) * | 2017-11-29 | 2019-06-04 | 北京兆易创新科技股份有限公司 | Improve the method and device of NOR type storage array reading speed |
| CN109841259B (en) * | 2017-11-29 | 2020-12-29 | 北京兆易创新科技股份有限公司 | Method and device for improving NOR type memory array reading speed |
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