CN106205696A - Semiconductor memory devices and operational approach thereof - Google Patents
Semiconductor memory devices and operational approach thereof Download PDFInfo
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- CN106205696A CN106205696A CN201510256059.1A CN201510256059A CN106205696A CN 106205696 A CN106205696 A CN 106205696A CN 201510256059 A CN201510256059 A CN 201510256059A CN 106205696 A CN106205696 A CN 106205696A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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Abstract
A kind of semiconductor memory devices includes: include the memory cell array of multiple memory cell, memory cell array is performed programming pulse and applies operation and the peripheral circuit of verification operation, to including that what programming pulse applied that the programming operation of operation and verification operation performs to pass through/unsuccessfully check operation passes through/unsuccessfully check circuit, and Control peripheral circuit and pass through/unsuccessfully check circuit to perform to pass through/unsuccessfully check the control logic of operation during programming pulse applies operation.
Description
Cross-Reference to Related Applications
This application claims the korean patent application of Application No. 10-2014-0178426 of December in 2014 submission on the 11st
Priority, entire contents is incorporated herein by reference.
Technical field
Various exemplary embodiments relate generally to a kind of electronic equipment, more particularly to a kind of semiconductor memory devices
And operational approach.
Background technology
Semiconductor memory devices is generally divided into volatile memory devices and non-volatile memory devices.
Non-volatile memory devices operates with relatively low write and reading speed, but it can not have electricity
Stored data are possessed in the case of the supply of source.Therefore, regardless of/powering-off state of powering, nonvolatile memory sets
Standby may serve to stores the data needing to possess.The example of non-volatile memory devices includes read only memory
(ROM), mask type ROM (MROM), programming ROM (PROM), erasable programmable ROM
(EPROM), electrically erasable ROM (EEPROM), flash memory, phase change random access memory devices
(PRAM), magnetic resistance RAM (MRAM), resistance-type RAM (RRAM) and ferroelectric type RAM (FRAM).
Flash memory is divided into NOR and NAND type.
Flash memory has the advantage of both RAM and ROM.Such as, flash memory can be such as RAM mono-
Sample freely programs and wipes.Being similar to ROM, even if flash memory does not has power supply, supply can also possess storage
Data.Flash memory is as such as mobile phone, digital camera, personal digital assistant (PDA) and MP3
The storage medium of the portable electric appts of player and be widely used.
Summary of the invention
Embodiment is for a kind of semiconductor memory devices, when it can reduce programming operation by using page buffer
Between, and improve the reliability passing through/unsuccessfully checking operation of programming operation.
Semiconductor memory devices may include that memory cell array according to an embodiment of the invention, and it includes
Multiple memory cells；Peripheral circuit, it is suitable to that memory cell array performs programming pulse and applies operation and checking behaviour
Make；Pass through/unsuccessfully checking circuit, its programming operation be suitable to including programming pulse applying operation and verification operation performs logical
Cross/unsuccessfully check；And control logic, its be suitable to Control peripheral circuit and by/unsuccessfully check circuit to execute at programming pulse
Perform during add operation to pass through/unsuccessfully check.
Semiconductor memory devices may include that memory cell array according to an embodiment of the invention, and it includes
Multiple memory cells；Voltage generator, it is suitable to during programming pulse applies operation and during verification operation to storage
Device cell array applies programming pulse and verifying voltage；Multiple page buffers, it is suitable to apply the operation phase at programming pulse
Between control the potential level of bit line of memory cell array in response to programming data, and sense during verification operation
The programming state of the memory cell chosen in the plurality of memory cell；Pass through/unsuccessfully checking circuit, it is suitable to right
Including programming pulse apply operation and verification operation programming operation perform pass through/unsuccessfully check operation；And control logic,
It is suitable to control to pass through during programming pulse applies operation/unsuccessfully check circuit with execution pass through/unsuccessfully check operation.
The operational approach of semiconductor memory devices according to an embodiment of the invention may include that to be executed programming pulse
The memory cell chosen being added in multiple memory cell；The data of the memory cell chosen by sensing and to choosing
In memory cell perform verification operation；Result based on verification operation resets programming pulse and the programming that will reset
Pulse is applied to the memory cell chosen；And in applying the programming pulse reset, utilize sensing during verification operation
To data perform to pass through/unsuccessfully check operation.
Accompanying drawing explanation
Fig. 1 is the block diagram describing the semiconductor memory devices according to an embodiment；
Fig. 2 is to describe the page buffer shown in Fig. 1 and pass through/unsuccessfully check the block diagram of circuit；
Fig. 3 is the flow chart of the operation describing the semiconductor equipment according to an embodiment；
Fig. 4 is voltage and the waveform of signal of the operation for describing the semiconductor memory devices according to an embodiment
Figure；
Fig. 5 is the block diagram describing the accumulator system including the semiconductor memory devices shown in Fig. 1；
Fig. 6 is the block diagram of the example application describing the accumulator system shown in Fig. 5；
Fig. 7 is the block diagram describing and including the calculating system with reference to the accumulator system described by Fig. 6.
Detailed description of the invention
Hereinafter, with reference to the accompanying drawings various exemplary embodiments are described in detail.In the accompanying drawings, for the ease of retouching
For the sake of stating, the thickness of assembly and length may be exaggerated.In the following description, rise for simplicity that is simple and that illustrate
See, and in order to avoid making the design of the present invention obscure, the detailed description of the function for relevant and composition may be eliminated.
Running through specification and drawings, identical reference number refers to identical element.
Additionally, " connect/couple " represents that an assembly is directly coupled to another assembly or is couple to by intermediate module
Another assembly.Unless specifically stated otherwise, otherwise singulative can include plural form.Additionally, made in the description
" include/comprise " or " include/include " represent can exist or increase one or more assembly, step,
Operation and element.
Fig. 1 is the block diagram describing the semiconductor memory devices according to an embodiment.
With reference to Fig. 1, semiconductor memory devices 100 can include memory cell array 110, address decoder 120,
Read write circuit 130, control logic 140, voltage generator 150 and pass through/unsuccessfully check circuit 160.
Memory cell array 110 can include multiple memory block BLK1 to BLKz.The plurality of memory block
BLK1 to BLKz can be couple to address decoder 120 by wordline WL.Memory block BLK1 to BLKz can
To be couple to read write circuit 130 by bit line BL1 to BLm.Each in memory block BLK1 to BLKz
Multiple memory cell can be included.In one embodiment, the plurality of memory cell can be non-volatile memories
Device unit.The memory cell being couple to same word line in the plurality of memory cell can be defined as single page
Face.In other words, memory cell array 110 can include multiple page.
Address decoder 120, reading write circuit 130 and voltage generator 150 may serve as driving memorizer
The peripheral circuit of cell array 110.
Address decoder 120 can be couple to memory cell array 110 by wordline WL.Address decoder 120 can
To be controlled by control logic 140.Address decoder 120 can be by the input/output in semiconductor memory devices 100
Buffer (not shown) receives address AD DR.
When performing programming pulse during programming operation and applying operation, address decoder 120 can be by by voltage generator
The 150 programming pulse Vpgm generated are applied to the wordline chosen in the wordline of memory block chosen.When programming behaviour
When performing verification operation during work, the verifying voltage that address decoder 120 can will be generated by voltage generator 150
Vverify is applied to the wordline chosen in the wordline of memory block chosen.
The programming operation of semiconductor memory devices 100 can be performed based on the page.Connect in response to programming operation request
Address AD DR received can include block address, row address and column address.Address decoder 120 can be in response to block ground
Location and row address select in memory block and in wordline.Column address can be by address decoder 120
Carry out decoding and be provided to read write circuit 130.
Read write circuit 130 and can include multiple page buffer PB1 to PBm.The plurality of page buffer PB1
Memory cell array 110 can be couple to by bit line BL1 to BLm to PBm.Page buffer PB1 to PBm
In each can temporarily store data DATA provided from external equipment during programming operation, and in response to being deposited
The potential level of corresponding bit line is set to programming and allows voltage or program-inhibit voltage by data DATA of storage.
Additionally, the plurality of page buffer PB1 to PBm each can sense corresponding storage during verification operation
The programming state of device unit, and carry out verification of programming operation based on programming state.
Read write circuit 130 to be controlled by controlling logic 140.
According to an exemplary embodiment, read write circuit 130 and can include page buffer (or page register)
And column select circuit.
Control logic 140 to be couple to address decoder 120, read write circuit 130 and voltage generator 150.
Control logic 140 and can receive order by the input/output (i/o) buffer (not shown) of semiconductor memory devices 100
CMD.Control logic 140 and can be configured to respond to order CMD to control the whole of semiconductor memory devices 100
Gymnastics is made.Additionally, control logic 140 can control voltage generation during the programming operation of memory cell array 110
Device 150 and address decoder 120, thus depositing of being applied to programming pulse Vpgm or verifying voltage Vverify to choose
Reservoir block.Control logic 140 can control to read write circuit 130, such that it is able to by controlling and sensing memory
The current potential of bit line BL1 to the BLm of cell array 110 performs verification operation.Additionally, apply when performing programming pulse
During operation, control logic 140 and can control to pass through/unsuccessfully check circuit 160 by using during verification operation before
The data sensed exporting failed bit count signal FBC and execution and pass through/unsuccessfully check operation.Additionally, control
Logic 140 processed can passing through/unsuccessfully check operation during control to pass through/unsuccessfully inspection circuit 160 be selectively carrying out electric current
Measuring method and data method of counting, thus improve the reliability passing through/unsuccessfully checking operation.
Voltage generator 150 can generate programming pulse Vpgm to be applied to choose during programming pulse applies operation
Memory block, and during programming verification operation, generate verifying voltage Vverify to be applied to the memory block chosen.
During programming pulse applies operation, passing through/unsuccessfully check circuit 160 can be in response to failure bit count signal
FBC, by counting the number of the failed bit of the memory cell that there occurs misprogrammed in multiple memory cells
Number exports programming and passes through/failure signal PASS/FAIL.When the number of the failed bit counted is more than utilizing mistake
During the number of the bit-errors of permission that correction code is corrected, pass through/unsuccessfully check that circuit 160 can export unsuccessfully believes
Number FAIL, and signal is passed through in output when the number of the failed bit counted is less than the number of the bit-errors allowed
PASS。
During programming pulse applies operation, by/unsuccessfully check that circuit 160 can be stored in reading write electricity by use
Sensing data in the page buffer on road 130 perform to pass through/unsuccessfully check operation.Pass through/unsuccessfully check circuit 160
Current sense method and data method of counting can be selectively carrying out.According to current sense method, can measure corresponding to
The magnitude of current of the sensing data being stored in page buffer is to estimate the number of unsuccessfully bit.According to data counts method,
The logical value of the sensing data being stored in page buffer can be counted, so that it is determined that the logical value counted is made
Number for failure bit.Additionally, by/unsuccessfully check that circuit 160 can utilize current sense method to obtain by use
The number of failed bit and utilize the number of failed bit that data counts method obtains to pass through/unsuccessfully believe exporting programming
Number PASS/FAIL, thus pass through/unsuccessfully check circuit 160 and can improve the degree of accuracy of the number counting to failure bit.
Fig. 2 is to describe the page buffer shown in Fig. 1 and pass through/unsuccessfully check the block diagram of circuit.
Fig. 2 describes one in the page buffer shown in Fig. 1, is i.e. couple to pass through/unsuccessfully check the page of circuit 160
Face buffer PB1.But, it practice, read multiple page buffer PB1 to PBm that write circuit 130 includes
Can be couple to pass through/unsuccessfully check circuit 160, such as page buffer PB1.Additionally, page buffer PB1 arrives
The each of PBm can have the configuration substantially the same with page buffer PB1.
Main latch 132 and cache latches 131 can be included with reference to Fig. 2, page buffer PB1.Main latch
Device 132 and cache latches 131 can be couple to the bit line BL1 of correspondence by sense node SO.Additionally, it is main
Latch 132 and cache latches 131 can transmit, by sense node SO, the data latched.
Such as, during programming operation, it is input to cache latches 131 can pass for the programming data of caching
Deliver to main latch 132.Voltage or program-inhibit voltage is allowed when the potential level of sense node SO is set to programming
Time, in response to the programming data being stored in main latch 132, next programming data can be input to cache lock
Storage 131.
During verification operation, page-buffer PB1 can utilize main latch 132 in response to the memory cell chosen
Programming state and latching sense data, and operate by utilizing the sensing data that latched to carry out verification of programming.
Additionally, during passing through/unsuccessfully check to operate, the sensing data being stored in main latch 132 can be sent to
Cache latches 131, and be stored in the data in cache latches 131 and can be output to/unsuccessfully examine
Look into circuit 160.The sensing data being stored in main latch 132 can be inverted and be sent to cache latches
131。
Pass through/unsuccessfully check circuit 160 can include current measuring unit 161, data counts unit 162 and pass through/
Failure signal signal generating unit 163.
Current measuring unit 161 can based on each main latch 132 being stored in page buffer PB1 to PBm
In the corresponding current value of sensing data and estimate the number of failed bit.Additionally, DATA REASONING unit 161 can ring
The number of the failed bit estimated by Ying Yu exports first and passes through/failure signal PASS/FAIL1.
Data counts unit 162 can be by locking each cache being stored in page buffer PB1 to PBm
The first data (such as, " 0 ") and the number of the second data (such as, " 1 ") in data in storage 131 are counted
Number so that it is determined that the number of failure bit, and in response to determined by the number of failure bit export and second pass through/failure
Signal PASS/FAIL2.
Pass through/failure signal signal generating unit 163 can be by using first passing through/losing from current measuring unit 161 output
Lose signal PASS/FAIL1 or come defeated from the second of data counts unit 162 output by/failure signal PASS/FAIL2
Go out programming and pass through/failure signal PASS/FAIL.Pass through/failure signal signal generating unit 163 can include multiplexer,
And selectively output first pass through/failure signal PASS/FAIL1 and second passes through/failure signal PASS/FAIL2 in
One pass through/failure signal PASS/FAIL as programming.
Fig. 3 is the flow chart of the operation describing the semiconductor memory devices according to an embodiment.
Fig. 4 is voltage and the waveform of signal of the operation for describing the semiconductor memory devices according to an embodiment
Figure.
Referring to Fig. 1 to Fig. 4, the operational approach of semiconductor memory devices is described.
1) programming pulse (S310) is applied
Bit line BL1 can be arrived by the plurality of page buffer PB1 to PBm based on the programming data of temporarily storage
The potential level of BLm is set to programming and allows voltage or program-inhibit voltage.
When performing programming pulse during programming operation and applying operation, address decoder 120 can be in response to address
ADDR selects one in memory block BLK1 to BLKz, and the programming that will be generated by voltage generator 150
Pulse Vpgm is applied to the wordline chosen in the memory block chosen.
2) verification operation (S320) is performed
After programming pulse applies operation (S310), voltage generator 150 the verifying voltage Vverify generated can
With the wordline chosen being applied in the memory block chosen, and page buffer PB1 to PBm can sense with
The potential level of its corresponding bit line BL1 to BLm, and sensing data are stored in main latch 132, from
And perform to program verification operation.
3) the result (S330) is determined
When the result of above-mentioned verification operation (S320) determines that out that the threshold voltage of target programmed memory cell is more than checking
During voltage Vverify, it may be determined that programming is passed through.When the threshold voltage of at least one in target programmed memory cell
During less than verifying voltage Vverify, it may be determined that program fail.
4) programming pulse (S340) is reset
When determining program fail in determining operation (S330) at above-mentioned the result, control logic 140 and can control electricity
Pressure maker 150 is by resetting programming pulse Vpgm by programming pulse Vpgm increase stepped voltage.
The plurality of page buffer PB1 to PBm can by above-mentioned verification operation (S320) period at main latch
The data sensed in 132 are sent to cache latches 131 to be stored therein.
5) apply programming pulse and operation (S350) is passed through/unsuccessfully checked in execution
After above-mentioned programming pulse reset operation (S340), address decoder 120 can be in response to address AD DR
Select in memory block BLK1 to BLKz, and the programming pulse that will be reset by voltage generator 150
Vpgm is applied to the wordline chosen in the memory block chosen.
Meanwhile, pass through/unsuccessfully inspection circuit 160 can be by each to be stored in page buffer PB1 to PBm
Cache latches 131 in data carry out counting the number determining unsuccessfully bit, and programming is passed through/failure
Signal PASS/FAIL exports control logic 140.
Control logic 140 and can determine that the memory block chosen is in response to programming by/failure signal PASS/FAIL
Normal memory block or bad memory block, and perform subsequent operation.
Fig. 5 is the block diagram describing the accumulator system 1000 including the semiconductor memory devices 100 shown in Fig. 1.
With reference to Fig. 5, accumulator system 1000 can include semiconductor memory devices 100 and controller 1100.
Semiconductor memory devices 100 can configuring in the way of above with reference to substantially the same described by Fig. 1 and
Operation.Therefore, it is described in detail with regard to this omission.
Controller 1100 can be couple to main frame and semiconductor memory devices 100.Controller 1100 can answer main frame
Request accesses semiconductor memory devices 100.Such as, controller 1100 can control semiconductor memory devices 100
Read operation, programming operation, erasing operation and/or consistency operation.Controller 1100 can provide semiconductor memory
Interface between equipment 100 and main frame.Controller 1100 can drive for controlling consolidating of semiconductor memory devices 100
Part.
Controller 1100 can include random access memory (RAM) 1110, processing unit 1120, HPI 1130,
Memory interface 1140 and error correction block 1150.RAM 1110 can serve as the operation storage of processing unit 1120
Device, cache memory between semiconductor memory devices 100 and main frame and/or semiconductor memory devices 100
And the buffer storage between main frame.Processing unit 1120 can control the operation of controller 1100.
HPI 1130 can include in main frame and the agreement of the swapping data of controller 1100.Such as, control
Device 1100 processed can pass through such as USB (universal serial bus) (USB) agreement, multimedia card (MMC) agreement, peripheral group
Part interconnection (PCI) agreement, PCI-quickly (PCI-E) agreement, Advanced Technology Attachment (ATA) agreement, serial-ATA
Agreement, parallel-ATA agreement, minicomputer low profile interface (SCSI) agreement, enhancement mode mini-hard disk interface (ESDI)
Agreement, integrated drive electronics (IDE) agreement, proprietary protocol etc. various agreements in one or more of come and main frame
Communicate.
Memory interface 1140 can be with semiconductor memory devices 100 interface.Such as, memory interface 1140 is permissible
Including NAND Flash interface or NOR flash interface.
Error correction block 1150 can utilize error correction code (ECC) to detect and correct and set from semiconductor memory
Mistake in standby 100 data read.Processing unit 1120 can control semiconductor memory devices 100 with based on mistake
The misrouting result of correcting block 1150 controls read voltage, and again performs read operation.According to exemplary reality
Executing example, error correction block 1150 can provide the assembly as controller 1100.
Controller 1100 and semiconductor memory devices 100 are desirably integrated in a semiconductor equipment.Show according to one
The embodiment of example, controller 1100 and semiconductor memory devices 100 be desirably integrated in single semiconductor equipment thus
Form memory card, such as PC card (PC memory Card Internation Association (PCMCIA)), compact flash card
(CF), smart media card (SMC), memory stick, multimedia card (MMC, RS-MMC or MMC micro),
SD card (SD, miniSD, micro SD or SDHC), general quick flashing bunkerage (UFS) etc..
Controller 1100 and semiconductor memory devices 100 are desirably integrated in single semiconductor equipment thus form solid-state
Drive (SSD).SSD can include the bunkerage for storing data in semiconductor memory devices.Work as storage
When device system 1000 is used as SSD, the operation rate of the main frame being couple to accumulator system 1000 can significantly increase.
In another example, accumulator system 1000 can serve as one of some elements in various electronic equipment, institute
State various electronic equipment such as computer, super mobile PC (UMPC), work station, net book, personal digital assistant (PDA),
Portable computer, web-tablet, radio telephone, mobile phone, smart phone, e-book, portable multimedia broadcasting
Put device (PMP), portable game machine, navigator, black box, digital camera, three-dimensional television, DAB note
Record device, digital audio-frequency player, digital picture recorder, digital picture player, digital video recorder, numeral regard
Frequently player, for transmitting/receive the equipment of information in wireless environments, for the equipment of home network, for computer
The equipment of network, the equipment for long-distance communication network, RFID device, for calculating other equipment etc. of system.
Can be with various according to an exemplary embodiment, semiconductor memory devices 100 or accumulator system 1000
Form encapsulates.Such as, semiconductor memory devices 100 or accumulator system 1000 can pass through such as encapsulation stacking
(PoP), BGA (BGA), wafer-level package (CSP), plastic leaded chip carrier (PLCC), plastics pair
Row inline package (PDIP), waffle packet mode tube core, wafer form tube core, chip on board (COB), ceramic double-row are straight
Insert formula encapsulation (CERDIP), plastics tolerance quad-flat-pack (MQFP), thin quad-flat-pack (TQFP),
Little outline packages integrated circuit (SOIC), shrink little outline packages (SSOP), Outline Package (TSOP),
System (SIP), multi-chip package (MCP), wafer scale preparation encapsulation (WFP), the stacking of wafer-level process in encapsulation
The various methods such as encapsulation (WSP) encapsulate.
Fig. 6 is the block diagram of the example application 2000 describing the accumulator system 1000 shown in Fig. 5.
With reference to Fig. 6, accumulator system 2000 can include semiconductor memory devices 2100 and controller 2200.Half
Conductor memory equipment 2100 can include semiconductor memory chips.Semiconductor memory chips can be divided into group.
Fig. 6 describes by the first semiconductor storage communicated with controller 2200 to kth channel C H1 to CHk
Device chipset.Each in semiconductor memory chips can be to set with above with reference to the semiconductor memory described by Fig. 1
Standby 100 substantially similar ways configure and operate.
Each group can be communicated with controller 2200 by single common-use tunnel.Controller 2200 can with reference
Controller 1100 substantially similar way described by Fig. 5 configures, and is configured to control semiconductor memory devices
Multiple semiconductor memory chips of 2100.
Fig. 7 is the block diagram describing and having the calculating system 3000 as explained above with the accumulator system 2000 described by Fig. 6.
With reference to Fig. 7, calculating system 3000 can include CPU 3100, random access memory (RAM)
3200, user interface 3300, power supply 3400, system bus 3500 and accumulator system 2000.
Accumulator system 2000 can be conductively coupled to CPU 3100, RAM 3200 by bus 3500, be used
Family interface 3300 and power supply 3400.There is provided via user interface 3300 or pass through what CPU 3100 processed
Data can be stored in accumulator system 2000.
In the figure 7, semiconductor memory devices 2100 can be couple to system bus 3500 by controller 2200.So
And, semiconductor memory devices 2100 can be directly coupled to system bus 3500.CPU 3100 and RAM
3200 functions that can perform controller 2200.
As it is shown in fig. 7, calculating system 3000 can include accumulator system 2000 as shown in Figure 6.But, storage
Device system 2000 can replace by the accumulator system 1000 shown in Fig. 5.According to an embodiment, calculate system
3000 can include above with reference to the accumulator system 1000 and 2000 described by Fig. 5 and Fig. 6.
According to an embodiment, semiconductor memory devices can reduce the programming operation time by using page buffer
And improve the reliability passing through/unsuccessfully checking operation of programming operation.
It will be obvious to a person skilled in the art that it is the most permissible
The exemplary embodiment of the above-mentioned present invention is carried out various amendment.Thus, the invention is intended to contain fallen with appended
Amendment in the range of claim and equivalent thereof.
By above example it can be seen that this application provides following technical scheme.
1. 1 kinds of semiconductor memory devices of technical scheme, including:
Memory cell array, it includes multiple memory cell；
Peripheral circuit, it is suitable to that described memory cell array is performed programming pulse and applies operation and verification operation；
Pass through/unsuccessfully checking circuit, it is suitable to including that described programming pulse applies the programming behaviour of operation and described verification operation
As execution pass through/unsuccessfully check operation；And
Controlling logic, it is suitable to control described peripheral circuit during described programming pulse applies operation and described pass through/failure
Check circuit with perform pass through/unsuccessfully check operation.
Technical scheme 2. includes according to the semiconductor memory devices described in technical scheme 1, wherein said peripheral circuit:
Multiple page buffers, it is suitable to control in response to programming data during described programming pulse applies operation described
The potential level of the bit line of memory cell array, and by sensing the current potential of described bit line during described verification operation
Level temporarily stores the sensing data of the memory cell chosen in the plurality of memory cell,
Each in wherein said page buffer described passing through/unsuccessfully check operation during described sensing data are exported
Pass through described in/unsuccessfully check circuit.
Technical scheme 3. is according to the semiconductor memory devices described in technical scheme 2, in wherein said multiple page buffers
Each include:
Main latch, is suitable to the programming in response in the described memory cell chosen during described verification operation
State and store sensing data；And
Cache latches, be suitable to described passing through/unsuccessfully check operation during receive and be stored temporarily in described main latch
The sensing data of storage in device, and pass through described in described sensing data are exported/unsuccessfully check circuit.
Technical scheme 4., according to the semiconductor memory devices described in technical scheme 1, wherein said is passed through/unsuccessfully check electricity
Road is by using current sense method or data counts method to count the number of failure bit, described to perform
Pass through/unsuccessfully check operation.
Technical scheme 5., according to the semiconductor memory devices described in technical scheme 2, wherein said is passed through/unsuccessfully check electricity
Road includes:
Current measuring unit, is suitable to the first number measuring the current value corresponding with the first sensing data to determine unsuccessfully bit
Mesh, and described first number based on failure bit exports first and passes through/failure signal；
Data counts unit, is suitable to count to determine failure to the first data in the second sensing data or the second data
Second number of bit, and described second number based on failure bit exports second and passes through/failure signal；And
Pass through/failure signal signal generating unit, be suitable to pass through described first/failure signal or described second passes through/failure signal
Described control logic is exported by/failure signal as programming,
The sensing data of the wherein said memory cell chosen are stored in the plurality of page buffer as the first sensing data
In the main latch of device, and it is sent to and is stored in the high speed of the plurality of page buffer as the second sensing data
In buffer lock storage.
Technical scheme 6., according to the semiconductor memory devices described in technical scheme 1, wherein said is passed through/unsuccessfully check electricity
Road described programming pulse apply operation during perform described in pass through/unsuccessfully check operation, it is after first time verification operation
Perform.
Technical scheme 7. is according to the semiconductor memory devices described in technical scheme 1, and wherein said control logic is based on described
By/unsuccessfully check the memory block chosen that the result of operation determines in described memory cell array for normal or
Bad memory block.
8. 1 kinds of semiconductor memory devices of technical scheme, including:
Memory cell array, it includes multiple memory cell；
Voltage generator, it is suitable to execute to described memory cell array during programming pulse applies operation and verification operation
Add programming pulse and verifying voltage；
Multiple page buffers, it is suitable to control in response to programming data during described programming pulse applies operation described
The potential level of the bit line of memory cell array, and during described verification operation, sense the plurality of memory cell
In the programming state of the memory cell chosen；
Pass through/unsuccessfully checking circuit, it is suitable to including that described programming pulse applies the programming behaviour of operation and described verification operation
As execution pass through/unsuccessfully check operation；And
Controlling logic, it is suitable to pass through/unsuccessfully check circuit during described programming pulse applies operation described in control to perform
Described pass through/unsuccessfully check operation.
Technical scheme 9. is according to the semiconductor memory devices described in technical scheme 8, in wherein said multiple page buffers
Each described passing through/unsuccessfully check operation during the data sensed during described verification operation are exported described
Pass through/unsuccessfully check circuit.
Technical scheme 10. is according to the semiconductor memory devices described in technical scheme 9, wherein said multiple page buffers
In each include:
Main latch, is suitable to the programming in response in the described memory cell chosen during described verification operation
State and store sensing data；And
Cache latches, be suitable to described passing through/unsuccessfully check operation during receive and be stored temporarily in described main latch
The sensing data of storage in device, and pass through described in described sensing data are exported/unsuccessfully check circuit.
Technical scheme 11., according to the semiconductor memory devices described in technical scheme 8, wherein said is passed through/unsuccessfully check electricity
Road performs described logical by using current sense method or data counts method to count the number of failure bit
Cross/unsuccessfully check operation.
Technical scheme 12., according to the semiconductor memory devices described in technical scheme 8, wherein said is passed through/unsuccessfully check electricity
Road includes:
Current measuring unit, is suitable to the first sensing number measured be stored in the main latch of the plurality of page buffer
According to corresponding current value to determine unsuccessfully the first number of bit, and described first number based on failure bit comes defeated
Go out first and pass through/failure signal；
Data counts unit, is suitable to the second sensing number exported from the cache latches of how described page buffer
The first data or the second data according to carry out counting to determine unsuccessfully the second number of bit, and based on failure bit
Described second number exports second and passes through/failure signal；And
Pass through/failure signal signal generating unit, be suitable to pass through described first/failure signal or described second passes through/failure signal
Described control logic is exported by/failure signal as programming.
Technical scheme 13., according to the semiconductor memory devices described in technical scheme 8, wherein said is passed through/unsuccessfully check electricity
Road described programming pulse apply operation during perform described in pass through/unsuccessfully check operation, it is after first time verification operation
Perform.
Technical scheme 14. is according to the semiconductor memory devices described in technical scheme 8, and wherein said control logic is based on institute
State by/unsuccessfully check that the memory block chosen that the result of operation determines in described memory cell array is normal
Or bad memory block.
The operational approach of 15. 1 kinds of semiconductor memory devices of technical scheme, described operational approach includes:
Programming pulse is applied to the memory cell chosen in multiple memory cell；
By the data of memory cell chosen described in sensing, the described memory cell chosen is performed verification operation；
Result based on described verification operation resets described programming pulse and the programming pulse of replacement is applied to described choosing
In memory cell；And
In the programming pulse applying described replacement, utilize the data that sense during described verification operation perform to pass through/
Failure checks operation.
Technical scheme 16. according to the operational approach described in technical scheme 15, wherein perform described in pass through/unsuccessfully check operation
Including:
By current sense method or data counts method, the number of failure bit is counted.
Technical scheme 17. according to the operational approach described in technical scheme 15, wherein when the result of described verification operation be programming
When operation is confirmed as unsuccessfully, perform the replacement of described programming pulse and the applying of the programming pulse of described replacement.
Technical scheme 18., according to the operational approach described in technical scheme 15, also includes:
After the applying of the replacement of described programming pulse and the programming pulse of described replacement, again perform described checking behaviour
Make.
Technical scheme 19. is according to the operational approach described in technical scheme 18, the replacement of wherein said programming pulse, described heavy
The applying of the programming pulse put and the execution again of described verification operation are repeated, until the result of described verification operation
It is that described programming operation is confirmed as passing through.
Technical scheme 20., according to the operational approach described in technical scheme 15, also includes:
Based on described by/unsuccessfully check that the result of operation determines that the memory block including the plurality of memory cell is
Normal or bad memory block.
Claims (10)
1. a semiconductor memory devices, including:
Memory cell array, it includes multiple memory cell；
Peripheral circuit, it is suitable to that described memory cell array is performed programming pulse and applies operation and verification operation；
Pass through/unsuccessfully checking circuit, it is suitable to including that described programming pulse applies the programming behaviour of operation and described verification operation
As execution pass through/unsuccessfully check operation；And
Controlling logic, it is suitable to control described peripheral circuit during described programming pulse applies operation and described pass through/failure
Check circuit with perform pass through/unsuccessfully check operation.
Semiconductor memory devices the most according to claim 1, wherein said peripheral circuit includes:
Multiple page buffers, it is suitable to control in response to programming data during described programming pulse applies operation described
The potential level of the bit line of memory cell array, and by sensing the current potential of described bit line during described verification operation
Level temporarily stores the sensing data of the memory cell chosen in the plurality of memory cell,
Each in wherein said page buffer described passing through/unsuccessfully check operation during described sensing data are exported
Pass through described in/unsuccessfully check circuit.
Semiconductor memory devices the most according to claim 2, each bag in wherein said multiple page buffers
Include:
Main latch, is suitable to the programming in response in the described memory cell chosen during described verification operation
State and store sensing data；And
Cache latches, be suitable to described passing through/unsuccessfully check operation during receive and be stored temporarily in described main latch
The sensing data of storage in device, and pass through described in described sensing data are exported/unsuccessfully check circuit.
Semiconductor memory devices the most according to claim 1, wherein said passes through/unsuccessfully checks circuit by using
The number of failure bit is counted by current sense method or data counts method, passes through/unsuccessfully examines described in performing
Look into operation.
Semiconductor memory devices the most according to claim 2, wherein said by/unsuccessfully check circuit include:
Current measuring unit, is suitable to the first number measuring the current value corresponding with the first sensing data to determine unsuccessfully bit
Mesh, and described first number based on failure bit exports first and passes through/failure signal；
Data counts unit, is suitable to count to determine failure to the first data in the second sensing data or the second data
Second number of bit, and described second number based on failure bit exports second and passes through/failure signal；And
Pass through/failure signal signal generating unit, be suitable to pass through described first/failure signal or described second passes through/failure signal
Described control logic is exported by/failure signal as programming,
The sensing data of the wherein said memory cell chosen are stored in the plurality of page buffer as the first sensing data
In the main latch of device, and it is sent to and is stored in the high speed of the plurality of page buffer as the second sensing data
In buffer lock storage.
Semiconductor memory devices the most according to claim 1, wherein said passes through/unsuccessfully checks that circuit is in described volume
Pass through described in performing during journey pulse applying operation/unsuccessfully checking operation, it performs after first time verification operation.
Semiconductor memory devices the most according to claim 1, wherein said control logic passes through/failure based on described
Check that the result of operation determines that the memory block chosen in described memory cell array is normal or bad memorizer
Block.
8. a semiconductor memory devices, including:
Memory cell array, it includes multiple memory cell；
Voltage generator, it is suitable to execute to described memory cell array during programming pulse applies operation and verification operation
Add programming pulse and verifying voltage；
Multiple page buffers, it is suitable to control in response to programming data during described programming pulse applies operation described
The potential level of the bit line of memory cell array, and during described verification operation, sense the plurality of memory cell
In the programming state of the memory cell chosen；
Pass through/unsuccessfully checking circuit, it is suitable to including that described programming pulse applies the programming behaviour of operation and described verification operation
As execution pass through/unsuccessfully check operation；And
Controlling logic, it is suitable to pass through/unsuccessfully check circuit during described programming pulse applies operation described in control to perform
Described pass through/unsuccessfully check operation.
Semiconductor memory devices the most according to claim 8, in wherein said multiple page buffers each
Described pass through/unsuccessfully check operation during the data sensed during described verification operation are exported described in pass through/failure
Check circuit.
10. an operational approach for semiconductor memory devices, described operational approach includes:
Programming pulse is applied to the memory cell chosen in multiple memory cell；
By the data of memory cell chosen described in sensing, the described memory cell chosen is performed verification operation；
Result based on described verification operation resets described programming pulse and the programming pulse of replacement is applied to described choosing
In memory cell；And
In the programming pulse applying described replacement, utilize the data that sense during described verification operation perform to pass through/
Failure checks operation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020140178426A KR20160071120A (en) | 2014-12-11 | 2014-12-11 | Semiconductor memory device and operating method thereof |
| KR10-2014-0178426 | 2014-12-11 |
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| Publication Number | Publication Date |
|---|---|
| CN106205696A true CN106205696A (en) | 2016-12-07 |
| CN106205696B CN106205696B (en) | 2020-09-22 |
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|---|---|
| US (1) | US9455044B2 (en) |
| KR (1) | KR20160071120A (en) |
| CN (1) | CN106205696B (en) |
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| CN110875066A (en) * | 2018-09-03 | 2020-03-10 | 爱思开海力士有限公司 | Semiconductor device and semiconductor system including the same |
| CN111145822A (en) * | 2018-11-02 | 2020-05-12 | 爱思开海力士有限公司 | Memory device and memory system including the same |
| CN111354407A (en) * | 2018-12-24 | 2020-06-30 | 爱思开海力士有限公司 | Semiconductor memory device and method of operating the same |
| CN111599400A (en) * | 2020-04-08 | 2020-08-28 | 长江存储科技有限责任公司 | Failure bit number statistical method and memory device |
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| KR102314135B1 (en) * | 2015-06-22 | 2021-10-18 | 삼성전자 주식회사 | Flash memory device performing adaptive loop, Memory system and Operating method thereof |
| US11437094B2 (en) * | 2015-08-13 | 2022-09-06 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, storage device, and operation method of storage device |
| KR102615659B1 (en) * | 2016-07-08 | 2023-12-20 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
| JP6356837B1 (en) * | 2017-01-13 | 2018-07-11 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor memory device and reading method |
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| KR102528274B1 (en) | 2018-11-06 | 2023-05-02 | 삼성전자주식회사 | Nonvolatile memory device and method for operating thereof |
| KR102693232B1 (en) * | 2019-06-03 | 2024-08-09 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method for operating thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN106205696B (en) | 2020-09-22 |
| US20160172050A1 (en) | 2016-06-16 |
| US9455044B2 (en) | 2016-09-27 |
| KR20160071120A (en) | 2016-06-21 |
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