CN106409335B - Content addressable memory cell circuit and its search and write operation method, memory - Google Patents
Content addressable memory cell circuit and its search and write operation method, memory Download PDFInfo
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- CN106409335B CN106409335B CN201510465735.6A CN201510465735A CN106409335B CN 106409335 B CN106409335 B CN 106409335B CN 201510465735 A CN201510465735 A CN 201510465735A CN 106409335 B CN106409335 B CN 106409335B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
- G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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Abstract
The invention discloses a kind of content addressable memory cell circuit and its search and write operation methods, memory.The present invention includes: the first and second memristor, search signal wire, write signal line, matched line, output line, the first and second data line, public pressure wire, the first, second, and third transistor；First memristor and the second memristor are connected, and connecting place is dividing point；First memristor is connected with the first data line, and the second memristor is connected with the second data line；Dividing point, public pressure wire and write signal line are connected with the first transistor, and the output of write signal line is for controlling conducting and disconnection between dividing point and public pressure wire；Dividing point, search signal wire, third transistor are connected with second transistor respectively, search for the output of signal wire for controlling conducting and disconnection between dividing point and third transistor；Matched line, output line and second transistor are connected with third transistor respectively, and the output of second transistor is for controlling the conducting and disconnection of matched line and output line.
Description
Technical field
The present invention relates to analog circuit field more particularly to a kind of content addressable memory cell circuit and its search and write behaviour
Make method, memory.
Background technique
Content Addressable Memory (full name in English: Content Addressable Memory, abbreviation: CAM) is a kind of
Special storage array.It is judged rapidly by being compared all data item stored in input data and CAM simultaneously
Whether input data matches with the storing data item in CAM, and provides the corresponding address and match information of matched data item.
CAM is to be widely used in the fields such as telecommunication, network the features such as its high-speed searching, large capacity.
Memristor is the 4th kind of basic circuit elements in addition to resistance, capacitor, inductance, it represents charge and magnetic flux
Relationship between amount.The resistance of memristor can with by the magnitude of current change, even if electric current stop, the resistance of memristor is still
Value before so resting on, until receiving reversed electric current, it can be just pushed back.The high-impedance state and low resistance state of memristor
It can be used to store " 0 " and " 1 ", be stored for information, have many advantages, such as non-volatile, low-power consumption, high speed, high integration.It will
Memristor and CAM combine, and the storage material of CAM is served as with memristor, and CAM can be made to remain to save data during power down,
Its power consumption is greatly lowered.
Referring to Fig. 1, Fig. 1 is a kind of existing structural schematic diagram of the content storage unit based on memristor.Such as Fig. 1 institute
Show, the source electrode and drain electrode of metal-oxide-semiconductor T5, T3, T4, T6 are sequentially connected in series, wherein the source electrode of T5 is connected with data line D/S, the drain electrode of T6
And data lineIt is connected.T5 is connected with search data line SS respectively with the grid of T6.The grid of T3 simultaneously and the source electrode of T1,
One end of memristor 2 is connected.The grid of T4 is connected with one end of the source electrode of T2, memristor 3 simultaneously.The grid of T1 and the grid of T2
It is connected respectively with write signal line WS.The drain electrode of T1 is connected with data line D/S, and the drain electrode of T2 is connected with data line.Memristor 2 it is another
One end is connected with public pressure wire VL respectively with the other end of memristor 3.Matched line ML and output line ML (n+1) is respectively and MOS
The source electrode and drain electrode of pipe T7 is connected, and the grid of T7 is connected with the source electrode of the drain electrode of T3, T4 simultaneously.
The course of work of circuit shown in Fig. 1 is described below.
In write operation, signal wire SS input low level is searched for, so that metal-oxide-semiconductor T5 and T6 end.Write signal line WS input
High level so that metal-oxide-semiconductor T1 and T2 be connected, at this time data line D/S andChange memristor 2 and 3 by metal-oxide-semiconductor T1 and T2
Resistance value, to carry out write operation storing data.
In read operation, write signal line WS input low level, so that metal-oxide-semiconductor T1 and T2 end.Search for signal wire SS input
High level, so that metal-oxide-semiconductor T5 and T6 are connected.The current potential of public pressure wire VL is set as VDD/2.According to what is be stored in front of memristor
Data (being indicated with high low resistance) come determine metal-oxide-semiconductor T3 or T4 be connected.If T3 conducting if metal-oxide-semiconductor T7 grid current potential just
For the voltage on data line D/S, the current potential of the grid of metal-oxide-semiconductor T7 is data line if T4 conductingOn voltage.To sum up institute
It states, when the voltage of memristor storage is consistent with the voltage on data line, then the voltage of metal-oxide-semiconductor T7 grid is high level, metal-oxide-semiconductor T7
Conducting ML (n) end electric current can be transmitted to ML (n+1) end, it is on the contrary then cannot.
However, the metal-oxide-semiconductor used is more in this kind of circuit arrangement so that wiring is complicated, increase system power consumption and
Manufacturing cost.
Summary of the invention
The embodiment of the invention provides a kind of simple content addressable memory cell circuits of structure.
In a first aspect, providing a kind of content addressable memory cell circuit, the circuit includes: the first memristor ME1, second
Memristor ME2, search signal wire SS, write signal line WS, matched line WL, output line OP, the first data line D/S, the second data linePublic pressure wire VL, the first transistor M1, second transistor M2, third transistor M3；
One end of the first memristor ME1 is connected with one end of the second memristor ME2, and connecting place is partial pressure
Point；The other end of the first memristor ME1 is connected with the first data line D/S, the other end of the second memristor ME2
With second data lineIt is connected；
The dividing point, the public pressure wire VL and the write signal line WS respectively with the first transistor M1 phase
Even, the output of the write signal line WS is for controlling conducting and disconnection between the dividing point and the public pressure wire VL；
The dividing point, described search signal wire SS, the third transistor M3 respectively with the second transistor M2 phase
Even, the output of described search signal wire is for controlling conducting and disconnection between the dividing point and the third transistor M3；
The matched line WL, the output line and the second transistor M2 are connected with the third transistor M3 respectively,
The output of the second transistor M2 is for controlling the conducting and disconnection of the matched line WL Yu the output line.
With reference to first aspect, in the first implementation of first aspect, the circuit further includes the 4th transistor M,
For being connected with the matched line WL and the output line, for control the conducting of the matched line WL and the output line OP with
It disconnects.
With reference to first aspect, in second of implementation of first aspect, the anode of the first memristor ME1 and institute
The anode for stating the second memristor ME2 is connected, alternatively, the negative terminal of the first memristor ME1 and the second memristor ME2's is negative
End is connected.
With reference to first aspect, in the third implementation of first aspect, the anode of the first memristor ME1 and institute
It states the second memristor ME2 negative terminal to be connected, alternatively, the negative terminal of the first memristor ME1 and the second memristor ME2 anode phase
Even.
Second aspect provides a kind of memory, which is characterized in that including content addressed storage as described in any one of the above embodiments
Element circuit.
The third aspect provides a kind of write operation method based on content addressable memory cell circuit described in first aspect,
The described method includes:
Input voltage is to described search signal wire SS, so that the dividing point and the third transistor M3's is separated；
Input voltage is to the write signal line WS, so that being connected between the dividing point and the public pressure wire VL；
Input voltage is distinguished to the first data line D/S and the second data lineAnd pass through the public pressure wire
Input voltage is to the dividing point, so that one of resistance value in the first memristor ME1 and the second memristor ME2
Greater than the preset times of another resistance value, wherein the preset times are greater than 1 times.
In conjunction with the third aspect, in the first implementation of the third aspect, in the content addressable memory cell circuit,
The anode of the first memristor ME1 is connected with the anode of the second memristor ME2, alternatively, the first memristor ME1
Negative terminal is connected with the negative terminal of the second memristor ME2；
The first data line D/S, the public pressure wire VL, second data lineOn voltage successively reduce
Or it successively increases.
In conjunction with the first implementation of the third aspect, in second of implementation of the third aspect, the common electrical
Voltage on crimping VL is voltage and second data line on the first data line D/SOn voltage be averaged
Value.
In conjunction with the third aspect, in the third implementation of the third aspect, the anode of the first memristor ME1 and institute
It states the second memristor ME2 negative terminal to be connected, alternatively, the negative terminal of the first memristor ME1 and the second memristor ME2 anode phase
Even；
The first data line D/S and second data lineOn voltage be all larger than or respectively less than described public
Voltage on pressure-wire VL.
Fourth aspect provides a kind of search operation side based on content addressable memory cell circuit described in first aspect
Method, which comprises
Input voltage is to the write signal line WS, so that the dividing point and the public pressure wire VL's is separated；
Input high level is to the matched line WL；
Input voltage is distinguished to the first data line D/S and the second data lineWherein the first data line D/S
With the second data lineThe voltage of one of them be high level, another voltage is low level, so that the dividing point A
Place forms high level or low level；
Input voltage is to described search signal wire SS, so that being connected between the dividing point and the third transistor M3；
When the output line OP exports high level, the number for reading the content addressable memory cell circuit storage is determined
According to one between 0 and 1, otherwise determine the data for reading the content addressable memory cell circuit storage between 0 and 1
Another.
In conjunction with fourth aspect, in the first implementation of fourth aspect, the input voltage to described search signal
Line SS, so that being connected between the dividing point and the third transistor M3, before further include:
Input voltage is to described search signal wire SS, so that the dividing point and the third transistor M3's is separated.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that
In the present invention, the structural wiring of content addressable memory cell circuit is simple, reduces content addressable memory cell electricity
The power consumption and cost of manufacture on road.
Detailed description of the invention
Fig. 1 is a kind of existing structural schematic diagram of content addressable memory cell circuit；
Fig. 2 is a kind of structural schematic diagram of embodiment of contents of the present invention addressable memory cell circuit；
Fig. 3 is the flow diagram of the write operation based on content addressable memory cell circuit shown in Fig. 2；
Fig. 4 is the flow diagram of the search operation based on content addressable memory cell circuit shown in Fig. 2.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
Term " includes " in description and claims of this specification and above-mentioned attached drawing and " having " and they
Any deformation, it is intended that cover it is non-exclusive include, for example, containing the process, method of a series of steps or units, being
System, product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include be not clearly listed or
For the intrinsic other step or units of these process, method, system, product or equipment.
As shown in Fig. 2, Fig. 2 is a kind of structural schematic diagram of embodiment of contents of the present invention addressable memory cell circuit.
As shown in Fig. 2, the element circuit in the present embodiment includes the first memristor ME1, the second memristor ME2, search letter
Number line SS, write signal line WS, matched line WL, output line, the first data line D/S, the second data linePublic pressure wire VL,
The first transistor M1, second transistor M2, third transistor M3.
One end of the first memristor ME1 is connected with one end of the second memristor ME2.For convenience of description, by
The connecting place of one memristor ME1 and the second memristor ME2 are known as dividing point A.The other end of the first memristor ME1 with it is described
First data line D/S is connected, the other end and second data line of the second memristor ME2It is connected.
The dividing point A, the public pressure wire VL and the write signal line WS respectively with the first transistor M1 phase
Even, the output of the write signal line WS is for controlling conducting and disconnection between the dividing point A and the public pressure wire VL.
The dividing point A, described search signal wire SS, the third transistor M3 respectively with the second transistor M2 phase
Even, the output of described search signal wire SS leads through and off between the dividing point A and the third transistor M3 for controlling
It opens.
The matched line WL, the output line and the second transistor M2 are connected with the third transistor M3 respectively,
The output of the second transistor M2 is for controlling the conducting and disconnection of the matched line WL Yu the output line.
In the present embodiment, there are many frame modes that the first memristor ME1 is connected with the second memristor ME2.
For example, the first memristor ME1 is connected with the second memristor ME2 phase the same end.As shown in Fig. 2, memristor
Device has one end of black surround to be known as negative terminal, and the other end is known as anode.In Fig. 2, the anode of the first memristor ME1 and described the
The anode of two memristor ME2 is connected.Alternatively, the negative terminal and described second for being also possible to the first memristor ME1 are recalled in practical application
The negative terminal for hindering device ME2 is connected.
For example, one end the first memristor ME1 different with the second memristor ME2 is connected.First data
Line D/S and second data lineOn voltage be all larger than or the respectively less than described public pressure wire VL on voltage.This
Sample, the direction of the potential difference formed between the first data line D/S to dividing point A, with dividing point A to the second data line
Between formed potential difference it is contrary.Since the first memristor ME1 and the second memristor ME2 different one end is connected, that
The potential difference of opposite direction can make the resistance of one of memristor become larger, so that the resistance of another memristor becomes smaller.
Optionally, in the present embodiment, the circuit further includes the 4th transistor M, for the matched line WL and described
Output line OP is connected, for controlling the conducting and disconnection of the matched line WL Yu the output line OP.In this manner it is achieved that circuit
Tri-state function.Specifically, input high level is to the matched line WL；Input voltage is to the 4th transistor M, so that described
It is connected between matched line WL and the output line.In this way, output line OP can directly export high level.
For example, when the 4th transistor M is metal-oxide-semiconductor, the source electrode and drain electrode of the 4th metal-oxide-semiconductor M respectively with matched line WL and defeated
Outlet OP is connected.The grid of input high level to the 4th metal-oxide-semiconductor M export so that being connected between matched line WL and the output line
Line OP directly exports high level.
In the present embodiment, transistor can be field-effect tube, triode or other transistors, and this is not restricted.For
Facilitate understanding, the circuit structure in the present embodiment is described in detail by taking metal-oxide-semiconductor as an example below.
Specifically, the grid of the first metal-oxide-semiconductor M1 is connected with write signal line WS, source electrode is connected with public pressure wire VL, drain electrode
It is connected with dividing point A.The grid of second metal-oxide-semiconductor M2 is connected with search signal wire SS, and source electrode is connected with dividing point A, drains and the
The grid of three metal-oxide-semiconductor M3 is connected.The drain electrode of third metal-oxide-semiconductor M3 is connected with matched line WL, and source electrode is connected with output line.
The operating method of content addressable memory cell circuit shown in Fig. 2 includes write operation and search operation.Below to Fig. 2
The write operation workflow of shown circuit is described.
As shown in figure 3, Fig. 3 is the flow diagram of the write operation based on content addressable memory cell circuit shown in Fig. 2.This
In embodiment, which includes:
301, input voltage is to described search signal wire SS, so that dividing point A's and third transistor M3 is separated.
Specifically, input low level is to search signal wire SS, so that the 2nd NMOS when second transistor M2 is NMOS tube
The source electrode and drain electrode of pipe M2 it is separated so that dividing point A's and third transistor M3 is separated.
302, input voltage is to the write signal line WS, so that being connected between dividing point A and public pressure wire VL.
Specifically, when the first transistor M1 is NMOS tube, input high level to write signal line WS, so that the first NMOS tube
It is connected between the source electrode and drain electrode of M1, in this way, the voltage of public pressure wire VL can live the voltage clamp of dividing point A.
303, input voltage is distinguished to the first data line D/S, the second data lineAnd electricity is inputted by public pressure wire
It is depressed into dividing point A, so that one of resistance value in the first memristor ME1 and the second memristor ME2 is greater than another
The preset times of a resistance value, wherein the preset times are greater than 1 times.
In the present embodiment, memristor is defined as according to memristor resistance difference to represent different logical values.For example, when recalling
When hindering the resistance value of device higher than the first default value, memristor is defined as to represent logical zero, when the resistance value of memristor is lower than second
When default value, memristor is defined as to represent logical one.Alternatively, when the resistance value of memristor is higher than the first default value, it will
Memristor is defined as representing logical one, when the resistance value of memristor is lower than the second default value, memristor is defined as representing and is patrolled
It collects " 0 ".Wherein, the first default value is greater than the second default value.In this way, working as the first memristor M1 and the second memristor M2 table
When showing " 10 ", one between 0 and 1 of the data stored in content addressable memory cell circuit, as the first memristor M1 and the
When two memristor M2 indicate " 01 ", another between 0 and 1 of the data stored in content addressable memory cell circuit.
Below to indicate logical zero when the resistance value of memristor is higher than the first default value, when the resistance value of memristor is lower than
Logical one is indicated when the second default value, and when the first memristor M1 and the second memristor M2 expression " 01 ", content addressed storage
The data stored in element circuit are described for being 0.
Specifically, the first memristor M1 and the second memristor M2 respectively include anode and negative terminal, wherein the first memristor M1
Anode and the second memristor M2 anode be connected, alternatively, the negative terminal phase of the negative terminal of the first memristor M1 and the second memristor M2
Even.The first data line D/S, the public pressure wire VL, second data lineOn voltage successively reduce or
Successively increase.For example, the voltage on public pressure wire VL is voltage and second data line on the first data line D/SOn voltage average value.
Since the potential difference and dividing point A of the first data line D/S to dividing point A is to the second data linePotential difference
Direction it is identical, and the anode of the first memristor M1 and second resistor M2 be directed toward negative terminal it is contrary, therefore, the first memristor
Device M1 forms high resistance, and the second memristor M2, which forms low resistance namely the first memristor M1, indicates logical zero, the second memristor
M2 indicates logical one, data " 0 " is written in content addressed storage unit circuit.Alternatively, the first memristor M1 forms low electricity
Resistance, the second memristor M2 forms high resistance namely the first memristor M1 indicates that logical one, the second memristor M2 indicate logic
" 0 ", data " 1 to be written in content addressed storage unit circuit.
Make a reservation for it is noted that pressure difference of the resistance of the memristor in the present embodiment only at the both ends of the memristor is greater than
Can just it change when numerical value.Therefore, in the present embodiment, the first data line D/S, the public pressure wire VL, second number
According to lineOn the size of voltage the first memristor M1 and the resistance value of the second memristor M2 need to be enabled to change, and
And it needs so that the resistance value of one of them in the first memristor M1 and the second memristor M2 is greater than preset times of another resistance value
Number, wherein the preset times are greater than 1 times, and (specific value of concrete reason and preset times carries out in the embodiment shown in fig. 4
It explains.)
Certainly, in practical application, the voltage of the voltage of public pressure wire input can also not have to be located at the first data line D/S
The voltage of input and the second data lineBetween the voltage of input, as long as making the first memristor and the second memristor both ends
Pressure difference it is contrary, and the pressure difference at the first both ends memristor ME1 and the pressure difference at the second both ends memristor ME2 make this two to recall
The one of resistance value for hindering device is greater than the preset times of another resistance value.
For example, when the anode of the first memristor M1 and the negative terminal of the second memristor M2 is connected or the first memristor M1
When the anode of negative terminal and the second memristor M2 are connected, and the first data line D/S and second data lineOn electricity
Pressure be all larger than or the respectively less than described public pressure wire VL on voltage when, due to the first memristor M1 and the second memristor M2 two
The direction that the anode of person is directed toward negative terminal is identical, and the both ends pressure difference of both first memristor M1 and the second memristor M2 on the contrary, because
This, the resistance value of one of them in the first memristor M1 and the second memristor M2 is greater than another resistance value.Certainly, the first memristor
The pressure difference at the both ends device M1 and the pressure difference at the second both ends memristor M2 need to be sufficiently large, to make the resistance value of the first memristor M1 respectively
It changes with the resistance value in the second memristor M2.
As shown in figure 4, Fig. 4 is the flow diagram of the search operation based on content addressable memory cell circuit shown in Fig. 2.
In the present embodiment, which includes:
401, input voltage is to the write signal line WS, so that dividing point A's and public pressure wire VL is separated.
In the present embodiment, by being read out to the data stored in content addressed storage unit circuit, without
It is write-in, therefore first by the separated of dividing point A and public pressure wire VL, to avoid write-in data.
Specifically, input low level is to write signal line WS, so that the first transistor when the first transistor M1 is NMOS tube
The source electrode and drain electrode of M1 it is separated so that dividing point A's and public pressure wire VL is separated.
402, input high level is to the matched line WL.
Matched line WL input high level.Third transistor M3 is controlled and is led on and off between this matched line WL and output line OP
It opens.When closed, output line OP exports high level, and upon opening, output line OP exports low level.It is possible to use output line
OP output high level indicates that the data read are consistent with the data of search, and output low level indicates the data and search that read
Data it is inconsistent.Alternatively, indicating that the data read are inconsistent with output line OP output high level, output low level indicates to read
The data got are consistent with the data of search, and this is not restricted.
403, input voltage is distinguished to the first data line D/S and the second data lineWherein first data line
D/S and the second data lineThe voltage of one of them be high level, another voltage is low level, so that the partial pressure
High level or low level are formed at point A.
In the present embodiment, input high level to the first data line D/S can be used, and input low level is to the second data lineIt whether is 1 to indicate to search the data stored in the plain content addressable memory cell circuit, with input low level to the first number
According to line D/S, and input high level is to the second data lineIt is stored in the plain content addressable memory cell circuit to indicate to search
Whether data are 0.Alternatively, be also possible to input high level to the first data line D/S, and input low level is to the second data lineIt whether is 0 to indicate to search the data stored in the plain content addressable memory cell circuit, with input low level to the first number
According to line D/S, and input high level is to the second data lineIt is stored in the plain content addressable memory cell circuit to indicate to search
Whether data are 1, and this is not restricted.
In the present embodiment, pass through input voltage to the first data line D/S and the second data lineSo that dividing point A
Place forms voltage, and the voltage (for high level or low level) at dividing point A determines third transistor conducting or disconnects.
And since the resistance value of one of them in the first memristor M1 and the second memristor M2 is greater than the preset times of another resistance value, because
This can be by the first data line D/S and the second data lineVoltage setting so that the voltage at dividing point A
For high level or low level.
It is noted that due to the first data line D/S and the second data lineVoltage be for reading of content
Data in addressable memory cell circuit, therefore, the first data line D/S and the second data lineOn voltage make this
Pressure difference between two data lines does not change the resistance value of the first memristor M1 and the second memristor M2.
404, input voltage is to described search signal wire SS, so that leading between the dividing point and the third transistor M3
It is logical.
In the present embodiment, is connected between dividing point A and third transistor M3 by making, is determined by the voltage of dividing point A
Determining third transistor M3 is conducting or disconnects, namely determines that the high level on matched line WL whether may be used by the voltage of dividing point A
To be exported by output line OP.
Specifically, input high level is to searching for signal wire when second transistor M2 and third transistor M3 is NMOS tube
SS, so that being connected between the source electrode and drain electrode of second transistor M2, so that being led between dividing point A and third transistor M3
It is logical, so that the grid for clicking and entering input third NMOS tube M3 of dividing point A.
405, when the output line OP exports the high level, determination reads the content addressable memory cell circuit
Otherwise one between 0 and 1 of the data of storage determines that the data for reading the content addressable memory cell circuit storage are
Another between 0 and 1.
Content addressable memory cell electricity is indicated by high value of the first memristor and when the second memristor is low resistance below
The data of road storage are 0, and the voltage of the first data line D/S input is low level, the second data lineThe voltage of input is
Indicate that the data 0 of search carry out citing description when high level.
The resistance value of the first memristor is greater than the resistance value of the second memristor in the content addressable memory cell circuit shown in Fig. 2
When preset times (namely the data stored in content addressable memory cell circuit are 0):
If the first data line D/S input low level, the second data lineInput high level (namely the data to be searched for are
0), then the voltage at dividing point A is high level, therefore the 3rd NMOSM3 is connected, and output line OP exports high level, namely works as and search
The data stored in the data and content addressable memory cell circuit of rope export high level when identical.
If the first data line D/S input high level, the second data lineInput low level (namely the data to be searched for are
1), then the voltage at dividing point A is low level, therefore third NMOS tube M3 is disconnected, and output line OP exports low level, namely works as
The data stored in the data and content addressable memory cell circuit of search export low level when not identical.
It can be seen that during the above-mentioned search work of content addressable memory cell circuit shown in Fig. 2, need shape at dividing point A
When at high level, wherein the specific voltage of the high level needs that low level need to be formed at dividing point A so that third NMOS tube M3 is connected
When, which needs so that third NMOS tube M3 is disconnected.And the voltage specifically formed at dividing point A is decided by
The resistance value difference of one memristor ME1 and the second memristor ME2, therefore, as long as the specific setting of preset times makes at dividing point A
The voltage when high level of formation is higher than third NMOS tube M3 conduction threshold, and the voltage when low level of formation is lower than the 3rd NMOS
The conduction threshold of pipe M3.Similarly, when third transistor is not NMOS tube but other transistors, the setting of preset times
Principle is same as above.
Optionally, in the present embodiment, in step 404 input voltage to described search signal wire SS, so that the dividing point
It is connected between the third transistor M3, before further include: input voltage to described search signal wire SS, so that the partial pressure
Point is separated with the third transistor M3's.In this way, partial pressure is connected again after can first allowing the voltage stabilization at dividing point to get off
Point and the third transistor M3.
The present invention also provides a kind of memory, the memory include it is described herein any one content addressed deposit
Storage unit circuit.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the present invention
Portion or part steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can store journey
The medium of sequence code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (11)
1. a kind of content addressable memory cell circuit, which is characterized in that the circuit includes: the first memristor ME1, the second memristor
Device ME2, search signal wire SS, write signal line WS, matched line WL, output line OP, the first data line D/S, the second data line
Public pressure wire VL, the first transistor M1, second transistor M2, third transistor M3；
One end of the first memristor ME1 is connected with one end of the second memristor ME2, and connecting place is dividing point；Institute
The other end for stating the first memristor ME1 is connected with the first data line D/S, the other end of the second memristor ME2 and institute
State the second data lineIt is connected；
The dividing point, the public pressure wire VL and the write signal line WS are connected with the first transistor M1 respectively, institute
The output of write signal line WS is stated for controlling conducting and disconnection between the dividing point and the public pressure wire VL；
The dividing point, described search signal wire SS, the third transistor M3 are connected with the second transistor M2 respectively, institute
The output of search signal wire is stated for controlling conducting and disconnection between the dividing point and the third transistor M3；
The matched line WL, the output line and the second transistor M2 are connected with the third transistor M3 respectively, described
The output of second transistor M2 is for controlling the conducting and disconnection of the matched line WL Yu the output line.
2. content addressable memory cell circuit according to claim 1, which is characterized in that
The circuit further includes the 4th transistor M, described for controlling for being connected with the matched line WL and the output line
The conducting and disconnection of matched line WL and the output line OP.
3. content addressable memory cell circuit according to claim 1, which is characterized in that
The anode of the first memristor ME1 is connected with the anode of the second memristor ME2, alternatively, first memristor
The negative terminal of ME1 is connected with the negative terminal of the second memristor ME2.
4. content addressable memory cell circuit according to claim 1, which is characterized in that the first memristor ME1's
Anode is connected with the second memristor ME2 negative terminal, alternatively, the negative terminal and second memristor of the first memristor ME1
ME2 anode is connected.
5. a kind of memory, which is characterized in that including the described in any item content addressable memory cell electricity of such as Claims 1-4
Road.
6. a kind of write operation method based on content addressable memory cell circuit described in claim 1, which is characterized in that described
Method includes:
Input voltage is to described search signal wire SS, so that the dividing point and the third transistor M3's is separated；
Input voltage is to the write signal line WS, so that being connected between the dividing point and the public pressure wire VL；
Input voltage is distinguished to the first data line D/S and the second data lineAnd electricity is inputted by the public pressure wire
It is depressed into the dividing point, so that one of resistance value in the first memristor ME1 and the second memristor ME2 is greater than separately
The preset times of one resistance value, wherein the preset times are greater than 1 times.
7. write operation method according to claim 6, which is characterized in that in the content addressable memory cell circuit, institute
The anode for stating the first memristor ME1 is connected with the anode of the second memristor ME2, alternatively, the first memristor ME1's is negative
End is connected with the negative terminal of the second memristor ME2；
The first data line D/S, the public pressure wire VL, second data lineOn voltage successively reduce or
Successively increase.
8. write operation method according to claim 7, which is characterized in that the voltage on the public pressure wire VL is described
Voltage and second data line on first data line D/SOn voltage average value.
9. write operation method according to claim 6, which is characterized in that the anode of the first memristor ME1 and described
Second memristor ME2 negative terminal is connected, alternatively, the negative terminal of the first memristor ME1 and the second memristor ME2 anode phase
Even；
The first data line D/S and second data lineOn voltage be all larger than or the respectively less than described common voltage
Voltage on line VL.
10. a kind of search operation method based on content addressable memory cell circuit described in claim 1, which is characterized in that
The described method includes:
Input voltage is to the write signal line WS, so that the dividing point and the public pressure wire VL's is separated；
Input high level is to the matched line WL；
Input voltage is distinguished to the first data line D/S and the second data lineWherein the first data line D/S and
Two data linesThe voltage of one of them be high level, another voltage is low level, so that shape at the dividing point
At high level or low level；
Input voltage is to described search signal wire SS, so that being connected between the dividing point and the third transistor M3；
When the output line OP exports high level, determine that the data for reading the content addressable memory cell circuit storage are
One between 0 and 1, otherwise determine that the data for reading the content addressable memory cell circuit storage are another between 0 and 1
One.
11. search operation method according to claim 10, which is characterized in that the input voltage to described search signal
Line SS, so that being connected between the dividing point and the third transistor M3, before further include:
Input voltage is to described search signal wire SS, so that the dividing point and the third transistor M3's is separated.
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| CN201510465735.6A CN106409335B (en) | 2015-07-31 | 2015-07-31 | Content addressable memory cell circuit and its search and write operation method, memory |
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| CN201510465735.6A CN106409335B (en) | 2015-07-31 | 2015-07-31 | Content addressable memory cell circuit and its search and write operation method, memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019019920A1 (en) * | 2017-07-26 | 2019-01-31 | The Hong Kong University Of Science And Technology | Hybrid memristor/field-effect transistor memory cell and its information encoding scheme |
| CN107545922B (en) * | 2017-09-12 | 2020-07-14 | 中国联合网络通信集团有限公司 | Content address storage unit circuit, write operation method thereof and memory |
| CN108962316B (en) * | 2018-06-25 | 2020-09-08 | 华中科技大学 | Content addressable memory unit based on memristor and CMOS and data search matching method |
| US10998047B1 (en) * | 2020-01-15 | 2021-05-04 | Hewlett Packard Enterprise Development Lp | Methods and systems for an analog CAM with fuzzy search |
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