CN109786393A - 集成电路 - Google Patents

集成电路 Download PDF

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CN109786393A
CN109786393A CN201810300232.7A CN201810300232A CN109786393A CN 109786393 A CN109786393 A CN 109786393A CN 201810300232 A CN201810300232 A CN 201810300232A CN 109786393 A CN109786393 A CN 109786393A
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deep trench
semiconductor
layer
active region
area
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颜于华
高境鸿
王柏仁
蔡宗翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路包含一半导体基底、一隔离区、一第一主动元件以及至少一深沟槽隔离结构。隔离区是位于半导体基底中。第一主动元件是位于半导体基底上。深沟槽隔离结构从隔离区的一底部朝向半导体基底的一底部延伸。深沟槽隔离结构具有至少一气隙于其中。

Description

集成电路
技术领域
本揭露是关于一种半导体元件，特别是关于一种集成电路与其深沟槽隔离结构。
背景技术
集成电路是形成于半导体基底(通常为硅基底)的表面上。多个半导体元件可通过多个隔离结构所相互隔离。这些隔离结构是形成在靠近半导体基底的表面的位置。隔离结构包含场氧化区以及浅沟槽隔离区。
来自信号输入端(如天线)的射频电流是通过半导体基底与隔离结构耦合的。在半导体基底与隔离结构中的耦合电流可能会对在输出端与输入端之间的输出元件(例如低噪声放大器(low noise amplifier；LNA)及功率放大器(power amplifier；PA))产生不必要的电阻与电容。然而，在集成电路的微缩中，要再提供额外的空间给更多的隔离结构是相当困难的。举例来说，制造成本将会因此增加，且更大的隔离结构可能会对元件的操作速度有不良的影响。
发明内容
在一些实施方式中，一种集成电路包含一半导体基底、一隔离区、一第一主动元件以及至少一深沟槽隔离结构。隔离区是位于半导体基底中。第一主动元件是位于半导体基底上。深沟槽隔离结构从隔离区的一底部朝向半导体基底的一底部延伸。深沟槽隔离结构具有至少一气隙于其中。
附图说明
本揭露的态样可从以下的详细说明及随附的附图理解。值得注意的是，根据产业上的实际应用，各个特征并未按照比例绘制，事实上，各个特征的尺寸可以任意的放大或缩小，以利清楚地说明。
图1为本揭露一些实施方式的在半导体元件中形成深沟槽隔离结构的方法的流程图；
图2至图13为依据本揭露一些实施方式的制造深沟槽隔离结构的过程中，半导体元件在不同阶段的剖面图及上视图。
具体实施方式
以下提供本揭露的多种不同的实施方式或实施例，以实现本揭露的不同技术特征。元件的实施方式和配置是如下所述以简化本揭露。当然，这些叙述仅为示例，而非用以限制本揭露。举例而言，第一特征是形成于第二特征上的叙述可包括第一特征与第二特征是直接接触的实施方式，亦可包括额外特征形成于第一与第二特征之间的实施方式，使得第一特征与第二特征可非直接接触。此外，本揭露可重复地使用元件符号于多个实施方式中。此重复是为了简洁，并非用以讨论各个实施方式及/或配置之间的关系。
此外，空间相对用语，如“下”、“下方”、“低”、“上”、“上方”等，是用以方便描述一元件或特征与其他元件或特征在附图中的相对关系。除了附图中所示的方位以外，这些空间相对用语亦可用来帮助理解元件在使用或操作时的不同方位。当元件被转向其他方位(例如旋转90度或其他方位)时，本文所使用的空间相对叙述亦可帮助理解。
来自输入端的射频电流会通过等效电阻与电容耦合通过半导体基底与介电层，因而在输出端产生不理想的输出。此噪声(射频电流)可通过不同方式来降低。其中一种方式为扩大隔离区，但元件尺寸或主动区尺寸则会因应隔离区的扩大而有所让步。通过增加深沟槽隔离结构于既有的隔离区中，可显著地降低从半导体基底所量测到的噪声。深沟槽隔离结构不仅包含常规的介电材料，还可包含气隙于其中。此气隙的介电常数大约为1。
图1绘示方法100的流程图，其中方法100为依据本揭露一些实施方式的半导体元件的制造方法。在步骤110中，一隔离区是形成于半导体基底的复数主动区之间。接着，在步骤120中，至少一深沟槽被形成，此深沟槽从隔离区朝向半导体基底的一底部延伸。接着，在步骤130中，层间介电层是形成于半导体基底上，此层间介电层会填满深沟槽以形成深沟槽隔离结构。下文中将讨论依据图1的方法100所形成的半导体元件的一些实施方式。虽然本文中的方法100是描述为一连串的步骤或制程，但应了解到本揭露的范围并不局限于这些步骤或制程的顺序。举例来说，在下文中所描述的步骤中，一些步骤的顺序可与文中所述不同，或者同时发生。此外，并非下文中的所有步骤都是必须的。此外，下文中的步骤可通过一或多个制程所实现。
图2绘示半导体基底18的剖面图。半导体基底18具有绝缘体上半导体(semiconductor-on-insulator；SOI)结构。半导体层20是位于埋入式(buried)绝缘层22上。当埋入式绝缘层22是由介电氧化物所形成时，埋入式绝缘层22可为埋入式氧化物(buried oxide；BOX)层。埋入式绝缘层22是位于处理基底(handle substrate)24上。半导体基底18的垂直堆叠由下而上地包含处理基底24、埋入式绝缘层22、及位于埋入式绝缘层22的上表面上的半导体层20。在一些实施方式中，半导体基底18还包含缓冲层。在一些其他实施方式中，半导体基底18是由半导体块材(bulk semiconductor material)所形成的，例如硅。
处理基底24包含第一半导体材料。此第一半导体材料可为，但不限于，硅、锗、硅锗、硅碳、硅锗碳、砷化镓、砷化铟、磷化铟、三五族(III-V)化合物半导体材料、二六族(II-VI)化合物半导体材料、有机半导体材料、其他半导体材料、或相似物。此外，处理基底24的材料可为单晶材料，例如半导体磊晶材料。
埋入式绝缘层22可为介电材料层，例如，但不限于，硅氧化物。埋入式氧化层的下表面接触处理基底24的上表面。半导体层20包含第二半导体材料。此第二半导体材料可为，但不限于，硅、锗、硅锗、硅碳、硅锗碳、砷化镓、砷化铟、磷化铟、三五族(III-V)化合物半导体材料、二六族(II-VI)化合物半导体材料、有机半导体材料、其他半导体材料、或相似物。此外，半导体层20的材料可为单晶材料，例如半导体磊晶材料。半导体层20的部分或整体可被局部体或完全地掺杂有p型掺杂物或n型掺杂物以形成主动区。半导体层20的下表面接触埋入式绝缘层22的上表面。
请参阅图3。硬遮罩层36是形成于半导体层20上并被图案化而形成浅沟槽隔离区28的沟槽20t。硬遮罩层36的形成方式可包含沉积一毯覆式的介电材料层、涂布光阻于此介电材料层上，利用曝光显影图案化此光阻以形成多个开口，并通过蚀刻制程移除位于这些开口下方的部分介电材料层。此蚀刻制程可为干蚀刻(例如非等向性离子蚀刻)或湿蚀刻。介电材料层的剩余部分可构成硬遮罩层36。当硬遮罩层36形成时，被硬遮罩层36所覆盖的至少一区域可定义为主动区。硬遮罩层36的图案会被转移至半导体层20。沟槽20t的长度方向是实质上平行的，且沟槽20t是实质上平行于半导体层20中。沟槽20t的深度等于半导体层20的厚度，因此后续形成的浅沟槽隔离区28会接触埋入式绝缘层22。
请参阅图4A及图4B。图4A绘示浅沟槽隔离区28的上视图，其中浅沟槽隔离区是位于半导体层20中。图4B绘示图4A的A-A’线的剖面图。在形成沟槽20t之后，沟槽衬垫30是保形地形成于沟槽20t中。沟槽衬垫30可包含硅氧化物，但其他介电材料亦可用于形成沟槽衬垫30。接着，介电材料32填满沟槽20t的剩余部分。在一些实施方式中，介电材料包含未掺杂氧化材料。介电材料32的填入可通过高密度等离子化学气相沉积(high-density plasmachemical vapor deposition；HDPCVD)所实现。然而，其他适当的方法，例如次大气压化学气相沉积(sub-atmospheric CVD；SACVD)、高深宽比制程(high aspect ratio process；HARP)或旋涂制程等等，亦可用于形成介电材料32。化学机械研磨(chemical mechanicalpolish；CMP)可接着用来移除位于硬遮罩层36上方的剩余介电材料32。接着，硬遮罩层36可被移除，而留下浅沟槽隔离区28于半导体层20中。
在一些实施方式中，浅沟槽隔离区包含两沟槽。如图4A所示，伸长的浅沟槽隔离区28将半导体层20分为不同的区域。在两浅沟槽隔离区28之间的半导体层20可被称为伪主动区21，而半导体层20的剩余区域可被称为第一主动区20a与第二主动区20b。第一主动区20a与第二主动区20b是由浅沟槽隔离区28(包含伪主动区21)所分隔的。
请参阅图5A及图5B，图5A绘示栅极结构38在半导体层20上的形成。图5B绘示图5A的B-B’线的剖面图，如图5A及图5B所示，栅极结构38包含栅极电极342以及位于栅极电极342下方的栅极介电层346。在一些实施方式中，栅极电极342为多晶硅栅极电极。栅极介电层346的材料可为，例如，二氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)介电材料、上述的组合、或相似物。在第一主动区20a上的栅极结构38会形成在第一主动区20a上的最终的金氧半导体(MOS)元件的部分，而在第二主动区20b上的栅极结构38会形成在第二主动区20b上的最终的金氧半导体元件的部分。伪主动区21并非用于形成金氧半导体元件，故无栅极结构。在如图5B所示的一些实施方式中，多个栅极结构38均用于形成p型金氧半导体元件。在其他实施方式中，多个栅极结构38均用于形成n型金氧半导体元件。在其他实施方式中，一栅极结构38是用于形成p型金氧半导体元件，而另一栅极结构38是用于形成n型金氧半导体元件。在一些实施方式中，二或多个主动元件是分别形成于第一主动区20a及第二主动区20b上。栅极结构38与浅沟槽隔离区28的长度方向可实质上平行。这些栅极结构38是通过浅沟槽隔离区28及伪主动区21相互分隔的。这些浅沟槽隔离区28是紧邻于伪主动区21的相对两侧，而使伪主动区21位于浅沟槽隔离区28之间。伪主动区21的面积是小于常规第一主动区20a及第二主动区20b的面积。两浅沟槽隔离区28的边缘几乎彼此接触，使得伪主动区21呈狭缝般地暴露于两浅沟槽隔离区28之间。
请参阅图6。离子植入制程是用以形成轻掺杂漏极(lightly doped drain；LDD)区域352。栅极结构38是用以做为遮罩以帮助控制植入区的轮廓与离子分布。在图6中，轻掺杂漏极区域352是形成于半导体层20中。
请参阅图7。在离子植入制程后，间隔物348是形成以围绕栅极结构38。间隔物材料可先沉积于半导体层20上以覆盖栅极结构38、浅沟槽隔离区28、伪主动区21、及这些元件之间的区域。间隔物材料可接着被回蚀(etch back)以移除位于栅极结构38上方与之间的间隔物材料。通过调整蚀刻制程的参数，围绕栅极结构38的间隔物材料的选定部分会在回蚀后留下。间隔物348是由氮化硅或其他能够被保形地沉积的介电材料所形成的。在一些实施方式中，在形成间隔物348之间，间隔物衬垫(未绘示于图中)可选择性地形成。
请参阅图8。在形成间隔物348后，源/漏区域354可被形成。源/漏区域354是通过植入适当的p型杂质或n型杂质，而形成于半导体层20中的第一主动区20a及第二主动区20b中。第一主动区20a及第二主动区20b可由硅锗、硅碳、或相似物所形成，此材料的选用可取决于欲形成的金氧半导体元件是属于n型或p型。在一些实施方式中，当栅极结构38是用以形成p通道金氧半导体元件时，源/漏区域354是属于p型。在一些实施方式中，当栅极结构38是用以形成n通道金氧半导体元件时，源/漏区域354是属于n型。
请参阅图9。光阻层402是沉积于半导体层20上并被图案化。光罩(未绘示于图中)可被放置于光阻层202上方。光罩与光阻层402接着被暴露于辐射(例如紫外光)中。烘烤或固化步骤可被执行以硬化光阻层402。显影剂接着用以移除光阻的曝光(或未曝光)部分，这是取决于光阻为正光阻或负光阻。接着，图案(如图9所示的图案)可形成。开口402a及402c是位于浅沟槽隔离区28，并分别邻近第一主动区20a及第二主动区20b。开口402a及402c的长度方向是实质上平行于浅沟槽隔离区28。开口402b是位于开口402a与402c之间，并露出伪主动区21及部分的浅沟槽隔离区28。开口402b的宽度是大于伪主动区21的宽度。在一些实施方式中，如图9所示，开口402a、402b、及402c是等距地分隔。在其他实施方式中，开口402a、402b、及402c是被不同的距离分隔的。开口402a、402b、及402c的尺寸可彼此不同。举例来说，开口402b的宽度可大于开口402a的宽度。开口402a、402b、及402c是维持在浅沟槽隔离区28的边界内，且不重叠第一主动区20a及第二主动区20b(源/漏区域354)。由于开口402a、402b、及402c定义欲在后续步骤中所形成的深沟槽隔离区，故开口402a、402b、及402c并不会过度地宽。此沟槽的高深宽比对于在深沟槽隔离结构中形成气隙是具有显著影响的。在一些实施方式中，开口的数量可大于3，且深沟槽的数量也会对应改变。
请参阅图10A及图10B。图10A绘示在半导体基底18中形成深沟槽502a、502b及502c的上视图。图10B绘示图10A的C-C’线的剖面图。蚀刻制程可被执行以移除部分浅沟槽隔离区28、埋入式绝缘层22及处理基底24。在一些实施方式中，位于两浅沟槽隔离区28之间的伪主动区21为完全被此蚀刻制程所移除。在一些实施方式中，伪主动区21是部分地被此蚀刻制程所移除。由于蚀刻的目标材料包含伪主动区21(半导体层20)、浅沟槽隔离区28(沟槽衬垫30)、埋入式绝缘层22及处理基底24，此蚀刻制程可包含不同蚀刻剂。这些材料的不同会造成在蚀刻过程中选用不同的蚀刻剂。此蚀刻制程可针对不同目标重复地执行。
光阻层402中的图案会被转移至下方的层中。开口402a、402b、及402c暴露浅沟槽隔离区28及伪主动区21。在此蚀刻制程中，浅沟槽隔离区28及伪主动区21会先被移除。接着，此蚀刻制程会将开口402a、402b、及402c向下延伸，使得下方的埋入式绝缘层22及部分的处理基底24被移除，从而在半导体基底18中形成深沟槽502a、502b及502c。深沟槽502a、502b及502c的底部位于处理基底24中，如图10B所示。包含两槽状结构的浅沟槽隔离区28会接着被分离成分开的部分，如图10B所示。如图10A所示，浅沟槽隔离区28现在会形成四个条状结构，在深沟槽502a、502b及502c的两侧所延伸。此蚀刻制程亦形成了被深沟槽所分隔的柱状结构，此柱状结构由上到下包含浅沟槽隔离区28、沟槽衬垫30、埋入式绝缘层22及处理基底24。这些柱状结构(包含处理基底24、埋入式绝缘层22及浅沟槽隔离区28)将深沟槽502a、502b及502c隔开。这些柱状结构可共同形成梳状结构，其中深沟槽502a、502b及502c为此梳状结构的底部，而柱状结构为此梳状结构的梳齿。
深沟槽502a、502b及502c从浅沟槽隔离区28朝向处理基底24延伸，并具有比浅沟槽隔离区28更高的深宽比。深沟槽502a、502b及502c的宽度分别与前述的开口402a、402b及402c相同，且深沟槽502a、502b及502c的高度是从浅沟槽隔离区28的顶面量测至处理基底24中的位置。深沟槽502a、502b及502c的宽度小于其高度，以形成由浅沟槽隔离区28向下延伸的窄槽。在一些实施方式中，浅沟槽隔离区28的厚度约为700埃至900埃，埋入式绝缘层22厚度约为1800埃至2200埃，处理基底24的厚度约为3000埃至3400埃。深沟槽502a、502b及502c的宽度约小于1150埃，且其深宽比(高度对宽度的比值)约等于或大于4.5。当深宽比越小时，在后续制程中形成气隙的难度越高。如果深沟槽502a、502b及502c的深宽比(高度对宽度的比值)约小于4.5，在后续制程中可能无法形成气隙。深沟槽502a、502b及502c是形成于已形成的浅沟槽隔离区28内，且深沟槽502a、502b及502c是通过进一步向下蚀刻半导体基底18所形成的，而无须侧向扩大隔离结构。
本文中所记载的“约”一词代表其所描述的数值范围可在不影响其基本功能的前提下，能容许一定程度的变化。举例来说，倘若深宽比小于4.5仍可在后续制程中于深沟槽502a、502b及502c中形成气隙，则本文所述的“深沟槽502a、502b及502c的深宽比约等于或大于4.5”的范围也涵盖到深宽比小于4.5的状况。
请参阅图11，图11绘示层间介电层70与深沟槽隔离结构58的形成。层间介电层70可包含硅氧化物，其可由，例如，化学气相沉积或相似制程所形成。于其他实施方式中，层间介电层70可包含已掺杂的氧化物、硼硅玻璃(boronphosphosilicate glass；BPSG)、磷硅玻璃(phosphosilicate glass；PSG)、或相似物。在一些实施方式中，在沉积层间介电层70之前，接触蚀刻停止层(contact etch stop layer，未绘示)可毯覆式地形成于半导体基底18上。在一些实施方式中，层间介电层70与浅沟槽隔离区28可包含相同材料。在其他实施方式中，层间介电层70与浅沟槽隔离区可包含不同材料。在毯覆式地沉积层间介电材料的过程中，半导体基底18的顶面(亦即，位于半导体基底18上方)具有第一层间介电材料沉积速率，而在深沟槽502a、502b及502c中具有第二层间介电材料沉积速率。第一沉积速率与第二沉积速率是实质上相等的。由于半导体基底18的顶面是相对(相较于深沟槽502a、502b及502c)宽广的，故层间介电材料沉积速率较不容易造成不规则的沉积。相反地，由于深沟槽502a、502b及502c具有约等于或高于4.5的深宽比，故深沟槽502a、502b及502c比半导体基底18的顶面更窄，因此，当相同的层间介电材料沉积速率发生在深沟槽502a、502b及502c内时，会产生气隙于深沟槽502a、502b及502c。层间介电材料沉积速率可通过调整化学气相沉积的功率来达到更快或更慢的速率。通过堆叠多层的层间介电材料，层间介电层70延伸进深沟槽502a、502b及502c中，且相同的层间介电沉积速率会导致气隙504a、504b及504c分别形成于深沟槽502a、502b及502c中。
请继续参阅图11。气隙504a、504b及504c是形成在接近深沟槽502a、502b及502c底部的位置，并低于浅沟槽隔离区28的顶面。在一些实施方式中，气隙504a、504b及504c的位置低于半导体层20与埋入式绝缘层22的界面。气隙504a、504b及504c的一端是开始于埋入式绝缘层22并沿着深度方向延伸至处理基底24的水平高度。在其他实施方式中，气隙504a、504b及504c的顶端可高于半导体层20与埋入式绝缘层22的界面。气隙504a、504b及504c的底端是低于埋入式绝缘层22与处理基底24的界面。气隙504a、504b及504c为位于深沟槽502a、502b及502c中的伸长形的狭缝。在一些实施方式中，深沟槽502a、502b及502c每一者具有多个气隙。
请继续参阅图11。浅沟槽隔离区28与深沟槽隔离结构58是交替排列的。浅沟槽隔离区28与深沟槽隔离结构58的顶部是交替排列的。四条浅沟槽隔离区28是被三深沟槽隔离结构58所分隔。换句话说，深沟槽隔离结构58与浅沟槽隔离区28在上视图中是交替的。深沟槽隔离结构58的顶部亦帮助形成浅沟槽隔离区28。至此，隔离区为浅沟槽隔离区28与深沟槽隔离结构58的组合。多个深沟槽隔离结构58共同形成一梳状结构，其中深沟槽隔离结构58为此梳状结构的梳齿。深沟槽隔离结构58可视为浅沟槽隔离区28朝向处理基底24的延伸，以在半导体基底18中创造更强健的隔离结构。深沟槽隔离结构58具有气隙504a、504b及504c于其中。气隙可帮助降低主动元件之间的干扰。至此，通过半导体基底18的耦合电流可被气隙504a、504b及504c所阻挡。深沟槽隔离结构58的增加并不会增加栅极结构38(主动元件)之间的距离。在半导体基底18中的隔离结构(包含浅沟槽隔离区28及深沟槽隔离结构58)占据相同的宽度，但具有更高的密度及更有效的噪声阻挡能力。这是因为气隙504a、504b及504c具有大约等于1的介电常数。在一些实施方式中，层间介电层70具有氧化材料，其介电常数约为4。由于气隙504a、504b及504c具有比介电材料更低的介电常数，故相较于介电材料，气隙504a、504b及504c能够更进一步地降低元件之间的干扰。因此，通过在对噪声敏感的电路内插入气隙，可有效地降低这些电路的干扰。
请参阅图12。源/漏接触孔72是形成于层间介电层70中，以暴露位于第一主动区20a与第二主动区20b中的源/漏区域354。光阻层(未绘示)的形成层间介电层70上，并通过曝光显影的方式图案化而形成多个开口。接着，位于光阻层的开口下方的部分层间介电层70可通过蚀刻制程移除，其中此蚀刻制程可为干蚀刻(例如非等向性离子蚀刻)或湿蚀刻。至少一源/漏区域354可随着源/漏接触孔72形成于层间介电层70中而暴露。
请参阅图13。源/漏接触插塞74接着形成于源/漏接触孔72中。源/漏接触插塞的例示性材料可包含钨、铜、铝或相似物。导电材料的填入制程可通过整体性电镀制程、选择性电镀制程、整体性沉积制程、选择性沉积制程、或相似制程所实现。导电材料可填满源/漏接触孔72，或填超过源/漏接触孔72。接着，平坦化制程(例如化学机械研磨)可被执行以平坦化层间介电层70的顶面。在一些实施方式中，一栅极结构38是耦合至一天线以接收信号，而此端点可被视为噪声输入端。另一栅极结构38为具有低噪声放大器(low noiseamplifier；LNA)/功率放大器(power amplifier；PA)的输出端。由于气隙的介电常数约等于1，故具有气隙的深沟槽隔离结构58可助于降低在输入端(栅极结构38)及输出端之间的耦合电流。因此，主动元件之间的不良干扰可被降低。
深沟槽隔离结构是从浅沟槽隔离区向下延伸并具有气隙于深沟槽中。深沟槽隔离结构与层间介电层分享相同的氧化层，且在深沟槽中的气隙提供比氧化层更低的介电常数(约等于1)。通过在深沟槽隔离结构中的气隙，主动元件之间的耦合电流可被有效地阻隔，而无须增加主动元件之间的距离。
在一些实施方式中，一种集成电路包含一半导体基底、一隔离区、一第一主动元件以及至少一深沟槽隔离结构。隔离区是位于半导体基底中。第一主动元件是位于半导体基底上。深沟槽隔离结构从隔离区的一底部朝向半导体基底的一底部延伸。深沟槽隔离结构具有至少一气隙于其中。
在一些实施方式中，半导体基底为位于绝缘体上半导体(SOI)基底上的一半导体，此SOI基底包含处理基底、位于处理基底上的半导体层、以及位于处理基底与半导体层之间的一埋入式绝缘层。第一主动元件是位于半导体层。
在一些实施方式中，气隙的顶端是低于半导体层与埋入式绝缘层的界面。
在一些实施方式中，气隙的底端是低于埋入式绝缘层与处理基底的界面。
在一些实施方式中，深沟槽隔离结构与埋入式绝缘层包含相同材料。
在一些实施方式中，集成电路还包含位于第一主动元件上的一层间介电层。层间介电层与深沟槽隔离结构包含相同材料。
在一些实施方式中，集成电路还包含一第二主动元件。隔离区是位于第一主动元件与第二主动元件之间。
在一些实施方式中，一种集成电路包含一半导体基底、一隔离区以及复数深沟槽隔离结构。隔离区是位于半导体基底中。深沟槽隔离结构是由绝缘区的一底部朝向半导体基底的一底部延伸。
在一些实施方式中，半导体基底为位于绝缘体上半导体(SOI)基底上的一半导体，此SOI基底包含处理基底、位于处理基底上的半导体层、以及位于处理基底与半导体层之间的一埋入式绝缘层。
在一些实施方式中，处理基底将多个深沟槽隔离结构相隔开。
在一些实施方式中，每一深沟槽隔离结构具有至少一气隙于其中。
在一些实施方式中，此些深沟槽隔离结构共同形成一梳状结构。
在一些实施方式中，集成电路还包含位于第一主动区上的一栅极条状结构。至少一深沟槽隔离结构与该栅极条状结构的长度方向彼此平行。
在一些实施方式中，一种制造半导体元件的方法包含形成一隔离区于一半导体基底的复数主动区之间。至少一深沟槽被形成且从隔离区朝向半导体基底的一底部延伸。一层间介电层是形成于半导体基底上。层间介电层填入深沟槽中而形成一深沟槽隔离结构以及位于深沟槽隔离结构中的一气隙。
在一些实施方式中，形成隔离区于此些主动区之间包含形成一第一隔离区以及一第二隔离区，其中第一隔离区与第二隔离区是被一伪主动区所隔开的。
在一些实施方式中，形成深沟槽包含至少蚀刻伪主动区以及半导体基底以形成深沟槽。
在一些实施方式中，半导体基底包含处理基底、位于处理基底上的半导体层、以及位于处理基底与半导体层之间的埋入式绝缘层。主动区是位于半导体层中。形成深沟槽包含至少蚀刻隔离区、埋入式绝缘层以及处理基底以形成深沟槽。
在一些实施方式中，深沟槽的深宽比大于4.5。
在一些实施方式中，层间介电层是以一第一沉积速率沉积于深沟槽中，并以一第二沉积速率沉积于半导体基底上，其中第一沉积速率与第二沉积速率实质上相同。
上文概述若干实施方式的特征，使得熟悉此项技术者可更好地理解本揭露的态样。熟悉此项技术者应了解，可轻易使用本揭露作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施方式的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭露的精神及范畴，且可在不脱离本揭露的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (1)

1.一种集成电路，其特征在于，包含：
一半导体基底；
一隔离区，位于该半导体基底中；
一第一主动元件，位于该半导体基底上；以及
至少一深沟槽隔离结构，从该隔离区的一底部朝向该半导体基底的一底部延伸，该深沟槽隔离结构具有至少一气隙于其中。
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