CN109786351A - 电连接器的加强 - Google Patents
电连接器的加强 Download PDFInfo
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- CN109786351A CN109786351A CN201811345632.6A CN201811345632A CN109786351A CN 109786351 A CN109786351 A CN 109786351A CN 201811345632 A CN201811345632 A CN 201811345632A CN 109786351 A CN109786351 A CN 109786351A
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- conductive material
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Abstract
在一些示例中,一种装置,包括半导体元件、层元件和电连接半导体元件和层元件的单个连接器元件。在一些示例中,单个连接器元件包括两个或更多个分立连接器元件,并且两个或更多个分立连接器元件中的每个分立连接器元件电连接半导体元件和层元件。在一些示例中,单个连接器元件还包括附接到两个或更多个分立连接器元件的导电材料。
Description
技术领域
本公开内容涉及半导体装置,更具体而言,涉及半导体封装。
背景技术
装置可以包括集成电路和载体元件,它们通过诸如引线键合(wire bond)或金属柱的连接器元件电连接。制造工艺可包括在相对高的温度下将导线或柱连接到集成电路。在连接导线之后,可以降低装置的温度,使集成电路和导线或柱热收缩。
集成电路和导线或柱可以被配置为以不同的速率热收缩,因为每个元件可以包括不同的材料。例如,集成电路可以包括具有比导线或柱(其可以包括金属)低得多的热膨胀系数(CTE)的硅。结果,导线或柱可以比集成电路热收缩得更多,从而在集成电路和导线或柱之间的界面处产生应力。
发明内容
本公开内容描述了用于在半导体元件和层元件之间形成电连接的技术。电连接可包括两个或更多个分立连接器元件,其中,每个分立连接器元件电连接半导体元件和层元件。可以在两个或更多个分立连接器元件上形成导电材料以形成单个连接器元件。在两个或更多个分立连接器元件电连接到半导体元件之后并且在两个或更多个分立连接器元件电连接到层元件之后,导电材料可以形成在两个或更多个分立连接器元件上。
在一些示例中,一种装置包括半导体元件、层元件和电连接半导体元件和层元件的单个连接器元件。单个连接器元件包括两个或更多个分立连接器元件,并且两个或更多个分立连接器元件中的每个分立连接器元件电连接半导体元件和层元件。单个连接器元件还包括附接到两个或更多个分立连接器元件的导电材料。
在一些示例中,一种方法包括将两个或更多个分立连接器元件的每个分立连接器元件电连接到层元件。该方法还包括将两个或更多个分立连接器元件的每个分立连接器元件电连接到半导体元件。该方法还包括在将两个或更多个分立连接器元件电连接到层元件之后并且在将两个或更多个分立连接器元件电连接到半导体元件之后,在两个或更多个分立连接器元件上形成导电材料。形成导电材料包括形成单个连接器元件以电连接半导体元件和层元件。
在一些示例中,一种装置包括半导体元件、层元件和电连接半导体元件和层元件的单个连接器元件。单个连接器元件包括两个或更多个分立连接器元件,其中,两个或更多个分立连接器元件中的每个分立连接器元件电连接到半导体元件上的焊盘并且电连接到层元件。单个连接器元件包括形成在两个或更多个分立连接器元件的每个分立连接器元件、半导体元件上的焊盘和层元件上的导电材料。
在附图和以下说明中阐述了一个或多个示例的细节。根据说明书和附图以及权利要求,其他特征、目的和优点将是显而易见的。
附图说明
图1是根据本公开内容的一些示例的包括电连接半导体元件和层元件的单个连接器元件的装置的概念框图。
图2A和2B是根据本公开内容的一些示例的电连接半导体元件和层元件的连接器元件的透视图。
图2C和2D是根据本公开内容的一些示例的包括三个分立连接器元件和导电材料的单个连接器元件的横截面图。
图3A-3C是根据本公开内容的一些示例的包括电连接半导体元件和层元件的引线键合的装置的概念框图。
图4A和4B是根据本公开内容的一些示例的导电材料附接到引线键合之前和之后的引线键合的侧视图。
图5是根据本公开内容的一些示例的附接到引线键合的导电材料的侧视图。
图6是根据本公开内容的一些示例的电连接半导体元件和两个层元件的两个大支柱的概念框图。
图7A-7C是根据本公开内容的一些示例的电连接半导体元件和两个层元件的八个较小支柱的概念框图。
图8A和8B是根据本公开内容的一些示例的将导电材料附接到引线键合的电解过程的概念框图。
图9A和9B是根据本公开内容的一些示例的通过电解过程形成单个连接器元件的概念框图。
图10A和10B是根据本公开内容的一些示例的在使用电解过程将导电材料附接到引线键合之前掩蔽层元件的概念框图。
图11是示出根据本公开内容的一些示例的用于形成单个连接器元件的示例性技术的流程图。
具体实施方式
本公开内容涉及用于在两个元件(例如半导体元件和层元件)之间形成连接器元件的装置和方法。连接器元件可包括两个或更多个分立连接器元件,其中,导电材料形成在分立连接器元件上。在一些示例中,单个较大的连接器元件可以由两个或更多个分立连接器元件和导电材料形成。与连接器元件内的分立连接器元件相比,较大的连接器元件可具有更好的电、热和机械特性。另外,与将单个较大的预先形成的连接器元件附接到半导体元件相比,在一个或多个分立连接器元件上形成导电材料的过程可导致半导体元件和层元件上的较小应力。
为了组装另一个装置,将具有一百微米直径的铜线连接到具有相对脆性材料(例如氮化镓(GaN)或碳化硅(SiC))的半导体元件。连接过程可能涉及温度变化,该温度变化导致导线相对于半导体材料的膨胀和收缩以不同的速率膨胀和收缩。膨胀和收缩的速率可以基于每种材料的热膨胀系数(CTE)。相对的膨胀和收缩可能导致应力和半导体材料的损坏。
相反,本公开内容的装置可包括直径为30微米的一条或多条导线,其可连接到半导体元件。在由连接过程引起的热膨胀和收缩期间,导线的较小直径可以对半导体元件造成较小的应力。然后,可以在导线上形成导电材料以生成直径为100微米的单个连接器元件。在一条或多条导线上形成导电材料的过程不会对半导体元件造成显著的应力。直径为100微米的单个连接器元件的热、电和机械特性可以类似于100微米的导线的特性,但是本公开内容的装置的组装过程可以对半导体元件造成较小的应力。
本文描述的尺寸是用于解释本公开内容的技术的示例。例如,可以以与针对较小导线所描述的相同方式将直径为100微米的导线镀覆至更大的直径。此外,这些技术也适用于其他连接器元件,例如支柱、凸块和球。在支柱、凸块或球上形成导电材料可以改善连接器元件的特性,同时限制由于将连接器元件附接到半导体元件而引起的应力。
在一些示例中,可以在一条或多条导线中使用具有比铜更高延展性的材料,例如金或铝,以减少由附接过程引起的应力。然而,铜可能具有比其他导电材料(例如焊料或铝)更低的电阻率。铜的相对低的电阻率可导致较低的功率耗散和在装置操作期间产生的较少的热量。本公开内容的技术还可应用于支柱、凸块、球和任何其他连接器元件。可以在诸如支柱、凸块和球的连接器元件上形成导电材料,以改善连接器元件的电、热和/或机械特性。
图1是根据本公开内容的一些示例的包括电连接半导体元件110和层元件120的单个连接器元件150的装置100的概念框图。装置100可以是电力电子系统、数字和/或模拟系统、计算机系统、电子装置和/或任何其他应用的一部分。在一些示例中,装置100可包括多于一个的半导体元件、多于一个的层元件,和/或多于一个的单个连接器元件。
半导体元件110可以包括一个或多个电气部件,例如晶体管、二极管、电容器等。在一些示例中,半导体元件110可以包括一个或多个功率晶体管,其被配置为从层元件120接收电功率或将电功率输送到层元件120。半导体元件110可以包括半导体材料,例如硅、锗、镓、砷、GaN、SiC和/或任何其他半导体材料。与硅相比,GaN和SiC可能相对较脆,因此在将分立连接器元件130A和130B电连接到半导体元件110的过程中更容易受损。GaN和SiC是可以支持比硅或砷化镓更高开关频率的宽带隙材料。
层元件120可包括载体、金属层、模制互连基板(MIS)、层合基板、陶瓷材料、直接铜键合(DCB)基板、活性金属钎焊(AMB)基板、印刷电路板(PCB)和/或任何其他层元件。层元件120可以被配置为在参考电压(例如参考地)、高侧电源电压或低侧电源电压下导电。层元件120可以作为半导体元件110与装置100的另一部件(例如另一半导体元件或输入/输出节点(例如,引脚、焊盘、暴露的金属块或引线))之间的电连接而操作。
分立连接器元件130A和130B可以电连接到元件110和120并且配置成在元件110和120之间导电。分立连接器元件130A和130B可以附接到位于半导体元件110上的焊盘。分立连接器元件130A和130B可以包括金属线、金属柱、导电凸块或导电球。分立连接器元件130A和130B可以包括铜、金、铝、焊料和/或任何其他导电材料。分立连接器元件130A和130B可以使用诸如引线键合、焊接、胶合、带绕(taping)、粘附或任何其他附接工艺的工艺附接到元件110和/或120。
在一些示例中,装置100可以包括两个或更多个分立连接器元件,例如导线、支柱、凸块等。两个或更多个分立连接器元件中的每一个可以电连接到元件110和120。因此,两个或更多个分立连接器元件中的每一个都可以作为元件110和120之间的并联连接而操作。在分立连接器元件电连接到元件110和120之前,每个分立连接器元件可以是分立部件。在电连接到元件110和120之后,在沿两个分立连接器元件的长度的某些点处,分立连接器元件可以物理地接触另一个分立连接器元件。
元件110和120之间的电连接可能存在许多期望的特性。例如,元件110和120之间的低电阻可以减少在元件110和120之间流动的电的功耗。可能期望低功耗以改善装置100的效率和减少在分立连接器元件130A和130B周围产生的热量。另外,元件110和120之间的电连接可以通过将热量从半导体元件110传递出去而作为散热器操作,其中半导体元件110可以在装置100的操作期间产生热量。因此,在元件110和120之间的电连接的大横截面积可以增加离开半导体元件110的热传导。此外,元件110和120之间的电连接的大横截面积可以比具有较小横截面积的电连接更强。
可以使用诸如电解镀覆、无电镀覆和/或喷涂的工艺在分立连接器元件130A和130B上形成导电材料140。导电材料140可以包括铜、镍、银和/或可以在分立连接器元件130A和130B上形成的任何其他导电材料。在一些示例中,可以存在两层或更多层导电材料140,例如铜层以增加导电性(例如,更低的电阻)和镍层以防止腐蚀。
根据本公开内容的技术,单个连接器元件150包括分立连接器元件130A和130B以及导电材料140。与没有导电材料140的分立连接器元件130A和130B的特性相比,单个连接器元件150可具有更好的电、热和机械特性。与附接具有单个连接器元件150的尺寸的分立连接器元件相比,将分立连接器元件130A和130B附接到半导体元件110的过程可以对半导体元件110造成相对低的应力。将具有单个连接器元件150的尺寸的分立连接器元件焊接或引线键合到半导体元件110可以对半导体元件110造成相对高的应力,因为例如热膨胀和热收缩与分立连接器元件130A和130B的尺寸成比例。
相反,在分立连接器元件130A和130B上形成导电材料140的过程可能对半导体元件110造成很小的应力或没有应力。因此,为了形成具有相对大尺寸的单个连接器元件150,组装过程可以包括附接相对薄的分立连接器元件130A和130B,然后形成导电材料140,以增加元件110和120(例如,单个连接器元件150)之间的电连接的横截面积。与将大的分立连接器元件引线键合或焊接到半导体元件110相比,通过形成导电材料140构造单个连接器元件150可以导致对半导体元件110的较小的总应力,其中大的分立连接器元件具有与单个连接器元件150相同的尺寸。
图2A和2B是根据本公开内容的一些示例的电连接半导体元件210和层元件220的连接器元件230A-230C和250的透视图。半导体元件210包括通过连接器元件230A-230C电连接到层元件220的第一焊盘和通过连接器元件232电连接到层元件222的第二焊盘。在一些示例中,第一焊盘可以电连接到半导体元件210的功率晶体管的负载端子(例如,漏极端子或发射极端子),并且第二焊盘可以电连接到控制端子(例如,栅极端子)。导电材料240可以围绕连接器元件230A-230C形成以形成连接器元件250,并围绕连接器元件232形成以形成连接器元件252。
装置200包括功率半导体封装,其可以包括作为第一级互连技术的元件之间的引线键合。连接器元件230A-230C和250的载流能力可以是功率封装的主要重要特性。一种用于增加载流能力的技术是增加导线或其他连接器元件的直径。另一种技术是选择具有较低电阻的线材。再另一种技术是将多条导线键合到相同触点,如图2A中的分立连接器元件230A-230C所示。也可以将带状物键合到触点上,其中带状物具有粗导线的尺寸。
诸如装置200的功率封装的一个重要方面可以是元件的散热。由于连接器元件230A-230C的直径相对较小,连接器元件230A-230C的引线键合可能不会移除由半导体元件210产生的大部分热量。可以包括GaN芯片的半导体元件210的块状材料可能相对易碎。因此,连接器元件230A-230C可以设计成具有机械低应力互连,以避免损坏半导体元件210。因此,连接器元件230A-230C的引线键合互连可以不放置在半导体元件210的有源区域上方。在FE处理方面,将连接器元件230A-230C放置在半导体元件210的非有源区域上方可能更昂贵。因此,本公开内容的低应力互连技术借助由于键合小直径导线的应力较低而可能允许键合到有源区域而可以降低半导体产品的成本。
连接器元件230A-230C可以包括三条导线,这三条导线键合到相同的连接以用于高功率互连。在一些示例中,可以存在不同数量的连接器元件以电连接半导体元件210和层元件220。连接器元件230A-230C可以被配置为处理高功率电流和/或低功率电流。图2A示出了用于连接到半导体元件210的负载端子(例如,发射极)的焊盘的三条粗键合线,而仅有一条细线连接半导体元件210的栅极焊盘。连接器元件230A-230C可以楔形键合到元件210和220。
如果半导体元件210包括GaN,则键合焊盘可以位于装置200的非有源区域上方,以便不破坏或机械损坏GaN衬底和半导体元件210的敏感结构。另一种降低键合的应力的技术是使用多条导线而不是一条大导线。半导体元件210可以包括顶侧冷却或双侧冷却方法以从半导体元件210移除热量。半导体元件210产生的热量可以通过管芯附接材料传递到散热器中,该散热器可以是封装的一部分或者附接在封装上。对于双侧冷却,半导体元件210的功率部件的两侧可以附接到冷却散热器。
使用多条导线,如图2A所示,由于导线的直径有限,可能具有较低的载流能力和较低的载热能力的缺点。与图2B中示出的连接器元件250相比,连接器元件230A-230C可在每个连接器元件之间具有未使用的空间。连接器元件250可以具有比连接器元件230A-230C更大的直径,这可以导致更高的载流能力和更高的载热能力。连接器元件230A-230C可以在半导体元件210上和半导体元件210上的焊盘上占用相对大的空间,这可能增加前段(FE)生产(例如,半导体生产)和后段(BE)生产(例如,封装生产)的成本。对于包括GaN的半导体元件210,第一级互连元件的芯片尺寸的人为增加可能导致FE的更高成本。特殊的冷却方法可能很复杂并且可能并不总是可行的,因此需要一种能够消散更多热量的连接器元件。
本公开内容的技术包括使用多个分立连接器元件,例如引线键合或金属柱。分立连接器元件230A-230C可以在彼此之间具有相对小的距离,以便改善在分立连接器元件230A-230C周围形成导电材料240的过程。形成导电材料240可以包括镀覆工艺或其他形成工艺,以利用半导体元件210的焊盘上可能更大的接触面积将导线互连到连接器元件250(例如,一条“导线电缆”)。键合和镀覆工艺可以包括低机械应力引线键合参数,以便不损坏可以包括碳化硅或GaN的衬底(例如,半导体元件210)和其他结构。
如图2B所示,连接器元件250可以在每个连接器元件230A-230C之间没有隔离或间隙。从连接器元件230A-230C形成连接器元件250的过程可包括铜、银和/或任何其他导电材料的电镀覆或无电镀覆。连接器元件250可包括比每个连接器元件230A-230C更大的直径。另外,连接器元件250的互连区域可以大于所有连接器元件230A-230C的组合互连区域。
由于通过导电材料240(例如,铜)去除连接器元件230A-230C之间的隔离(例如,间隙),连接器元件250的较大互连横截面积可以导致更好的电和热性能。连接器元件250还可以包括在半导体元件210的焊盘和层元件220的焊盘上更大面积的可能的互连,以获得更好的热和电性能。另外,与作为单个步骤的键合连接器元件250相比,在连接器元件230A-230C上形成导电材料240之前电连接分立连接器元件230A-230C可以降低由于键合工艺导致的半导体元件210上的应力。连接器元件250还可以经受较少的焊盘腐蚀和较少的键合空心引起的碎裂。与带键合相比,连接器元件250可在焊盘之间形成更好的角度。
装置200可以包括在半导体元件210下面的载体或基板。半导体元件210可以通过诸如焊接或胶合的管芯附接方法附接到基板。在管芯附接步骤之后,连接器元件230A-230C可以电连接到元件210和220。如果连接器元件230A-230C包括导线,则电连接过程可以包括引线键合(例如,球形键合或楔形键合)。接下来,可以在连接器元件230A-230C上形成诸如铜或铜涂覆材料的导电材料。与其他键合材料相比,铜和/或铜涂覆材料可以具有相对低的成本并且可以容易地镀覆。
图2C和2D是根据本公开内容的一些示例的包括三个分立连接器元件230A-230C和270A-270C以及导电材料240、280A和280B的单个连接器元件250和290的横截面图。图2C示出了在例如沿元件210和220之间的连接器元件250的中途截取的连接器元件250的横截面。连接器元件230A-230C中的每一个可以包括在20微米和100微米之间、在30微米和80微米之间或者在40微米和70微米之间的直径。连接器元件250的直径可以更大,例如在100微米和500微米之间或者在150微米和300微米之间。
图2D示出了包括导电材料的两个层280A和280B的示例性单个连接器元件290。可以在形成外层280B之前形成内层280A。内层280A可以包括具有低电阻率的导电材料,以改善单个连接器元件290的电特性。外层280B可以包括阻止腐蚀的导电材料,例如镍或银。
图3A-3C是根据本公开内容的一些示例的包括电连接半导体元件310和层元件320的引线键合330A和330B的装置300的概念框图。引线键合330A和330B是连接器元件的示例。连接器元件的其他示例包括导电柱和导电凸块。
图3C示出了包括引线键合330A和330B以及导电材料340的连接器元件350。在一些示例中,在引线键合330A和330B上形成导电材料340之前,每个引线键合330A和330B可以电连接到元件310和320。将引线键合330A和330B电连接到元件310和320的过程可以包括引线键合、胶合、带绕、附接和/或将引线键合330A和330B附接到元件310和320的任何其他方式。将引线键合330A和330B电连接到元件310和320的过程可以包括相对高的温度,这可以使引线键合330A和330B以及元件310和320的材料基于每种材料的CTE以不同的速率膨胀。当温度下降时,材料可能会根据每种材料的CTE以不同的速率收缩。不同的膨胀和收缩速率可能对装置300的部件造成应力。
连接器元件330A、330B和350的尺寸(例如,直径)可以在半导体元件310的表面附近和层元件320的表面附近更大。引线键合330A和330B在元件310和320附近的部分可以被称为引线键合330A和330B的“球”或“球形键合”(参见例如图4A和4B中的球形键合432)。
图4A和4B是根据本公开内容的一些示例的在导电材料440附接到引线键合430之前和之后的引线键合430的侧视图。引线键合430是连接器元件的一个示例,并且可以包括诸如铜、铝、金的金属或任何其他导电材料。导电材料440可以围绕引线键合430形成,以产生单个连接器元件,其比引线键合430大并且可以具有更好的电、热和机械性能。
导电材料440可包括铜、银、镍、钯或任何其他导电材料。在一些示例中,导电材料440可以包括多层材料,例如第一层铜和第二层镍。在连接器元件430和导电材料440之间可以存在界面,除非连接器元件430和导电材料440都是相同材料,这可能导致界面消失。在键合和/或附接过程期间,铜线可能对表面410造成更高的应力,因此如果表面410包括诸如GaN的脆性材料,则可能希望将铝或金用于引线键合430。
诸如铜的导电材料440可以通过例如电镀覆形成在引线键合430上,这可能不会对表面410造成与将引线键合430连接到表面410一样多的应力。铜材料可以比金材料和铝材料更硬且更不可延展。因此,将金线或铝线键合和/或附接到表面410可能不会导致与将铜线键合和/或将附接到表面410一样高的应力。然而,导电材料440中的铜的硬度可能不一定是在引线键合430上形成导电材料440的过程期间对表面410造成应力的重要因素。
引线键合430电连接到表面410,表面410可包括半导体元件或层元件上的焊盘。导电材料440可以加强引线键合430的球形键合432。在一些示例中,导电材料440可以用于仅镀覆或覆盖连接器元件430,而不是将多个连接器元件形成为单个连接器元件(例如,条或带)。导电材料440(例如,镀铜)不仅可以增加连接器元件430和球的直径(即,连接器元件430最接近表面410的部分),导电材料440还可以增加与表面410上的键合焊盘的接触面积。增大的接触面积可以减少在芯片焊盘上腐蚀的发生。
表面410、球形键合432和导电材料440之间增大的接触面积可以改善表面410的散热。表面410处的厚导电材料层440可以允许热量从表面410快速转移到引线键合430和导电材料440。在一些示例中,在表面410处可以存在由一层铜覆盖的铝层,并且将球形键合432附接到铝可以允许通过球形键合432和导电材料440进行散热。
裂纹诱导可能发生在连接器元件430和表面410上的焊盘之间的中空空间中。裂纹会发生是由于装置中的功率循环。例如,半导体元件中的开关可以以高频率接通和断开,使得通过引线键合430的电流以高频率开始和停止。一种避免裂纹诱导的技术是将少量聚酰亚胺材料附接到中空空间中。聚酰亚胺材料可以分配或喷射到中空空间中。在连接器元件430的球形键合432下方和周围也可能发生腐蚀。在连接器元件430上形成导电材料440还可以降低表面410和连接器元件430之间的界面附近的裂纹和腐蚀的可能性。
在一些示例中,可以存在形成于连接器元件430上的两层导电材料440。例如,可以在连接器元件430上形成诸如铜的导电材料层440,以便增加载流能力并改善表面410的散热。然后,可以在第一导电材料层440(例如,铜层)上形成诸如镍的导电材料层440,以防止在连接器元件430上和表面410与连接器元件430的界面处的腐蚀。
在球形键合432周围形成导电材料440可以在表面410和球形键合432之间形成光滑的界面。与图4A中所示的没有导电材料440的界面相比,光滑的界面可以导致界面处的电阻减小。较低的电阻可以导致较低的功耗,从而提高装置的效率。较低的功耗可以导致产生的热量较低,从而改善装置的热性能。
图4A和4B示出了仍然完整的焊盘的区域460A和460B。焊盘的区域470可能被腐蚀,因为区域470靠近球形键合432。导电材料440可以覆盖区域470以防止或减少区域470中的腐蚀。焊盘(例如,区域460A和460B)可以包括铝或另一种导电材料。
图5是根据本公开内容的一些示例的附接到引线键合530的导电材料540的侧视图。对于高电子迁移率(HEM)基板(例如,GaN),由于基板材料的脆性,在有源区域上的键合可能是不可行的。可以“人工”放大硅管芯以便为半导体元件510上的引线键合焊盘腾出空间。半导体元件510的基板材料可能太脆,使得半导体元件510的材料可能在引线键合期间被机械应力损坏。利用过度镀覆的低应力键合可以实现元件510和520之间的最终电、热和机械接触,并且对于HEM材料可允许在半导体元件510的有源区域上的键合。
与将直径为50微米的导线附接到半导体元件510相比,将直径为30微米的导线附接到半导体元件510可以导致较低的应力。如果附接过程发生在半导体元件510的有源区域上,则附接过程可能损坏或破坏半导体元件510。附接直径为30微米的导线(例如,连接器元件530),然后镀覆导电材料540以形成直径为50微米的单个连接器元件550可导致与具有直径为50微米的分立连接器元件类似的特性。
在一些示例中,电解镀覆和/或无电镀覆可用于在连接器元件530上形成导电材料540。如果使用电镀覆,则可应用水平和垂直镀覆原理。层元件520可以由永久掩模,例如机械附接到层元件520的橡胶掩模掩蔽。层元件520也可以由临时掩模掩蔽,例如耐镀覆抗蚀剂,其可以在电镀覆过程完成之后通过湿化学法去除。
图6是根据本公开内容的一些示例的电连接半导体元件610和两个层元件620A与620B的两个大支柱630A和630B的概念框图。支柱630A和630B可包括诸如铜、铝或另一金属的材料。支柱630A和630B可以通过焊接或另一附接工艺附接到元件610、620A和620B。附接材料632A和632B可包括焊料或粘合材料,例如胶带或胶水。装置600还可以包括半导体元件610和支柱630A与630B之间的附接材料。
与图7A-7C中的每个小支柱730A-730H相比,每个支柱630A和630B可以具有相对大的横截面积。在焊接过程期间,对半导体元件610的应力可以与每个支柱630A和630B的横截面积成比例。因此,与每个支柱730A-730H的附接会对半导体元件710所导致的应力相比,每个支柱630A和630B的附接会导致更多的对半导体元件610的应力。支柱630A和630B可以包括更具延展性的材料,例如焊料,其可以在附接过程期间导致较低的应力,但焊料的电阻率会高于诸如铜等较硬的材料。
图7A-7C是根据本公开内容的一些示例的电连接半导体元件710和两个层元件720A和720B的八个较小支柱730A-730H的概念框图。图7B示出了形成在支柱730A-730H和层元件720A与720B上的导电材料740。图7C示出了形成在支柱730A-730H以及层元件720A和720B的仅一部分上的导电材料740。在图7C中可以不在所有层元件720A和720B上形成导电材料740,因为层元件720A和720B的部分可以被掩蔽。
与支柱630A和630B相比,形成在支柱730A-730H上的导电材料740可具有类似的电、热和机械特性。然而,与将支柱630A和630B附接到半导体元件610和元件620A与620B相比,将支柱730A-730H附接到半导体元件710和元件720A与720B可以造成更低的应力。与支柱630A和630B的接触面积相比,较低的应力可以是支柱730A-730H的较小接触面积的结果。图7A-7C的技术也可以在诸如导线、导电凸块和导电球的连接器元件上实现。
在一些示例中,每个支柱730A-730H的直径可以在30微米和100微米之间或者在40微米和70微米之间。导电材料740的深度可以在30微米和80微米之间或者在40微米和60微米之间,以形成具有大约300、400或500微米乘以100或200微米的横截面尺寸的连接器元件750。
图8A和8B是根据本公开内容的一些示例的将导电材料840附接到引线键合的电解过程的概念框图。可以通过电镀覆过程(例如电镀覆)和/或无电过程在连接器元件830上形成导电材料840。图8A和8B示出了没有掩蔽层元件820的过程,使得导电材料852A和852B可以形成在层元件820的未掩蔽表面上。
可任选地掩蔽键合的载体(例如,层元件820)以避免任何不需要的镀层。在电镀覆的情况下,层元件820可以电连接到第一电极,并且浸入液体860的镀浴中,液体860连接到第二电极。液体860可以包括铜或任何其他可镀覆的材料,并且液体860可以涂覆连接器元件830以形成连接器元件850。导电材料840(例如,铜)的镀覆可以加强连接器元件830。在元件810或820上的单个键合焊盘上的多条导线的情况下,导线可以一起生长以生成单个互连带(例如,单个连接器元件)。
图9A和9B是根据本公开内容的一些示例的通过电解过程形成单个连接器元件950的概念框图。在电解过程期间,液体960可在分立连接器元件930A-930C上形成导电材料940以产生单个连接器元件950。液体960还可在层元件920上形成以形成导电材料952A和952B。将导电材料952A和952B添加到层元件920可以降低层元件920上的腐蚀的可能性。
图10A和10B是根据本公开内容的一些示例的在使用电解过程将导电材料1040附接到引线键合1030之前掩蔽层元件1020的概念框图。掩模1070A和1070B可以覆盖层元件1020以防止在层元件1020的部分或全部上形成导电材料1040。可以在镀覆过程完成之后去除掩模1070和1070B。
图11是示出根据本公开内容的一些示例的用于形成单个连接器元件的示例性技术的流程图。参考图1中的装置100描述图11的技术,尽管其它部件,例如图2A、2B、3A-3C、5和7A-7C中的装置200、300、500和700可以例示类似的技术。
在图11的示例中,分立连接器元件130A和130B电连接到层元件120(1102),并且分立连接器元件130A和130B电连接到半导体元件110(1104)。分立连接器元件130A和130B可以通过引线键合、焊接、胶合、带绕等附接到层元件120。分立连接器元件130A和130B可以包括导线、金属柱、凸块、球或任何其他连接器元件。分立连接器元件130A和130B可以包括诸如铜、焊料、金、铝、镍、银等的材料。
分立连接器元件130A和130B的附接过程可以对半导体元件110造成应力,该应力与分立连接器元件130A和130B与半导体元件110接触的表面积成比例。因此,非常细的导线附接到半导体元件110将导致比附接相对较粗的线更低的应力。
在图11的示例中,在分立连接器元件130A和130B电连接到元件110和120之后,在分立连接器元件130A和130B上形成导电材料140(1106)。形成过程可包括电解过程,例如电镀覆,或无电过程,例如无电镀覆。导电材料140可包括铜、镍、银或任何其他导电材料。与分立连接器元件130A和130B相比,单个连接器元件150可具有改善的电特性(例如,更低的电阻和更低的功耗),更好的热特性(例如,更高的导热率)和更好的机械特性(例如,更高的拉伸强度)。
分立连接器元件130A和130B以及导电材料140一起可以形成单个连接器元件150,其具有比分立连接器元件130A和130B更大的横截面积。在一些示例中,单个连接器元件150可以包括多于一个分立连接器元件,其中围绕分立连接器元件形成有导电材料140。导电材料140可以填充在分立连接器元件之间的间隙中,使得电可以在分立连接器元件之间流动而不必流到元件110或120。
因此,导电材料140可以在第一分立连接器元件和第二分立连接器元件之间产生直接电连接。直接电连接可允许电在第一分立连接器元件和第二分立连接器元件之间流动,而不流过半导体元件110上的焊盘或流过层元件120。导电材料140还可在元件110和120之间形成电连接,该电连接与分立连接器元件130A和130B分开,使得电可以仅通过导电材料140从元件110流到元件120,而不接触分立连接器元件130A和130B。
在一些示例中,导电材料140可以具有相对低的电阻率(例如,铜镀覆)。分立连接器元件130A和130B可包括具有相对低硬度的材料(例如,金或铝),而铜可以是较硬的材料。导电材料140还可以防止腐蚀(例如,银或镍)。
在导电材料140已经形成在分立连接器元件130A和130B上之后,可以去除元件110或120上的任何掩模。然后,可以围绕元件110、120和150形成封装材料,以防止元件110、120和150的移动。
以下编号的示例说明了本公开内容的一个或多个方面。
示例1.一种装置,包括半导体元件、层元件和电连接半导体元件和层元件的单个连接器元件。单个连接器元件包括两个或更多个分立连接器元件,并且两个或更多个分立连接器元件中的每个分立连接器元件电连接半导体元件和层元件。单个连接器元件还包括附接到两个或更多个分立连接器元件的导电材料。
示例2.示例1的装置,其中,导电材料填充两个或更多个分立连接器元件之间的间隙。
示例3.示例1-2的装置或其任何组合,其中,导电材料电连接两个或更多个分立连接器元件中的第一分立连接器元件和两个或更多个分立连接器元件中的第二分立连接器元件。
实施例4.示例1-3的装置或其任何组合,其中,导电材料电连接半导体元件和层元件。
示例5.示例1-4的装置或其任何组合,其中,单个连接器元件包括在两个或更多个分立连接器元件中的每个分立连接器元件之间和周围的导电材料。
示例6.示例1-5的装置或其任何组合,其中,导电材料是附接到两个或更多个分立连接器元件的第一导电材料层。单个连接器元件还包括附接到第一导电材料层的第二导电材料层,并且其中,第二导电材料层包括镍或银。
示例7.示例1-6的装置或其任何组合,其中,导电材料包括附接到两个或更多个分立连接器元件并通过电解过程形成的镀铜。
示例8.示例1-7的装置或其任何组合,其中,两个或更多个分立连接器元件中的每个分立连接器元件包括引线键合。
示例9.示例1-8的装置或其任何组合,其中,两个或更多个分立连接器元件中的每个分立连接器元件包括金属柱。
示例10.示例1-9的装置或其任何组合,其中,两个或更多个分立连接器元件包括金、铝或铜。
示例11.示例1-10的装置或其任何组合,还包含附接于层元件表面的导电材料。
示例12.示例1-11的装置或其任何组合,其中,半导体元件包括焊盘,其中,单个连接器元件将焊盘电连接到层元件。
示例13.示例1-12的装置或其任何组合,其中,半导体元件包括氮化镓。
示例14.示例1-13的装置或其任意组合,其中,层元件包括金属载体、层合基板、陶瓷、直接铜键合基板、活性金属钎焊基板、模制互连基板或印刷电路板。
示例15.一种方法,包括将两个或更多个分立连接器元件中的每个分立连接器元件电连接到层元件。该方法还包括将两个或更多个分立连接器元件中的每个分立连接器元件电连接到半导体元件。该方法还包括在将两个或更多个分立连接器元件电连接到层元件之后并且在将两个或更多个分立连接器元件电连接到半导体元件之后,在两个或更多个分立连接器元件上形成导电材料。形成导电材料包括形成单个连接器元件以电连接半导体元件和层元件。
示例16.示例15的方法,其中,在两个或更多个分立连接器元件上形成导电材料包括通过电解过程或通过无电过程在两个或更多个分立连接器元件上形成铜层。
示例17.示例15-16的方法或其任何组合,还包括在层元件的至少一部分上形成导电材料。
示例18.示例15-17的方法或其任何组合,还包括在两个或更多个分立连接器元件上形成导电材料之前掩蔽层元件的至少一部分。
示例19.示例15-18的方法或其任何组合,其中,在两个或更多个分立连接器元件上形成导电材料包括在两个或更多个分立连接器元件上形成第一导电材料层。该方法还包括在第一导电材料层上形成第二导电材料层,其中,第二导电材料层包括镍或银。
示例20.示例15-19的方法或其任何组合,其中,形成单个连接器元件包括填充两个或更多个分立连接器元件中的第一分立连接器元件与两个或更多个分立连接器元件中的第二分立连接器元件之间的间隙。
示例21.示例15-20的方法或其任何组合,其中,形成单个连接器元件包括在两个或更多个分立连接器元件中的第一分立连接器元件与两个或更多个分立连接器元件中的第二分立连接器元件之间形成直接电连接。
示例22.示例15-21的方法或其任何组合,其中,在两个或更多个分立连接器元件中的每个分立连接器元件上形成导电材料包括在分立连接器元件上形成第一导电材料层。形成单个连接器元件还包括在第一导电材料层上形成第二导电材料层,第二导电材料层包括镍或银。
示例23.一种装置,包括半导体元件、层元件和电连接半导体元件和层元件的单个连接器元件。单个连接器元件包括两个或更多个分立连接器元件,其中,两个或更多个分立连接器元件中的每个分立连接器元件电连接到半导体元件上的焊盘并且电连接到层元件。单个连接器元件包括形成在两个或更多个分立连接器元件中的每个分立连接器元件、半导体元件上的焊盘和层元件上的导电材料。
示例24.示例23的装置,其中,导电材料包括第一导电材料层。该装置还包括在第一导电材料层上形成的第二导电材料层。
已经描述了本公开内容的各种示例。设想了所描述的系统、操作或功能的任何组合。这些和其他示例在以下权利要求的范围内。
Claims (20)
1.一种装置,包括:
半导体元件;
层元件;以及
单个连接器元件,其电连接所述半导体元件和所述层元件,其中,所述单个连接器元件包括:
两个或更多个分立连接器元件,其中,所述两个或更多个分立连接器元件中的每个分立连接器元件电连接所述半导体元件和所述层元件;以及
导电材料,其附接到所述两个或更多个分立连接器元件。
2.根据权利要求1所述的装置,其中,所述导电材料填充所述两个或更多个分立连接器元件之间的间隙。
3.根据权利要求1所述的装置,其中,所述导电材料电连接所述两个或更多个分立连接器元件中的第一分立连接器元件和所述两个或更多个分立连接器元件中的第二分立连接器元件。
4.根据权利要求1所述的装置,其中,所述导电材料电连接所述半导体元件和所述层元件。
5.根据权利要求1所述的装置,其中,所述单个连接器元件包括在所述两个或更多个分立连接器元件中的每个分立连接器元件之间和周围的导电材料。
6.根据权利要求1所述的装置,
其中,所述导电材料是附接到所述两个或更多个分立连接器元件的第一导电材料层。
其中,所述单个连接器元件还包括附接到所述第一导电材料层的第二导电材料层,并且
其中,所述第二导电材料层包括镍或银。
7.根据权利要求1所述的装置,其中,所述导电材料包括附接到所述两个或更多个分立连接器元件并通过电解过程形成的镀铜。
8.根据权利要求1所述的装置,其中,所述两个或更多个分立连接器元件包括金、铝或铜。
9.根据权利要求1所述的装置,还包含附接于所述层元件表面的导电材料。
10.根据权利要求1所述的装置,其中,所述半导体元件包括氮化镓。
11.根据权利要求1所述的装置,其中,所述层元件包括金属载体、层合基板、陶瓷、直接铜键合基板、活性金属钎焊基板、模制互连基板或印刷电路板。
12.一种方法,包括:
将两个或更多个分立连接器元件中的每个分立连接器元件电连接到层元件;
将所述两个或更多个分立连接器元件中的每个分立连接器元件电连接到半导体元件;以及
在将所述两个或更多个分立连接器元件电连接到所述层元件之后并且在将所述两个或更多个分立连接器元件电连接到所述半导体元件之后,在所述两个或更多个分立连接器元件上形成导电材料,
其中,形成所述导电材料包括形成单个连接器元件以电连接所述半导体元件和所述层元件。
13.根据权利要求12所述的方法,其中,在所述两个或更多个分立连接器元件上形成所述导电材料包括通过电解过程或通过无电过程在所述两个或更多个分立连接器元件上形成铜层。
14.根据权利要求12所述的方法,还包括在所述层元件的至少一部分上形成导电材料。
15.根据权利要求12所述的方法,还包括在所述两个或更多个分立连接器元件上形成所述导电材料之前掩蔽所述层元件的至少一部分。
16.根据权利要求12所述的方法,
其中,在所述两个或更多个分立连接器元件上形成所述导电材料包括在所述两个或更多个分立连接器元件上形成第一导电材料层,
其中,所述方法还包括在所述第一导电材料层上形成第二导电材料层,并且
其中,所述第二导电材料层包括镍或银。
17.根据权利要求12所述的方法,其中,形成所述单个连接器元件包括填充所述两个或更多个分立连接器元件中的第一分立连接器元件与所述两个或更多个分立连接器元件中的第二分立连接器元件之间的间隙。
18.根据权利要求12所述的方法,其中,形成所述单个连接器元件包括在所述两个或更多个分立连接器元件中的第一分立连接器元件与所述两个或更多个分立连接器元件中的第二分立连接器元件之间形成直接电连接。
19.一种装置,包括:
半导体元件;
层元件;以及
单个连接器元件,其电连接所述半导体元件和所述层元件,其中,所述单个连接器元件包括:
两个或更多个分立连接器元件,其中,所述两个或更多个分立连接器元件中的每个分立连接器元件电连接到所述半导体元件上的焊盘并且电连接到所述层元件;以及
形成在所述两个或更多个分立连接器元件的每个分立连接器元件上、所述半导体元件上的焊盘上以及所述层元件上的导电材料。
20.根据权利要求19所述的装置,
其中,所述导电材料包括第一导电材料层,并且
其中,所述装置还包括在所述第一导电材料层上形成的第二导电材料层。
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US15/811,375 US10700037B2 (en) | 2017-11-13 | 2017-11-13 | Reinforcement for electrical connectors |
US15/811,375 | 2017-11-13 |
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US11355460B1 (en) * | 2020-12-07 | 2022-06-07 | Infineon Technologies Ag | Molded semiconductor package with high voltage isolation |
FR3121570A1 (fr) * | 2021-03-30 | 2022-10-07 | Safran | Procede de réalisation d’une connexion électrique |
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US6852567B1 (en) * | 1999-05-31 | 2005-02-08 | Infineon Technologies A.G. | Method of assembling a semiconductor device package |
US7969021B2 (en) * | 2000-09-18 | 2011-06-28 | Nippon Steel Corporation | Bonding wire for semiconductor device and method for producing the same |
US6897152B2 (en) * | 2003-02-05 | 2005-05-24 | Enthone Inc. | Copper bath composition for electroless and/or electrolytic filling of vias and trenches for integrated circuit fabrication |
US7202109B1 (en) * | 2004-11-17 | 2007-04-10 | National Semiconductor Corporation | Insulation and reinforcement of individual bonding wires in integrated circuit packages |
US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
US7993979B2 (en) * | 2007-12-26 | 2011-08-09 | Stats Chippac Ltd. | Leadless package system having external contacts |
US9961798B2 (en) * | 2013-04-04 | 2018-05-01 | Infineon Technologies Austria Ag | Package and a method of manufacturing the same |
US9362240B2 (en) * | 2013-12-06 | 2016-06-07 | Infineon Technologies Austria Ag | Electronic device |
JP6272213B2 (ja) * | 2014-11-26 | 2018-01-31 | 三菱電機株式会社 | 半導体装置 |
CN109005670B (zh) * | 2016-04-04 | 2022-08-26 | 罗姆股份有限公司 | 功率模块及其制造方法 |
US10224306B2 (en) * | 2016-11-03 | 2019-03-05 | Stmicroelectronics (Grenoble 2) Sas | Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device |
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