CN109783415A

CN109783415A - A kind of correction processor BM3803 reads the device of timing

Info

Publication number: CN109783415A
Application number: CN201811408908.0A
Authority: CN
Inventors: 赵磊; 伍攀峰; 张毅; 韩德崇; 王勇; 刘庆民
Original assignee: Shandong Institute of Space Electronic Technology
Current assignee: Shandong Institute of Space Electronic Technology
Priority date: 2018-11-23
Filing date: 2018-11-23
Publication date: 2019-05-21
Anticipated expiration: 2038-11-23
Also published as: CN109783415B

Abstract

The invention discloses the devices that a kind of correction processor BM3803 reads timing, latch 54AC374 is driven using the rising edge of system clock CLK, forward position interception is carried out to chip selection signal IOSN and address wire ADDR, obtain IOSN2 and ADDR2, along interception after being carried out using 54AC32 to chip selection signal IOSN2, obtain IOSN3, IOSN3 and ADDR2 finally participates in decoding, so that revised chip selection signal IOSN3 is completely by address wire ADDR2 envelope, when carrying out the extension of I/O chip selection signal using decoder, it can effectively avoid decoder and accidentally export.

Description

A kind of correction processor BM3803 reads the device of timing

Technical field

The invention belongs to spaceborne computer technical fields, and in particular to a kind of correction processor BM3803 reads the dress of timing It sets.

Background technique

Domestic aerospace only one I/O chip selection signal (IOSN) of processor BM3803, is far from satisfying department of computer science The requirement to chip selection signal quantity of system is needed to carry out quantity extension to I/O chip selection signal using decoder, generally be selected using piece Signal makes can control signal as decoder, and address wire is inputted as the decoding of decoder.Since the intrinsic timing of BM3803 is special Property, in the finish time for carrying out read operation to I/O regional address, the area the I/O chip selection signal and address wire (ADDR) of BM3803 is almost It cancels simultaneously, sees the phase relation of ADDR and IOSN in Fig. 2.If directly using the multidigit address wire ADDR of BM3803 and piece choosing letter Number IOSN is decoded, decoding movement will at the end of, due to the difference of circuit system delay and signal load, participate in decoding Address wire be possible to change earlier than chip selection signal, see the phase relation of ADDR1 and IOSN1 in Fig. 2, i.e. decoder is in When enabled state (chip selection signal IOSN1 is effective), decoding input ADDR1 is changed, and decoder will export accidentally piece choosing, accidentally The width of piece choosing is about T_error, T_errorSize and address wire ADDR1 and the phase difference that changes of chip selection signal IOSN1 it is related.

If executing FIFO operation using the piece choosing of decoder output, resetting or reset, once there is accidentally piece choosing, it is possible to Cause to malfunction, be evaded.When timing progress system design is read in the area I/O according to BM3803, to avoid malfunctioning, Must assure that the finish time of read operation, address wire will not change prior to chip selection signal, this will fully consider system delay and The loading condition of signal, and need special consideration should be given to the Delay Variation under high and low temperature state, the highly reliable design of computer system is difficult Degree is big.

Summary of the invention

In view of this, the object of the present invention is to provide the devices that a kind of correction processor BM3803 reads timing, using hardware The method of timing is corrected, it can be achieved that address wire substantially increases the tolerance to system delay to the envelope of chip selection signal.

A kind of correction processor BM3803 reads the device of timing, latch or door including model 54AC374 and translates Code device；The system master clock CLK of BM3803 is output to the end CP of latch, i.e. input end of clock；The address wire of BM3803 output The ADDR and chip selection signal IOSN of output enters the different input terminals of latch；The latched device of address wire ADDR, which latches, to be obtained Signal ADDR2 be sent into decoder input terminal；The signal IOSN2 that the latched device of chip selection signal IOSN obtains after latching be sent into or One input terminal of door, chip selection signal IOSN is sent to or the output end output signal of another input terminal of door or door IOSN3, then it is connected to the enable end EN of decoder；Signal ADDR2 generates several sub-pieces choosings, for I/O system after decoder for decoding It uses.

Preferably, the model 54AC138 of the decoder.

The invention has the following beneficial effects:

A kind of correction processor BM3803 of the invention reads the device of timing, is driven using the rising edge of system clock CLK Latch 54AC374 carries out forward position interception to chip selection signal IOSN and address wire ADDR, obtains IOSN2 and ADDR2, uses Edge intercepts after 54AC32 carries out chip selection signal IOSN2, obtains IOSN3, IOSN3 and ADDR2 and finally participates in decoding, so that amendment Chip selection signal IOSN3 afterwards completely can when carrying out the extension of I/O chip selection signal using decoder by address wire ADDR2 envelope Decoder is effectively avoided accidentally to export.

Detailed description of the invention

Fig. 1 is the circuit diagram for the device that a kind of correction processor BM3803 of the invention reads timing；

Fig. 2 is that BM3803I/O reads timing amendment schematic diagram.

Specific embodiment

The present invention will now be described in detail with reference to the accompanying drawings and examples.

As shown in Figure 1, a kind of correction processor BM3803 of the invention reads the device of timing, including model 54AC374 Latch or door and decoder (model is chosen as 54AC138)；The system master clock CLK of BM3803 is output to latch The end CP, i.e. input end of clock；The address wire ADDR of BM3803 output and the chip selection signal IOSN of output enter latch Different input terminals；The latched device of address wire ADDR latches the input terminal that the signal ADDR2 obtained is sent into decoder；Chip selection signal The IOSN2 that the latched device of IOSN obtains after latching is sent into or an input terminal of door, chip selection signal IOSN be sent to or door it is another The output end of one input terminal or door exports IOSN3, then is connected to the enable end EN of decoder；Signal ADDR2 is through decoder for decoding Afterwards, several sub-pieces choosings are generated, are used for I/O system.

As shown in Fig. 2, the process that BM3803 reads data shares 5 clock sections, lead_in is preceding blanking interval, data1 and Data2 is the read cycle 1 and 2, and latent period can be by the related register of software configuration BM3803, the operation of foundation I/O equipment Speed, is set as integer 0~15, and lead_out is the final blanking phase.

In the rising edge of read cycle data1,54AC374 latches ADDR and IOSN using the rising edge of CLK, and ADDR has been at this time Through stabilization, the ADDR2 of 54AC374 output is the currently active state.IOSN is still in invalid state, the IOSN2 of 54AC374 output For current invalid state, 2 inputs of 54AC32 are all invalid piece choosings, and the IOSN3 of output is also current invalid state.

If latent period number is set as Integer N, N number of system clock week will increase between read cycle data1 and data2 Phase.First latent period (when latent period number be greater than 0 when) or read cycle data2 (when latent period number be 0 when) it is upper Edge is risen, 54AC374 continues to latch ADDR and IOSN using the rising edge of CLK, and ADDR does not change at this time, still in stable state, The ADDR2 of 54AC374 output is remained unchanged.IOSN is in effective status, and the IOSN2 of 54AC374 output is the currently active state, 2 inputs of 54AC32 are all effective piece choosings, and the IOSN3 of output is also the currently active state.

In the rising edge of lead_out, 54AC374 continues to latch ADDR and IOSN using the rising edge of CLK, at this time ADDR Do not change, still in stable state, the ADDR2 of 54AC374 output is remained unchanged.IOSN is in effective status, 54AC374 output IOSN2 be the currently active state, 2 of 54AC32 inputs are all effective piece choosings, and the IOSN of output is also the currently active state, But IOSN 2~13ns after the rising edge of lead_out is cancelled, and the IOSN3 of 54AC32 output is in invalid state therewith.From And make the complete envelope I/O chip selection signal IOSN3 of address wire ADDR2, will not occur accidentally piece after the decoder for decoding such as 54AC138 Choosing output.

The rising edge of the system clock CLK of BM3803 of the present invention drives latch 54AC374, to chip selection signal IOSN and ground Location line ADDR carries out forward position interception, obtains IOSN2 and ADDR2, and edge intercepts after being carried out using 54AC32 to chip selection signal IOSN2, Obtain IOSN3.IOSN3 and ADDR2 finally participates in decoding.As it can be seen that revised chip selection signal IOSN3 is completely by address wire ADDR2 envelope, forward position lag behind address wire and change about 1 clock cycle, and rear edge changes about 1 clock cycle than address wire in advance (delay that a clock cycle subtracts 54AC32), i.e. T1 in Fig. 2.By BM3803 work in case where 30MHz dominant frequency, Front and back is along the delay surplus for having about 33ns or so.When carrying out the extension of I/O chip selection signal using decoder, decoding can effectively avoid Device accidentally exports.

The device that modified BM 3803 reads timing is passed through to be greater than 300 hours and be verified, the operation is stable.

In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention. All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in of the invention Within protection scope.

Claims

1. the device that a kind of correction processor BM3803 reads timing, which is characterized in that latch including model 54AC374, Or door and decoder；The system master clock CLK of BM3803 is output to the end CP of latch, i.e. input end of clock；BM3803 is defeated The chip selection signal IOSN of address wire ADDR and output out enter the different input terminals of latch；Address wire ADDR is latched Device latches the input terminal that the signal ADDR2 obtained is sent into decoder；The signal that the latched device of chip selection signal IOSN obtains after latching IOSN2 is sent into or an input terminal of door, and chip selection signal IOSN is sent to or the output end of another input terminal of door or door is defeated Signal IOSN3 out, then it is connected to the enable end EN of decoder；Signal ADDR2 generates several sub-pieces choosings, supplies after decoder for decoding I/O system uses.

2. the device that a kind of correction processor BM3803 as described in claim 1 reads timing, which is characterized in that the type of decoder Number be 54AC138.