CN109782542A - Semiconductor adapter plate exposure method and exposure equipment - Google Patents
Semiconductor adapter plate exposure method and exposure equipment Download PDFInfo
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- CN109782542A CN109782542A CN201711111867.4A CN201711111867A CN109782542A CN 109782542 A CN109782542 A CN 109782542A CN 201711111867 A CN201711111867 A CN 201711111867A CN 109782542 A CN109782542 A CN 109782542A
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Abstract
The invention provides an exposure method and exposure equipment for a semiconductor adapter plate, and relates to the field of integrated circuit manufacturing, wherein the semiconductor adapter plate comprises a first area and a second area; the semiconductor adapter plate exposure method comprises the following steps: placing the first area of the semiconductor adapter plate into an exposure area of exposure equipment; exposing a first area of the semiconductor adapter plate by using a first mask plate; translating the semiconductor adapter plate, and placing a second area of the semiconductor adapter plate into an exposure area of exposure equipment; exposing a second area of the semiconductor adapter plate by using a second mask plate; wherein the pattern of the second area is stitched to the pattern of the first area. The method solves the technical problems that the existing exposure method can not meet the requirements of users on the large-size silicon inserter process and the user experience is poor, can realize the manufacture of the large-size semiconductor adapter plate, and improves the user experience.
Description
Technical field
The present invention relates to ic manufacturing technology field, more particularly, to a kind of semiconductor pinboard exposure method and
Exposure sources.
Background technique
In the manufacturing process of various semiconductor devices (such as memory device), exposure method is widely used in semiconductor switching
The patterning of plate, however in existing exposure method, since the lens sizes of exposure sources are limited, so semiconductor pinboard
It is size-constrained, can only the lesser semiconductor pinboard of manufactured size, pattern it is complicated also to use double exposure mode, such as
Twice, double exposure is overlapped on identical field, could be completed to semiconductor for vertical and horizontal direction exposure on one block semiconductor pinboard
The exposure of pinboard, it is high that this kind of Exposure mode has the disadvantages that pattern accuracy requirement, and not can be carried out large scale semiconductor
The production of pinboard, therefore, far from requirement of the user to large scale silicon inserter technique is met, the Experience Degree of user is not high.
In conclusion existing exposure method, which exists, is not able to satisfy requirement of the user to large scale silicon inserter technique, use
The poor problem of family Experience Degree.
Summary of the invention
In view of this, the purpose of the present invention is to provide semiconductor pinboard exposure method and exposure sources, to alleviate
The demand existing in the prior art that user is not able to satisfy to large scale silicon inserter technique, the poor technology of user experience
Problem can improve user experience.
In a first aspect, the embodiment of the invention provides a kind of semiconductor pinboard exposure method, semiconductor pinboard includes
First area and second area；
The described method includes:
By the exposure region of the first area merging exposure sources of the semiconductor pinboard；
It is exposed using first area of first mask plate to the semiconductor pinboard；
The semiconductor pinboard is translated, by the second area merging exposure sources of the semiconductor pinboard
Exposure region；
It is exposed using second area of second mask plate to the semiconductor pinboard, wherein the second area
The pattern of first area described in pattern splicing.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
It states first area and what the second area collectively constituted the semiconductor pinboard works as layer pattern.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein institute
First area and the respective length of the second area are stated within 26 millimeters, the first area and the second area are respectively
Width within 33 millimeters.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein institute
Stating semiconductor pinboard further includes third region；
The method also includes:
The semiconductor pinboard is translated, by the third region merging exposure sources of the semiconductor pinboard
Exposure region；
It is exposed using third region of the third mask plate to the semiconductor pinboard.
With reference to first aspect, the embodiment of the invention provides the 4th kind of possible embodiments of first aspect, wherein institute
The boundary between first area and the second area is stated in fold-line-shaped.
With reference to first aspect, the embodiment of the invention provides the 5th kind of possible embodiments of first aspect, wherein institute
The boundary stated between first area and the second area partly overlaps in fold-line-shaped.
Second aspect, the embodiment of the present invention also provide a kind of exposure sources, comprising: light source assembly, support plate, lens group, base
Platform and mobile mechanism；
The support plate is for placing different mask plates；
The light that the light source assembly issues is incident upon the base station through mask plate and the lens group, forms exposure region；
The base station is used to translate semiconductor pinboard for placing semiconductor pinboard, the mobile mechanism,
The different zones of semiconductor pinboard are made to be placed in the exposure region；Wherein, there is pattern splicing between the different mask plate
Corresponding relationship.
In conjunction with second aspect, the embodiment of the invention provides the first possible embodiments of second aspect, wherein institute
Stating light source assembly includes light source and the first lens；
The light that the light source issues is through first lens projects to the support plate.
In conjunction with the first possible embodiment of second aspect, the embodiment of the invention provides second of second aspect
Possible embodiment, wherein the lens group includes the second lens and the third lens, first lens, the second lens, the
The flat shape of three lens is ellipse.
In conjunction with second aspect, the embodiment of the invention provides the third possible embodiments of second aspect, wherein institute
The wavelength for stating light source is any one of ultraviolet light, deep ultraviolet light or extreme ultraviolet region, and the mobile mechanism is using mechanical
Any one of hand, motor or hydraulic cylinder.
The embodiment of the present invention bring it is following the utility model has the advantages that
In semiconductor pinboard exposure method provided in an embodiment of the present invention, the semiconductor pinboard is divided into the firstth area first
The different zones such as domain and second area, by the exposure region that the first area of above-mentioned semiconductor pinboard is placed in exposure sources；
It is exposed using first area of first mask plate to semiconductor pinboard；Then semiconductor pinboard is translated, it will
The exposure region of the second area merging exposure sources of semiconductor pinboard；Using the second mask plate to the second of semiconductor pinboard
Region is exposed, wherein the pattern of first area described in the pattern splicing of the second area.Therefore, which can be with
It realizes the exposure to large scale semiconductor pinboard, meets production of the user to large scale semiconductor pinboard, semiconductor switching
More components can be formed on plate, and the lines of pattern do not need the fine of production yet, avoid vertical and horizontal double exposure, this
Outside, which is exposed by the subregion to semiconductor pinboard, can be expanded exposure field, be met the big field of silicon inserter
Size requirement, can satisfy requirement of the user to large scale silicon inserter technique, improve user experience.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of flow diagram for semiconductor pinboard exposure method that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram of semiconductor pinboard in Fig. 1；
Fig. 3 is the structural schematic diagram for the mask plate that the embodiment of the present invention one provides: (a) first the second exposure mask of mask plate (b)
Version；
Fig. 4 is another structural schematic diagram of mask plate that the embodiment of the present invention one provides: (a) the first mask plate (b) the
Two mask plates；
Fig. 5 is that second embodiment of the present invention provides the flow diagrams of another semiconductor pinboard exposure method；
Fig. 6 is the structural schematic diagram of semiconductor pinboard in Fig. 4；
Fig. 7 is the structural schematic diagram for the exposure sources that the embodiment of the present invention three provides.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Existing exposure method, which exists, at present is not able to satisfy requirement of the user to large scale silicon inserter technique, user experience
Poor problem is spent, this is based on, a kind of semiconductor pinboard exposure method and exposure sources provided in an embodiment of the present invention can
To alleviate the demand existing in the prior art for not being able to satisfy user to large scale silicon inserter technique, user experience is poor
Technical problem can improve user experience.
To be exposed to a kind of semiconductor pinboard disclosed in the embodiment of the present invention first convenient for understanding the present embodiment
Light method describes in detail.
Embodiment one:
As shown in Figure 1 to Figure 3, the embodiment of the invention provides a kind of semiconductor pinboard exposure method, which turns
Fishplate bar exposure method can be applied in the exposure field of semiconductor storage unit, be particularly suitable for large scale silicon inserter technique
(silicon interposer process), specifically, the semiconductor pinboard exposure method can be applied to 2.5D or
3D IC (integrated circuit) manufacturing field.
Fig. 1 is combined to turn the semiconductor so that semiconductor pinboard includes first area 100 and second area 200 as an example below
Fishplate bar exposure method is illustrated.Wherein, the pattern of first area described in the pattern splicing of the second area.
The semiconductor pinboard exposure method mainly comprises the steps that
Step S101: by the exposure region of the first area merging exposure sources of above-mentioned semiconductor pinboard.
Above-mentioned semiconductor pinboard can be large scale semiconductor pinboard, i.e. the size of semiconductor pinboard is greater than single
Expose the maximum scan field size (26*33 millimeters) of full-size or scanner.
Above-mentioned semiconductor pinboard is semiconductor pinboard to be exposed, i.e. semiconductor pinboard is pre-coated with photoresist
(resist, also known as photoresist), photoresist by three kinds of photosensitive resin, sensitizer and solvent main components form to photosensitive
The mixing liquid of sense.Wherein, in exposure region photocuring reaction can soon occur for photosensitive resin, so that this material after illumination
Significant change occurs for the physical property of material, especially dissolubility, affinity etc., then handles, dissolves solvable through solvent appropriate
Property part, can be obtained required image or pattern.Specifically, the pattern based on mask plate, photoresist has the portion being exposed
The part divided and be not exposed.It recycles developer solution to develop photoresist, the part that photoresist is exposed can be removed, protect
The part (positive photoresist) for staying photoresist not to be exposed, or the part that removal photoresist is not exposed, retain photoresist quilt
The part (negative photoresist) of exposure, so that photoresist be made to form required pattern.It should be pointed out that photoresist should have
Smaller surface tension makes photoresist have good mobility and covering.
Further, above-mentioned photoresist can be positive photoresist, it is also possible to negative photoresist, positive photoresist exposes
It can remove after light, retain after negative photoresist exposure, above-mentioned positive photoresist generallys use photolysis type photoresist and is made, on
It states negative photoresist and generallys use photo-crosslinking type photoresist and be made.Preferably, here using photoresist be exposure process
In relatively conventional negative photoresist.
Specifically, the photoresist used in the present embodiment is SU-8 series negative photoresist.
The precision of exposure sources in the present embodiment is having a size of 50 nanometers, that is, the minimum dimension in first area that is exposed
It is 50 nanometers.
When it is implemented, the step is mainly executed by following steps:
Semiconductor pinboard to be exposed uniformly coated with SU-8 series negative photoresist is placed into exposure sources by A
On base station.
B control mobile mechanism translates semiconductor pinboard, and the first area of semiconductor pinboard is made to be placed in exposure
Area.
Step S102: it is exposed using first area of first mask plate to above-mentioned semiconductor pinboard.
Wherein, the first circuit pattern of photoetching is provided on above-mentioned first mask plate.
Specifically, the first mask plate to be placed on to the top of the exposure region of above-mentioned exposure sources, the light of exposure sources is opened
Source is exposed using first area of first mask plate to above-mentioned semiconductor pinboard, is realized the on the first mask plate
One circuit pattern is transferred to the first area of semiconductor pinboard.
Step S103: translating above-mentioned semiconductor pinboard, and the second area of above-mentioned semiconductor pinboard is placed in
The exposure region of exposure sources.
Specifically, closing the light source of exposure sources after the completion of first area exposes, controlling the mobile mechanism of exposure sources
Semiconductor pinboard is translated, by the exposure region of the second area merging exposure sources of semiconductor pinboard.
Above-mentioned mobile mechanism can be manipulator, motor or hydraulic cylinder.Mobile mechanism in the present embodiment uses machine
Tool hand.
Step S104: it is exposed using second area of second mask plate to above-mentioned semiconductor pinboard.
Wherein, the second circuit pattern of photoetching is provided on the second mask plate.
Specifically, the second mask plate to be placed on to the top of the exposure region of above-mentioned exposure sources, it is again turned on exposure sources
Light source, be exposed using second area of second mask plate to above-mentioned semiconductor pinboard, realization will be on the second mask plate
Second circuit pattern be transferred to the second area of semiconductor pinboard, complete the figure of the pattern splicing first area of second area
Case, to realize the splicing of the pattern of second area and the pattern of first area.
It should be pointed out that the first area and the second area collectively constitute the semiconductor pinboard work as layer
Pattern, the i.e. pattern of first area and the pattern splicing of second area obtain the current layer pattern of semiconductor pinboard.
In order to reduce the alignment error of the first circuit pattern and second circuit pattern, the first circuit pattern and the second electricity are improved
The alignment precision of road pattern, in the present embodiment, the boundary between first area and second area are in fold-line-shaped.
When specific implementation, the lower edge of the pattern boundaries of the first mask plate can be set to broken line 10, the second mask plate
The top edges of pattern boundaries be arranged to match the broken line 20 of (shape, size are adapted) with above-mentioned broken line 10 so that
Boundary between first area and second area is in fold-line-shaped, can easily realize pair between pattern by this kind of mode
Standard improves alignment precision, while this method is simple and easy, is easy alignment, facilitates the splicing of pattern.
Further, square waveform, zigzag, sine wave or cosine wave isopulse wave can be set into above-mentioned fold-line-shaped
Shape, also can be set is step.The setting shape of fold-line-shaped can be arranged according to actual needs, can from pattern accuracy, set
Difficulty etc. is set to comprehensively consider.
In the present embodiment, fold-line-shaped is set as step, and fold-line-shaped 3 includes sequentially connected first line department 31, second
Line department and 32 third fold line portions 33, above-mentioned first line department is parallel with above-mentioned third fold line portion, above-mentioned second line department with it is upper
It states the first line department and above-mentioned third fold line portion is mutually perpendicular to, this fold-line-shaped setting is simple and convenient, and is conducive to raising pair
Quasi- precision.
In one embodiment, above-mentioned first area and the respective length of above-mentioned second area are above-mentioned within 26 millimeters
First area and the respective width of above-mentioned second area are within 33 millimeters.
Further, above-mentioned first area and the respective length of above-mentioned second area are 15 to 25 millimeters, above-mentioned first
Region and the respective width of above-mentioned second area are 20 to 30 millimeters.
Specifically, in the present embodiment, above-mentioned first area and the respective length of above-mentioned second area are 23 millimeters, above-mentioned
First area and the respective width of above-mentioned second area are 28 millimeters.
In semiconductor pinboard exposure method provided in an embodiment of the present invention, the semiconductor pinboard is divided into the firstth area first
The different zones such as domain and second area, by the exposure region that the first area of above-mentioned semiconductor pinboard is placed in exposure sources；
It is exposed using first area of first mask plate to the semiconductor pinboard；Then semiconductor pinboard is carried out flat
It moves, by the exposure region of the second area merging exposure sources of semiconductor pinboard；Using the second mask plate to semiconductor pinboard
Second area be exposed, the wherein pattern of the pattern splicing first area of second area.Therefore, which can be with
It realizes the exposure to large scale semiconductor pinboard, meets production of the user to large scale semiconductor pinboard, semiconductor switching
More components can be formed on plate, and the lines of pattern do not need the fine of production yet, avoid vertical and horizontal double exposure, this
Outside, which is exposed by the subregion to semiconductor pinboard, can be expanded exposure field, be met the big field of silicon inserter
Size requirement, can satisfy requirement of the user to large scale silicon inserter technique, improve user experience, meanwhile, first area
Boundary between second area is in fold-line-shaped, can reduce the error of combinations of patterns in traditional technology, improve the alignment of pattern
Precision is conducive to the quality for improving the chip of semiconductor pinboard and its carrying, improves user experience.
The alignment precision for ensuring the first circuit pattern and second circuit pattern is considered how, further, above-mentioned
Fold-line-shaped between one region and above-mentioned second area partly overlaps, i.e., the folding between above-mentioned first area and above-mentioned second area
Linear part be it is completely overlapped, in other words, above-mentioned first area partly overlaps with above-mentioned second area.
Referring to Fig. 4, it is illustrated for when fold-line-shaped is step below.It, can be by the when specific implementation
The broken line 10 of the lower edge setting of the pattern boundaries of one mask plate include broken line 101 and broken line 102 (broken line 101 and broken line 102 it
Between part constitute the boundary between the first area and the second area, i.e. fold-line-shaped part), the figure of the second mask plate
The broken line 20 that (shape, size be adapted) is matched with above-mentioned broken line 10 of the top edge setting on case boundary include broken line 201 and
Broken line 202 when splicing, keeps broken line 101 and broken line 202 overlapped, and broken line 102 and broken line 201 are overlapped, so that
Boundary between first area and second area is in the boundary between fold-line-shaped and first area and second area in fold-line-shaped portion
Dividing is overlapping, can conveniently realize the alignment between pattern by this kind of mode, further improve pair of pattern
Quasi- precision reduces the unfavorable image that combinations of patterns error generates the photoetching quality of semiconductor pinboard, improves chip
Yield, while this method is simple and easy, is easy alignment, facilitates the splicing of pattern.
Embodiment two:
As shown in Figure 5 and Figure 6, the embodiment of the invention provides another semiconductor pinboard exposure method, work as semiconductor
Switching board size further increases, and semiconductor pinboard to be exposed in the present embodiment is divided into first area 100, second area
200 and third region 300, the boundary between first area and second area is in fold-line-shaped 3, likewise, in order to guarantee the secondth area
The alignment in domain and third zone map, further, the boundary between above-mentioned second area and above-mentioned third region are in the second folding
Linear 4, the second fold-line-shaped 4 here is arranged to sinusoidal waveform (including a cycle), and the second mask plate and third mask plate can
It is used to form the second fold-line-shaped.
Specifically, the exposure method includes:
Step S201: by the exposure region of the first area merging exposure sources of above-mentioned semiconductor pinboard.
Step S202: it is exposed using first area of first mask plate to above-mentioned semiconductor pinboard.
Step S203: translating above-mentioned semiconductor pinboard, and the second area of above-mentioned semiconductor pinboard is placed in
The exposure region of exposure sources.
The different situation of exposure demand when being exposed in view of the region different to semiconductor pinboard, such as first
Demand when region, second area exposure to light exposure, exposure power etc. is different.
Further, this method further includes the steps that replacing light source:
Step S204: replacing the light source of exposure sources, to meet the conditions of exposure of second area.
Step S205: it is exposed using second area of second mask plate to above-mentioned semiconductor pinboard.
Step S206: translating above-mentioned semiconductor pinboard, and the third region of above-mentioned semiconductor pinboard is placed in
The exposure region of exposure sources；
Step S207: it is exposed using third region of the third mask plate to above-mentioned semiconductor pinboard.
It should be noted that the specific implementation step of the above-mentioned exposure to third region is referred to second area progress,
If the conditions of exposure in third region is different from the conditions of exposure of second area, also may include replacement light source the step of, in order to
Description is succinct, and which is not described herein again.
In addition, step S204 is only to describe to be easy to use, it is not offered as its sequencing, also should not be construed as to the present invention
The limitation of embodiment, step S204 can be carried out before second area exposure after completing first area exposure, such as
Step S204 can also be carried out before step S203.
In view of the increase of semiconductor switching board size, inserter instrument increase, the increase of the complexity of circuit pattern, partly lead
Body pinboard can also include the fourth region, the 5th region ....At this point, specific exposure method is referred to first area and the
The exposure method in two regions, and so on, details are not described herein.
Embodiment three:
Fig. 7 shows the structural schematic diagram of exposure sources provided in an embodiment of the present invention, which includes: light source group
Part 61, lens group 62, base station, support plate and mobile mechanism's (being not shown in the drawing)；
Above-mentioned support plate is for placing different mask plates 63；
The light that above-mentioned light source assembly issues is incident upon above-mentioned base station through mask plate and said lens group, forms exposure region；
Above-mentioned base station is used to place semiconductor pinboard 64, and photoresist 65 is coated on above-mentioned semiconductor pinboard, above-mentioned
Mobile mechanism makes the different zones of above-mentioned semiconductor pinboard be placed in above-mentioned exposure for translating to above-mentioned semiconductor pinboard
Light area；Wherein, it is different to can be realized semiconductor pinboard with the corresponding relationship of pattern splicing between the different mask plate
The pattern splicing in region works as layer pattern to obtain semiconductor pinboard.
Further, above-mentioned mobile mechanism uses any one of manipulator, motor or hydraulic cylinder,
Preferably, above-mentioned mobile mechanism uses manipulator.
Further, above-mentioned light source assembly includes light source 611 and the first lens 612；The light that above-mentioned light source issues is through upper
The first lens projects are stated to above-mentioned support plate.
Wherein, above-mentioned light source needs claimed below: a. has wavelength appropriate.Wavelength is shorter, and the characteristic size that can be exposed is got over
It is small；B. there are enough energy, energy is bigger, and the time for exposure is shorter；C. exposure energy must be evenly distributed in exposure region, and one
As using the concepts such as the uniformity or unevenness of light, the depth of parallelism of light measure whether light is uniformly distributed.
Preferably, the wavelength of above-mentioned light source is any one of ultraviolet light, deep ultraviolet light or extreme ultraviolet region.Its
In, the region ultraviolet light (UV), mainly g line (wavelength 436nm) or i line (wavelength 365nm)；Common ultraviolet source is high
It presses arc lamp (high-pressure sodium lamp), there are many sharp spectrum lines for high-pressure sodium lamp, and g line (436nm) therein is used after filtering
Or i line (365nm).
The region deep ultraviolet light (DUV), the laser or wavelength that laser that wavelength is 248nm, wavelength are 193nm are 157nm
Laser；Common deep ultraviolet light source, can be used excimer laser.Such as KrF excimer laser (248nm), ArF standard point
Sub- laser (193nm) and F2Excimer laser (157nm) etc..
The region extreme ultraviolet (EUV), wavelength are 10~15nm；It is corresponding to use EUV light source.
Preferably, said lens group includes the second lens 621 and the third lens 622.
Further, the flat shape of above-mentioned first lens, the second lens, the third lens is ellipse.
The Exposure mode of the exposure sources is using scanning stepping projection exposure (Scanning-Stepping Project
Printing), it is exposed using 6 inches of mask plate according to the ratio of 4:1, exposure area (Exposure Field) 26mm
× 33mm (mm is millimeter).The exposure sources have the advantage that the visual field for increasing and exposing every time；It is uneven to provide silicon chip surface
Whole compensation；The dimensional homogeneity of entire silicon wafer is improved, precision is higher；In addition, the exposure sources are with the following functions: smoothly spreading out
Effect is penetrated, Uniform Illumination, optical filtering and cold light processing is realized, realizes floodlighting and light intensity regulating etc..
Exposure sources provided in an embodiment of the present invention have with semiconductor pinboard exposure method provided by the above embodiment
Identical technical characteristic reaches identical technical effect so also can solve identical technical problem.
The technical effect and preceding method of exposure sources provided by the embodiment of the present invention, realization principle and generation are implemented
Example is identical, and to briefly describe, Installation practice part does not refer to place, can refer to corresponding contents in preceding method embodiment.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
It with the specific work process of device, can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
In all examples being illustrated and described herein, any occurrence should be construed as merely illustratively, without
It is as limitation, therefore, other examples of exemplary embodiment can have different values.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
The flow chart and block diagram in the drawings show the system of multiple embodiments according to the present invention, method and computer journeys
The architecture, function and operation in the cards of sequence product.In this regard, each box in flowchart or block diagram can generation
A part of one module, section or code of table, a part of above-mentioned module, section or code include one or more use
The executable instruction of the logic function as defined in realizing.It should also be noted that in some implementations as replacements, being marked in box
The function of note can also occur in a different order than that indicated in the drawings.For example, two continuous boxes can actually base
Originally it is performed in parallel, they can also be executed in the opposite order sometimes, and this depends on the function involved.It is also noted that
It is the combination of each box in block diagram and or flow chart and the box in block diagram and or flow chart, can uses and execute rule
The dedicated hardware based system of fixed function or movement is realized, or can use the group of specialized hardware and computer instruction
It closes to realize.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.The apparatus embodiments described above are merely exemplary, for example, the division of said units,
Only a kind of logical function partition, there may be another division manner in actual implementation, in another example, multiple units or components can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be through some communication interfaces, device or unit it is indirect
Coupling or communication connection can be electrical property, mechanical or other forms.
Above-mentioned unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
It, can be with if above-mentioned function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in the executable non-volatile computer-readable storage medium of a processor.Based on this understanding, of the invention
Technical solution substantially the part of the part that contributes to existing technology or the technical solution can be with software in other words
The form of product embodies, which is stored in a storage medium, including some instructions use so that
One computer equipment (can be personal computer, server or the network equipment etc.) executes in each embodiment of the present invention
State all or part of the steps of method.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-
Only Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can be with
Store the medium of program code.
Finally, it should be noted that above above-described embodiment, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, protection scope of the present invention answers above-mentioned be subject to the protection scope in claims.
Claims (10)
1. a kind of semiconductor pinboard exposure method, which is characterized in that semiconductor pinboard includes first area and second area；
The described method includes:
By the exposure region of the first area merging exposure sources of the semiconductor pinboard；
It is exposed using first area of first mask plate to the semiconductor pinboard；
The semiconductor pinboard is translated, by the exposure of the second area merging exposure sources of the semiconductor pinboard
Area；
It is exposed using second area of second mask plate to the semiconductor pinboard, wherein the pattern of the second area
Splice the pattern of the first area.
2. the method according to claim 1, wherein the first area and the second area collectively constitute institute
That states semiconductor pinboard works as layer pattern.
3. the method according to claim 1, wherein the first area and the respective length of the second area
Within 26 millimeters, the first area and the respective width of the second area are within 33 millimeters.
4. the method according to claim 1, wherein the semiconductor pinboard further includes third region；
The method also includes:
The semiconductor pinboard is translated, by the exposure of the third region merging exposure sources of the semiconductor pinboard
Area；
It is exposed using third region of the third mask plate to the semiconductor pinboard.
5. method according to claim 1 to 4, which is characterized in that the first area and secondth area
Boundary between domain is in fold-line-shaped.
6. according to the method described in claim 5, it is characterized in that, boundary between the first area and the second area
It partly overlaps in fold-line-shaped.
7. a kind of exposure sources, which is characterized in that including light source assembly, support plate, lens group, base station and mobile mechanism；
The support plate is for placing different mask plates；
The light that the light source assembly issues is incident upon the base station through mask plate and the lens group, forms exposure region；
The base station makes half for translating to semiconductor pinboard for placing semiconductor pinboard, the mobile mechanism
The different zones of conductor pinboard are placed in the exposure region；Wherein, with pair of pattern splicing between the different mask plate
It should be related to.
8. exposure sources according to claim 7, which is characterized in that the light source assembly includes light source and the first lens；
The light that the light source issues is through first lens projects to the support plate.
9. exposure sources according to claim 8, which is characterized in that the lens group includes that the second lens and third are saturating
Mirror, first lens, the second lens, the third lens flat shape be ellipse.
10. according to exposure sources described in claim 7,8 or 9, which is characterized in that the wavelength of the light source is ultraviolet light, depth
Any one of ultraviolet light or extreme ultraviolet region, the mobile mechanism are any using manipulator, motor or hydraulic cylinder
It is a kind of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711111867.4A CN109782542A (en) | 2017-11-10 | 2017-11-10 | Semiconductor adapter plate exposure method and exposure equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711111867.4A CN109782542A (en) | 2017-11-10 | 2017-11-10 | Semiconductor adapter plate exposure method and exposure equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109782542A true CN109782542A (en) | 2019-05-21 |
Family
ID=66485390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711111867.4A Pending CN109782542A (en) | 2017-11-10 | 2017-11-10 | Semiconductor adapter plate exposure method and exposure equipment |
Country Status (1)
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|---|---|
| CN (1) | CN109782542A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110794654A (en) * | 2019-11-19 | 2020-02-14 | 江苏上达电子有限公司 | Novel exposure machine structure exposure method capable of producing super-long products |
| CN110794655A (en) * | 2019-11-19 | 2020-02-14 | 江苏上达电子有限公司 | Roller type curved surface exposure method |
| WO2024016384A1 (en) * | 2022-07-21 | 2024-01-25 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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