JP2001308004A - Method of manufacturing semiconductor device and electron beam exposure method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, capable of surely connecting the divided patterns together, lessening a width change in a line at a joint between the transferred patterns, when the divided patterns are formed on a mask and then transferred to a resist for the formation of the pattern of a semiconductor device. SOLUTION: This manufacturing method comprises a first process of forming a first mask, in which a tapered projection getting gradually thinner in width toward its tip, is provided to the connecting edge of a first pattern out of the adjacent divided patterns, and the length of the projection is set 1 to 5 times as long as the width of the pattern (a), a second process of forming a second mask, in which a recessed part complementary in shape to the projection of the first pattern, is provided to the connecting edge of a second pattern out of the adjacent divided patterns, and the length of the recessed part is set 1 to 5 times as long as the width of the pattern (b), and a third process of transferring the first and second pattern to a resist, combining the projection of the first pattern and recessed part of the second pattern together by the use of the first and second mask (c).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of dividing a design pattern into a plurality of patterns, forming respective masks, and sequentially using these masks to form an electron beam. The present invention relates to a method of manufacturing a semiconductor device in which a design pattern is formed on a wafer by irradiating a plurality of divided patterns on the wafer by irradiating the wafer. The invention also relates to an exposure method using an electron beam.

[0002]

2. Description of the Related Art Generally, when a pattern of a semiconductor exposure apparatus is formed on a resist on a wafer using an electron beam exposure apparatus, a transmission hole for projecting an electron beam in accordance with the shape of a pattern area. Is used. However, the area that can be collectively transferred with one mask is limited. When the design pattern is a hollow pattern, it is necessary to prevent the mask from being in a hollow state. Further, when the design pattern is very large, the mask may be deformed.

Therefore, when a pattern is formed on a stencil mask, a design pattern is divided into a plurality of small pattern areas, and each mask is created. Exposure is performed by irradiating an electron beam while these masks are sequentially arranged in an electron optical system, and the pattern formed on the mask is transferred to a resist applied on a wafer. At this time, the divided small areas are collectively transferred by deflecting the electron beam or moving the position of the mask and the wafer. As a result, the plurality of divided pattern areas are exposed adjacent to each other, whereby the entire design pattern is formed on the wafer.

FIGS. 15 and 16 show examples of divided patterns. When the design pattern is a hollow pattern as shown in FIG. 15A, the pattern on the mask is changed to FIG. 15B and FIG. It is divided into two patterns as shown. Also, even when the design pattern is a very long line segment as shown in FIG. 16A, the pattern on the mask is shown in FIGS. 16B and 16C in order to prevent deformation of the mask. Is divided into such two patterns. The plurality of divided pattern areas are exposed adjacent to each other, whereby the entire design pattern is formed on the wafer.

According to such a pattern forming method, there is a limit in the accuracy of alignment of a pattern area divided on a mask on a wafer. Therefore, a plurality of divided pattern areas are exposed adjacently or overlapped. In this case, a positional shift occurs to a considerable extent. In recent semiconductor devices having an ultrafine pattern, pattern deformation due to this positional shift causes a pattern connection failure, disconnection, and the like, and has been a serious problem.

Conventionally, as a countermeasure against this problem, as shown in FIG. 17, a method of preventing disconnection or the like by overlapping a part of a pattern in a hatched portion has been adopted.

[0007]

However, according to the technique of partially overlapping the pattern as described above, as shown in FIG. 17, the pattern line width of the overlap-exposed portion becomes large. In addition, the amount of increase in the pattern line width itself also varies due to the variation in the amount of overlap caused by the pattern displacement error.

[0008] Therefore, Japanese Patent Publication No. 27060
No. 99, in a line interconnected in an adjacent pattern, at least one protrusion which is relatively narrower than a line width is provided at an end of one line, and the protrusion is provided at an end of the other line. Providing a projection having a line-symmetric shape is described. However, when working on the tip shape of a pattern, a concept for optimizing the shape has not been established.

In particular, in the case where projections are provided at the tips of the respective patterns and the projections of these patterns are overlapped to connect the patterns, the line width of the overlapping exposure portion is increased due to the blur of the exposure beam. Depends heavily on quantity. Since the beam blur amount of the electron beam exposure apparatus changes due to the space charge effect or the like, the dimensions of the projections provided in the pattern cannot be made the same at all positions on the mask. Also, when the beam blur amount changes due to the instability of the electron optical system, the line width changes at the joint of the pattern.

In view of the above, the present invention provides a method of forming a plurality of divided patterns on each mask and transferring the divided patterns onto a resist applied on a wafer by using an electron beam exposure apparatus, thereby forming a pattern of a semiconductor device. It is an object of the present invention to provide a method of manufacturing a semiconductor device and an electron beam exposure method capable of reducing a change in line width of a connection portion of a transferred pattern when forming the pattern and reliably connecting a plurality of divided patterns. I do.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises: forming a plurality of divided patterns obtained by dividing a desired pattern on each mask; A method for manufacturing a semiconductor device, wherein a desired pattern is formed by transferring a divided pattern of each mask to a resist applied on a wafer using an electron beam exposure apparatus, wherein the semiconductor device according to the first aspect of the present invention is provided. The method of manufacturing the device comprises the steps of: (a) forming, at the connection end of the first pattern among the plurality of divided patterns adjacent to each other, a projection whose line width becomes narrower toward the distal end; Forming a first mask so that the length of the first mask is 1 to 5 times the pattern width; and (b) connecting a second pattern of the plurality of divided patterns adjacent to each other to a second pattern. 1 pattern Forming a recess having a complementary shape to the convex portion, so that the length of the recess is from 1 to 5 times the pattern width, a step of creating a second mask, (c) first
And transferring the first and second patterns to a resist applied on the wafer so as to combine the convex portions of the first pattern and the concave portions of the second pattern using the second mask. I do.

Further, the method of manufacturing a semiconductor device according to the second aspect of the present invention comprises the steps of: (a) connecting a first end of a plurality of divided patterns adjacent to each other to a first end of a plurality of divided patterns having a curved surface at a tip end; Forming a first mask so as to form a concave portion surrounded by the convex portion; and (b) connecting a second pattern of the plurality of divided patterns adjacent to each other to a connection end of the second pattern.
Forming a step provided corresponding to the position of the curved surface of the two protrusions of the first pattern, and a protrusion provided corresponding to the recess of the first pattern continuously with the step. And (c) using the first and second masks to combine the first and second patterns so as to combine the irregularities of the first and second patterns. Transferring the pattern to a resist applied on the wafer.

Further, the method of manufacturing a semiconductor device according to the third aspect of the present invention comprises the steps of: (a) connecting the first pattern to the connection end of the first pattern among the plurality of divided patterns adjacent to each other in the longitudinal direction; Forming a first mask so as to form an inclined portion cut obliquely with respect to the first pattern; and (b) forming a second end of a connection end of a second pattern among a plurality of divided patterns adjacent to each other. Forming a second mask so as to form an inclined portion having a shape complementary to the inclined portion of the first pattern on the side of (a), (c) using the first and second masks, Transferring the first and second patterns to a resist applied on a wafer so as to combine the inclined portions of the first pattern and the inclined portions of the second pattern.

In addition, the method for manufacturing a semiconductor device according to the fourth aspect of the present invention comprises the steps of: (a) connecting the first pattern to the connecting end of the first pattern among a plurality of divided patterns adjacent to each other; Forming a first mask so as to form an inclined portion cut obliquely with respect to a direction and a concave portion provided in a part of the inclined portion; and (b) a plurality of divisions adjacent to each other. Forming a second mask so that the connection end of the second pattern in the pattern has a shape complementary to the unevenness of the first pattern; and (c) forming the first and second masks. Transferring the first and second patterns to a resist applied on the wafer so as to combine the irregularities of the first and second patterns.

According to the above-described manufacturing method, when transferring a plurality of patterns divided on a mask to a resist applied on a wafer to form a pattern of a semiconductor device, the tip shapes of the divided patterns are complemented. Therefore, when a position error of each pattern occurs, the portion to be double-exposed is reduced, and even when the blur amount of the exposure beam changes, the line width change of the connection portion of the pattern of the semiconductor device is reduced. In addition, a plurality of divided patterns can be reliably connected. The method of manufacturing a semiconductor device described above is such that a plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are formed on a wafer by using an electron beam. By transferring and connecting the divided patterns on the wafer, the desired pattern can be understood as an electron beam exposure method for transferring and exposing the desired pattern.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a pattern on a mask used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. When the design pattern is a long line segment as shown in FIG. 1A, this is divided into two complementary patterns 110 and 120 as shown in FIGS. 1B and 1C. To create each mask. The pattern 110 has a protrusion at the connection end, and the pattern 120 has a recess at the connection end. These dimensions will be described later in detail. The pattern on these masks is transferred to the resist formed on the wafer by sequentially irradiating an electron beam with a mask on which a pattern 110 having a convex portion is formed and a mask on which a pattern 120 having a concave portion is formed. Thus, regions such as a gate electrode, an impurity diffusion region, and a wiring are defined.

Next, an electron beam exposure apparatus for irradiating an electron beam will be described with reference to FIG. FIG. 2 is a diagram showing an image forming relationship in the electron optical system of the electron beam exposure apparatus. The electron gun 11 emits an electron beam downward. Below the electron gun 11, two-stage condenser lenses 13 and 15 are provided. The electron beam passes through these condenser lenses 13 and 15 and forms a crossover in an opening provided in the blanking diaphragm 17. By operating these two condenser lenses 13 and 15 as a zoom lens, the current density with which the mask 20 is irradiated can be varied.

Above and below the condenser lenses 13 and 15,
Two-stage diaphragms 12 and 16 having rectangular openings (sub-field limiting openings) are provided. These rectangular apertures pass only electron beams in a region corresponding to one sub-view included in the main view. An image formed by the opening of the first diaphragm 12 is formed on the second diaphragm 16 by the condenser lenses 13 and 15.

On the side of the blanking diaphragm 17, a sub-field-of-view selecting deflector 18 is arranged. The sub-field-of-view selecting deflector 18 sequentially scans the electron beam of the illumination system mainly in the X-axis direction, and performs exposure of a plurality of sub-fields arranged in the X-axis direction in one main field of view. A condenser lens 19 is arranged below the sub-field-of-view selection deflector 18. The condenser lens 19 converts the electron beam into a parallel beam, impinges the beam on the mask 20, and forms an image of the opening of the second diaphragm 16 on the mask 20. Below the mask 20, two-stage projection lenses (objective lenses) 22, 23 are provided. Further, an image position adjusting deflector 14 is provided between the projection lenses 22 and 23.

Here, the deflection of the electron beam in the electron beam exposure apparatus shown in FIG. 2 will be described. In this electron beam exposure apparatus, the sub-field selection deflector 18 deflects the electron beam of the illumination system in order to irradiate the divided mask with the electron beam at a high speed. Further, the image position adjusting deflector 14 deflects the electron beam of the projection system in order to make the illuminated mask transmission image adjacent to the wafer stage 25 in accordance with the movement of the wafer stage 25.

For reasons such as not having to enlarge the deflection range of the electron beam of the illumination system, the mask 20
Is mounted on a mask stage 21 that can move in the X-axis direction and the Y-axis direction. The wafer 24 is also mounted on a wafer stage 25 that can move in the X-axis direction and the Y-axis direction. By scanning the mask stage 21 and the wafer stage 25 in directions opposite to each other on the Y-axis, a plurality of main visual fields arranged in the Y-axis direction in the stripes of the chip pattern (rows of the main visual field) are sequentially exposed. Further, the mask stage 21 and the wafer stage 25
Are intermittently scanned in the X-axis direction to sequentially expose a plurality of stripes. The mask stage 21 and the wafer stage 25 are equipped with an accurate position measuring system using a laser interferometer. Further, by adjusting a separate alignment means and a deflector, each of the main field of view and the The sub-views are accurately joined.

When one sub-field of the mask 20 is irradiated with the electron beam, the electron beam patterned by the mask 20 is reduced and deflected by the two-stage projection lenses 22 and 23 to a predetermined position on the wafer 24. Is imaged. An appropriate resist is applied on the wafer 24 on which a necessary conductive film or insulating film is formed, and the resist remains in a portion where a dose exceeding a threshold is given in the case of a negative resist. . Thus, the pattern on the mask 20 is transferred to the resist on the wafer 24.

Actually, the position error E1 due to the deflection of the projection system, the mask stage 21 and the wafer stage 25
The line width of the pattern transferred to the resist changes due to the positional deviation of the pattern on the wafer due to the positional error E2 of FIG. FIG. 3 shows a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when a conventional rectangular pattern as shown in FIG. 16 is used. FIG. Here, the design line width of the pattern was 0.1 μm (100 nm).

When the overlap amount of the projection pattern is zero as shown in FIG. 3B, it is shown in FIG.
As shown in (1), the line width of the transfer pattern is constant, and becomes a desired 100 nm. However, when the projection pattern overlaps by 5 nm as shown in FIG. 3A, the line width of the transfer pattern at the connection portion becomes as thick as 105 nm as shown in FIG. 3D. Would. Conversely, FIG.
In the case where the projection pattern underlaps by 5 nm as shown in FIG. 3C, the line width of the transfer pattern at the connection portion becomes as thin as 95 nm as shown in FIG. Therefore, when controlling the line width change amount of the pattern connection portion to ± 5% or less, the respective projection pattern positional accuracy E1 and E2 required for the electron beam exposure apparatus are ± 5%.
/√2=±3.5 nm. As described above, the pattern position accuracy required for the electron beam exposure apparatus becomes very severe.

FIG. 4 shows a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when a pattern having a convex portion at the tip is used. FIG. By optimizing the size of the convex portion in accordance with the condition of the amount of blur of the electron beam of the electron beam exposure apparatus, the overlap amount of the projection pattern can be set to a reference value as designed, as shown in FIG. In some cases, as shown in FIG. 4E, the line width of the transfer pattern can be kept constant and can be set to a desired value of 100 nm. Further, even when the projection pattern overlaps with the reference value as shown in FIG.
As shown in the figure, the line width change of the transfer pattern with respect to the overlap amount is relatively small, and the positional error of the projection pattern is +
Even when about 13 nm is generated, the line width change amount of the transfer pattern is +
It can be maintained at about 5%. Conversely, when the projection pattern under-laps below the reference value as shown in FIG. 4 (c), a part of the pattern is always overlap-exposed as shown in FIG. 4 (f). The risk of cutting is very low.

However, in the electron beam exposure apparatus, the amount of blur of the electron beam may change depending on the pattern density, the beam deflection position, and the like. When the amount of blur of the electron beam becomes large, as shown in FIG. 4H, even if the overlap amount is a reference value using a projection pattern as shown in FIG. The transfer pattern of the connection part becomes thick. When the projection pattern overlaps with the reference value as shown in FIG. 4A, the line width of the transfer pattern is further increased as shown in FIG. 4G. In such a case, FIG.
As shown in FIG. 4C, it is necessary to obtain a desired transfer pattern as shown in FIG. 4I by making the projection pattern underlap the reference value.

On the other hand, FIG. 5 shows a case where the pattern according to the present embodiment shown in FIG. 1 is used, and the line of the pattern transferred to the resist corresponds to the overlap amount of the pattern projected by the two masks. It is a figure showing change of width. Here, the design line width W of the pattern in FIG.
m (100 nm), and the length L1 of the convex portion of the pattern 110 and the concave portion of the pattern 120 was 400 nm.

When the overlap amount of the projection pattern is zero as shown in FIG.
As shown in (1), the line width of the transfer pattern is constant, and becomes a desired 100 nm. Further, even when the projection patterns overlap as shown in FIG. 5A, the increase in the line width of the transfer pattern caused by the pattern position error is dispersed in the longitudinal direction of the pattern. As shown in the figure, the change in the line width of the transfer pattern is small. Conversely, even when the projected pattern underlaps as shown in FIG. 5C, the thinning of the line width of the transfer pattern caused by the pattern position error is dispersed in the pattern longitudinal direction.
As shown in FIG. 5F, the change in the line width of the transfer pattern is small. According to the dimensions shown in FIG. 5, even if a positional error of the projection pattern occurs by about ± 20 nm, the line width change amount of the transfer pattern becomes ± 5% or less.

Further, when the overlap amount of the projection pattern is zero as shown in FIG. 5B, the continuity of the transfer pattern line width can be obtained regardless of the blur amount of the electron beam. Further, even if there is an overwrap or an underlap, a change in the line width of the transfer pattern due to a change in the blur amount of the electron beam is dispersed in the pattern longitudinal direction. As described above, according to the present embodiment, a very stable line width is exhibited with respect to a pattern position error and an electron beam blur.

For the above reason, the pattern 11 shown in FIG.
The longer the length L1 of the convex portion and the concave portion of the pattern 120, the better. However, the longer the length L1 of the convex portion and the concave portion, the sharper the tip of the pattern becomes, making it difficult to manufacture a mask. According to the current processing technology, the length L1 of the convex portion and the concave portion can be increased to about 500 nm.
Therefore, it is appropriate that the length L1 of the convex portion and the concave portion is 1 to 5 times the design line width W of the pattern.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. Even if an attempt is made to form a pattern as shown in FIG. 1, there may be a case where an acute angle at the tip of the mask pattern is rounded as shown in FIG. 6 due to a manufacturing error depending on the performance of the mask drawing apparatus. In such a case, even if the pattern 111 shown in FIG. 6A and the pattern 121 shown in FIG. 6B are joined, sufficient stitching accuracy cannot be obtained.

Therefore, taking into account errors during the manufacture of the mask,
The pattern is optimized as shown in FIG. That is, FIG.
The pattern 112 shown in FIG. 7A is provided with a step 113 having dimensions L3 and L4 as shown in the figure and a convex part 114 continuous with the step 113, so that the pattern 122 shown in FIG. Improve matching. Here, the sum of the length of the step portion 113 and the length of the convex portion 114 (including the dotted line portion) is L2. Further, since the concave portion of the pattern 122 becomes shorter due to the dulling of the pattern, when designing the pattern 122 shown in FIG. 7B, the length L1 shown in FIG.
Is corrected to the length L5, and based on this, FIG.
Of the pattern 112 shown in FIG. Pattern 12
Since the acute angle pattern at the two edges 2 is rounded, the concave portion of the pattern 122 has a shape surrounded by two convex portions having a curved surface at the tip.

The design shape parameter L2 of the pattern 112
L4 and the like are optimized by, for example, a simulation as shown in FIG. First, in step S1, the pattern shape is determined using the parameters L2 to L4 predicted in advance without considering the mask manufacturing error. next,
In step S2, a mask manufacturing error parameter is applied to this pattern shape to predict the pattern shape of the mask to be manufactured. The mask manufacturing error parameter corresponds to a beam blur of a mask drawing apparatus, a minimum address size, and the like. For example, by approximating the beam blur of the mask drawing apparatus with a Gaussian distribution, the pattern shape of the mask to be manufactured can be calculated from the convolution integral of the design pattern and this Gaussian distribution.

Next, in step S3, the stitching accuracy is determined by simulation. In this simulation, first, a calculation for superimposing the mask pattern predicted in step S2 and the beam blur of the electron beam exposure apparatus is performed. This calculation is performed for each of the pattern 112 and the pattern 122 shown in FIG. Thereafter, assuming that the pattern 112 and the pattern 122 are arranged at a predetermined combination position, calculating the line width of the pattern formed on the wafer based on the dose of the electron beam to the resist on the wafer To determine the stitching accuracy.

Based on the result of step S3, step S
At 4, the stitching accuracy is determined. If the stitching accuracy does not satisfy the predetermined criterion, the process returns to step S1, and the calculation is repeated by changing the parameters L2 to L4. By obtaining the parameters L2 to L4 in this way, it is possible to obtain a pattern having an optimum shape in consideration of a manufacturing error of the mask drawing apparatus.

Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. FIG. 9 is a plan view showing patterns on two masks used in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. When the design pattern is a long line segment as shown in FIG. 9A, this is divided into two complementary patterns 210 and 220 as shown in FIGS. 9B and 9C. To create each mask. The pattern 210 has, at the connection end, an inclined portion 211 obtained by cutting the pattern obliquely to the longitudinal direction, and the pattern 220 also has a similar inclined portion 221 at the connection end. By adopting such a shape, even if the overlap amount of the two patterns changes, the line width change of the pattern formed on the resist can be suppressed similarly to the first embodiment.

FIG. 10 shows that when the pattern according to the present embodiment shown in FIG. 9 is used, the line width of the pattern transferred to the resist corresponds to the overlap amount of the pattern projected by the two masks. It is a figure showing a change. Here, the design line width W of the pattern in FIG.
(100 nm) and the length L of the inclined portions 211 and 221.
6 was 400 nm.

When the overlap amount of the projection pattern is zero as shown in FIG. 10B, the line width of the transfer pattern is constant as shown in FIG.
It will be the desired 100 nm. Further, even when the projection patterns overlap as shown in FIG. 10A, the increase in the line width of the transfer pattern caused by the pattern position error is dispersed in the longitudinal direction of the pattern. As shown in the figure, the change in the line width of the transfer pattern is small.
Conversely, even when the projection pattern under-laps as shown in FIG. 10C, the thinning of the line width of the transfer pattern caused by the pattern position error is dispersed in the pattern longitudinal direction, so that FIG. As shown in the figure, the change in the line width of the transfer pattern is small.

Further, as shown in FIG. 10D, the portion where the transfer pattern becomes thick is shifted between the upper edge and the lower edge, so that the change in the line width is smaller than in the first embodiment. As shown in FIG. 10F, the same applies to a portion where the transfer pattern becomes thin. Inclined portions 211 and 2
The allowable range of the length L6 of 21 is the same as the length L1 in the first embodiment.

In this embodiment, as in the second embodiment, the pattern may be designed in consideration of the rounding of the tip of the mask pattern due to a manufacturing error depending on the performance of the mask drawing apparatus. FIG. 11 shows a pattern shape in that case. When the inclined portion 213 of the pattern 212 shown in FIG. 11A and the inclined portion 223 of the pattern 222 shown in FIG.
The first mask is formed such that the step 13 has a step 214 provided corresponding to the position of the curved surface of the inclined portion 223, and the step formed such that the inclined portion 223 is provided corresponding to the position of the curved surface of the inclined portion 213 A second mask is created to have a portion 224. Here, the design shape parameters L2 to L4 of the patterns 212 and 222 can be optimized by, for example, a simulation as shown in FIG.

Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described. FIG. 12 is a plan view showing patterns on two masks used in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
When the design pattern is a long line segment as shown in FIG. 12A, this is divided into two complementary patterns 310 and 320 as shown in FIGS. 12B and 12C. To create each mask. Pattern 310 is
In the connection end, an inclined portion is provided at an upper edge of the connection end, and a recess is provided in a part of the inclined portion. The pattern 320 is formed complementary to the pattern 310. By adopting such a shape, even if the overlap amount of the two patterns changes, the line width change of the pattern formed on the resist can be suppressed similarly to the first embodiment.

FIG. 13 shows that when the pattern according to the present embodiment shown in FIG. 12 is used, the line width of the pattern transferred to the resist corresponds to the overlap amount of the pattern projected by the two masks. It is a figure showing a change. Here, the design line width W of the pattern in FIG.
m (100 nm), and the length L7 of the concave portion was 400 nm.

When the overlap amount of the projection pattern is zero as shown in FIG. 13B, the line width of the transfer pattern is constant as shown in FIG.
It will be the desired 100 nm. Further, even when the projection pattern overlaps as shown in FIG. 13A, the increase in the line width of the transfer pattern caused by the pattern position error is dispersed in the pattern longitudinal direction. As shown in (1), the change in the line width of the transfer pattern is small.
Conversely, even when the projection pattern underlaps as shown in FIG. 13C, the thinning of the line width of the transfer pattern caused by the pattern position error is dispersed in the pattern longitudinal direction, so that FIG. As shown in the figure, the change in the line width of the transfer pattern is small.

Further, as shown in FIG. 13D, the portion where the transfer pattern becomes thick is shifted between the upper edge and the lower edge, so that the change in the line width is smaller than in the first embodiment. As shown in FIG. 13F, the same applies to a portion where the transfer pattern becomes thin. Further, even if the two patterns 310 and 320 are displaced in the vertical direction, there is little possibility that the patterns are disconnected. The allowable range of the length L7 of the concave portion is the same as the length L1 in the first embodiment.

In this embodiment, as in the second embodiment, the pattern may be designed in consideration of the rounding of the tip of the mask pattern due to a manufacturing error depending on the performance of the mask drawing apparatus. FIG. 14 shows a pattern shape in that case. In the case where the pattern 311 shown in FIG. 14A and the pattern 321 shown in FIG. 14B form a concave part surrounded by two convex parts having a curved surface at the tip at a part of the inclined part. , The slope of the pattern 311 is the pattern 3
The first mask is formed so as to have a stepped portion provided corresponding to the position of the curved surface of one of the protrusions of pattern 21.
The second mask is created so that the 21 inclined portions have step portions provided corresponding to the positions of the curved surfaces of the one convex portion of the pattern 311. Here, the design shape parameters L2 to L4 of the patterns 311 and 321 can be optimized by, for example, a simulation as shown in FIG.

Next, a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention will be described. FIG. 18 is a plan view showing patterns on two masks used in the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.
When the design pattern is a long line segment as shown in FIG. 18 (e), this is converted into two complementary patterns 510-540 and 511-5 as shown in FIGS. 18 (a)-(d).
41, and each mask is created.

Here, FIG. 18A is an ideal oblique line similar to FIG. 1, and the projections 51 of each of the divided patterns 510 and 511 are shown.
0a and the concave portion 511a are formed. On the other hand, FIG. 18B shows an example in which the convex portion 520a is formed into a tapered shape in five steps, and the concave portion 521a is correspondingly formed in five steps. The width of the first part of the convex part 520a is 9 nm.

FIG. 18C shows that the convex portion 530a is formed into a tapered shape in four steps, and the concave portion 531a is correspondingly formed.
Is also an example in which four steps are used. The width of the first part of the convex part 530a is 11 nm.

FIG. 18D shows that the convex portion 540a is tapered in three steps, and the concave portion 541a is correspondingly formed.
Is also an example in which three steps are used. The width of the first part of the convex part 540a is 14 nm.

The features and effects of the fifth embodiment shown in FIGS. 18B to 18D are as follows. Commercial electron beam lithography systems usually used for reticle pattern formation are:
This is for sequentially irradiating spots of an electron beam in the X and Y directions (two perpendicular directions), and is basically not very suitable for drawing oblique lines. Therefore, by making the pattern stepwise, it becomes easy to draw a mask pattern with a commercially available electron beam drawing apparatus. In addition, since a rectangular approximation is often useful for the leading end of the originally divided pattern, a stepwise pattern is preferable for that purpose.

[0051]

As described above, according to the present invention, when a plurality of patterns divided on a mask are transferred to a resist applied on a wafer to form a pattern of a semiconductor device, the divided patterns are formed. By making the leading end shape of the pattern complementary, the portion that is double-exposed when a position error occurs in each pattern is reduced, and even when the blur amount of the exposure beam changes, the connection portion of the pattern of the semiconductor device is changed. Can be reduced, and a plurality of divided patterns can be reliably connected.

[Brief description of the drawings]

FIG. 1 is a plan view showing patterns on two masks used in a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an imaging relationship in an electron optical system of an electron beam exposure apparatus.

FIG. 3 shows a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when a conventional rectangular pattern as shown in FIG. 16 is used. It is a top view.

FIG. 4 shows a case where a pattern having a convex portion at the tip is used.
FIG. 9 is a plan view showing a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks.

FIG. 5 is a plan view showing a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when the pattern shown in FIG. 1 is used.

FIG. 6 is a plan view showing a mask pattern whose tip is rounded due to a manufacturing error depending on the performance of the mask drawing apparatus.

FIG. 7 is a plan view showing patterns on two masks used in a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing a simulation for optimizing a design shape parameter in the second embodiment of the present invention.

FIG. 9 is a plan view showing patterns on two masks used in a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

10 is a plan view showing a change in line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when the pattern shown in FIG. 9 is used.

FIG. 11 is a plan view showing patterns on two masks used in a modification of the third embodiment of the present invention.

FIG. 12 is a plan view showing patterns on two masks used in a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

13 is a plan view showing a change in a line width of a pattern transferred to a resist with respect to an overlap amount of a pattern projected by two masks when the pattern shown in FIG. 12 is used.

FIG. 14 is a plan view showing patterns on two masks used in a modification of the fourth embodiment of the present invention.

FIG. 15 is a plan view showing a hollow design pattern and two patterns obtained by dividing the hollow design pattern.

FIG. 16 is a plan view showing a design pattern of a long line segment and two patterns obtained by dividing the design pattern.

FIG. 17 is a plan view showing that by overlapping a part of the pattern, the pattern line width of a portion subjected to the overlapping exposure is increased.

FIG. 18 is a plan view showing patterns on two masks used in a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Electron gun 12 1st diaphragm 13, 15, 19 Condenser lens 14 Image position adjustment deflector 16 2nd diaphragm 17 Blanking diaphragm 18 Sub-field selection deflector 20 Mask 21 Mask stage 22, 23 Projection lens 24 Wafer 25 Wafer stage 110-112, 120-122 Divided pattern 113 Step 114 Convex 210, 220, 212, 222 Divided pattern 211, 221, 213, 223 Inclined part 310, 320, 311, 321 Divided pattern 510-540, 511- 541 division pattern

Claims (20)

[Claims] 1. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on a wafer by using an electron beam exposure apparatus. Accordingly, there is provided a method of manufacturing a semiconductor device for forming the desired pattern, wherein: (a) a line width is increased toward a connection end of a first pattern among a plurality of divided patterns adjacent to each other in a direction toward the tip; Forming a first convex portion such that a narrow convex portion is formed and the length of the convex portion is 1 to 5 times the pattern width; and (b) the plurality of divided patterns adjacent to each other. A concave portion having a shape complementary to the convex portion of the first pattern is formed at the connection end of the second pattern, and the length of the concave portion is 1 to 5 times the pattern width. Create a second mask And (c) using the first and second masks to combine the first and second patterns on the wafer so that the convex portions of the first pattern and the concave portions of the second pattern are combined. Transferring to a resist applied thereon. 2. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on a wafer using an electron beam exposure apparatus. Accordingly, there is provided a method of manufacturing a semiconductor device for forming the desired pattern, wherein: (a) two projections each having a curved surface at a tip end at a connection end of a first pattern among a plurality of divided patterns adjacent to each other; Forming a first mask so as to form a concave portion surrounded by the portion; and (b) connecting the first mask to a connection end of a second pattern of the plurality of divided patterns adjacent to each other. A step portion provided corresponding to the position of the curved surface of the two convex portions of the pattern;
Forming a second mask so as to form a convex portion provided corresponding to the concave portion of the first pattern continuously with the step portion; and (c) forming the first and second masks. Transferring the first and second patterns to a resist applied on a wafer so as to combine the irregularities of the first pattern and the second pattern using a mask. The above method. 3. The step (a) includes a step of forming a first mask such that a length of a concave portion of the first pattern is 1 to 5 times a pattern width, and the step (b) includes: 3. The method according to claim 2, further comprising the step of forming a second mask such that a length of the convex portion of the second pattern is 1 to 5 times a pattern width. 4. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on a wafer by using an electron beam exposure apparatus. A method of manufacturing the semiconductor device for forming the desired pattern, wherein: (a) connecting the first pattern to a connection end of the first pattern among a plurality of divided patterns adjacent to each other in the longitudinal direction; (B) forming a first mask so as to form an inclined portion which is cut obliquely with respect to the above; and (b) a connecting end of a second pattern of the plurality of divided patterns adjacent to each other; Forming a second mask so as to form an inclined portion having a shape complementary to the inclined portion of the first pattern; and (c) using the first and second masks to form the second mask. 1 putter Transferring the first and second patterns to a resist applied on a wafer so as to combine the inclined portion of the second pattern with the inclined portion of the second pattern. . 5. The step (a) includes a step of forming a first mask so that an inclined portion of the first pattern has a curved surface at a tip, and the step (b) includes a step of forming the first mask. Forming a second mask so that the inclined portion has a curved surface at the tip; and, in the step (a), the inclined portion of the first pattern is the second mask.
Forming a first mask so as to have a step portion provided corresponding to the position of the curved surface of the inclined portion of the pattern, and step (b) comprises: First
5. The method according to claim 4, further comprising the step of: forming a second mask to have a step provided corresponding to the position of the curved surface of the inclined portion of the pattern. 6. The step (a) includes a step of forming a first mask such that a length of an inclined portion of the first pattern is 1 to 5 times a pattern width, and the step (b) includes: 6. The method according to claim 4, further comprising the step of forming a second mask such that the length of the inclined portion of the second pattern is 1 to 5 times the pattern width. 7. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on a wafer by using an electron beam exposure apparatus. A method of manufacturing the semiconductor device for forming the desired pattern, wherein: (a) connecting the first pattern to a connection end of the first pattern among a plurality of divided patterns adjacent to each other in the longitudinal direction; Forming a first mask so as to form an inclined portion cut obliquely with respect to the concave portion and a concave portion provided in a part of the inclined portion; and (b) the plurality of divided portions adjacent to each other. Forming a second mask so that the connection end of the second pattern in the pattern has a shape complementary to the unevenness of the first pattern; and (c) the first and second masks. Using a mask, Serial first pattern and to combine the unevenness of the second pattern, said method characterized by comprising a, a step of transferring the resist applied to the first and second patterns on the wafer. 8. The step (a) includes forming a first mask in a part of the inclined portion of the first pattern so as to form a concave portion surrounded by two convex portions having a curved surface at a tip. The step (b) includes the steps of:
A step of forming a second mask so as to form a concave portion surrounded by two convex portions having a curved surface at a front end, and the step (a) includes: forming the inclined portion of the first pattern into the second mask.
Forming a first mask so as to have a stepped portion provided corresponding to the position of the curved surface of one of the protrusions of the pattern, and the step (b) includes the step of tilting the second pattern. The part is the first
8. The method according to claim 7, further comprising the step of forming a second mask so as to have a step provided corresponding to the position of the curved surface of one of the protrusions of the pattern. 9. The method according to claim 1, wherein the step (a) includes a step of forming a first mask such that a length of the concave portion of the first pattern is 1 to 5 times a pattern width. 9. The method according to 7 or 8. 10. The method according to claim 1, wherein the convex portion and the concave portion or the inclined portion is formed in a step shape.
9. The method according to any one of 9 above. 11. A plurality of division patterns obtained by dividing a desired pattern are formed on each mask, and the division patterns of each mask are transferred to a resist applied on the wafer by using an electron beam, and An electron beam exposure method for transferring and exposing the desired pattern by joining together the divided patterns, wherein (a) a tip end is provided at a connection end of a first pattern of a plurality of divided patterns adjacent to each other. (B) forming a first mask such that a convex portion whose line width becomes narrower as going in the direction and the length of the convex portion becomes 1 to 5 times the pattern width; A concave portion having a shape complementary to the convex portion of the first pattern is formed at a connection end of the second pattern of the plurality of divided patterns adjacent to each other, and the length of the concave portion is one of the pattern width. ~ 5 times Forming a second mask, and (c) using the first and second masks to combine the protrusions of the first pattern with the recesses of the second pattern. Transferring the first and second patterns to a resist applied on the wafer. 12. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on the wafer by using an electron beam, and are transferred to the resist. An electron beam exposure method for transferring and exposing the desired pattern by joining together the divided patterns, wherein (a) a tip end is provided at a connection end of a first pattern of a plurality of divided patterns adjacent to each other. Forming a first mask so as to form a concave portion surrounded by two convex portions having a curved surface, and (b) a connection end of a second pattern among the plurality of divided patterns adjacent to each other. A step portion provided corresponding to the position of the curved surface of the two convex portions of the first pattern;
Forming a second mask so as to form a convex portion provided corresponding to the concave portion of the first pattern continuously with the step portion; and (c) forming the first and second masks. Transferring the first and second patterns to a resist applied on a wafer so as to combine the irregularities of the first pattern and the second pattern using a mask. The above method. 13. The step (a) includes a step of forming a first mask such that a length of a concave portion of the first pattern is 1 to 5 times a pattern width, and the step (b) includes: 13. The method according to claim 12, further comprising the step of forming a second mask such that the length of the protrusion of the second pattern is 1 to 5 times the pattern width. 14. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist coated on the wafer by using an electron beam, and An electron beam exposure method for transferring and exposing the desired pattern by joining the divided patterns in (a), wherein (a) the connecting end of a first pattern of a plurality of divided patterns adjacent to each other is Forming a first mask so as to form an inclined portion obtained by cutting the first pattern so as to be inclined with respect to the longitudinal direction; and (b) a second mask of the plurality of adjacent divided patterns. Forming a second mask at a connection end of the pattern so as to form an inclined portion having a shape complementary to the inclined portion of the first pattern; and (c) the first and second masks. Ma Transferring the first and second patterns to a resist applied on a wafer using a mask so as to combine the inclined portions of the first pattern and the inclined portions of the second pattern. The method as described above. 15. The step (a) includes a step of forming a first mask such that an inclined portion of the first pattern has a curved surface at a tip, and the step (b) includes a step of forming a first mask of the second pattern. Forming a second mask so that the inclined portion has a curved surface at the tip; and, in the step (a), the inclined portion of the first pattern is the second mask.
Forming a first mask so as to have a step portion provided corresponding to the position of the curved surface of the inclined portion of the pattern, and step (b) comprises: First
15. The method according to claim 14, further comprising the step of forming the second mask so as to have a step provided corresponding to the position of the curved surface of the inclined portion of the pattern. 16. The step (a) is performed so that the length of the inclined portion of the first pattern is 1 to 5 times the pattern width.
Forming a second mask so that the length of the inclined portion of the second pattern is 1 to 5 times the pattern width. A method according to claim 14 or claim 15, characterized in that: 17. A plurality of divided patterns obtained by dividing a desired pattern are formed on each mask, and the divided patterns of each mask are transferred to a resist applied on the wafer by using an electron beam, and An electron beam exposure method for transferring and exposing the desired pattern by joining the divided patterns, wherein (a) the connecting end of a first pattern among a plurality of divided patterns adjacent to each other (B) forming a first mask so as to form an inclined portion obtained by cutting the first pattern obliquely with respect to the longitudinal direction and a concave portion provided in a part of the inclined portion; Forming a second mask such that a connection end of a second pattern of the plurality of divided patterns adjacent to each other has a shape complementary to the unevenness of the first pattern; and (c) the step of: No. Transferring the first and second patterns to a resist applied on a wafer using a first and a second mask so as to combine the irregularities of the first and second patterns. The method as described above. 18. A step (a) of forming a first mask so as to form, at a part of an inclined portion of the first pattern, a concave portion surrounded by two convex portions having a curved surface at a tip. The step (b) includes the steps of:
A step of forming a second mask so as to form a concave portion surrounded by two convex portions having a curved surface at a front end, and the step (a) includes: forming the inclined portion of the first pattern into the second mask.
Forming a first mask so as to have a stepped portion provided corresponding to the position of the curved surface of one of the protrusions of the pattern, and the step (b) includes the step of tilting the second pattern. The part is the first
18. The method according to claim 17, further comprising the step of forming a second mask so as to have a step provided corresponding to the position of the curved surface of one of the protrusions of the pattern. 19. The method according to claim 19, wherein the step (a) includes a step of forming a first mask such that a length of a concave portion of the first pattern is 1 to 5 times a pattern width. 1
19. The method according to 7 or 18. 20. The method according to claim 11, wherein the convex and concave portions or the inclined portion are formed in a step shape.
20. The method according to any one of claims 19 to 19.