CN109739782B - Continuous sampling method - Google Patents
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- CN109739782B CN109739782B CN201811610596.1A CN201811610596A CN109739782B CN 109739782 B CN109739782 B CN 109739782B CN 201811610596 A CN201811610596 A CN 201811610596A CN 109739782 B CN109739782 B CN 109739782B
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Abstract
The invention discloses a continuous sampling system and a continuous sampling method thereof, wherein the method comprises the following steps: forbidding the PWM module and forcibly pulling up the output of the PWM module; forbidding data transmission of the SPI module, and reading sampling data received by the SPI module in the cache; writing the AD conversion command into a transmission FIFO of the SPI module; disabling interruption of the DSP chip; clearing a counter of the PWM module and enabling the PWM module; enabling data transmission of the SPI module; enabling the DSP chip to interrupt. The invention uses the DSP chip to drive the AD sampling chip to realize continuous sampling, and the CPU occupies less time and has high sampling efficiency.
Description
Technical Field
The invention relates to a continuous sampling system and a continuous sampling method thereof, belonging to the technical field of computer information acquisition.
Background
The current methods for sampling by using DSP to drive ADS868x are mainly divided into 3 types:
the first method comprises the following steps: and (3) driving in an inquiry mode:
as shown in fig. 2, when the query mode is used for driving, (1) the DSP first pulls down the CS, and then writes a command to the SPI peripheral of the DSP; (2) waiting for the command to be sent; (3) reading a conversion result from the SPI peripheral, (4) waiting for the conversion result to be read, pulling up a CS signal, completing 1 time of sampling through the steps, and repeating the process for multiple times if multiple channels are to be sampled.
And the second method comprises the following steps: driving in an interrupt mode:
as shown in fig. 3, the steps of the clock interrupt mode driving and the query mode are the same, and only a plurality of CPUs do not need to wait for the completion of the command transmission, (1) the DSP pulls down the CS and can execute other tasks after writing the command into the SPI peripheral; (2) after the SPI finishes sending the command, an interrupt is generated, the CPU reads data in an interrupt program, and other tasks can be executed firstly without waiting for finishing reading the data; (3) the SPI peripheral reads the data and generates an interrupt, the CPU processes the data in the interrupt, the CS is pulled up, and the next conversion can be initiated.
And the third is that: interrupt + FIFO:
the intervention time of the CPU can be further reduced if a FIFO of the processor SPI peripheral is used. (1) The DSP pulls down the CS, writes the command for sending the command and the command for reading the result into an FIFO of the SPI peripheral, and then can execute other tasks; (2) when FIFO is empty, it generates interrupt, DSP reads the conversion result in the interrupt program, pulls up CS signal, and can execute next conversion.
The common disadvantages of the three prior art mentioned above are: the efficiency is low. The CPU efficiency is the lowest in the inquiry mode, and the inquiry needs to take much time for the SPI which is a slow device; the interrupt mode is much higher than the query efficiency, but the programming is more complex, if multi-path sampling is executed, the CPU needs to enter interrupt for many times, the efficiency is not high, and the sampling time sequence becomes inaccurate due to the interrupt delay, the condition can be improved by using the FIFO, but the essence is not improved.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a continuous sampling system and a continuous sampling method thereof, which can realize efficient continuous sampling.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
in one aspect, the invention provides a continuous sampling system, comprising a DSP chip and an AD sampling chip;
the DSP chip comprises a PWM module and an SPI module, the PWM module is connected with a CS pin of the AD sampling chip, and the SPI module is connected with an SCLK pin, an SDO pin and an SDI pin of the AD sampling chip;
the DSP chip passes through PWM module output drive AD sampling chip, produces the SPI drive signal who accords with AD sampling chip chronogenesis through the SPI module, realizes AD sampling chip continuous sampling.
Further, the DSP chip is a TI TMS320F28 2837x series DSP chip.
Further, the AD sampling chip is an ADs868x chip.
Further, the SPI module has 16 stages of FIFOs.
Further, the PWM module comprises a period register, a counter and a comparison register;
when the value of the counter is smaller than the value of the comparison register, the PWM module outputs a low level;
when the value of the counter is larger than or equal to the value of the comparison register, the PWM module outputs a high level;
when the value of the counter is equal to the value of the period register, the counter is cleared.
In another aspect, the present invention provides a continuous sampling method, which uses the continuous sampling system, and the method includes the following steps:
forbidding the PWM module and forcibly pulling up the output of the PWM module;
forbidding data transmission of the SPI module, and reading sampling data received by the SPI module in the cache;
writing the AD conversion command into a transmission FIFO of the SPI module;
disabling interruption of the DSP chip;
clearing a counter of the PWM module and enabling the PWM module;
enabling data transmission of the SPI module;
enabling the DSP chip to interrupt.
Further, the method further includes configuring a PWM module, specifically including:
configuring the value of the period register of the PWM module:
PWM period = (T _ SCLK + T _ DLY) × 2
Configuring the value of the comparison register of the PWM module:
PWM comparison value = T _ SCLK × 2+ T _ DLY + Td + Tm
In the formula: t _ SCLK represents SCLK clock period of SPI module; t _ DLY represents the delay time between the SPI module sending data; td represents the delay time for the start of the PWM cycle compared to the first rising edge of the SCLK clock; tm represents an increase margin.
Further, the method also comprises configuring the SPI module, and the clock speed and the insertion time between data of the SPI module are configured.
Further, the format of the sampling data is as follows:
invalid word, sample data 1, invalid word, sample data 2, … …;
in a corresponding manner, the first and second optical fibers are,
the write format of the AD conversion command is:
command 1, invalid word, command 2, invalid word, … ….
Compared with the prior art, the continuous sampling system and the continuous sampling method thereof provided by the invention have the advantages that the DSP chip is used for driving the AD sampling chip to realize continuous sampling, the CPU occupies less time, and the sampling efficiency is high.
Drawings
Fig. 1 is a block diagram of a continuous sampling system according to an embodiment of the present invention;
FIG. 2 is a timing waveform diagram of an SPI interface of an ADS868x series AD sampling chip;
FIG. 3 is a schematic diagram of the PWM module of the DSP chip according to the embodiment of the present invention;
FIG. 4 is a driving waveform diagram of an SPI module of a DSP chip provided according to an embodiment of the invention;
FIG. 5 is a flow chart of a continuous sampling method provided in accordance with an embodiment of the present invention;
FIG. 6 is a timing waveform diagram of SPI interface of ADS868x series AD sampling chip driven by TI TMS320F37x series DSP;
fig. 7 is a schematic diagram of parameter calculation of the PWM module and the SPI module of the DSP chip according to the embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 1, the continuous sampling system provided by the embodiment of the present invention includes a DSP chip and an AD sampling chip.
The DSP chip adopts TI TMS320F28 2837x series DSP chip (DSP chip for short in the following), and the AD sampling chip adopts ADS868x series AD sampling chip. The ADS868x series AD sampling chip has an SPI interface and multiple sampling channels, and as shown in fig. 2, is an SPI interface timing waveform diagram of the ADS868x series AD sampling chip. The DSP chip can drive ADS868x series AD sampling chips to perform continuous sampling through SPI timing.
The DSP chip comprises a PWM module and an SPI module, the PWM module is connected with a CS pin of the AD sampling chip, and the SPI module is connected with an SCLK pin, an SDO pin and an SDI pin of the AD sampling chip; the DSP chip passes through PWM module output drive AD sampling chip, produces the SPI drive signal who accords with AD sampling chip chronogenesis through the SPI module, realizes AD sampling chip continuous sampling.
The working principle of the PWM module is shown in fig. 3, the PWM module generally has a PWM period register, a counter and a comparison register, after the period register and the comparison register are set by software, the counter is started, the counter counts up by 1 from 0, when the value of the counter is smaller than the value of the comparison register, the PWM module outputs a low level, when the value is greater than or equal to the comparison register, the PWM module outputs a high level, when the value of the counter is equal to the value of the PWM period register, the counter is cleared, and the counter counts up by 1 from 0 again, so that PWM pulses can be periodically generated.
The SPI peripheral of TI TMS320F37x series DSP chip has 16-level FIFO, after writing data into FIFO, CPU can execute other tasks, SPI hardware can automatically send out the data in FIFO, simultaneously receive the data of SPI slave computer, in addition, the SPI peripheral also has a characteristic, namely when sending data, a certain time delay can be inserted between every two words, according to this characteristic, when sending data through the SPI peripheral, if write 3 words into FIFO, the drive waveform of sending data is as shown in figure 4.
The invention combines the characteristics of the PWM module and the SPI module of the DSP chip to generate an SPI driving signal which accords with the time sequence of an ADS868x chip, so as to realize continuous sampling, and finally, when 2 channels are continuously sampled, the driving waveforms of the SPI interfaces CS, SCLK, SDI and SDO of the ADS868x series are shown in the attached figure 6: the CS pin is driven using the PWM output of the DSP chip to obtain PWM waves of a plurality of consecutive PWM periods, the SPI interface is driven using the SPI peripheral of the DSP chip, and the obtained waveforms are shown in fig. 6. By the cooperation of the two peripherals, the driving waveform is obtained in which the CS signal goes low before the SCLK clock appears and goes high after the SPI sends 2 words (32 th SCLK clock falling edge), CS goes low again before the next sampling (33 th SCLK clock rising edge), and goes high after the SPI sends 2 words again (64 th SCLK clock falling edge), and 2 consecutive samplings are completed.
After finishing sampling for 2 times, the FIFO data of the processor SPI peripheral is sent out, SCLK is kept at low level, but at this time, CS still keeps the previous PWM waveform, because as long as there is no SCLK, the AD sampling chip will not perform the sampling operation either, until the next continuous sampling starts, and the above process can be repeated again.
The driving method has the following characteristics:
the driving of the CS is realized by configuring the PWM module, and after the driving is enabled, the CS outputs the waveform all the time without software interference.
The SPI is driven by utilizing the FIFO + insertion delay characteristic of the TMS320F37x series DSP chip SPI peripheral device, so that the continuous transmission of data and the delay between two data are realized, firstly, the continuous transmission of the data ensures that the time of each data to be transmitted is completely the same, and thus, the SCLK waveform can be completely matched with the CS waveform driven by the PWM module in time sequence; and then, the time delay is inserted between the two data, so that the CS can be pulled up for a period of time, the time sequence requirement of continuous sampling of an AD sampling chip is met, and in addition, the time of pulling up and pulling down the CS is not accurate by inserting the time delay, so that the programming is easy to realize.
By utilizing the timing characteristics of the ADS868x chip, after the continuous sampling of a plurality of channels is completed, software does not need to process, the CS signal still keeps the previous output state, no sampling error is caused, and the software only needs to process once when the next continuous sampling is executed.
To explain the principle and characteristics of the above-mentioned driving in more detail, the following gives details of continuous sampling of the DSP chip, the processor may completely encapsulate the driver into a function, and each time sampling is to be performed, the function is called, and the function may be returned after simple processing, but the hardware drives the ADS868x to sample all the time, and when the function is called next, the last sampling result may be directly read and a new conversion may be started, and the software processing steps are as shown in fig. 5.
Step 1: start the continuous sampling process
Step 2: the PWM module is disabled and the PWM output is forced high so that it is forced high regardless of what state CS was previously.
And step 3: disabling transmission of the SPI peripheral equipment, and then reading data buffered by the SPI, wherein the data are sampling data after continuous sampling is finished last time, and the format of the data is as follows: invalid word, sample data 1, invalid word, sample data 2, … ….
And 4, step 4: the PWM module is configured to include values of the PWM period register and the PWM compare register (calculation methods of these two values will be given later).
And 5: and configuring an SPI module, including the clock speed and the data inter-insertion time of the SPI.
Step 6: multiple commands sampled consecutively are written into the transmit FIFO of the SPI, noting that the format of the command writes is: command 1, invalid word, command 2, invalid word, … ….
And 7: disabling DSP chip interrupts
And 8: and resetting the enable PWM counter to enable the PWM module, wherein the value of the PWM counter is 0 and is smaller than the PWM period register, so that the output immediately changes from high to low, namely CS changes from high to low, and the sampling starts.
And step 9: the transmission of the SPI peripheral is enabled, and at this time, the data to be transmitted has been written into the transmission FIFO, and the SPI immediately starts transmitting the data.
Step 10: enabling DSP chip interrupts
Step 11: return to
In the above steps, steps 4 and 5 can be completed in the initialization stage, and are not changed any more later, so that the occupation time of the CPU can be further reduced; step 7 disables DSP interrupts, preventing steps 8 and 9 from being interrupted, so that the waveforms of CS and SCLK may not fit well, not meeting the timing requirements of ADS868x, and DSP interrupts may be re-enabled at step 10.
By using the steps, the CPU only needs a short time to configure the register each time to realize the continuous sampling of a plurality of channels, and because the sampling time sequence is driven by the PWM of the processor and the SPI peripheral hardware, the sampling time is more deterministic, and the dispersion is smaller.
The method for calculating the parameters of the PWM module and the SPI module in the DSP chip comprises the following steps:
the method for driving the AD sampling chips of the ADS868x series needs the PWM module and the SPI module of the DSP chip to be matched with each other, so that the selection of the configuration parameters of the two modules needs to be calculated according to a determined method, the stable operation of a driving program is ensured, and all the parameters are shown in the attached figure 7.
The selection of the clock (SCLK) frequency can comprehensively consider the SPI interface speed and the sampling speed of an ADS868x series AD sampling chip, and a value suitable for application is selected.
The sending delay of each 2 data of the SPI interface of the DSP processor is based on the number of SCLK periods, and when the value is larger, the driving program can be more stable, but the sampling interval of continuous sampling channels can be increased, and the selection can be carried out according to the requirement.
The PWM period depends on the SCLK clock period (T _ SCLK) and the delay time (T _ DLY)
PWM period = (T _ SCLK + T _ DLY) × 2
The PWM comparison value register determines the time for pulling up the CS signal, the pulling-up time is after the falling edge of the 32 th clock cycle, and since there is a certain delay in step 8 and step 9 when starting the conversion, there is a delay (Td) in the beginning of the PWM cycle (CS changes from high to low) compared to the first rising edge of SCLK, the value of the PWM comparison register can be:
PWM comparison value = T _ SCLK × 2+ T _ DLY + Td + Tm
Where Tm is an increased margin, which may make the driver more stable.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A continuous sampling method is characterized in that a continuous sampling system is adopted in the method and comprises a DSP chip and an AD sampling chip; the DSP chip comprises a PWM module and an SPI module, the PWM module is connected with a CS pin of the AD sampling chip, and the SPI module is connected with an SCLK pin, an SDO pin and an SDI pin of the AD sampling chip; the DSP chip drives the AD sampling chip through the output of the PWM module, and generates an SPI driving signal according with the time sequence of the AD sampling chip through the SPI module, so that the continuous sampling of the AD sampling chip is realized;
the method comprises the following steps:
forbidding the PWM module and forcibly pulling up the output of the PWM module;
forbidding data transmission of the SPI module, and reading sampling data received by the SPI module in the cache;
writing the AD conversion command into a transmission FIFO of the SPI module;
disabling interruption of the DSP chip;
clearing a counter of the PWM module and enabling the PWM module;
enabling data transmission of the SPI module;
enabling the DSP chip to interrupt.
2. The continuous sampling method according to claim 1, further comprising configuring a PWM module, in particular comprising:
configuring the value of the period register of the PWM module:
PWM period = (T _ SCLK + T _ DLY) × 2
Configuring the value of the comparison register of the PWM module:
PWM comparison value = T _ SCLK × 2+ T _ DLY + Td + Tm
In the formula: t _ SCLK represents SCLK clock period of SPI module; t _ DLY represents the delay time between the SPI module sending data; td represents the delay time for the start of the PWM cycle compared to the first rising edge of the SCLK clock; tm represents an increase margin.
3. The continuous sampling method of claim 1, further comprising configuring the SPI module, including configuring a clock speed and an insertion time between data of the SPI module.
4. The continuous sampling method of claim 1, wherein the format of the sampled data is:
invalid word, sample data 1, invalid word, sample data 2, … …;
in a corresponding manner, the first and second optical fibers are,
the write format of the AD conversion command is:
command 1, invalid word, command 2, invalid word, … ….
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