CN109698723A - A kind of fully integrated photoreceiver of silica-based high speed for chip chamber light network - Google Patents
A kind of fully integrated photoreceiver of silica-based high speed for chip chamber light network Download PDFInfo
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- CN109698723A CN109698723A CN201811644632.6A CN201811644632A CN109698723A CN 109698723 A CN109698723 A CN 109698723A CN 201811644632 A CN201811644632 A CN 201811644632A CN 109698723 A CN109698723 A CN 109698723A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
Abstract
The invention discloses a kind of fully integrated photoreceivers of the silica-based high speed for chip chamber light network, which is characterized in that including the four fully integrated photoreceivers of road 25Gbps；Every fully integrated photoreceiver of road 25Gbps includes photodetector and photoreceiver, for receiving and processing the optical signal of 25Gbps, the transmission rate of the total 100Gbps of realization；Photodetector carries out photoelectric conversion, output light electric current I for capturing faint light pulse signalPD；Photoreceiver inputs the photoelectric current I to export from photodetector for the ultra-weak electronic signal that balanced amplification is obtained from photodetectorPD, export as differential voltage signal VOUTN,VOUTP.The invention enables the sensory characteristics of photoreceiver to greatly promote；It attached direct current offset and eliminate structure, while promoting sensitivity behaviour, also improve the dynamic range of photoreceiver；The bandwidth that system is improved while keeping high-gain, ensure that the transmission of high speed signal；Biggish output voltage swing is provided, being adapted to for photoreceiver and other signal processing systems is beneficial to.
Description
Technical field
The present invention relates to technical field of optical fiber communication more particularly to a kind of silica-based high speed complete or collected works for chip chamber light network
At photoreceiver.
Background technique
Since the eighties of last century sixties, silicon integrated circuit is developed rapidly according to " Moore's Law ", the integrated level of chip
It doubles within every 18 months, various integrated levels are higher, with better function, the lower IC chip of power consumption greatly improves and convenient
The life style of the mankind.Microelectronics has been widely used for various electronic systems, the development, industry, section to national economy
The progress of skill and national defence plays a crucial role.The development of silicon integrated circuit depends directly on its minimum process size not
Disconnected to reduce, the characteristic size of transistor is reduced to current 16nm even 10nm from 10 μm or more of early stage.Existing physics adds
Chinese musical scale degree has entered nanometer scale, that is, is up to the limit of Physical Processing, it is difficult to be improved by further decreasing line width
Chip integration and performance.
In light network field of communication technology, with currently, optical communication system transmission rate from Mbps grades and Gbps by
Tbps grades are gradually developed to, rate average 1.5 years of core backbone network double, hence it is evident that are faster than the processing speed of I/O.It develops
100Gb/s optical interconnected chips and module are the extremely important research topics in the current communications field one, and China's informationization is built
It is equipped with great strategy and realistic meaning.
Currently, realizing that the light network receiver scheme of 100Gb/s mainly uses the framework of 4 × 25Gb/s of multidiameter delay, collection
Hybrid integrated and single-chip integration are broadly divided at mode.The mode of hybrid integrated is generally divided into Wire bonding and Flip-
Two kinds of chip bonding.It by detector and is received more simple in the method and process that circuit is attached using Wire bonding
It is single, however bring ghost effect often deteriorates the performance of receiver to bonding wire in high frequency；Using Flip-chip
Bonding flip chip bonding is a kind of preferable hybrid package scheme.Mode compared to Wire-bonding, flip chip bonding is without longer
Lead greatly reduces the ghost effect of interconnection line in high frequency, and more compact.Face-down bonding technique is primary disadvantage is that work
Skill is complicated, at high cost, it is desirable that low temperature and low-resistance solder；And the pad on detector still can bring biggish distribution to join
Number.However realize that the technology of hybrid integrated has fallen into development bottleneck under 25Gb/s rate using bonding.Because in height
The problem of insertion loss, seems especially prominent under frequency, can generate serious signal reflex when packaged especially so as to cause impedance
Mismatch.In addition, the electromagnetic interference of external environment can increase photoreceiver influence, it is easier to draw when using hybrid integrated mode
Into the noise of external environment, lead to the sensitivity decrease of optical receiver systems.So nowadays, hybrid package technology is gradually
It can not meet the requirement of high speed information and communication system.And the message transmission rate that forward requirement light network can support will reach
400Gb/s is even more, in order to reduce the complexity of such high rate data transmission system, improves the capacity and density of light network, real
Existing single chip integrated advantage just displays, by the way that opto chip and IC chip are processed on the same substrate:
(1), ghost effect caused by capable of effectively reducing because of pad capacitance, bond-wire inductor, to improve bandwidth；(2), can reduce
Because of the electromagnetic interference that external environment generates, noise is reduced, the sensitivity of optical receiver systems is improved；(3), mixed compared to multi-chip
Intersection at packaged type, single-chip integration can substantially reduce packaging cost, be conducive to be mass produced.
In view of the potential advantages and application of light network technology, 100Gb/s and the above optical interconnected chips and module are super at present
One hot spot of high speed optical communication integrated circuit fields and the research topic in forward position.However standard CMOS process and silicon optoelectronic
The manufacture craft of device still has some subtle compatibility issues, and current most CMOS technology manufacturer cannot achieve two
The single-chip integration of person.SiGe is the important semiconductor material of one kind after Si and GaAs, with traditional Si based transistor phase
Than device and circuit based on SiGe heterojunction transistor technology have better frequency and noise characteristic, present good
Microwave high-frequency section operating potential；And compared with GaAs, InP technical products, SiGe heterojunction transistor technical products have into again
The advantages that this is low, thermal conductivity is good, especially can be mutually compatible with mature CMOS technology, and production chains are stronger.SiGe BiCMOS
Technology is embedded in SiGe HBT technique in CMOS (complementary metal oxide semiconductor) technique, and existing CMOS technology low-power consumption is high
Integrated feature, and the high current driving capability of bipolar transistor can be utilized；Surmount CMOS work in frequency and speed simultaneously
Skill；In addition in photodetector structure design, it can be designed that vertical PIN photoelectric detector using SiGe HBT structure and hang down
Straight heterogeneous section phototransistor (HPT) is easy the high performance photodetector of design, and the doping of Ge ingredient also can be in certain journey
The performance of detector is promoted on degree.By 2015, SiGe BiCMOS technique integrated application aspect in photoelectricity and achieves huge dash forward
It is broken.0.25 μm of SiGe BiCMOS technique has following three big features: (1), the Ge type PIN photodetection of the waveguide that integrates coupling
Device under -2V bias-three dB bandwidth can be greater than 70GHz, wavelength be 1.55 μm when Photoresponse be greater than 1A/W, dark current
Less than 400nA；(2), the characteristic frequency ft of heterojunction bipolar transistor SiGe HBT can reach 240GHz, maximum frequency fmax energy
To 290GHz；(3), due to the SiGe BiCMOS technique can CMOS technique compatible, electro-optical passive device, Electro-optical Modulation
Device and cmos circuit can be together with single-chip integrations.Traditional silicon light (Silicon-on-Insulator SOI) technique and high-performance
Requirement fundamental difference of SiGe BiCMOS (Bulk-Silicon) technique to substrate, but pass through part SOI (Local-SOI) skill
Art can effectively alleviate the problem.SiGe BiCMOS technique is prepared on germanium (Ge) layer, lateral PIN photoelectric detector choosing
It is grown in selecting property in silicon waveguide and SiGe HBT shares same substrate, to realize photodetector and receiver front end electricity
The single-chip integration on road.
Summary of the invention
The technical problem to be solved in the present invention is that for the defects in the prior art, providing a kind of mutual for chip chamber light
The fully integrated photoreceiver of silica-based high speed even.
The technical solution adopted by the present invention to solve the technical problems is:
The present invention provides a kind of fully integrated photoreceiver of the silica-based high speed for chip chamber light network, including four road 25Gbps
Fully integrated photoreceiver；Every fully integrated photoreceiver of road 25Gbps includes photodetector and photoreceiver, for receiving
And the optical signal of 25Gbps is handled, realize the transmission rate of total 100Gbps；Wherein:
Photodetector, including grating interconnected, waveguide, photodiode；Photodetector is faint for capturing
Light pulse signal carries out photoelectric conversion, output light electric current IPD；
Photoreceiver, including trans-impedance amplifier, Dummy circuit, limiting amplifier, output buffer stage, direct current offset are eliminated
Circuit；Limiting amplifier uses modified Cherry-Hooper structure, introduces conjugate pole, improves circuit bandwidth；Direct current offset
Eliminating circuit includes low-pass filter and high gain operational amplifier, eliminates the offset of DC level；Photoreceiver is for equilibrium
Amplify the ultra-weak electronic signal obtained from photodetector, inputs the photoelectric current I to export from photodetectorPD, export as difference
Voltage signal VOUTN,VOUTP。
Further, in photodetector of the invention, the optical signal of optical fiber transmission after being captured by grating, passes through
Waveguide transmission is to photoelectric diode；Photodetector in optical waveguide after certain distance transmits decaying and distortion it is micro-
Weak light pulses signal carries out photoelectric conversion.
Further, in photoreceiver of the invention:
Trans-impedance amplifier is used to handle the photoelectric current I of photodetector outputPD, it is converted into voltage signal and is put
Greatly；
Dummy circuit is for providing a DC level identical with trans-impedance amplifier, real to provide the input of pseudo-differential
Existing conversion of the single-ended signal to differential signal；
Limiting amplifier is used to handle the voltage signal of trans-impedance amplifier transmission, is amplified to for digital circuit
The level of processing；
Output buffer stage effect is to allow the Circuit Matching of silica-based high speed fully integrated photoreceiver and rear class；
The effect of DC drift eliminator is the direct current offset of input terminal, make circuit input current in a certain range
It can all be worked normally when variation, to improve the dynamic range of circuit.
Further, trans-impedance amplifier of the invention input is photo-signal IPDWith offset cancellation voltage signal Voffset,
Output is voltage signal VOUTN1；Trans-impedance amplifier is responsible for converting voltage signal for the current signal of input, and amplifies；Its
In:
Trans-impedance amplifier circuit includes transistor Q1, transistor Q2, transistor M11And resistance R1, resistance RF, resistance R2；
Offset cancellation voltage signal VoffsetIt is connected to transistor M11Grid, transistor M11Drain electrode and photo-signal IPDIt is connected to crystal together
Pipe Q1Base stage, source electrode ground connection；Transistor Q1Collector meets transistor Q2Base stage while connecting resistance R1To voltage VCC, emitter
Ground connection；Transistor Q2Collector meets voltage VCC, base stage is simultaneously voltage signal VOUTN1Output end, emitter connecting resistance R2It arrives
Ground meets feedback resistance R simultaneouslyFTo transistor Q1Base stage.
Further, Dummy circuit of the invention input is offset cancellation voltage signal Voffset, export as voltage signal
VOUTP1, Dummy circuit is for exporting DC reference voltage；Wherein:
Dummy circuit includes transistor Q3, transistor Q4, transistor M12And resistance R3, resistance RF2, resistance R4；Offset disappears
Except voltage signal VoffsetIt is connected to transistor M12Grid, transistor M12Drain electrode meets transistor Q3Base stage, source electrode ground connection；Transistor
Q3Collector meets transistor Q4Base stage while connecting resistance R3To voltage VCC, emitter ground connection；Transistor Q4Collector connects voltage
VCC, base stage is simultaneously voltage signal VOUTP1Output end, emitter connecting resistance R4Feedback resistance R is met simultaneously to groundF2To crystal
Pipe Q3Base stage.
Further, limiting amplifier of the invention includes two-stage, in which:
First order limiting amplifier includes transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor
Q10, transistor Q11, transistor Q12, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance RF3, resistance RF4；
Transistor Q5Base stage accesses input voltage VOUTN1, collector and resistance RF3With transistor Q7Base stage be connected, emitter and brilliant
Body pipe Q12Collector, Q6Emitter be connected；Transistor Q11, transistor Q12Electric current, transmitting are provided to circuit as tail current
Pole respectively with resistance R9, resistance R10Be connected, collector respectively with transistor Q7, transistor Q8, transistor Q5, transistor Q6It is connected
It connects；Transistor Q7, transistor Q8Collector respectively with resistance R7, resistance R8It is connected；Resistance R7, resistance R8The other end and crystal
Pipe Q9, transistor Q10, transistor R5, transistor R6It is connected；Voltage VDDIt is input to resistance R5, resistance R6, transistor Q9Current collection
Pole, transistor Q10Collector；Transistor Q9, transistor Q10Emitter and feedback resistance RF3, resistance RF4Line connection；Output
VOUTP2By transistor Q9Base stage draw, export VOUTN2By transistor Q10Base stage draw.
Further, second level limiting amplifier of the invention is double-width grinding both-end export structure, and input is respectively the
The forward voltage signal V of level-one limiting amplifier output endOUTP2With reverse voltage signal VOUTN2, output is respectively forward voltage
Signal VOUTP3With reverse voltage signal VOUTN3；Second level limiting amplifier is used for limited range enlargement input voltage signal, makes output electricity
It presses signal between suitable dynamic range, and expands the bandwidth of photoreceiver；Second level clipping amplifier circuit includes crystal
Pipe transistor Q13, transistor Q14, transistor Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20
And resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance RF5, resistance RF6；Its structure and the first order
Limiting amplifier is consistent.
Further, output buffer stage of the invention is double-width grinding both-end export structure, and input is respectively second level limit
The forward voltage signal V of width amplifier outOUTP3With reverse voltage signal VOUTN3, output is respectively forward voltage signal VOUTP
With reverse voltage signal VOUTN；Output buffer stage is responsible for adjusting output voltage signal, and output voltage signal is made to reach suitable defeated
The amplitude of oscillation out, and the output resistance of 50 Ω is provided to carry out impedance matching with back-end circuit；Wherein:
Output buffer circuit includes transistor Q21, transistor Q22, transistor Q23, transistor Q24And resistance R17, electricity
Hinder R18, resistance R19；Input forward voltage signal VOUTP3It is connected to transistor Q22Base stage, transistor Q22Collector connecting resistance R18To electricity
Press VDD, collector is simultaneously voltage signal VOUTNOutput end, input reverse voltage signal VOUTN3It is connected to transistor Q21Base
Pole, transistor Q21Collector connecting resistance R17To voltage VDD, collector is simultaneously voltage signal VOUTPOutput end, resistance R19
Both ends meet transistor Q respectively21With transistor Q22Emitter, bias voltage VB1It is respectively connected to transistor Q23With transistor Q24Base
Pole, transistor Q23With transistor Q24Collector meets transistor Q respectively21With transistor Q22Emitter, emitter are all grounded.
Further, DC drift eliminator of the invention input is respectively the forward voltage of second level limiting amplifier
Signal VOUTP3With reverse voltage signal VOUTN3, export as offset cancellation voltage signal Voffset；DC drift eliminator is responsible for
Eliminate the direct current offset that circuit generates；Wherein:
DC drift eliminator includes transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor
M6, transistor M7, transistor M8, transistor M9, transistor M10And resistance R20, resistance R21, resistance R22, resistance R23And capacitor
C1, capacitor C2, capacitor C3；Input voltage signal VOUTN3With VOUTP3Respectively by by resistance R20Capacitor C1With resistance R21Capacitor C2Group
At low-pass filter be input to transistor M3With transistor M4Grid, transistor M1, transistor M2, transistor M3, transistor M4、
Transistor M5, transistor M6With resistance R22Form amplifier, transistor M3With transistor M4Grid is two input terminals of amplifier, brilliant
Body pipe M3With transistor M4Drain electrode is two output ends of amplifier, is respectively connected to transistor M9With transistor M10Grid, transistor
M7, transistor M8, transistor M9, transistor M10Form current mirror network, transistor M9With transistor M10Grid is current mirror network
Two input terminals, resistance R23One termination transistor M10With transistor M8Drain electrode, another termination capacitor C3To ground, meanwhile, the end
For offset cancellation voltage signal VoffsetOutput end.
The beneficial effect comprise that: the fully integrated light-receiving of silica-based high speed for chip chamber light network of the invention
Machine is realized the transmission rate of the total 100Gbps of 4 × 25Gbps using single chip integrated mode, is conducive to high-speed communication system
It develops；Source and the mechanism of device error are assessed and had detected at the nanoscale, provides more precise and high efficiency to emulate
Model；Sufficiently 9 Cr 2 steel using electromagnetic heating coupling effect of the research between period adjacent under high-speed high frequency working environment and between silicon substrate；
Using the structure of pseudo-differential, noise is reduced, so that the sensory characteristic of photoreceiver greatly promotes；It attached direct current offset
Structure is eliminated, while promoting sensitivity behaviour, also improves the dynamic range of photoreceiver；Using capacitor degeneracy technology,
The bandwidth that system is improved while keeping high-gain, ensure that the transmission of high speed signal；Biggish output voltage swing is provided,
It is beneficial to being adapted to for photoreceiver and other signal processing systems.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples, in attached drawing:
Fig. 1 is silica-based high speed (4 × 25Gbps) fully integrated photoreceiver that the embodiment of the present invention is used for chip chamber light network
Functional block diagram；
Fig. 2 (a) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 2 (b) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 2 (c) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 2 (d) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 2 (e) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 2 (f) is silica-based high speed (4 × 25Gbps) fully integrated light-receiving that the embodiment of the present invention is used for chip chamber light network
The circuit diagram of machine；
Fig. 3 is the single channel gain-bandwidth simulation curve of the embodiment of the present invention；
Fig. 4 is single channel output eye figure of the embodiment of the present invention when inputting 25Gbps pseudo-random signal.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
Following disclosure provides many different embodiments or example is used to realize different structure of the invention.For letter
Change disclosure of the invention, hereinafter the component of specific examples and setting are described.They are merely examples, and purpose is not
It is to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or letter.This repetition be for
Simplified and clear purpose, itself do not indicate discussed various embodiments and/or be arranged between relationship.In addition, this hair
It is bright provide the example of various specific techniques and material, but those of ordinary skill in the art may be aware that other techniques
The use of applicability and/or other materials.In addition, structure of the fisrt feature described below in the "upper" of second feature can be with
Be formed as the embodiment directly contacted including the first and second features, also may include that other feature is formed in first and second
Embodiment between feature, such first and second feature may not be direct contact.
In description of the invention, it should be noted that unless otherwise specified and limited, term " connected " " connection " should be done extensively
Reason and good sense solution, for example, it may be mechanical connection or electrical connection, the connection being also possible to inside two elements can be directly connected,
It can also manage as the case may be indirectly connected through an intermediary, for those of ordinary skill in the related art
Solve the concrete meaning of above-mentioned term.
The fully integrated photoreceiver of silica-based high speed for chip chamber light network of the embodiment of the present invention, including four road 25Gbps
Fully integrated photoreceiver；Every fully integrated photoreceiver of road 25Gbps includes photodetector and photoreceiver, for receiving
And the optical signal of 25Gbps is handled, realize the transmission rate of total 100Gbps；Wherein:
Photodetector, including grating interconnected, waveguide, photodiode；Photodetector is faint for capturing
Light pulse signal carries out photoelectric conversion, output light electric current IPD；
Photoreceiver, including trans-impedance amplifier, Dummy circuit, limiting amplifier, output buffer stage, direct current offset are eliminated
Circuit；Limiting amplifier uses modified Cherry-Hooper structure, introduces conjugate pole, improves circuit bandwidth；Direct current offset
Eliminating circuit includes low-pass filter and high gain operational amplifier, eliminates the offset of DC level；Photoreceiver is for equilibrium
Amplify the ultra-weak electronic signal obtained from photodetector, inputs the photoelectric current I to export from photodetectorPD, export as difference
Voltage signal VOUTN,VOUTP。
In photodetector, the optical signal of optical fiber transmission, after being captured by grating, by waveguide transmission to photo-diode
Pipe；Photodetector carries out light to the faint light pulse signal of decaying and distortion in optical waveguide after certain distance transmits
Electricity conversion.
In photoreceiver:
Trans-impedance amplifier is used to handle the photoelectric current I of photodetector outputPD, it is converted into voltage signal and is put
Greatly；
Dummy circuit is for providing a DC level identical with trans-impedance amplifier, real to provide the input of pseudo-differential
Existing conversion of the single-ended signal to differential signal；
Limiting amplifier is used to handle the voltage signal of trans-impedance amplifier transmission, is amplified to for digital circuit
The level of processing；
Output buffer stage effect is to allow the Circuit Matching of silica-based high speed fully integrated photoreceiver and rear class；
The effect of DC drift eliminator is the direct current offset of input terminal, make circuit input current in a certain range
It can all be worked normally when variation, to improve the dynamic range of circuit.
Trans-impedance amplifier input is photo-signal IPDWith offset cancellation voltage signal Voffset, export as voltage signal
VOUTN1；Trans-impedance amplifier is responsible for converting voltage signal for the current signal of input, and amplifies；Wherein:
Trans-impedance amplifier circuit includes transistor Q1, transistor Q2, transistor M11And resistance R1, resistance RF, resistance R2；
Offset cancellation voltage signal VoffsetIt is connected to transistor M11Grid, transistor M11Drain electrode and photo-signal IPDIt is connected to crystal together
Pipe Q1Base stage, source electrode ground connection；Transistor Q1Collector meets transistor Q2Base stage while connecting resistance R1To voltage VCC, emitter
Ground connection；Transistor Q2Collector meets voltage VCC, base stage is simultaneously voltage signal VOUTN1Output end, emitter connecting resistance R2It arrives
Ground meets feedback resistance R simultaneouslyFTo transistor Q1Base stage.
The input of Dummy circuit is offset cancellation voltage signal Voffset, export as voltage signal VOUTP1, Dummy circuit is used for
Export DC reference voltage；Wherein:
Dummy circuit includes transistor Q3, transistor Q4, transistor M12And resistance R3, resistance RF2, resistance R4；Offset disappears
Except voltage signal VoffsetIt is connected to transistor M12Grid, transistor M12Drain electrode meets transistor Q3Base stage, source electrode ground connection；Transistor
Q3Collector meets transistor Q4Base stage while connecting resistance R3To voltage VCC, emitter ground connection；Transistor Q4Collector connects voltage
VCC, base stage is simultaneously voltage signal VOUTP1Output end, emitter connecting resistance R4Feedback resistance R is met simultaneously to groundF2To crystal
Pipe Q3Base stage.
Limiting amplifier includes two-stage, in which:
First order limiting amplifier includes transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor
Q10, transistor Q11, transistor Q12, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance RF3, resistance RF4；
Transistor Q5Base stage accesses input voltage VOUTN1, collector and resistance RF3With transistor Q7Base stage be connected, emitter and brilliant
Body pipe Q12Collector, Q6Emitter be connected；Transistor Q11, transistor Q12Electric current, transmitting are provided to circuit as tail current
Pole respectively with resistance R9, resistance R10Be connected, collector respectively with transistor Q7, transistor Q8, transistor Q5, transistor Q6It is connected
It connects；Transistor Q7, transistor Q8Collector respectively with resistance R7, resistance R8It is connected；Resistance R7, resistance R8The other end and crystal
Pipe Q9, transistor Q10, transistor R5, transistor R6It is connected；Voltage VDDIt is input to resistance R5, resistance R6, transistor Q9Current collection
Pole, transistor Q10Collector；Transistor Q9, transistor Q10Emitter and feedback resistance RF3, resistance RF4Line connection；Output
VOUTP2By transistor Q9Base stage draw, export VOUTN2By transistor Q10Base stage draw.
Second level limiting amplifier is double-width grinding both-end export structure, and input is respectively the output of first order limiting amplifier
The forward voltage signal V at endOUTP2With reverse voltage signal VOUTN2, output is respectively forward voltage signal VOUTP3With backward voltage
Signal VOUTN3；Second level limiting amplifier is used for limited range enlargement input voltage signal, makes output voltage signal in suitable dynamic
Between range, and expand the bandwidth of photoreceiver；Second level clipping amplifier circuit includes transistor Q13, transistor
Q14, transistor Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20And resistance R11, resistance R12、
Resistance R13, resistance R14, resistance R15, resistance R16, resistance RF5, resistance RF6；Its structure is consistent with first order limiting amplifier.
Output buffer stage is double-width grinding both-end export structure, and input respectively second level limiting amplifier output end is just
To voltage signal VOUTP3With reverse voltage signal VOUTN3, output is respectively forward voltage signal VOUTPWith reverse voltage signal
VOUTN；Output buffer stage is responsible for adjusting output voltage signal, so that output voltage signal is reached suitable output voltage swing, and provide 50
The output resistance of Ω is to carry out impedance matching with back-end circuit；Wherein:
Output buffer circuit includes transistor Q21, transistor Q22, transistor Q23, transistor Q24And resistance R17, electricity
Hinder R18, resistance R19；Input forward voltage signal VOUTP3It is connected to transistor Q22Base stage, transistor Q22Collector connecting resistance R18To electricity
Press VDD, collector is simultaneously voltage signal VOUTNOutput end, input reverse voltage signal VOUTN3It is connected to transistor Q21Base
Pole, transistor Q21Collector connecting resistance R17To voltage VDD, collector is simultaneously voltage signal VOUTPOutput end, resistance R19
Both ends meet transistor Q respectively21With transistor Q22Emitter, bias voltage VB1It is respectively connected to transistor Q23With transistor Q24Base
Pole, transistor Q23With transistor Q24Collector meets transistor Q respectively21With transistor Q22Emitter, emitter are all grounded.
DC drift eliminator input is respectively the forward voltage signal V of second level limiting amplifierOUTP3With reversed electricity
Press signal VOUTN3, export as offset cancellation voltage signal Voffset；DC drift eliminator is responsible for eliminating the direct current that circuit generates
Offset；Wherein:
DC drift eliminator includes transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor
M6, transistor M7, transistor M8, transistor M9, transistor M10And resistance R20, resistance R21, resistance R22, resistance R23And capacitor
C1, capacitor C2, capacitor C3；Input voltage signal VOUTN3With VOUTP3Respectively by by resistance R20Capacitor C1With resistance R21Capacitor C2Group
At low-pass filter be input to transistor M3With transistor M4Grid, transistor M1, transistor M2, transistor M3, transistor M4、
Transistor M5, transistor M6With resistance R22Form amplifier, transistor M3With transistor M4Grid is two input terminals of amplifier, brilliant
Body pipe M3With transistor M4Drain electrode is two output ends of amplifier, is respectively connected to transistor M9With transistor M10Grid, transistor
M7, transistor M8, transistor M9, transistor M10Form current mirror network, transistor M9With transistor M10Grid is current mirror network
Two input terminals, resistance R23One termination transistor M10With transistor M8Drain electrode, another termination capacitor C3To ground, meanwhile, the end
For offset cancellation voltage signal VoffsetOutput end.
The working principle of the present embodiment is as follows: the optical signal transmitted from optical fiber is captured by the grating of photodetector,
Then by waveguide transmission to photodiode.It, can be by wave when photodiode is biased in normal working condition
The optical signal for leading transmission is converted into electric signal, is exported later to high-speed light receiver.High-speed light receiver receives transmission
And after the photoelectric current come, voltage signal is converted by trans-impedance amplifier first, and amplify with certain multiple.By
Amplified voltage signal, the signal that the output with Dummy forms one group of pseudo-differential together are input to first order limiting amplifier；
Limiting amplifier converts the signal of pseudo-differential to after differential signal and is transmitted to second level limiting amplifier；Second level limited range enlargement
Output to output buffer stage exports after differential signal is carried out certain amplification by device.In order to guarantee that limiting amplifier work exists
Correct working condition is eliminated using direct current offset of the DC drift eliminator to trans-impedance amplifier and Dummy.
The first order of the photodetector as the fully integrated photoreceiver of high speed, performance suffer from weight for whole performance
It influences.In general, a good photodetector needs higher responsiveness, preferable sensitivity and biggish dynamic model
It encloses.The main function of trans-impedance amplifier is to convert current signal to more tractable voltage signal, carries out the conversion of dimension.Separately
On the one hand, trans-impedance amplifier will carry out certain amplification, to be easier to rear class while guaranteeing to close enough bandwidth to signal
The processing of circuit.Dummy circuit provides an artifact sub-signal together with trans-impedance amplifier circuit, can reduce the factors such as power supply
The common-mode noise of generation efficiently reduces the equivalent input noise current of input terminal, and the sensitivity for improving photoreceiver is special
Property, while the influence generated due to lead coupling is reduced, to improve the stability of circuit.Two-stage limiting amplifier is equal
Using follow-on Chery-Hooper limiting amplifier, using emitter follower as feedback network.The increasing of limiting amplifier
Beneficial curve has a gain spike in high frequency treatment, to compensate the bandwidth loss as caused by multi-stage cascade.Direct current offset is eliminated
Circuit is DC level signal due to processing, so having a low-pass filter to prevent to light in input and output port
The performance of receiver has an impact.For the signal of input, DC drift eliminator is formed using high gain operational amplifier
Feedback network reduces the gain of low frequency signal, feeds back to the input terminal of photoreceiver, thus cancellation of DC offset.Output buffering
The effect of circuit is matched with 50 Ω of rear class.
If Fig. 3 shows, the gain of the present embodiment photoreceiver, bandwidth simulation curve.The low-frequency gain of photoreceiver is
67.23dB, bandwidth 26.88GHz.
As shown in figure 4, the present embodiment photoreceiver exports eye diagram results when inputting 25Gbps pseudo-random signal.Light-receiving
The amplitude of oscillation of machine is up to 800mV.Eye figure eyes opening width is big, and eyelid is relatively thin, and global shape is preferable.
It should be understood that for those of ordinary skills, it can be modified or changed according to the above description,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (9)
1. a kind of fully integrated photoreceiver of silica-based high speed for chip chamber light network, which is characterized in that including four road 25Gbps
Fully integrated photoreceiver；Every fully integrated photoreceiver of road 25Gbps includes photodetector and photoreceiver, for receiving
And the optical signal of 25Gbps is handled, realize the transmission rate of total 100Gbps；Wherein:
Photodetector, including grating interconnected, waveguide, photodiode；Photodetector is for capturing faint light arteries and veins
It rushes signal and carries out photoelectric conversion, output light electric current IPD；
Photoreceiver, including trans-impedance amplifier, Dummy circuit, limiting amplifier, output buffer stage, DC drift eliminator；
Limiting amplifier uses modified Cherry-Hooper structure, introduces conjugate pole, improves circuit bandwidth；Direct current offset is eliminated
Circuit includes low-pass filter and high gain operational amplifier, eliminates the offset of DC level；Photoreceiver is for balanced amplification
The ultra-weak electronic signal obtained from photodetector inputs the photoelectric current I to export from photodetectorPD, export as differential voltage
Signal VOUTN,VOUTP。
2. the silica-based high speed fully integrated photoreceiver according to claim 1 for chip chamber light network, which is characterized in that
In photodetector, the optical signal of optical fiber transmission, after being captured by grating, by waveguide transmission to photoelectric diode；Photoelectricity
Detector carries out photoelectric conversion to the faint light pulse signal of decaying and distortion in optical waveguide after certain distance transmits.
3. the silica-based high speed fully integrated photoreceiver according to claim 1 for chip chamber light network, which is characterized in that
In photoreceiver:
Trans-impedance amplifier is used to handle the photoelectric current I of photodetector outputPD, it is converted into voltage signal and amplifies；
Dummy circuit is for providing a DC level identical with trans-impedance amplifier, to provide the input of pseudo-differential, realizes single
Conversion of the end signal to differential signal；
Limiting amplifier is used to handle the voltage signal of trans-impedance amplifier transmission, is amplified to for digital circuit processing
Level；
Output buffer stage effect is to allow the Circuit Matching of silica-based high speed fully integrated photoreceiver and rear class；
The effect of DC drift eliminator is the direct current offset of input terminal, changes circuit in a certain range in input current
Shi Jieke is worked normally, to improve the dynamic range of circuit.
4. the silica-based high speed fully integrated photoreceiver according to claim 3 for chip chamber light network, which is characterized in that
Trans-impedance amplifier input is photo-signal IPDWith offset cancellation voltage signal Voffset, export as voltage signal VOUTN1；Across resistance
Amplifier is responsible for converting voltage signal for the current signal of input, and amplifies；Wherein:
Trans-impedance amplifier circuit includes transistor Q1, transistor Q2, transistor M11And resistance R1, resistance RF, resistance R2；Offset disappears
Except voltage signal VoffsetIt is connected to transistor M11Grid, transistor M11Drain electrode and photo-signal IPDIt is connected to transistor Q together1Base
Pole, source electrode ground connection；Transistor Q1Collector meets transistor Q2Base stage while connecting resistance R1To voltage VCC, emitter ground connection；It is brilliant
Body pipe Q2Collector meets voltage VCC, base stage is simultaneously voltage signal VOUTN1Output end, emitter connecting resistance R2Simultaneously to ground
Meet feedback resistance RFTo transistor Q1Base stage.
5. the silica-based high speed fully integrated photoreceiver according to claim 3 for chip chamber light network, which is characterized in that
The input of Dummy circuit is offset cancellation voltage signal Voffset, export as voltage signal VOUTP1, Dummy circuit is for exporting direct current
Reference voltage；Wherein:
Dummy circuit includes transistor Q3, transistor Q4, transistor M12And resistance R3, resistance RF2, resistance R4；Electricity is eliminated in offset
Press signal VoffsetIt is connected to transistor M12Grid, transistor M12Drain electrode meets transistor Q3Base stage, source electrode ground connection；Transistor Q3Collection
Electrode meets transistor Q4Base stage while connecting resistance R3To voltage VCC, emitter ground connection；Transistor Q4Collector meets voltage VCC,
Base stage is simultaneously voltage signal VOUTP1Output end, emitter connecting resistance R4Feedback resistance R is met simultaneously to groundF2To transistor Q3Base
Pole.
6. the silica-based high speed fully integrated photoreceiver according to claim 3 for chip chamber light network, which is characterized in that
Limiting amplifier includes two-stage, in which:
First order limiting amplifier includes transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor Q10、
Transistor Q11, transistor Q12, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance RF3, resistance RF4；It is brilliant
Body pipe Q5Base stage accesses input voltage VOUTN1, collector and resistance RF3With transistor Q7Base stage be connected, emitter and crystal
Pipe Q12Collector, Q6Emitter be connected；Transistor Q11, transistor Q12Electric current, emitter are provided to circuit as tail current
Respectively with resistance R9, resistance R10Be connected, collector respectively with transistor Q7, transistor Q8, transistor Q5, transistor Q6It is connected；
Transistor Q7, transistor Q8Collector respectively with resistance R7, resistance R8It is connected；Resistance R7, resistance R8The other end and transistor
Q9, transistor Q10, transistor R5, transistor R6It is connected；Voltage VDDIt is input to resistance R5, resistance R6, transistor Q9Current collection
Pole, transistor Q10Collector；Transistor Q9, transistor Q10Emitter and feedback resistance RF3, resistance RF4Line connection；Output
VOUTP2By transistor Q9Base stage draw, export VOUTN2By transistor Q10Base stage draw.
7. the silica-based high speed fully integrated photoreceiver according to claim 6 for chip chamber light network, which is characterized in that
Second level limiting amplifier is double-width grinding both-end export structure, and input is respectively the forward direction of first order limiting amplifier output end
Voltage signal VOUTP2With reverse voltage signal VOUTN2, output is respectively forward voltage signal VOUTP3With reverse voltage signal VOUTN3；
Second level limiting amplifier is used for limited range enlargement input voltage signal, makes output voltage signal between suitable dynamic range,
And expand the bandwidth of photoreceiver；Second level clipping amplifier circuit includes transistor Q13, transistor Q14, transistor
Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20And resistance R11, resistance R12, resistance R13, electricity
Hinder R14, resistance R15, resistance R16, resistance RF5, resistance RF6；Its structure is consistent with first order limiting amplifier.
8. the silica-based high speed fully integrated photoreceiver according to claim 7 for chip chamber light network, which is characterized in that
Output buffer stage is double-width grinding both-end export structure, and input is respectively the forward voltage letter of second level limiting amplifier output end
Number VOUTP3With reverse voltage signal VOUTN3, output is respectively forward voltage signal VOUTPWith reverse voltage signal VOUTN；Output is slow
It rushes grade to be responsible for adjusting output voltage signal, output voltage signal is made to reach suitable output voltage swing, and the output electricity of 50 Ω is provided
Resistance is to carry out impedance matching with back-end circuit；Wherein:
Output buffer circuit includes transistor Q21, transistor Q22, transistor Q23, transistor Q24And resistance R17, resistance R18、
Resistance R19；Input forward voltage signal VOUTP3It is connected to transistor Q22Base stage, transistor Q22Collector connecting resistance R18To voltage VDD,
Its collector is simultaneously voltage signal VOUTNOutput end, input reverse voltage signal VOUTN3It is connected to transistor Q21Base stage, crystal
Pipe Q21Collector connecting resistance R17To voltage VDD, collector is simultaneously voltage signal VOUTPOutput end, resistance R19Both ends difference
Meet transistor Q21With transistor Q22Emitter, bias voltage VB1It is respectively connected to transistor Q23With transistor Q24Base stage, transistor
Q23With transistor Q24Collector meets transistor Q respectively21With transistor Q22Emitter, emitter are all grounded.
9. the silica-based high speed fully integrated photoreceiver according to claim 7 for chip chamber light network, which is characterized in that
DC drift eliminator input is respectively the forward voltage signal V of second level limiting amplifierOUTP3With reverse voltage signal
VOUTN3, export as offset cancellation voltage signal Voffset；DC drift eliminator is responsible for eliminating the direct current offset that circuit generates；
Wherein:
DC drift eliminator includes transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6、
Transistor M7, transistor M8, transistor M9, transistor M10And resistance R20, resistance R21, resistance R22, resistance R23And capacitor C1、
Capacitor C2, capacitor C3；Input voltage signal VOUTN3With VOUTP3Respectively by by resistance R20Capacitor C1With resistance R21Capacitor C2Composition
Low-pass filter be input to transistor M3With transistor M4Grid, transistor M1, transistor M2, transistor M3, transistor M4, it is brilliant
Body pipe M5, transistor M6With resistance R22Form amplifier, transistor M3With transistor M4Grid is two input terminals of amplifier, crystal
Pipe M3With transistor M4Drain electrode is two output ends of amplifier, is respectively connected to transistor M9With transistor M10Grid, transistor
M7, transistor M8, transistor M9, transistor M10Form current mirror network, transistor M9With transistor M10Grid is current mirror network
Two input terminals, resistance R23One termination transistor M10With transistor M8Drain electrode, another termination capacitor C3To ground, meanwhile, the end
For offset cancellation voltage signal VoffsetOutput end.
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