CN207200709U - Digital light receiver - Google Patents
Digital light receiver Download PDFInfo
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- CN207200709U CN207200709U CN201721005336.2U CN201721005336U CN207200709U CN 207200709 U CN207200709 U CN 207200709U CN 201721005336 U CN201721005336 U CN 201721005336U CN 207200709 U CN207200709 U CN 207200709U
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- output end
- input
- decoder
- balanced device
- preamplifier
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Abstract
A kind of digital light receiver is the utility model is related to, including：Photodetector, preamplifier, main amplifier, balanced device, agc circuit, decision device, decoder, input, output end, clock recovery circuitry, wherein：The photodetector, the preamplifier, the balanced device, the decision device, the decoder are sequentially connected in series in the input and the output end；The agc circuit is serially connected between the output end of the balanced device and the input of the main amplifier and forms feedback control loop；The input of the clock recovery circuitry electrically connects with the output end of the balanced device, and its output end electrically connects with the input of the decision device and the input of the decoder respectively；The output end of the decoder electrically connects with the output end.The utility model embodiment has the beneficial effect that this digital light receiver photoelectric transformation efficiency height, and cost is low, performance is good.
Description
Technical field
The utility model belongs to optoelectronic information technology technical field, and in particular to a kind of digital light receiver.
Background technology
Light receiver, be in fiber optic communication systems, with minimum additional noise and distortion, recover optical fiber transmission after by
Information entrained by light carrier, therefore the output characteristics concentrated expression of the photoreceiver performance of whole optical fiber telecommunications system.Light
Receiver is made up of photoelectric detector and image intensifer.Its function is the optical signal for coming optical fiber or optical cable transmission, is detected through light
Device is changed into electric signal, then, then this amplified circuit of faint electric signal is amplified into enough level, is sent to receiving terminal
Electric end.
Photodetector is the core devices of light receiver,.The photodetector commonly used in optical communication system is PIN light
Electric diode and avalanche diode (APD).The performance comparision of two kinds of detectors：Because the PIN of same performance is compared with APD, PIN
Price it is cheap, and PIN noise is low.Therefore it is most important to develop high performance photodetector.
Utility model content
In order to solve the above-mentioned problems in the prior art, the utility model provides a kind of digital light receiver, bag
Include：Photodetector, preamplifier, main amplifier, balanced device, automatic growth control (Automatic Generation
Control, abbreviation AGC) circuit, decision device, decoder, input, output end, clock recovery circuitry, wherein：The photoelectricity is visited
Device, the preamplifier, the balanced device, the decision device, the decoder is surveyed to be sequentially connected in series in the input and institute
State output end；The agc circuit is serially connected between the output end of the balanced device and the input of the main amplifier and formed instead
Present loop；The input of the clock recovery circuitry electrically connects with the output end of the balanced device, its output end respectively with it is described
The input of the input of decision device and the decoder electrically connects；The output end of the decoder is electrically connected with the output end
Connect.
In one embodiment of the present utility model, the agc circuit includes peak detector and AGC amplifier, and institute
State peak detector and the AGC amplifier is sequentially connected in series the input of output end and the main amplifier in the balanced device
Between to form backfeed loop.
In one embodiment of the present utility model, in addition to warning circuit, the input of the warning circuit with it is described
The output end electricity of clock recovery circuitry.
In one embodiment of the present utility model, the preamplifier is the preposition amplification of field-effect transistor mutual impedance
Device.
In one embodiment of the present utility model, the photodetector includes：
SOI substrate 11, including Si substrate layers 110, the SiO stacked gradually2Layer 120 and Si layers, the Si layers are included successively
Horizontally arranged n-type doping area 111, i types area 112 and p-type doped region 113；
Crystallization Ge layers 12, on the surface of i types area 112；
Metal electrode 13, the metal electrode 13 are respectively arranged at the n-type doping area 111 and the p-type doped region 113
On；
SiO2Passivation layer 14, on the crystallization Ge layers 12 and the Si layers.
The digital light receiver of the utility model embodiment has that photoelectric transformation efficiency is high, and cost is low and the spy such as excellent performance
Point.
Brief description of the drawings
Fig. 1 is a kind of structural representation for smooth receiver that the utility model embodiment provides；
Fig. 2 is a kind of structural representation for agc circuit that the utility model embodiment provides；
Fig. 3 is a kind of structural representation for photodetector that the utility model embodiment provides；
Fig. 4 is a kind of schematic diagram for laser crystallization technique that the utility model embodiment provides.
Embodiment
Further detailed description, but embodiment party of the present utility model are to the utility model with reference to specific embodiment
Formula not limited to this.
Embodiment one
Fig. 1, Fig. 2, Fig. 3 are referred to, Fig. 1 is a kind of structural representation for smooth receiver that the utility model embodiment provides
Figure；Fig. 2 is a kind of structural representation for agc circuit that the utility model embodiment provides；Fig. 3 carries for the utility model embodiment
A kind of structural representation of the photodetector supplied；The light receiver includes：Including：Photodetector, preamplifier, master are put
Big device, balanced device, agc circuit, decision device, decoder, input, output end, clock recovery circuitry, wherein：The photoelectricity is visited
Device, the preamplifier, the balanced device, the decision device, the decoder is surveyed to be sequentially connected in series in the input and institute
State output end；The agc circuit is serially connected between the output end of the balanced device and the input of the main amplifier and formed instead
Present loop；The input of the clock recovery circuitry electrically connects with the output end of the balanced device, its output end respectively with it is described
The input of the input of decision device and the decoder electrically connects；The output end of the decoder is electrically connected with the output end
Connect.
In one embodiment of the present utility model, the agc circuit includes peak detector and AGC amplifier, and institute
State peak detector and the AGC amplifier is sequentially connected in series the input of output end and the main amplifier in the balanced device
Between to form backfeed loop.
In one embodiment of the present utility model, in addition to warning circuit, the input of the warning circuit with it is described
The output end electricity of clock recovery circuitry.
In one embodiment of the present utility model, the preamplifier is the preposition amplification of field-effect transistor mutual impedance
Device.
In one embodiment of the present utility model, the photodetector includes：
SOI substrate 11, including Si substrate layers 110, the SiO stacked gradually2Layer 120 and Si layers, the Si layers are included successively
Horizontally arranged n-type doping area 111, i types area 112 and p-type doped region 113；
Crystallization Ge layers 12, on the surface of i types area 112；
Metal electrode 13, the metal electrode 13 are respectively arranged at the n-type doping area 111 and the p-type doped region 113
On；
SiO2Passivation layer 14, on the crystallization Ge layers 12 and the Si layers.
Wherein, the crystallization Ge layers are by the laser Ge layers that crystallization process makes again, refer to Fig. 4, Fig. 4 is this practicality
A kind of schematic diagram for laser crystallization technique that new embodiment provides.Crystallization process is a kind of side of thermal induced phase transition crystallization to laser again
Method, the process of recrystallization is melted by laser crystallization, big crystal grain can be grown, it is thin that the higher Ge of crystallization degree can be obtained
Film, the defects of significantly relatively low Ge materials.
Light receiver in the utility model embodiment at work, by light sender through optical fiber be transmitted through Lai optical signal from
Input inputs, and is changed into electric signal by photodetector, and electric signal is amplified to obtain one-level and put by preamplifier
Big electric signal, the one-level amplified signal that preamplifier exports is continued to be amplified to the letter required for decision device by main amplifier
Number level is two level amplification electric signal；Meanwhile when the electric signal of photodetector output rises and falls, pass through automatic gain control
Gain of the circuit processed to main amplifier is adjusted, so that the two level of main amplifier output amplifies electrical signal amplitude in certain limit
Do not influenceed by the one-level amplification electric signal inputted；Terminal decision device output signal by decoder enter row decoding handle it is laggard
Row signal regeneration obtains final output signal and exported from output end；When the optical signal of input is too weak or without optical signal,
An alarm signal is then exported by warning circuit.
The utility model embodiment is by using high performance photodetector, the light receiver photoelectric transformation efficiency of preparation
Height, cost is low, performance is good；Photodetector possesses high-speed response rate and the characteristic of high-quantum efficiency.
Above content is to combine specific preferred embodiment further detailed description of the utility model, it is impossible to
Assert that specific implementation of the present utility model is confined to these explanations.For the ordinary skill of the utility model art
For personnel, without departing from the concept of the premise utility, some simple deduction or replace can also be made, should all be regarded
To belong to the scope of protection of the utility model.
Claims (4)
- A kind of 1. digital light receiver, it is characterised in that including：Photodetector, preamplifier, main amplifier, balanced device, Agc circuit, decision device, decoder, input, output end, clock recovery circuitry, wherein：It is the photodetector, described preposition Amplifier, the balanced device, the decision device, the decoder are sequentially connected in series in the input and the output end；It is described Agc circuit is serially connected between the output end of the balanced device and the input of the main amplifier and forms feedback control loop；When described The input of clock restoring circuit electrically connects with the output end of the balanced device, its output end input with the decision device respectively Electrically connected with the input of the decoder；The output end of the decoder electrically connects with the output end.
- 2. smooth receiver according to claim 1, it is characterised in that the agc circuit includes peak detector and AGC is put Big device, and the peak detector and the AGC amplifier are sequentially connected in series output end and the main amplification in the balanced device To form backfeed loop between device.
- 3. smooth receiver according to claim 1, it is characterised in that also including warning circuit, the warning circuit it is defeated Enter end to electrically connect with the clock recovery circuitry.
- 4. smooth receiver according to claim 1, it is characterised in that the preamplifier is field-effect transistor mutual resistance Anti- preamplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721005336.2U CN207200709U (en) | 2017-08-11 | 2017-08-11 | Digital light receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721005336.2U CN207200709U (en) | 2017-08-11 | 2017-08-11 | Digital light receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207200709U true CN207200709U (en) | 2018-04-06 |
Family
ID=61797317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721005336.2U Expired - Fee Related CN207200709U (en) | 2017-08-11 | 2017-08-11 | Digital light receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207200709U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111835423A (en) * | 2020-08-07 | 2020-10-27 | 武汉锐奥特科技有限公司 | Communication system of QSFP28 type packaged 100G optical module |
-
2017
- 2017-08-11 CN CN201721005336.2U patent/CN207200709U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111835423A (en) * | 2020-08-07 | 2020-10-27 | 武汉锐奥特科技有限公司 | Communication system of QSFP28 type packaged 100G optical module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201009 Address after: Room 13202, unit 1, building 1, Xinlong natural olive international, No.9, south section of Gongyuan South Road, Yanta District, Xi'an City, Shaanxi Province 710000 Patentee after: Xi'an Demeter Information Technology Co.,Ltd. Address before: 710065, No. 7, No. 15, high tech Road, Xi'an hi tech Zone, Shaanxi, China, -A009 Patentee before: XI'AN CREATION KEJI Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180406 Termination date: 20210811 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |