CN109697950B

CN109697950B - Display device and display driving chip thereof

Info

Publication number: CN109697950B
Application number: CN201910129268.8A
Authority: CN
Inventors: 蔡勋; 刘庆春; 宣扬
Original assignee: Hefei Eswin IC Technology Co Ltd
Current assignee: Hefei Eswin IC Technology Co Ltd
Priority date: 2019-02-21
Filing date: 2019-02-21
Publication date: 2022-08-05
Anticipated expiration: 2039-02-21
Also published as: CN109697950A

Abstract

The technical scheme of the invention is different from the technical scheme that the traditional display driving chip continuously outputs periodic clock signals in working engineering.

Description

Display device and display driving chip thereof

Technical Field

The invention relates to the technical field of display equipment, in particular to a display device and a display driving chip thereof.

Background

With the continuous development of science and technology, more and more electronic devices with image display functions are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The main component of the electronic device for realizing the display function is a display device, and the display device needs to drive the pixel unit through the display driving chip to display an image. When the existing display driving chip carries out display driving, the problem of data rate mismatching exists, and the image display quality is influenced.

Disclosure of Invention

In view of this, the present invention provides a display device and a display driver chip thereof, which overcome the problem of data rate mismatch and improve image display quality.

In order to achieve the above purpose, the invention provides the following technical scheme:

a display driver chip, comprising:

the signal receiving module is used for recovering a clock signal and digital video data based on a differential signal input from the outside, outputting the clock signal and the digital video data, and synchronously closing the clock signal in a closing time period when the digital video data has the closing time period;

and the digital-analog driver is used for providing an analog data signal for the pixel unit based on the clock signal output by the signal receiving module and the digitized video data and driving the pixel unit to display an image.

Preferably, in the display driving chip, the signal receiving module includes:

a data clock recovery circuit for outputting the clock signal and the digitized video data;

the data buffer circuit is used for acquiring the clock signal and the digitized video data output by the data clock recovery circuit, sending the digitized video data to the digital-analog driver, and controlling the output state of the clock control circuit based on the output state of the digitized video data, when the digitized video data has a closing time period, controlling the clock control circuit to synchronously close the clock signal in the closing time period, and sending the clock signal output by the clock control circuit to the digital-analog driver.

Preferably, in the display driving chip, the digital-to-analog driver includes: a digital module and an analog module;

the digital module is used for performing scanning operation based on the clock signal output by the signal receiving module, sampling and registering the digital video data output by the signal receiving module based on the scanning operation, and keeping and registering the digital video data which is sampled and registered;

the analog module is used for acquiring the digital video data kept and registered by the digital module, carrying out level shift on the acquired digital video data, carrying out digital-to-analog conversion on the digital video data after level shift to form an analog data signal, buffering the analog data signal, sending the analog data signal to a corresponding pixel unit, and driving the pixel unit to display images.

Preferably, in the display driving chip, the digital module includes:

the shift register group is provided with a plurality of cascaded shift registers, and the first-stage shift register is used for acquiring the clock signal output by the signal receiving module;

the sampling register group is provided with a plurality of cascaded sampling registers, the sampling registers are connected with the shift registers in a one-to-one correspondence mode, and the first-stage sampling register is used for acquiring the digitized video data output by the signal receiving module;

and the holding register group is provided with a plurality of holding registers, and the holding registers are connected with the sampling registers in a one-to-one correspondence mode.

Preferably, in the display driving chip, the first stage sampling register is connected to the signal receiving module through a data receiver.

Preferably, in the display driver chip, the shift register is a bidirectional shift register.

Preferably, in the display driving chip, the analog module includes:

a level shifter group having a plurality of level shifters, the level shifters being connected to the holding registers in a one-to-one correspondence;

the digital-to-analog converter is connected with the level shifter and performs digital-to-analog conversion based on a polarity signal;

and the buffer group is provided with a plurality of buffers and is used for acquiring analog data signals which are output by the digital-to-analog converter and correspond to the display channels and are subjected to digital-to-analog conversion so as to drive the pixel units which are correspondingly connected to display images.

The present invention also provides a display device, including:

a plurality of pixel units arranged in an array;

the display driving chip is used for driving the pixel unit to display images;

wherein the display driver chip is as claimed in any one of claims 1 to 7.

Preferably, in the display device, the display driving chip includes a plurality of buffers for outputting the analog data signals;

the pixel units are connected with the buffer through data lines, the pixel units in the same column are connected with the same buffer through the same data lines, and the pixel units in different columns are connected with different buffers through different data lines.

Preferably, in the above display device, the display device is a liquid crystal display.

As can be seen from the above description, the display device and the display driving chip thereof according to the technical solution of the present invention have at least the following advantages:

different from the technical scheme that the traditional display driving chip continuously outputs periodic clock signals in the work engineering, in the display driving chip of the technical scheme of the invention, the signal receiving module can synchronously output the clock signals based on the digital video signals, and synchronously close the clock signals in the closing time period when the digital video data has the closing time period, so that the clock signals and the digital video data are discontinuously output at the same time, the problem of mismatching of data rates is solved, and the image display quality is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a timing diagram of a display driver chip for performing display driving;

FIG. 2 is a schematic diagram of a display driver chip;

FIG. 3 is a timing diagram illustrating the display driving of the display driver chip shown in FIG. 2;

fig. 4 is a schematic structural diagram of a display driver chip according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another display driver chip according to an embodiment of the present invention;

fig. 6 is a timing diagram illustrating the display driving of the display driving chip according to the embodiment of the invention;

fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

As shown in fig. 1, fig. 1 is a timing diagram of display driving performed by a display driving chip, when the display driving chip performs display driving, a sufficient amount (one line) of data of a display channel needs to be continuously input, and then a pixel unit is controlled to perform display, which imposes a constraint on a circuit architecture of a front-end digital module of the display driving chip and needs to implement the display driving process by using the front-end digital module with a specific circuit structure. In fig. 1, T _ DA _ L [7:0], T _ DB _ L [7:0], T _ DC _ L [7:0] and T _ DD _ L [7:0] are digitized video data to be displayed, dpollv is a data inversion signal (the data inversion signal is 0 in fig. 1), T _ CLK _ L is a clock signal for controlling sampling of a current row of pixel units to display the digitized video data, and T _ STH _ L is a scan signal for the row of pixel units.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a display driver chip, where the display driver chip includes: a digital module and an analog module.

The digital module includes: a shift register group, a sampling register group and a holding register group. The shift register group comprises a plurality of cascaded shift registers, the sampling register group comprises a plurality of cascaded sampling registers, and the holding register group comprises a plurality of holding registers.

The shift registers, the sampling registers and the holding registers are the same in number and are in one-to-one correspondence. If the numbers of the shift registers, the sampling registers and the holding registers are all n, and n is a positive integer greater than 0, n display channels are formed. The n display channels respectively output a data signal, and the n data signals are sequentially a data signal Out 1-a data signal Outn.

When the same row of pixel units are subjected to display driving, each display channel transmits data to one pixel unit corresponding to the row of pixel units. The first stage shift register inputs a clock signal CLK in the horizontal direction and a scanning synchronization signal DIO1 in the horizontal direction to control the scanning operation of each stage of shift register, and the sampling registers are opened one by one to sequentially store the digital video data to be displayed by the current row of pixel units into each stage of sampling registers. The first stage sampling register inputs the digital video Data through the Data receiver, and the digital video Data are sequentially stored in the sampling registers of each stage according to the scanning operation. The shift register is a bidirectional shift register, and the scan synchronization signal DIO2 in the horizontal direction may be input to the last shift register to perform the reverse scan operation.

The latch signal is an enable signal for storing the digitized video Data into the corresponding holding register. When the latch signal is inputted to the holding register group, the digitized video Data is stored in the corresponding holding register according to the control timing.

The simulation module comprises: the level shifter group comprises a plurality of level shifters, and the buffer group comprises a plurality of buffers. The number of the level shifters is equal to that of the buffers, and the number of the level shifters is equal to that of the display channels.

For any display channel, a level shifter in the display channel acquires digitized video Data from a holding register which is correspondingly connected and sends the digitized video Data to a digital-to-analog converter, the digital-to-analog converter performs digital-to-analog conversion based on a polarity signal and gamma reference voltage, outputs a path of Data signal, sends the path of Data signal to a pixel unit through a corresponding buffer, and drives the pixel unit to perform image display.

In the display driving chip shown in fig. 2, when a Data input is detected, Data transmission is started, a display driving timing sequence of the display driving chip is shown in fig. 3, fig. 3 is a timing chart of the display driving chip shown in fig. 2 for performing display driving, and when a row of pixel units is scanned based on a scanning signal STH, a clock signal CLK is continuous, so that when a set of digitized video Data has an off period without output, because the clock signal CLK is continuous, the clock signal CLK in the corresponding off period (shown as a circular area in fig. 3) may cause a sampling register set to acquire wrong Data, thereby causing an image display error. In order to avoid this problem, it is conventionally selected to add an internal data buffer circuit in the display driver chip corresponding to each display channel, but this results in a larger area of the display driver chip.

In order to solve the above problem, an embodiment of the present invention provides a display driver chip, where the display driver chip may perform clock control on Data output to a driver display, so as to achieve rate matching between a clock signal CLK and digital video Data, reduce an area of an internal Data buffer circuit, and further reduce an area of the display driver chip.

Based on the above description, an embodiment of the present invention provides a display driver chip, as shown in fig. 4, fig. 4 is a schematic structural diagram of the display driver chip provided in the embodiment of the present invention, where the display driver chip includes: a signal receiving module 11, where the signal receiving module 11 is configured to recover a clock signal and digitized video Data based on a differential signal input from the outside, and output a clock signal CLK and the digitized video Data, and when the digitized video Data has an off period, synchronously turn off the clock signal CLK in the off period, so that the clock signal CLK and the digitized video Data are output at the same time or turned off at the same time; and the digital-to-analog driver 12, wherein the digital-to-analog driver 12 is configured to provide an analog Data signal for the pixel unit based on the clock signal CLK and the digitized video Data output by the signal receiving module 11, and drive the pixel unit to display an image. The off period refers to a period in which at least one cycle of the digitized video Data continues without output. The differential signal includes a clock signal and digitized video data coupled together, and the signal receiving module 11 recovers the clock signal and the digitized video data by dividing the clock signal and the digitized video data into two paths for output respectively through data processing.

The structure of the signal receiving module 11 is shown in fig. 5, and fig. 5 is a schematic structural diagram of another display driving chip according to an embodiment of the present invention, where the signal receiving module 11 includes: a Data clock recovery circuit 31, the Data clock recovery circuit 31 being configured to output the clock signal CLK and the digitized video Data; and the Data buffer circuit 32 is configured to obtain the clock signal CLK output by the Data clock recovery circuit 31 and the digitized video Data, send the digitized video Data to the digital-to-analog driver 12, and further control the output state of the clock control circuit 33 based on the output state of the digitized video Data, when the digitized video Data has an off period, control the clock control circuit 33 to synchronously turn off the clock signal CLK in the off period, and send the clock signal CLK output by the clock control circuit 33 to the digital-to-analog driver 12. The data buffer circuit 32 includes a buffer.

The scheme of the embodiment of the invention is that the Data clock recovery circuit 31 enters the Data buffer circuit 32 after sending the Data (including the clock signal CLK and the digitized video Data), and if the digitized video Data has a discontinuous stage after the clock signal CLK output by the Data buffer circuit 32 is controlled by the clock of the clock control circuit 33, the clock signal CLK and the digitized video Data finally output by the signal receiving module 11 are discontinuous at the same time.

The clock signal CLK output from the clock control circuit 33 is transmitted to the first stage shift register 211 of the shift register group 21. When the data buffer circuit 32 detects that data is entered, it may start data transmission, and transmit the clock signal CLK to the shift register 211 of the subsequent stage through the clock control circuit 33.

As shown in fig. 6, fig. 6 is a timing diagram of the display driving chip according to the embodiment of the present invention, if the digitized video Data output from the Data clock recovery circuit 31 to the Data buffer circuit 32 is suspended after a period of transmission (the digitized video Data in fig. 6 corresponds to a no-output period of 00, which may be regarded as a shutdown period of the digitized video Data), that is, the digitized video Data has a discontinuous problem, at this time, the Data buffer circuit 32 detects that no digitized video Data enters, and after the transmission of the stored digitized video Data is completed, the clock signal CLK is suspended through the clock control circuit 33. After the clock signal CLK is suspended, the shift register 211 at the rear end does not operate any more, thereby achieving rate matching with the digitized video Data output from the Data clock recovery circuit 31.

As shown in fig. 6, in the waveform diagram of the display driver chip according to the embodiment of the present invention after the redesign, the output clock signal CLK is turned off, and the 00 Data after the pause of the digitized video Data is not sampled. The key point of the technical scheme of the invention is that before Data is input into the digital module, the buffered clock signal CLK is controlled, after the digital video Data at the front end of the Data clock recovery circuit 31 is suspended, the clock signal CLK at the rear end can be closed, and the purpose that the whole Data of the Data clock recovery circuit 31 can be suspended is achieved.

The signal receiving module 11 according to the embodiment of the present invention may output the clock signal CLK synchronized with the clock of the digitized video Data based on the output state of the digitized video Data, and the implementation manner may be implemented by an integrated circuit, and is not limited to the manner shown in fig. 5.

As shown in fig. 5, the digital-analog driver 12 includes: a digital module and an analog module; the digital module is used for performing scanning operation based on the clock signal CLK output by the signal receiving module 11, performing sampling and registering on the digitized video Data output by the signal receiving module 11 based on the scanning operation, and performing holding and registering on the digitized video Data subjected to sampling and registering; the analog module is used for acquiring the digital video Data kept and registered by the digital module, performing level shift on the acquired digital video Data, performing digital-to-analog conversion on the digital video Data after the level shift to form an analog Data signal, buffering the analog Data signal, sending the analog Data signal to a corresponding pixel unit, and driving the pixel unit to display an image.

As shown in fig. 5, the digital module includes: a shift register group 21 having a plurality of cascaded shift registers 211, a first stage shift register being configured to obtain the clock signal output by the signal receiving module 11; the sampling register group 22 is provided with a plurality of cascaded sampling registers 221, the sampling registers 221 are connected with the shift registers 211 in a one-to-one correspondence manner, and the first-stage sampling register is used for acquiring the digitized video Data output by the signal receiving module 11; the holding register group 23 has a plurality of holding registers 231, and the holding registers 231 are connected to the sampling registers 221 in a one-to-one correspondence. The first stage sampling register is connected to the signal receiving module 11 through a Data receiver 27 to input digitized video Data.

The shift register 211 is a bidirectional shift register. The scan operation of each stage of the shift register 211 may be controlled based on the scan synchronization signal DIO1 input to the first stage of the shift register, or the scan operation of each stage of the shift register 211 may be controlled based on the scan synchronization signal DIO2 input to the last stage of the shift register. The scan direction when the scan sync signal DIO1 is input is opposite to the scan direction when the scan sync signal DIO2 is input.

The simulation module includes: a level shifter group 24 having a plurality of level shifters 241, the level shifters 241 being connected to the holding registers 231 in a one-to-one correspondence; the digital-to-analog converter 25 is connected with the level shifter 241 and performs digital-to-analog conversion based on a polarity signal; the buffer group 26 has a plurality of buffers 261, and the buffers 261 are configured to obtain the analog Data signals Data after digital-to-analog conversion output by the digital-to-analog converter 25 corresponding to the display channel, so as to drive the pixel units correspondingly connected to display an image.

In the mode shown in fig. 5, the display driver chip has n display channels, and outputs n analog data signals, which are sequentially an analog data signal Out 1-an analog data signal Outn. The shift register group 21 has n shift registers 211, corresponding to the n display channels one to one. The sampling register group 22 has n sampling registers 221, one-to-one corresponding to n display channels. The holding register group 23 has n holding registers 231, one-to-one corresponding to the n display channels. The level shifter group 24 has n level shifters 241, one-to-one corresponding to n display channels. The buffer group 26 has n buffers 261, one-to-one corresponding to n display channels.

The digital-to-analog driver 12 according to the embodiment of the present invention is configured to drive the pixel unit to display an image based on the clock signal CLK output by the signal receiving module 11 and the digitized video Data, and perform digital-to-analog conversion through corresponding Data processing to facilitate display driving, and a specific implementation manner of a circuit thereof is not limited to the manner shown in fig. 5.

In the control field of the display driving chip, Data transmission is required between the analog module for receiving Data and the digital module for driving and displaying, and the display driving chip can perform clock control on the Data output to the driving and displaying so that a clock signal CLK input to the digital-to-analog converter 12 is matched with digital video Data, thereby matching the speed between the input Data of the digital module and the output Data of the analog module, reducing the use of Data cache in the chip and reducing the area of the chip.

The scheme of the embodiment of the invention applies a model of buffer memory and clock control, does not need to add a data buffer circuit at the part of the digital module, and can solve the problem that the bidirectional shift register needs continuous clock input and is inconvenient for the structural design of the front-end digital module.

Based on the display driving chip described in the above embodiment, another embodiment of the present invention further provides a display device, as shown in fig. 7, where fig. 7 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device 41 includes: a plurality of pixel units P arranged in an array; the display driving chip 42, the display driving chip 42 is used for driving the pixel unit P to display an image; the display driving chip 42 is the display driving chip described in the above embodiments.

The display driving chip 42 includes a plurality of buffers for outputting the analog data signals; the pixel units are connected to the buffer through data lines 44, the pixel units P in the same column are connected to the same buffer through the same data lines 44, and the pixel units P in different columns are connected to different buffers through different data lines 44.

The display device is a liquid crystal display. The display device 41 may be an electronic device such as a mobile phone, a computer, a television, or a wearable device having a display function.

The display device 41 has a display area 43 and a frame area including the display area 43. The pixel unit P is located in the display area 43, and the display driving chip 42 is located in the frame area. The display driving chip 42 has a plurality of display channels, and each display channel individually corresponds to one column of pixel units P. Each display channel may be individually connected to a column of pixel cells P via a data line 44.

The display device 41 according to the embodiment of the present invention, which adopts the display driving chip according to the above-described embodiment, can achieve synchronization between the clock signal and the data signal, and avoid the problem that the clock signal is output at any time when the data signal is zero, thereby avoiding the problem of display errors caused by the clock signal.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the display device disclosed in the embodiment, since it corresponds to the display driving chip disclosed in the embodiment, the description is relatively simple, and the relevant points can be referred to the description of the corresponding parts of the display driving chip.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display driving chip, comprising:

the digital-analog driver is used for providing analog data signals for the pixel units and driving the pixel units to display images based on the clock signals output by the signal receiving module and the digitized video data;

the signal receiving module includes:

2. The display driver chip of claim 1, wherein the digital-to-analog driver comprises: a digital module and an analog module;

3. The display driver chip of claim 2, wherein the digital module comprises:

4. The display driver chip of claim 3, wherein the first stage sampling register is connected to the signal receiving module through a data receiver.

5. The display driver chip of claim 3, wherein the shift register is a bi-directional shift register.

6. The display driver chip of claim 3, wherein the analog module comprises:

7. A display device, characterized in that the display device comprises:

a plurality of pixel units arranged in an array;

the display driving chip is used for driving the pixel unit to display images;

wherein the display driver chip is as claimed in any one of claims 1 to 6.

8. The display device according to claim 7, wherein the display driver chip includes a plurality of buffers for outputting the analog data signals;

9. A display device as claimed in claim 7 or 8, characterized in that the display device is a liquid crystal display.