CN106782413A - Shift register, gate driving circuit and display panel - Google Patents
Shift register, gate driving circuit and display panel Download PDFInfo
- Publication number
- CN106782413A CN106782413A CN201710099409.7A CN201710099409A CN106782413A CN 106782413 A CN106782413 A CN 106782413A CN 201710099409 A CN201710099409 A CN 201710099409A CN 106782413 A CN106782413 A CN 106782413A
- Authority
- CN
- China
- Prior art keywords
- switching transistor
- shift register
- signal
- node
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000001360 synchronised effect Effects 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000012905 input function Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101001077374 Oryza sativa subsp. japonica UMP-CMP kinase 3 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of shift register, gate driving circuit and display panel, shift register includes：Input module, reseting module, node control module, the first output module, the second output module and the first compensating module.The shift register is by increasing by the first compensating module, when Section Point is in floating, the signal of the 3rd reference voltage end is supplied to the signal output end of shift register using the first compensating module, ensure the signal output end of shift register has signal output all the time, so as to when all signals of input shift register are synchronous with the signal in self-capacitance electrode, it is possible to achieve the signal of signal output end is synchronous with the signal in self-capacitance electrode.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display panel.
Background
In a Thin Film Transistor display, a gate driving signal is generally supplied to a gate of each Thin Film Transistor (TFT) in a pixel region by a gate driving device. The Gate driving device can be formed on an Array substrate of the liquid crystal display through an Array process, namely, a Gate Driver on Array (GOA) process of the Array substrate, the integration process not only saves cost, but also can achieve an aesthetic design of bilateral symmetry of a liquid crystal Panel (Panel), and simultaneously, a binding region of a Gate Integrated Circuit (IC) and a wiring space of a Fan-out (Fan-out) are also saved, thereby realizing the design of a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
In the embedded self-capacitance touch screen, when touch control and display are performed synchronously, in order to ensure that the touch control signal of the self-capacitance electrode is not interfered, other signals in the touch screen need to be synchronized with the signal on the self-capacitance electrode. However, in the conventional gate driving circuit, since the output terminals of the respective stages are in a floating state for a period of time, even if all signals input to the gate driving circuit are synchronized with the signal on the self-capacitance electrode, the signal on the gate line cannot be synchronized with the signal on the self-capacitance electrode.
Disclosure of Invention
Embodiments of the present invention provide a shift register, a gate driving circuit and a display panel, which can output signals to gate lines in synchronization with signals on self-capacitance electrodes when touch control and display are performed simultaneously.
Accordingly, an embodiment of the present invention provides a shift register, including: the device comprises an input module, a reset module, a node control module, a first output module, a second output module and a first compensation module; wherein,
the input module is used for providing a signal of the first reference voltage end to a first node under the control of an input signal end;
the reset module is used for providing a signal of the second reference voltage end to the first node under the control of a reset signal end;
the node control module is used for providing a signal of a first clock signal end to a second node under the control of the first clock signal end and providing a signal of a third reference voltage end to the first node under the control of the second node;
the first output module is used for providing a signal of a second clock signal end to a grid signal output end of the shift register under the control of the first node;
the second output module is used for providing a signal of the third reference voltage end to a grid signal output end of the shift register under the control of the second node;
the first compensation module is used for providing a signal of the third reference voltage end to a grid signal output end of the shift register under the control of the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first compensation module specifically includes: a first switching transistor; wherein,
and the grid electrode of the first switch transistor is connected with the first node, the first pole of the first switch transistor is connected with the third reference voltage end, and the second pole of the first switch transistor is connected with the grid signal output end of the shift register.
Preferably, the shift register provided in the embodiment of the present invention further includes: a second compensation module; wherein,
the second compensation module is used for providing a signal of the third reference voltage end to the grid signal output end of the shift register under the control of a third clock signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the second compensation module specifically includes: a second switching transistor; wherein,
and the grid electrode of the second switching transistor is connected with the third clock signal end, the first pole of the second switching transistor is connected with the third reference voltage end, and the second pole of the second switching transistor is connected with the grid signal output end of the shift register.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the input module specifically includes: a third switching transistor; wherein,
and the grid electrode of the third switching transistor is connected with the input signal end, the first pole of the third switching transistor is connected with the first reference voltage end, and the second pole of the third switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module specifically includes: a fourth switching transistor; wherein,
and the grid electrode of the fourth switching transistor is connected with the reset signal end, the first electrode of the fourth switching transistor is connected with the second reference voltage end, and the second electrode of the fourth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the node control module specifically includes: a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, and a first capacitor; wherein,
a gate and a first pole of the fifth switching transistor are both connected to the first clock signal terminal, and a second pole of the fifth switching transistor is connected to the second node;
a gate of the sixth switching transistor is connected to the second node, a first pole of the sixth switching transistor is connected to the third reference voltage terminal, and a second pole of the sixth switching transistor is connected to the first node;
a gate of the seventh switching transistor is connected to the first node, a first pole of the seventh switching transistor is connected to the third reference voltage terminal, and a second pole of the seventh switching transistor is connected to the second node;
a gate of the eighth switching transistor is connected with a gate signal output end of the shift register, a first pole of the eighth switching transistor is connected with the third reference voltage end, and a second pole of the eighth switching transistor is connected with the second node;
the first capacitor is connected between the second node and the third reference voltage terminal.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output module specifically includes: a ninth switching transistor and a second capacitor; wherein,
a gate of the ninth switching transistor is connected to the first node, a first pole of the ninth switching transistor is connected to the second clock signal terminal, and a second pole of the ninth switching transistor is connected to a gate signal output terminal of the shift register;
the second capacitor is connected between the gate and the second pole of the ninth switching transistor.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the second output module specifically includes: a tenth switching transistor; wherein,
and the grid electrode of the tenth switching transistor is connected with the second node, the first pole of the tenth switching transistor is connected with the third reference voltage end, and the second pole of the tenth switching transistor is connected with the grid signal output end of the shift register.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein,
except the first stage of shift register, the input signal end of each stage of shift register is connected with the grid signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is connected with the grid signal output end of the next stage of shift register adjacent to the reset signal end of each stage of shift register.
Correspondingly, the embodiment of the invention also provides a display panel which comprises the grid drive circuit provided by the embodiment of the invention.
The invention has the following beneficial effects:
the shift register, the gate driving circuit and the display panel provided by the embodiment of the invention comprise: the device comprises an input module, a reset module, a node control module, a first output module, a second output module and a first compensation module. The input module is used for providing a signal of a first reference voltage end to a first node under the control of an input signal end; the reset module is used for providing a signal of a second reference voltage end to the first node under the control of the reset signal end; the node control module is used for providing a first clock signal of the first clock signal end to a second node under the control of the first clock signal end and providing a signal of a third reference voltage end to the first node under the control of the second node; the first output module is used for providing a second clock signal of the second clock signal end to the grid signal output end of the shift register under the control of the first node; the second output module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the second node; the first compensation module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the first clock signal end. According to the shift register, the first compensation module is added, when the second node is in a floating state, the first compensation module is used for providing a signal of the third reference voltage end for the grid signal output end of the shift register, and therefore the grid signal output end of the shift register is guaranteed to have signal output all the time, and therefore when all signals input into the shift register are synchronous with signals on the self-capacitance electrode, the signals of the grid signal output end and the signals on the self-capacitance electrode can be synchronous.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 3 is a third schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a timing diagram of an input/output of the shift register shown in FIG. 3;
FIG. 5 is a timing diagram of an alternative input/output circuit corresponding to the shift register shown in FIG. 3.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driver circuit, and a display panel according to embodiments of the present invention with reference to the accompanying drawings.
As shown in fig. 1, a shift register according to an embodiment of the present invention includes: the system comprises an input module 1, a reset module 2, a node control module 3, a first output module 4, a second output module 5 and a first compensation module 6; wherein,
the Input module 1 is configured to provide a signal of a first reference voltage terminal Vref1 to a first node a under the control of an Input signal terminal Input;
the Reset module 2 is configured to provide a signal of a second reference voltage terminal Vref2 to a second node B under the control of a Reset signal terminal Reset;
the node control module 3 is used for providing the signal of the first clock signal terminal CK1 to the second node B under the control of the first clock signal terminal CK1 and providing the signal of the third reference voltage terminal Vref3 to the first node a under the control of the second node B;
the first Output module 4 is configured to provide a signal of the second clock signal terminal CK2 to the gate signal Output terminal Output of the shift register under the control of the first node a;
the second Output module 5 is configured to provide a signal of a third reference voltage terminal Vref3 to a gate signal Output terminal Output of the shift register under the control of the second node B;
the first compensation module 6 is configured to provide a signal of a third reference voltage terminal Vref3 to a gate signal Output terminal Output of the shift register under the control of the first node a.
An embodiment of the present invention provides a shift register, including: the device comprises an input module, a reset module, a node control module, a first output module, a second output module and a first compensation module. The input module is used for providing a signal of a first reference voltage end to a first node under the control of an input signal end; the reset module is used for providing a signal of a second reference voltage end to the first node under the control of the reset signal end; the node control module is used for providing a first clock signal of the first clock signal end to a second node under the control of the first clock signal end and providing a signal of a third reference voltage end to the first node under the control of the second node; the first output module is used for providing a second clock signal of the second clock signal end to the grid signal output end of the shift register under the control of the first node; the second output module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the second node; the first compensation module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the first clock signal end. According to the shift register, the first compensation module is added, when the second node is in a floating state, the first compensation module is used for providing a signal of the third reference voltage end for the grid signal output end of the shift register, and therefore the grid signal output end of the shift register is guaranteed to have signal output all the time, and therefore when all signals input into the shift register are synchronous with signals on the self-capacitance electrode, the signals of the grid signal output end and the signals on the self-capacitance electrode can be synchronous.
In practical implementation, in the shift register provided in the embodiment of the present invention, the phase of the signal at the first clock signal terminal is opposite to the phase of the signal at the second clock signal terminal.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the first compensation module 6 specifically includes: a first switching transistor M1; wherein,
a first switch transistor M1 has a gate connected to the first node a, a first pole connected to the third reference voltage terminal Vref3, and a second pole connected to the gate signal Output terminal Output of the shift register.
In practical implementation, in the shift register provided in the embodiment of the invention, the third clock signal terminal CK3 may be the same as the first clock signal terminal CK1, or the same as the second clock signal terminal CK 2; and the type of the first switching transistor M1 when the third clock signal terminal CK3 is identical to the first clock signal terminal CK1 is opposite to the type of the first switching transistor M1 when the third clock signal terminal CK3 is identical to the second clock signal terminal CK 2.
The above is merely an example of the specific structure of the first compensation module in the shift register, and in the specific implementation, the specific structure of the first compensation module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In specific implementation, in order to further ensure that a signal is always output from the gate signal output terminal of the shift register, so that when all signals input to the shift register are synchronized with a signal on the self-capacitance electrode, synchronization between the signal on the gate signal output terminal and the signal on the self-capacitance electrode can be achieved, as shown in fig. 2, the shift register provided in the embodiment of the present invention further includes: a second compensation module 7; wherein,
the second compensation module 7 is configured to provide a signal of a third reference voltage terminal Vref3 to the gate signal Output terminal Output of the shift register under the control of the third clock signal terminal CK 3.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the second compensation module 7 specifically includes: a second switching transistor M2; wherein,
a second switching transistor M2 has a gate connected to the third clock signal terminal CK3, a first pole connected to the third reference voltage terminal Vref3, and a second pole connected to the gate signal Output terminal Output of the shift register.
The above is merely an example of the specific structure of the second compensation module in the shift register, and in the specific implementation, the specific structure of the second compensation module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the input module 1 specifically includes: a third switching transistor M3; wherein,
the third switching transistor M3 has a gate connected to the Input signal terminal Input, a first pole connected to the first reference voltage terminal Vref1, and a second pole connected to the first node a.
The above is merely an example of the specific structure of the input module in the shift register, and in the specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the 2-reset module specifically includes: a fourth switching transistor M4; wherein,
the fourth switching transistor M4 has a gate connected to the Reset signal terminal Reset, a first pole connected to the second reference voltage terminal Vref2, and a second pole connected to the first node a.
The above is merely an example of the specific structure of the reset module in the shift register, and in the specific implementation, the specific structure of the reset module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the 3-node control module specifically includes: a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, and a first capacitor C1; wherein,
a fifth switching transistor M5 having a gate and a first pole both connected to the first clock signal terminal CK1, and a second pole connected to the second node B;
a sixth switching transistor M6 having a gate connected to the second node B, a first pole connected to the third reference voltage terminal Vref3, and a second pole connected to the first node a;
a seventh switching transistor M7 having a gate connected to the first node a, a first pole connected to the third reference voltage terminal Vref3, and a second pole connected to the second node B;
an eighth switching transistor M8, a gate of which is connected to the gate signal Output terminal Output of the shift register, a first pole of which is connected to the third reference voltage terminal Vref3, and a second pole of which is connected to the second node B;
the first capacitor C1 is connected between the second node B and the third reference voltage terminal Vref 3.
In practical implementation, in the shift register provided in the embodiment of the present invention, the size of the seventh switching transistor is generally set to be larger than that of the fifth switching transistor during process preparation, so that when the potential of the first node is a high potential, the rate at which the seventh switching transistor supplies the signal of the third reference voltage terminal to the second node under the control of the signal of the first node is greater than the rate at which the fifth switching transistor supplies the signal of the first clock signal terminal to the second node under the control of the first clock signal terminal, thereby ensuring that the potential of the second node is a low potential.
The above is merely an example of the specific structure of the node control module in the shift register, and in the specific implementation, the specific structure of the node control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the first output module 4 specifically includes: a ninth switching transistor M9 and a second capacitor C2; wherein,
a ninth switching transistor M9, having a gate connected to the first node a, a first pole connected to the second clock signal terminal CK2, and a second pole connected to the gate signal Output terminal Output of the shift register;
the second capacitor C2 is connected between the gate and the second pole of the ninth switch transistor M9.
The above is merely an example of the specific structure of the first output module in the shift register, and in the specific implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the second output module 5 specifically includes: a tenth switching transistor M10; wherein,
a tenth switching transistor M10 has a gate connected to the second node B, a first pole connected to the third reference voltage terminal Vref3, and a second pole connected to the gate signal Output terminal Output of the shift register.
The above is merely an example of the specific structure of the second output module in the shift register, and in the specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein.
In practical applications, the first pole of the switching transistor mentioned in the above embodiments of the present invention may be a source, and the second pole thereof may be a drain, or the first pole may be a drain, and the second pole thereof may be a source, which are not specifically distinguished herein.
Further, in the shift register provided in the embodiment of the present invention, the input module and the reset module are designed symmetrically, and function interchange can be achieved, so that the shift register provided in the embodiment of the present invention can implement bidirectional scanning. During forward scanning, the input signal end receives an input signal, the reset signal end receives a reset signal, the input module serves as an input function, and the reset module serves as a reset function. During reverse scanning, the input signal end receives a reset signal, the reset signal end receives the input signal, the reset module is used as an input function, and the input module is used as a reset function.
In practical implementation, in the shift register provided in the embodiment of the invention, when the valid pulse signal at the input signal terminal is a high-level signal, the third switching transistor M3 to the tenth switching transistor M10 are all N-type, and the first switching transistor M1 is P-type. During forward scanning, the potential of the first reference voltage end is high potential, and the potentials of the second reference voltage end and the third reference voltage end are both low potential; during reverse scanning, the potential of the second reference voltage terminal is high potential, and the potentials of the first reference voltage terminal and the third reference voltage terminal are both low potential.
Further, in the shift register according to the embodiment of the invention, when the third clock signal terminal is the same as the first clock signal terminal, the second switching transistor M2 is N-type; when the third clock signal terminal is the same as the second clock signal terminal, the second switching transistor M2 is P-type.
In a specific implementation, in the shift register provided in the embodiment of the invention, when the valid pulse signal at the input signal terminal is a low-level signal, the third to tenth switching transistors M3 to M10 are all P-type, and the first switching transistor M1 is P-type. During forward scanning, the potential of the first reference voltage end is a low potential, and the potentials of the second reference voltage end and the third reference voltage end are both high potentials; during reverse scanning, the potential of the second reference voltage terminal is a low potential, and the potentials of the first reference voltage terminal and the third reference voltage terminal are both high potentials.
Further, in the shift register according to the embodiment of the invention, when the third clock signal terminal is the same as the first clock signal terminal, the second switching transistor M2 is P-type; when the third clock signal terminal is the same as the second clock signal terminal, the second switching transistor M2 is N-type.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the N-type transistor is turned on under a high potential and turned off under a low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.
The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram, taking forward scan as an example. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.
Taking the shift register shown in fig. 3 as an example, in fig. 3, the third clock signal terminal is the same as the first clock signal terminal, the first switching transistor M1 is a P-type transistor, and the second switching transistor M2 through the tenth switching transistor M10 are all N-type transistors. The corresponding input/output timing sequence is shown in FIG. 4, and includes five stages T1-T5. In the period from T1 to T5, the signal of the first reference voltage terminal Vref1 is high, and the signals of the second reference voltage terminal Vref2 and the third reference voltage terminal Vref3 are low.
In stage T1, Input is 1, CK1 is 1, CK2 is 0, CK3 is 1, and Reset is 0.
Since Input is 1, the third switching transistor M3 is turned on, a high potential signal of the first reference signal terminal Vref1 is transmitted to the first node a through the third switching transistor M3, the potential of the first node a is high, the second capacitor C2 starts to be charged, the first switching transistor M1 is turned off, and the seventh switching transistor M7 and the ninth switching transistor M9 are turned on; since CK1 is equal to 1, the fifth switching transistor M5 is turned on, but since the seventh switching transistor M7 is turned on, a low potential signal of the third reference voltage terminal Vref3 is supplied to the second node B through the seventh switching transistor M7, the potential of the second node B is low, and the sixth switching transistor M6 and the tenth switching transistor M10 are turned off; since Reset is 0, the fourth switching transistor M4 is turned off; since the ninth switching transistor M9 is turned on and CK2 is equal to 0, the low-potential signal of the second clock signal terminal CK2 is Output to the gate signal Output terminal Output through the ninth switching transistor T9, and the potential of the gate signal Output terminal Output is low, the eighth switching transistor M8 is turned off; since CK3 is equal to 1 and the second switching transistor M2 is turned on, the low-potential signal of the third reference voltage terminal Vref3 is also Output to the gate signal Output terminal Output through the second switching transistor M2, thereby further ensuring that the potential of the gate signal Output terminal Output is low.
At this stage, when display and Touch driving are required to be simultaneously performed, as shown in a stage T1 shown in fig. 5, when all signals input into the shift register need to be synchronized with signals on the self-capacitance electrode, at this time, since signals of the gate signal Output terminal Output are provided by the second clock signal terminal CK2 and the third reference voltage terminal Vref3, signals of the gate signal Output terminal Output can be synchronized with signals on the self-capacitance electrode Touch, so that voltage differences between the gate line and the self-capacitance electrode Touch can be kept consistent, and accuracy of Touch control of the self-capacitance electrode Touch can be ensured.
In stage T2, Input is 0, CK1 is 0, CK2 is 1, CK3 is 0, and Reset is 0.
Since Input is 0, the third switching transistor M3 is turned off; since Reset is 0, the fourth switching transistor M4 is turned off; according to the bootstrap action of the second capacitor C2, the potential of the first node a is further pulled high, the first switching transistor M1 is turned off, the seventh switching transistor M7 and the ninth switching transistor M9 are turned on, and the second switching transistor M2 is turned off due to CK3 being 0; since CK1 is equal to 0, the fifth switching transistor M5 is turned off; however, since the seventh switching transistor M7 is turned on, the low potential signal of the third reference voltage terminal Vref3 is supplied to the second node B through the seventh switching transistor M7, the potential of the second node B is low, and the sixth switching transistor M6 and the tenth switching transistor M10 are turned off; since CK2 is equal to 1, the high potential signal of the second clock signal terminal CK2 is Output to the gate signal Output terminal Output through the ninth switching transistor M9, the potential of the gate signal Output terminal Output is high, the eighth switching transistor M8 is turned on, the low potential signal of the third reference voltage terminal Vref3 is provided to the second node B through the eighth switching transistor M8, and the potential of the second node B is further ensured to be low.
At this stage, when simultaneous driving of display and Touch is required, as shown in a stage T2 in fig. 5, when all signals input to the shift register need to be synchronized with signals on the self-capacitance electrode, at this time, since the signal of the gate signal Output terminal Output is provided by the second clock signal terminal CK2, the signal of the gate signal Output terminal Output can be synchronized with the signal on the self-capacitance electrode Touch, so that the voltage difference between the gate line and the self-capacitance electrode Touch can be kept consistent, and the accuracy of Touch on the self-capacitance electrode Touch can be ensured.
In stage T3, Input is 0, CK1 is 1, CK2 is 0, CK3 is 1, and Reset is 1.
Since Input is 0, the third switching transistor M3 is turned off; since Reset is 1, the fourth switching transistor T4 is turned on, a low-potential signal of the second reference voltage terminal Vref2 is transmitted to the first node a through the fourth switching transistor T4, so that the potential of the first node a becomes a low potential, the seventh switching transistor M7 and the ninth switching transistor M9 are turned off, and the first switching transistor M1 is turned on; since CK3 is equal to 1, the second switching transistor M2 is turned on; since CK1 is equal to 1, the fifth switching transistor M5 is turned on, the high potential signal of the first clock signal terminal CK1 is provided to the second node B through the fifth switching transistor M5, the potential of the second node B is high potential, the first capacitor C1 starts to charge, and the sixth switching transistor M6 and the tenth switching transistor M10 are turned on; since the first switching transistor M1, the second switching transistor M2 and the tenth switching transistor M10 are all turned on, a low-potential signal of the third reference voltage terminal Vref3 is provided to the gate signal Output terminal Output through the first switching transistor M1, the second switching transistor M2 and the tenth switching transistor M10, the potential of the gate signal Output terminal Output is still at a low potential, and the eighth switching transistor M8 is turned off.
At this stage, when simultaneous driving of display and Touch is required, as shown in a stage T3 in fig. 5, when all signals input to the shift register need to be synchronized with signals on the self-capacitance electrode, at this time, since the signal of the gate signal Output terminal Output is provided by the third reference voltage terminal Vref3, the signal of the gate signal Output terminal Output can be synchronized with the signal on the self-capacitance electrode Touch, so that the voltage difference between the gate line and the self-capacitance electrode Touch can be kept consistent, and the accuracy of Touch of the self-capacitance electrode Touch can be ensured.
In stage T4, Input is 0, CK1 is 0, CK2 is 1, and CK3 is 0, Reset is 0.
Since Input is 0, the third switching transistor M3 is turned off; since Reset is 0, the fourth switching transistor T4 is turned off; the potential of the first node a is still low, the seventh switching transistor M7 and the ninth switching transistor M9 are turned off, and the first switching transistor M1 is turned on; since CK1 is equal to 0, the fifth switching transistor M5 is turned off; the second node B is in a floating state, and due to the action of the first capacitor C1, the potential of the second node B is still at a high potential, and the sixth switching transistor M6 and the tenth switching transistor M10 are turned on; since CK3 is 0, the second switching transistor M2 is turned off; since the first switching transistor M1 and the tenth switching transistor M10 are both turned on, a low-potential signal of the third reference voltage terminal Vref3 is provided to the gate signal Output terminal Output through the first switching transistor M1 and the tenth switching transistor M10, the potential of the gate signal Output terminal Output is still at a low potential, and the eighth switching transistor M8 is turned off.
At this stage, if the first switch transistor M1 in the present invention is not provided, since the second node B is in a floating state at this stage, and the potential of the second node B is unstable, the tenth switch transistor M10 cannot be controlled to be in a conducting state, that is, the gate signal Output terminal Output of the shift register in this stage has no signal Output, in order to ensure that the gate signal Output terminal Output of the shift register in this stage has a signal Output, the first switch transistor M1 is added in the present invention, so that the first switch transistor M1 is in a conducting state under the control of the first node a, and a low potential signal of the third reference voltage terminal Vref3 is provided to the gate signal Output terminal Output through the first switch transistor M1.
At this stage, when simultaneous driving of display and Touch is required, as shown in a stage T4 in fig. 5, when all signals input to the shift register need to be synchronized with signals on the self-capacitance electrode, at this time, since the signal of the gate signal Output terminal Output is provided by the third reference voltage terminal Vref3, the signal of the gate signal Output terminal Output can be synchronized with the signal on the self-capacitance electrode Touch, so that the voltage difference between the gate line and the self-capacitance electrode Touch can be kept consistent, and the accuracy of Touch of the self-capacitance electrode Touch can be ensured.
In stage T5, Input is 0, CK1 is 1, CK2 is 0, CK3 is 1, and Reset is 0.
Since Input is 0, the third switching transistor M3 is turned off; since Reset is 0, the fourth switching transistor T4 is turned off; the potential of the first node a continues to be a low potential, the seventh switching transistor M7 and the ninth switching transistor M9 are turned off, and the first switching transistor M1 is turned on; since CK1 is equal to 1, the fifth switching transistor M5 is turned on; the high level signal of the first clock signal terminal CK1 is provided to the second node B through the fifth switching transistor M5, the second node B is high, the first capacitor C1 starts to charge, and the sixth switching transistor M6 and the tenth switching transistor M10 are turned on; since CK3 is equal to 1, the second switching transistor M2 is turned on; since the first switching transistor M1, the second switching transistor M2 and the tenth switching transistor M10 are all turned on, a low-potential signal of the third reference voltage terminal Vref3 is provided to the gate signal Output terminal Output through the first switching transistor M1, the second switching transistor M2 and the tenth switching transistor M10, the potential of the gate signal Output terminal Output is still at a low potential, and the eighth switching transistor M8 is turned off.
At this stage, when simultaneous driving of display and Touch is required, as shown in a stage T5 in fig. 5, when all signals input to the shift register need to be synchronized with signals on the self-capacitance electrode, at this time, since the signal of the gate signal Output terminal Output is provided by the third reference voltage terminal Vref3, the signal of the gate signal Output terminal Output can be synchronized with the signal on the self-capacitance electrode Touch, so that the voltage difference between the gate line and the self-capacitance electrode Touch can be kept consistent, and the accuracy of Touch of the self-capacitance electrode Touch can be ensured.
Thereafter, the stages T4 and T5 are repeated until the signal at the Input signal terminal Input of the next frame becomes high.
In summary, the shift register provided in the embodiments of the present invention not only can implement the function of normal Output of the existing shift register, but also can implement synchronization between the signal at the gate signal Output end Output and the signal at the self-capacitance electrode when the display and touch driving needs to be adopted and all the signals input to the shift register need to be synchronized with the signal at the self-capacitance electrode.
Based on the same inventive concept, the embodiment of the invention also provides a gate driving circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; except the first stage of shift register, the input signal end of each stage of shift register is connected with the grid signal output end of the adjacent previous stage of shift register; except the last stage of shift register, the reset signal end of each stage of shift register is connected with the grid signal output end of the next stage of shift register adjacent to the reset signal end of each stage of shift register.
Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises the gate driving circuit. The display panel may be: the display panel of any product with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display panel can refer to the embodiments of the gate driving circuit, and repeated descriptions are omitted.
In a specific implementation, the display panel provided in the embodiment of the present invention may be a liquid crystal display panel, or may also be an organic electroluminescent display panel, which is not limited herein.
The shift register, the gate driving circuit and the display panel provided by the embodiment of the invention comprise: the device comprises an input module, a reset module, a node control module, a first output module, a second output module and a first compensation module. The input module is used for providing a signal of a first reference voltage end to a first node under the control of an input signal end; the reset module is used for providing a signal of a second reference voltage end to the first node under the control of the reset signal end; the node control module is used for providing a first clock signal of the first clock signal end to a second node under the control of the first clock signal end and providing a signal of a third reference voltage end to the first node under the control of the second node; the first output module is used for providing a second clock signal of the second clock signal end to the grid signal output end of the shift register under the control of the first node; the second output module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the second node; the first compensation module is used for providing a signal of a third reference voltage end to a grid signal output end of the shift register under the control of the first clock signal end. According to the shift register, the first compensation module is added, when the second node is in a floating state, the first compensation module is used for providing a signal of the third reference voltage end for the grid signal output end of the shift register, and therefore the grid signal output end of the shift register is guaranteed to have signal output all the time, and therefore when all signals input into the shift register are synchronous with signals on the self-capacitance electrode, the signals of the grid signal output end and the signals on the self-capacitance electrode can be synchronous.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A shift register, comprising: the device comprises an input module, a reset module, a node control module, a first output module, a second output module and a first compensation module; wherein,
the input module is used for providing a signal of the first reference voltage end to a first node under the control of an input signal end;
the reset module is used for providing a signal of the second reference voltage end to the first node under the control of a reset signal end;
the node control module is used for providing a signal of a first clock signal end to a second node under the control of the first clock signal end and providing a signal of a third reference voltage end to the first node under the control of the second node;
the first output module is used for providing a signal of a second clock signal end to a grid signal output end of the shift register under the control of the first node;
the second output module is used for providing a signal of the third reference voltage end to a grid signal output end of the shift register under the control of the second node;
the first compensation module is used for providing a signal of the third reference voltage end to a grid signal output end of the shift register under the control of the first node.
2. The shift register of claim 1, wherein the first compensation module specifically comprises: a first switching transistor; wherein,
and the grid electrode of the first switch transistor is connected with the first node, the first pole of the first switch transistor is connected with the third reference voltage end, and the second pole of the first switch transistor is connected with the grid signal output end of the shift register.
3. The shift register of claim 1, further comprising: a second compensation module; wherein,
the second compensation module is used for providing a signal of the third reference voltage end to the grid signal output end of the shift register under the control of a third clock signal end.
4. The shift register of claim 3, wherein the second compensation module specifically comprises: a second switching transistor; wherein,
and the grid electrode of the second switching transistor is connected with the third clock signal end, the first pole of the second switching transistor is connected with the third reference voltage end, and the second pole of the second switching transistor is connected with the grid signal output end of the shift register.
5. The shift register according to any one of claims 1 to 4, wherein the input module specifically comprises: a third switching transistor; wherein,
and the grid electrode of the third switching transistor is connected with the input signal end, the first pole of the third switching transistor is connected with the first reference voltage end, and the second pole of the third switching transistor is connected with the first node.
6. The shift register according to any one of claims 1 to 4, wherein the reset module specifically comprises: a fourth switching transistor; wherein,
and the grid electrode of the fourth switching transistor is connected with the reset signal end, the first electrode of the fourth switching transistor is connected with the second reference voltage end, and the second electrode of the fourth switching transistor is connected with the first node.
7. The shift register according to any one of claims 1 to 4, wherein the node control module specifically comprises: a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, and a first capacitor; wherein,
a gate and a first pole of the fifth switching transistor are both connected to the first clock signal terminal, and a second pole of the fifth switching transistor is connected to the second node;
a gate of the sixth switching transistor is connected to the second node, a first pole of the sixth switching transistor is connected to the third reference voltage terminal, and a second pole of the sixth switching transistor is connected to the first node;
a gate of the seventh switching transistor is connected to the first node, a first pole of the seventh switching transistor is connected to the third reference voltage terminal, and a second pole of the seventh switching transistor is connected to the second node;
a gate of the eighth switching transistor is connected with a gate signal output end of the shift register, a first pole of the eighth switching transistor is connected with the third reference voltage end, and a second pole of the eighth switching transistor is connected with the second node;
the first capacitor is connected between the second node and the third reference voltage terminal.
8. The shift register according to any one of claims 1 to 4, wherein the first output module specifically comprises: a ninth switching transistor and a second capacitor; wherein,
a gate of the ninth switching transistor is connected to the first node, a first pole of the ninth switching transistor is connected to the second clock signal terminal, and a second pole of the ninth switching transistor is connected to a gate signal output terminal of the shift register;
the second capacitor is connected between the gate and the second pole of the ninth switching transistor.
9. The shift register according to any one of claims 1 to 4, wherein the second output module specifically comprises: a tenth switching transistor; wherein,
and the grid electrode of the tenth switching transistor is connected with the second node, the first pole of the tenth switching transistor is connected with the third reference voltage end, and the second pole of the tenth switching transistor is connected with the grid signal output end of the shift register.
10. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 9 in cascade; wherein,
except the first stage of shift register, the input signal end of each stage of shift register is connected with the grid signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is connected with the grid signal output end of the next stage of shift register adjacent to the reset signal end of each stage of shift register.
11. A display panel comprising the gate driver circuit according to claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710099409.7A CN106782413B (en) | 2017-02-23 | 2017-02-23 | Shift register, gate driving circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710099409.7A CN106782413B (en) | 2017-02-23 | 2017-02-23 | Shift register, gate driving circuit and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106782413A true CN106782413A (en) | 2017-05-31 |
| CN106782413B CN106782413B (en) | 2019-02-26 |
Family
ID=58959945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710099409.7A Active CN106782413B (en) | 2017-02-23 | 2017-02-23 | Shift register, gate driving circuit and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106782413B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154235A (en) * | 2017-07-21 | 2017-09-12 | 京东方科技集团股份有限公司 | Scan shift circuit, touch-control shift circuit, driving method and relevant apparatus |
| CN108288450A (en) * | 2018-02-06 | 2018-07-17 | 合肥京东方光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108877619A (en) * | 2018-06-22 | 2018-11-23 | 武汉华星光电半导体显示技术有限公司 | Show control circuit, the control method of equipment |
| CN111243650A (en) * | 2020-02-05 | 2020-06-05 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
| US11380374B2 (en) * | 2019-07-02 | 2022-07-05 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632564A (en) * | 2016-01-08 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register, grid integrated drive circuit and display device |
| CN105869562A (en) * | 2016-05-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display panel |
| US20160266699A1 (en) * | 2014-05-30 | 2016-09-15 | Boe Technology Group Co., Ltd. | Shift register, gate integrated driving circuit and display screen |
-
2017
- 2017-02-23 CN CN201710099409.7A patent/CN106782413B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160266699A1 (en) * | 2014-05-30 | 2016-09-15 | Boe Technology Group Co., Ltd. | Shift register, gate integrated driving circuit and display screen |
| CN105632564A (en) * | 2016-01-08 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register, grid integrated drive circuit and display device |
| CN105869562A (en) * | 2016-05-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display panel |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154235A (en) * | 2017-07-21 | 2017-09-12 | 京东方科技集团股份有限公司 | Scan shift circuit, touch-control shift circuit, driving method and relevant apparatus |
| US11307707B2 (en) | 2017-07-21 | 2022-04-19 | Boe Technology Group Co., Ltd. | Scan shift circuit, touch shift circuit, driving method and related apparatus |
| CN108288450A (en) * | 2018-02-06 | 2018-07-17 | 合肥京东方光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108288450B (en) * | 2018-02-06 | 2021-04-27 | 合肥京东方光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108877619A (en) * | 2018-06-22 | 2018-11-23 | 武汉华星光电半导体显示技术有限公司 | Show control circuit, the control method of equipment |
| CN108877619B (en) * | 2018-06-22 | 2021-06-01 | 武汉华星光电半导体显示技术有限公司 | Control circuit and control method of display device |
| US11380374B2 (en) * | 2019-07-02 | 2022-07-05 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, and device |
| US20230352063A1 (en) * | 2019-07-02 | 2023-11-02 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, and device |
| US11961582B2 (en) * | 2019-07-02 | 2024-04-16 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, and device |
| CN111243650A (en) * | 2020-02-05 | 2020-06-05 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106782413B (en) | 2019-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9747854B2 (en) | Shift register, gate driving circuit, method for driving display panel and display device | |
| CN105096889B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN105427825B (en) | A kind of shift register, its driving method and gate driving circuit | |
| CN105469738B (en) | A kind of shift register, gate driving circuit and display device | |
| US9530521B2 (en) | Shift register unit, gate driving circuit, and display device | |
| US9847067B2 (en) | Shift register, gate driving circuit, display panel, driving method thereof and display device | |
| US9378696B2 (en) | Shift register unit and driving method, shift register circuit and display apparatus | |
| CN106098101B (en) | A kind of shift register, gate driving circuit and display device | |
| CN105741744B (en) | A kind of shift register cell, gate driving circuit and display device | |
| CN106782413B (en) | Shift register, gate driving circuit and display panel | |
| WO2017118014A1 (en) | Shift register unit, gate drive circuit and display device | |
| CN106887216B (en) | The driving method of gate driving circuit, display panel and gate driving circuit | |
| CN105551422B (en) | A kind of shift register, gate driving circuit and display panel | |
| CN107633831B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| CN106504692B (en) | Shifting register, driving method thereof, grid driving circuit and display device | |
| CN107093414B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN105632444A (en) | Shift register, gate drive circuit and display panel | |
| CN105632562A (en) | Shifting register, grid drive circuit, display panel and display device | |
| CN107123390A (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN109166542B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN107633799A (en) | A kind of shift register, gate driving circuit and display device | |
| CN107068083B (en) | Grid line integrated drive electronics, display panel and display device | |
| CN107492338A (en) | A kind of gate driving circuit and display device | |
| CN106782399A (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN104934071B (en) | A kind of shift register, gate driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |