CN106782413B - Shift register, gate driving circuit and display panel - Google Patents
Shift register, gate driving circuit and display panel Download PDFInfo
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- CN106782413B CN106782413B CN201710099409.7A CN201710099409A CN106782413B CN 106782413 B CN106782413 B CN 106782413B CN 201710099409 A CN201710099409 A CN 201710099409A CN 106782413 B CN106782413 B CN 106782413B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a kind of shift register, gate driving circuit and display panel, shift register includes: input module, reseting module, node control module, the first output module, the second output module and the first compensating module.The shift register is by increasing by the first compensating module, when second node is when floating, the signal of third reference voltage end is supplied to the grid signal output end of shift register using the first compensating module, guarantee that the grid signal output end of shift register has signal output always, to which when all signals of input shift register are synchronous with the signal in self-capacitance electrode, the signal that grid signal output end may be implemented is synchronous with the signal in self-capacitance electrode.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift registers, gate driving circuit and display panel.
Background technique
In TFT thin film transistor monitor, usually pass through each thin film transistor (TFT) of the gate drive apparatus to pixel region
The grid of (TFT, Thin Film Transistor) provides gate drive signal.Gate drive apparatus can pass through array processes
It being formed in the array substrate of liquid crystal display, i.e., array substrate row drives (Gate Driver on Array, GOA) technique,
This integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in the both sides liquid crystal display panel (Panel), together
When, it also eliminates the binding region (Bonding) of grid integrated circuits (IC, Integrated Circuit) and is fanned out to
(Fan-out) wiring space, so as to realize the design of narrow frame；Also, this integrated technique may be omitted with grid
The Bonding technique of scanning line direction, to improve production capacity and yield.
And in embedded self-tolerant touch screen, when touch-control progress synchronous with display, in order to guarantee the touching of self-capacitance electrode
It is interference-free to control signal, needs to make the other signals in touch screen synchronous with the signal in self-capacitance electrode.But it is existing
Gate driving circuit, since output ends at different levels are in floating, even if input gate driving whithin a period of time
All signals of circuit are synchronous with the signal in self-capacitance electrode, can not also make on the signal and self-capacitance electrode on grid line
Signal is synchronous.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of shift register, gate driving circuit and display panel, work as touch-control
When progress synchronous with display, the signal synchronous with the signal in self-capacitance electrode can be exported to grid line.
Therefore, the embodiment of the invention provides a kind of shift registers, comprising: input module, reseting module, node control
Module, the first output module, the second output module and the first compensating module；Wherein,
The signal of first reference voltage end for being supplied to by the input module under the control at input signal end
First node；
The signal of second reference voltage end for being supplied to by the reseting module under the control at reset signal end
The first node；
The node control module is used for the letter of first clock signal terminal under the control of the first clock signal terminal
Number it is supplied to second node, the signal of the third reference voltage end is supplied to described under the control of the second node
One node；
First output module is used under the control of the first node, and the signal of second clock signal end is provided
To the grid signal output end of the shift register；
Second output module is used under the control of the second node, by the signal of the third reference voltage end
It is supplied to the grid signal output end of the shift register；
First compensating module is used under the control of the first node, by the letter of the third reference voltage end
Number it is supplied to the grid signal output end of the shift register.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, first compensation
Module specifically includes: first switch transistor；Wherein,
The first switch transistor, grid are connected with the first node, the first pole and the third reference voltage
End is connected, and the second pole is connected with the grid signal output end of the shift register.
Preferably, in shift register provided in an embodiment of the present invention, further includes: the second compensating module；Wherein,
Second compensating module is used under the control of third clock signal terminal, by the letter of the third reference voltage end
Number it is supplied to the grid signal output end of the shift register.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, second compensation
Module specifically includes: second switch transistor；Wherein,
The second switch transistor, grid are connected with the third clock signal terminal, and the first pole and the third are joined
It examines voltage end to be connected, the second pole is connected with the grid signal output end of the shift register.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, the input module
It specifically includes: third switching transistor；Wherein,
The third switching transistor, grid are connected with the input signal end, and the first pole and described first is with reference to electricity
Pressure side is connected, and the second pole is connected with the first node.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, the reseting module
It specifically includes: the 4th switching transistor；Wherein,
4th switching transistor, grid are connected with the reset signal end, and the first pole and described second is with reference to electricity
Pressure side is connected, and the second pole is connected with the first node.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, the node control
Module specifically includes: the 5th switching transistor, the 6th switching transistor, the 7th switching transistor, the 8th switching transistor and
One capacitor；Wherein,
5th switching transistor, grid and first are extremely connected with first clock signal terminal, the second pole with
The second node is connected；
6th switching transistor, grid are connected with the second node, the first pole and the third reference voltage
End is connected, and the second pole is connected with the first node；
7th switching transistor, grid are connected with the first node, the first pole and the third reference voltage
End is connected, and the second pole is connected with the second node；
8th switching transistor, grid are connected with the grid signal output end of the shift register, the first pole
It is connected with the third reference voltage end, the second pole is connected with the second node；
The first capacitor is connected between the second node and the third reference voltage end.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, first output
Module specifically includes: the 9th switching transistor and the second capacitor；Wherein,
9th switching transistor, grid are connected with the first node, the first pole and the second clock signal
End is connected, and the second pole is connected with the grid signal output end of the shift register；
Second capacitance connection is between the grid and the second pole of the 9th switching transistor.
In a kind of possible embodiment, in shift register provided in an embodiment of the present invention, second output
Module specifically includes: the tenth switching transistor；Wherein,
Tenth switching transistor, grid are connected with the second node, the first pole and the third reference voltage
End is connected, and the second pole is connected with the grid signal output end of the shift register.
Correspondingly, the embodiment of the invention also provides a kind of gate driving circuits, including cascade multiple present invention to implement
The shift register that example provides；Wherein,
In addition to first order shift register, the input signal end of every level-one shift register upper level adjacent thereto is moved
The grid signal output end of bit register is connected；
In addition to afterbody shift register, the reset signal end of every level-one shift register next stage adjacent thereto
The grid signal output end of shift register is connected.
Correspondingly, the embodiment of the invention also provides a kind of display panels, including grid provided in an embodiment of the present invention to drive
Dynamic circuit.
The present invention has the beneficial effect that:
A kind of shift register, gate driving circuit and display panel provided in an embodiment of the present invention, shift register packet
It includes: input module, reseting module, node control module, the first output module, the second output module and the first compensating module.
Input module is for being supplied to first node for the signal of the first reference voltage end under the control at input signal end；Reseting module
For the signal of the second reference voltage end to be supplied to first node under the control at reset signal end；Node control module is used for
The first clock signal of the first clock signal terminal is supplied to second node under the control of the first clock signal terminal, in the second section
The signal of third reference voltage end is supplied to the first node under the control of point；First output module is used in first node
Control under, the second clock signal of second clock signal end is supplied to the grid signal output end of shift register；Second
Output module is used under the control of second node, and the grid that the signal of third reference voltage end is supplied to shift register is believed
Number output end；First compensating module is used under the control of the first clock signal terminal, and the signal of third reference voltage end is provided
To the grid signal output end of shift register.The shift register is by increasing by the first compensating module, when second node is in floating
When connecing state, the grid signal that the signal of third reference voltage end is supplied to shift register is exported using the first compensating module
End, guarantees that the grid signal output end of shift register has signal output always, to work as all letters of input shift register
When number synchronous with the signal in self-capacitance electrode, the letter on the signal and self-capacitance electrode of grid signal output end may be implemented
Number synchronization.
Detailed description of the invention
Fig. 1 is one of the structural schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 2 is the second structural representation of shift register provided in an embodiment of the present invention；
Fig. 3 is the third structural representation of shift register provided in an embodiment of the present invention；
Fig. 4 is a kind of corresponding input and output sequential chart of shift register shown in Fig. 3；
Fig. 5 is the corresponding another input and output sequential chart of shift register shown in Fig. 3.
Specific embodiment
With reference to the accompanying drawing, to shift register provided in an embodiment of the present invention, gate driving circuit and display panel
Specific embodiment is described in detail.
A kind of shift register provided in an embodiment of the present invention, as shown in Figure 1, comprising: input module 1, reseting module 2,
Node control module 3, the first output module 4, the second output module 5 and the first compensating module 6；Wherein,
Input module 1 is for providing the signal of the first reference voltage end Vref1 under the control of input signal end Input
Give first node A；
Reseting module 2 is for providing the signal of the second reference voltage end Vref2 under the control of reset signal end Reset
Give second node B；
Node control module 3 is used for the signal of the first clock signal terminal CK1 under the control of the first clock signal terminal CK1
It is supplied to second node B, the signal of third reference voltage end Vref3 is supplied to first node under the control of second node B
A；
First output module 4 is used under the control of first node A, and the signal of second clock signal end CK2 is supplied to
The grid signal output end Output of shift register；
Second output module 5 is used under the control of second node B, and the signal of third reference voltage end Vref3 is provided
To the grid signal output end Output of shift register；
First compensating module 6 is used under the control of first node A, and the signal of third reference voltage end Vref3 is provided
To the grid signal output end Output of shift register.
A kind of shift register provided in an embodiment of the present invention, shift register include: input module, reseting module, section
Point control module, the first output module, the second output module and the first compensating module.Input module is used at input signal end
Control under the signal of the first reference voltage end is supplied to first node；Reseting module is used under the control at reset signal end
The signal of second reference voltage end is supplied to first node；Node control module is used under the control of the first clock signal terminal
First clock signal of the first clock signal terminal is supplied to second node, by third reference voltage under the control of second node
The signal at end is supplied to the first node；First output module is used under the control of first node, by second clock signal
The second clock signal at end is supplied to the grid signal output end of shift register；Second output module is used in second node
Under control, the signal of third reference voltage end is supplied to the grid signal output end of shift register；First compensating module is used
Under the control in the first clock signal terminal, the grid signal that the signal of third reference voltage end is supplied to shift register is defeated
Outlet.The shift register is by increasing by the first compensating module, when second node is when floating, utilizes the first compensating module
The signal of third reference voltage end is supplied to the grid signal output end of shift register, guarantees the grid letter of shift register
Number output end has signal output always, so that all signals when input shift register are same with the signal in self-capacitance electrode
When step, the signal that grid signal output end may be implemented is synchronous with the signal in self-capacitance electrode.
In the specific implementation, in shift register provided in an embodiment of the present invention, the signal of the first clock signal terminal with
The signal phase of second clock signal end is opposite.
Combined with specific embodiments below, the present invention is described in detail.It should be noted that the present embodiment is in order to more
The good explanation present invention, but do not limit the present invention.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the first compensation
Module 6 specifically includes: first switch transistor M1；Wherein,
First switch transistor M1, grid are connected with first node A, the first pole and third reference voltage end Vref3 phase
Even, the second pole is connected with the grid signal output end Output of shift register.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, third clock signal terminal CK3 can
Using with the first clock signal terminal CK1 as the same end, can also with second clock signal end CK2 be the same end；And when third
The type of first switch transistor M1 when clock signal end CK3 is identical as the first clock signal terminal CK1 with work as third clock signal
The type of first switch transistor M1 when holding CK3 identical as second clock signal end CK2 is opposite.
The above is only the specific structures for illustrating the first compensating module in shift register, in the specific implementation, first
The specific structure of compensating module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, be not limited thereto.
In the specific implementation, in order to further ensure the grid signal output end of shift register has signal output always,
To which it is defeated that grid signal may be implemented when all signals of input shift register are synchronous with the signal in self-capacitance electrode
The signal of outlet is synchronous with the signal in self-capacitance electrode, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2
It is shown, further includes: the second compensating module 7；Wherein,
Second compensating module 7 is used under the control of third clock signal terminal CK3, by third reference voltage end Vref3's
Signal is supplied to the grid signal output end Output of shift register.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the second compensation
Module 7 specifically includes: second switch transistor M2；Wherein,
Second switch transistor M2, grid are connected with third clock signal terminal CK3, the first pole and third reference voltage end
Vref3 is connected, and the second pole is connected with the grid signal output end Output of shift register.
The above is only the specific structures for illustrating the second compensating module in shift register, in the specific implementation, second
The specific structure of compensating module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, be not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, input module 1
It specifically includes: third switching transistor M3；Wherein,
Third switching transistor M3, grid are connected with input signal end Input, the first pole and the first reference voltage end
Vref1 is connected, and the second pole is connected with first node A.
The above is only the specific structures for illustrating input module in shift register, in the specific implementation, input module
Specific structure be not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot
Structure is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3,2 reseting modules
It specifically includes: the 4th switching transistor M4；Wherein,
4th switching transistor M4, grid are connected with reset signal end Reset, the first pole and the second reference voltage end
Vref2 is connected, and the second pole is connected with first node A.
The above is only the specific structures for illustrating reseting module in shift register, in the specific implementation, reseting module
Specific structure be not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot
Structure is not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3,3 node controls
Module specifically includes: the 5th switching transistor M5, the 6th switching transistor M6, the 7th switching transistor M7, the 8th switch crystal
Pipe M8 and first capacitor C1；Wherein,
5th switching transistor M5, grid and first are extremely connected with the first clock signal terminal CK1, the second pole and second
Node B is connected；
6th switching transistor M6, grid are connected with second node B, the first pole and third reference voltage end Vref3 phase
Even, the second pole is connected with first node A；
7th switching transistor M7, grid are connected with first node A, the first pole and third reference voltage end Vref3 phase
Even, the second pole is connected with second node B；
8th switching transistor M8, grid are connected with the grid signal output end Output of shift register, the first pole
It is connected with third reference voltage end Vref3, the second pole is connected with second node B；
First capacitor C1 is connected between second node B and third reference voltage end Vref3.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, generally when prepared by technique the
The size of the 5th switching transistor of ratio of the size setting of seven switching transistors is big, and setting is so that work as the current potential of first node in this way
When for high potential, the signal of third reference voltage end is supplied to by the 7th switching transistor under the control of the signal of first node
The rate of second node is greater than the 5th switching transistor under the control of the first clock signal terminal for the letter of the first clock signal terminal
Number it is supplied to the rate of second node, to guarantee that the current potential of second node is low potential.
The above is only the specific structures for illustrating shift register interior joint control module, in the specific implementation, node
The specific structure of control module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, be not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the first output
Module 4 specifically includes: the 9th switching transistor M9 and the second capacitor C2；Wherein,
9th switching transistor M9, grid are connected with first node A, and the first pole is connected with second clock signal end CK2,
Second pole is connected with the grid signal output end Output of shift register；
Second capacitor C2 is connected between the grid and the second pole of the 9th switching transistor M9.
The above is only the specific structures for illustrating the first output module in shift register, in the specific implementation, first
The specific structure of output module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, be not limited thereto.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the second output
Module 5 specifically includes: the tenth switching transistor M10；Wherein,
Tenth switching transistor M10, grid are connected with second node B, the first pole and third reference voltage end Vref3 phase
Even, the second pole is connected with the grid signal output end Output of shift register.
The above is only the specific structures for illustrating the second output module in shift register, in the specific implementation, second
The specific structure of output module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, be not limited thereto.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (TFT,
Thin Film Transistor), it is also possible to metal oxide semiconductor field effect tube (MOS, Metal Oxide
Scmiconductor), it is not limited thereto.
In the specific implementation, the first of the switching transistor mentioned in the above embodiment of the present invention extremely can be source electrode, the
Two extremely drain or first extremely can be drain electrode, and the second extremely source electrode is not distinguished specifically herein.
Further, due in above-mentioned shift register provided in an embodiment of the present invention, input module and reseting module
For symmetric design, may be implemented exchange function, thus above-mentioned shift register provided in an embodiment of the present invention may be implemented it is two-way
Scanning.In forward scan, input signal end receives input signal, and reset signal end receives reset signal, input module is made
For the function of input, reseting module is as the function of resetting.In reverse scan, input signal end receives reset signal, resets
Signal end receives input signal, and by reseting module function as input, input module is as the function of resetting.
In the specific implementation, effective when input signal end in above-mentioned shift register provided in an embodiment of the present invention
When pulse signal is high potential signal, third switching transistor M3 to the tenth switching transistor M10 is N-type, and first switch is brilliant
Body pipe M1 is p-type.Wherein, in forward scan, the current potential of the first reference voltage end is high potential, the second reference voltage end and the
The current potential of three reference voltage ends is low potential；In reverse scan, the current potential of the second reference voltage end is high potential, the first ginseng
The current potential for examining voltage end and third reference voltage end is low potential.
Further, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, when third clock
When signal end is identical as the first clock signal terminal, second switch transistor M2 is N-type；When third clock signal terminal and second clock
When signal end is identical, second switch transistor M2 is p-type.
In the specific implementation, effective when input signal end in above-mentioned shift register provided in an embodiment of the present invention
When pulse signal is low-potential signal, third switching transistor M3 to the tenth switching transistor M10 is p-type, and first switch is brilliant
Body pipe M1 is p-type.Wherein, in forward scan, the current potential of the first reference voltage end is low potential, the second reference voltage end and the
The current potential of three reference voltage ends is high potential；In reverse scan, the current potential of the second reference voltage end is low potential, the first ginseng
The current potential for examining voltage end and third reference voltage end is high potential.
Further, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, when third clock
When signal end is identical as the first clock signal terminal, second switch transistor M2 is p-type；When third clock signal terminal and second clock
When signal end is identical, second switch transistor M2 is N-type.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, N-type transistor is made in high potential
With lower conducting, end under low potential effect；P-type transistor ends under high potential effect, is connected under low potential effect.
Below with reference to circuit timing diagram, to above-mentioned shift register provided in an embodiment of the present invention by taking forward scan as an example
The course of work is described.High potential signal is indicated with 1 in described below, and 0 indicates low-potential signal.
By taking shift register shown in Fig. 3 as an example, wherein in Fig. 3, third clock signal terminal and the first clock signal terminal
Identical, first switch transistor M1 is P-type transistor, and second switch transistor M2 to the tenth switching transistor M10 is N-type crystalline substance
Body pipe.Corresponding input and output timing is as shown in figure 4, include five stages of T1-T5.Wherein in the T1-T5 stage, first with reference to electricity
The signal of pressure side Vref1 is high potential signal, and the signal of the second reference voltage end Vref2 and third reference voltage end Vref3 are
Low-potential signal.
In the T1 stage, Input=1, CK1=1, CK2=0, CK3=1, Reset=0.
Since Input=1, third switching transistor M3 are connected, the high potential signal of the first reference signal end Vref1 passes through
Third switching transistor M3 is transmitted to first node A, and the current potential of first node A is high potential, and the second capacitor C2 is started to charge, the
One switching transistor M1 cut-off, the 7th switching transistor M7 and the 9th switching transistor M9 conducting；Due to CK1=1, the 5th switch
Transistor M5 conducting, but since the 7th switching transistor M7 is connected, the low-potential signal of third reference voltage end Vref3 passes through
7th switching transistor M7 is supplied to second node B, and the current potential of second node B is low potential, the 6th switching transistor M6 and the
Ten switching transistor M10 cut-off；Since Reset=0, the 4th switching transistor M4 end；Since the 9th switching transistor M9 is led
It is logical, and the low-potential signal of CK2=0, second clock signal end CK2 exported by the 9th switching transistor T9 it is defeated to grid signal
The current potential of outlet Output, grid signal output end Output are low potential, then the 8th switching transistor M8 ends；And due to
CK3=1, second switch transistor M2 conducting, therefore the low-potential signal of third reference voltage end Vref3 passes through second switch crystalline substance
Body pipe M2, which is also exported, gives grid signal output end Output, is further ensured that the current potential of grid signal output end Output is low electricity
Position.
In this stage, when needing to drive simultaneously using display with touch-control, T1 stage as shown in Figure 5, input displacement is posted
When all signals of storage are required to synchronous with the signal in self-capacitance electrode, at this time due to grid signal output end Output's
Signal is provided by second clock signal end CK2 and third reference voltage end Vref3, therefore grid signal output end Output
Signal may be implemented synchronous with the signal on self-capacitance electrode Touch, grid line and self-capacitance electrode Touch may be implemented in this way
Between voltage difference be consistent, so as to ensure the accuracy of self-capacitance electrode Touch touch-control.
In the T2 stage, Input=0, CK1=0, CK2=1, CK3=0, Reset=0.
Since Input=0, third switching transistor M3 end；Since Reset=0, the 4th switching transistor M4 end；
According to the boot strap of the second capacitor C2, the current potential of first node A is further pulled up, first switch transistor M1 cut-off, the
Seven switching transistor M7 and the 9th switching transistor M9 conducting, since CK3=0, second switch transistor M2 end；Due to CK1
=0, the 5th switching transistor M5 cut-off；But since the 7th switching transistor M7 is connected, third reference voltage end Vref3's is low
Electric potential signal is supplied to second node B by the 7th switching transistor M7, and the current potential of second node B is low potential, the 6th switch
Transistor M6 and the tenth switching transistor M10 cut-off；Due to CK2=1, the high potential signal of second clock signal end CK2 passes through
9th switching transistor M9, which is exported, gives grid signal output end Output, and the current potential of grid signal output end Output is high electricity
Position, the 8th switching transistor M8 conducting, the low-potential signal of third reference voltage end Vref3 are mentioned by the 8th switching transistor M8
Second node B is supplied, is further ensured that the current potential of second node B is low potential.
In this stage, when needing to drive simultaneously using display with touch-control, T2 stage as shown in Figure 5, input displacement is posted
When all signals of storage are required to synchronous with the signal in self-capacitance electrode, at this time due to grid signal output end Output's
Signal is to be provided by second clock signal end CK2, therefore the signal of grid signal output end Output may be implemented and electricity certainly
The signal held on electrode Touch is synchronous, and the voltage difference that may be implemented between grid line and self-capacitance electrode Touch in this way keeps one
It causes, so as to ensure the accuracy of self-capacitance electrode Touch touch-control.
In the T3 stage, Input=0, CK1=1, CK2=0, CK3=1, Reset=1.
Since Input=0, third switching transistor M3 end；Since Reset=1, the 4th switching transistor T4 are connected,
The low-potential signal of second reference voltage end Vref2 is transferred to first node A, therefore first segment by the 4th switching transistor T4
The current potential of point A becomes low potential, and the 7th switching transistor M7 and the 9th switching transistor M9 cut-off, first switch transistor M1 are led
It is logical；Since CK3=1, second switch transistor M2 are connected；Since CK1=1, the 5th switching transistor M5 are connected, the first clock letter
The high potential signal of number end CK1 is supplied to second node B by the 5th switching transistor M5, and the current potential of second node B is high electric
Position, first capacitor C1 are started to charge, the 6th switching transistor M6 and the tenth switching transistor M10 conducting；Due to first switch crystalline substance
Body pipe M1, second switch transistor M2 and the tenth switching transistor M10 are both turned on, the low potential of third reference voltage end Vref3
It is defeated that signal by first switch transistor M1, second switch transistor M2 and the tenth switching transistor M10 is supplied to grid signal
Outlet Output, the current potential of grid signal output end Output are still low potential, the 8th switching transistor M8 cut-off.
In this stage, when needing to drive simultaneously using display with touch-control, T3 stage as shown in Figure 5, input displacement is posted
When all signals of storage are required to synchronous with the signal in self-capacitance electrode, at this time due to grid signal output end Output's
Signal is to be provided by third reference voltage end Vref3, therefore the signal of grid signal output end Output may be implemented and oneself
Signal on capacitance electrode Touch is synchronous, and the voltage difference that may be implemented between grid line and self-capacitance electrode Touch in this way keeps one
It causes, so as to ensure the accuracy of self-capacitance electrode Touch touch-control.
In the T4 stage, Input=0, CK1=0, CK2=1, due to CK3=0, Reset=0.
Since Input=0, third switching transistor M3 end；Since Reset=0, the 4th switching transistor T4 end；
The current potential of first node A is still low potential, the 7th switching transistor M7 and the 9th switching transistor M9 cut-off, first switch crystal
Pipe M1 conducting；Since CK1=0, the 5th switching transistor M5 end；Second node B is in floating, due to first capacitor C1
Effect, the current potential of second node B is still high potential, the 6th switching transistor M6 and the tenth switching transistor M10 conducting；Due to
CK3=0, second switch transistor M2 cut-off；Since first switch transistor M1 and the tenth switching transistor M10 are both turned on, the
The low-potential signal of three reference voltage end Vref3 is supplied to grid by first switch transistor M1 and the tenth switching transistor M10
Pole signal output end Output, the current potential of grid signal output end Output are still low potential, the 8th switching transistor M8 cut-off.
In this stage, if without the first switch transistor M1 in the present invention, since second node B is at this stage
Floating, the current potential of second node B is unstable, therefore it is in the conductive state not can control the tenth switching transistor M10, i.e.,
The grid signal output end Output of the stage shift register does not have signal output, in order to guarantee the stage shift register
Grid signal output end Output has signal output, passes through in the present invention and increases first switch transistor M1, in this way in first segment
Under the control of point A, first switch transistor M1 is in the conductive state, then the low-potential signal of third reference voltage end Vref3 is logical
It crosses first switch transistor M1 and is supplied to grid signal output end Output.
In this stage, when needing to drive simultaneously using display with touch-control, T4 stage as shown in Figure 5, input displacement is posted
When all signals of storage are required to synchronous with the signal in self-capacitance electrode, at this time due to grid signal output end Output's
Signal is to be provided by third reference voltage end Vref3, therefore the signal of grid signal output end Output may be implemented and oneself
Signal on capacitance electrode Touch is synchronous, and the voltage difference that may be implemented between grid line and self-capacitance electrode Touch in this way keeps one
It causes, so as to ensure the accuracy of self-capacitance electrode Touch touch-control.
In the T5 stage, Input=0, CK1=1, CK2=0, CK3=1, Reset=0.
Since Input=0, third switching transistor M3 end；Since Reset=0, the 4th switching transistor T4 end；
The current potential of first node A continues as low potential, and the 7th switching transistor M7 and the 9th switching transistor M9 cut-off, first switch are brilliant
Body pipe M1 conducting；Since CK1=1, the 5th switching transistor M5 are connected；The high potential signal of first clock signal terminal CK1 passes through
5th switching transistor M5 is supplied to second node B, and second node B is high potential, and first capacitor C1 is started to charge, the 6th switch
Transistor M6 and the tenth switching transistor M10 conducting；Since CK3=1, second switch transistor M2 are connected；Due to first switch
Transistor M1, second switch transistor M2 and the tenth switching transistor M10 are both turned on, the low electricity of third reference voltage end Vref3
Position signal is supplied to grid signal by first switch transistor M1, second switch transistor M2 and the tenth switching transistor M10
Output end Output, the current potential of grid signal output end Output are still low potential, the 8th switching transistor M8 cut-off.
In this stage, when needing to drive simultaneously using display with touch-control, T5 stage as shown in Figure 5, input displacement is posted
When all signals of storage are required to synchronous with the signal in self-capacitance electrode, at this time due to grid signal output end Output's
Signal is to be provided by third reference voltage end Vref3, therefore the signal of grid signal output end Output may be implemented and oneself
Signal on capacitance electrode Touch is synchronous, and the voltage difference that may be implemented between grid line and self-capacitance electrode Touch in this way keeps one
It causes, so as to ensure the accuracy of self-capacitance electrode Touch touch-control.
T4 stage and T5 stage are repeated always later, until the signal of next frame input signal end Input becomes high potential
Until.
In conclusion existing shift register not only may be implemented in above-mentioned shift register provided in an embodiment of the present invention
The function of normally exporting, and when needing to drive simultaneously using display with touch-control, all signals of input shift register are equal
When needing synchronous with the signal in self-capacitance electrode, the signal of grid signal output end Output also be may be implemented and self-capacitance electricity
Signal on extremely is synchronous.
Based on the same inventive concept, the embodiment of the invention also provides a kind of gate driving circuit, including it is cascade multiple
Shift register provided in an embodiment of the present invention；Wherein, in addition to first order shift register, every level-one shift register it is defeated
The grid signal output end for entering signal end upper level shift register adjacent thereto is connected；Except afterbody shift register it
Outside, the grid signal output end phase of the reset signal end of every level-one shift register next stage shift register adjacent thereto
Even.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display panels, including above-mentioned gate driving
Circuit.The display panel can be with are as follows: mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator
Etc. the display panel of any product having a display function.The implementation of the display panel may refer to above-mentioned gate driving circuit
Embodiment, overlaps will not be repeated.
In the specific implementation, above-mentioned display panel provided in an embodiment of the present invention can be liquid crystal display panel, can also be with
It is organic electroluminescent display panel, is not limited thereto.
A kind of shift register, gate driving circuit and display panel provided in an embodiment of the present invention, shift register packet
It includes: input module, reseting module, node control module, the first output module, the second output module and the first compensating module.
Input module is for being supplied to first node for the signal of the first reference voltage end under the control at input signal end；Reseting module
For the signal of the second reference voltage end to be supplied to first node under the control at reset signal end；Node control module is used for
The first clock signal of the first clock signal terminal is supplied to second node under the control of the first clock signal terminal, in the second section
The signal of third reference voltage end is supplied to the first node under the control of point；First output module is used in first node
Control under, the second clock signal of second clock signal end is supplied to the grid signal output end of shift register；Second
Output module is used under the control of second node, and the grid that the signal of third reference voltage end is supplied to shift register is believed
Number output end；First compensating module is used under the control of the first clock signal terminal, and the signal of third reference voltage end is provided
To the grid signal output end of shift register.The shift register is by increasing by the first compensating module, when second node is in floating
When connecing state, the grid signal that the signal of third reference voltage end is supplied to shift register is exported using the first compensating module
End, guarantees that the grid signal output end of shift register has signal output always, to work as all letters of input shift register
When number synchronous with the signal in self-capacitance electrode, the letter on the signal and self-capacitance electrode of grid signal output end may be implemented
Number synchronization.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (11)
1. a kind of shift register characterized by comprising input module, reseting module, node control module, the first output
Module, the second output module and the first compensating module；Wherein,
The input module is for being supplied to first node for the signal of the first reference voltage end under the control at input signal end；
The reseting module is for being supplied to described first for the signal of the second reference voltage end under the control at reset signal end
Node；
The node control module is for mentioning the signal of first clock signal terminal under the control of the first clock signal terminal
Second node is supplied, the signal of third reference voltage end is supplied to the first node under the control of the second node；
First output module is used under the control of the first node, and the signal of second clock signal end is supplied to institute
State the grid signal output end of shift register；
Second output module is used under the control of the second node, and the signal of the third reference voltage end is provided
To the grid signal output end of the shift register；
First compensating module is used under the control of the first node, and the signal of the third reference voltage end is provided
To the grid signal output end of the shift register.
2. shift register as described in claim 1, which is characterized in that first compensating module specifically includes: first opens
Close transistor；Wherein,
The first switch transistor, grid are connected with the first node, the first pole and the third reference voltage end phase
Even, the second pole is connected with the grid signal output end of the shift register.
3. shift register as described in claim 1, which is characterized in that further include: the second compensating module；Wherein,
Second compensating module is used under the control of third clock signal terminal, and the signal of the third reference voltage end is mentioned
Supply the grid signal output end of the shift register.
4. shift register as claimed in claim 3, which is characterized in that second compensating module specifically includes: second opens
Close transistor；Wherein,
The second switch transistor, grid are connected with the third clock signal terminal, and the first pole and the third are with reference to electricity
Pressure side is connected, and the second pole is connected with the grid signal output end of the shift register.
5. shift register according to any one of claims 1-4, which is characterized in that the input module specifically includes: the
Three switching transistors；Wherein,
The third switching transistor, grid are connected with the input signal end, the first pole and first reference voltage end
It is connected, the second pole is connected with the first node.
6. shift register according to any one of claims 1-4, which is characterized in that the reseting module specifically includes: the
Four switching transistors；Wherein,
4th switching transistor, grid are connected with the reset signal end, the first pole and second reference voltage end
It is connected, the second pole is connected with the first node.
7. shift register according to any one of claims 1-4, which is characterized in that the node control module specifically wraps
It includes: the 5th switching transistor, the 6th switching transistor, the 7th switching transistor, the 8th switching transistor and first capacitor；Its
In,
5th switching transistor, grid and first are extremely connected with first clock signal terminal, the second pole with it is described
Second node is connected；
6th switching transistor, grid are connected with the second node, the first pole and the third reference voltage end phase
Even, the second pole is connected with the first node；
7th switching transistor, grid are connected with the first node, the first pole and the third reference voltage end phase
Even, the second pole is connected with the second node；
8th switching transistor, grid are connected with the grid signal output end of the shift register, the first pole and institute
It states third reference voltage end to be connected, the second pole is connected with the second node；
The first capacitor is connected between the second node and the third reference voltage end.
8. shift register according to any one of claims 1-4, which is characterized in that first output module specifically wraps
It includes: the 9th switching transistor and the second capacitor；Wherein,
9th switching transistor, grid are connected with the first node, the first pole and the second clock signal end phase
Even, the second pole is connected with the grid signal output end of the shift register；
Second capacitance connection is between the grid and the second pole of the 9th switching transistor.
9. shift register according to any one of claims 1-4, which is characterized in that second output module specifically wraps
It includes: the tenth switching transistor；Wherein,
Tenth switching transistor, grid are connected with the second node, the first pole and the third reference voltage end phase
Even, the second pole is connected with the grid signal output end of the shift register.
10. a kind of gate driving circuit, which is characterized in that including cascade multiple such as the described in any item shiftings of claim 1-9
Bit register；Wherein,
In addition to first order shift register, the upper level displacement adjacent thereto of the input signal end of every level-one shift register is posted
The grid signal output end of storage is connected；
In addition to afterbody shift register, the next stage displacement adjacent thereto of the reset signal end of every level-one shift register
The grid signal output end of register is connected.
11. a kind of display panel, which is characterized in that including gate driving circuit as claimed in claim 10.
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| CN107154235B (en) | 2017-07-21 | 2019-11-19 | 京东方科技集团股份有限公司 | Scan shift circuit, touch-control shift circuit, driving method and relevant apparatus |
| CN108288450B (en) * | 2018-02-06 | 2021-04-27 | 合肥京东方光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108877619B (en) * | 2018-06-22 | 2021-06-01 | 武汉华星光电半导体显示技术有限公司 | Control circuit and control method of display device |
| US11380374B2 (en) * | 2019-07-02 | 2022-07-05 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, and device |
| CN111243650B (en) * | 2020-02-05 | 2022-01-11 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
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| CN105869562A (en) * | 2016-05-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display panel |
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| CN105869562A (en) * | 2016-05-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display panel |
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