CN109687864A - Programmable gate array containing programmable computing unit - Google Patents
Programmable gate array containing programmable computing unit Download PDFInfo
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- CN109687864A CN109687864A CN201710980620.XA CN201710980620A CN109687864A CN 109687864 A CN109687864 A CN 109687864A CN 201710980620 A CN201710980620 A CN 201710980620A CN 109687864 A CN109687864 A CN 109687864A
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- programmable
- computing unit
- gate array
- programmable gate
- logic cells
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
Programmable gate array containing programmable computing unit, the present invention propose a kind of programmable gate array, it contains multiple programmable computing units, multiple programmable logic cells and multiple reconfigurable interconnections.Each programmable computing unit contains at least one writeable storage array, the look-up table (LUT) of one function of the writeable a burst of column storage of storage.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technique
Programmable gate array belongs to semicustom integrated circuit, i.e., by backend process or field programming, realizes to logic electricity
The customization on road.United States Patent (USP) 4,870,302 discloses a kind of programmable gate array.It contains multiple programmable logic cells
(configurable logic element or configurable logic block) and reconfigurable interconnection
(configurable interconnect or programmable interconnect).Wherein, programmable logic cells exist
Realize displacement, logic NOT, AND(logical AND to the property of can choose under setting signal control), OR(logic sum), NOR(and non-),
NAND(and non-), XOR(exclusive or) ,+(arithmetic adds) ,-functions such as (arithmetic subtracts)；Reconfigurable interconnection can be under setting signal control
Selectively realize the functions such as connection, the disconnection between two interconnection lines.
Currently, many applications all refer to the calculating of complicated function.Complicated function typically contains multiple independents variable, it is basic
A kind of combination of function.Basic function contains one or a small amount of independent variable, and example includes surmounting function, such as index (exp), right
Number (log), trigonometric function (sina, cos) etc..In order to guarantee to execute speed, performance application requirement realizes complexity with hardware
Function.In existing programmable gate array, complicated function to solidify computing unit by realizing.These solidifications calculate single
Member is a part of stone (hard block), and circuit has been cured, cannot reconfigure to it.It is obvious that solidification meter
Further applying for programmable gate array will be limited by calculating unit.In order to overcome this difficulty, the present invention is by programmable gate circuit
Concept makes to solidify computing unit programmable.Particularly, programmable gate circuit in addition to containing programmable logic cells with
Outside, also containing programmable computing unit.Realize any one of many kinds of function to the programmable computing unit property of can choose.
Summary of the invention
The main object of the present invention is to promote programmable gate circuit in the application in complex mathematical computations field.
It is a further object of the present invention to provide a kind of programmable gate circuits, and not only its logic function can be customized, meter
Calculating function can also be customized.
A kind of it is a further object of the present invention to provide computing capabilitys more flexible, more powerful programmable gate array.
A kind of it is a further object of the present invention to provide chip areas smaller, the lower programmable gate array of cost.
In order to realize that these and other purpose, the present invention propose a kind of programmable gate array.It contains a programmable meter
Calculate cell array, an array of programmable logic cells and multiple reconfigurable interconnections.Each programmable computing unit contains at least
One writeable storage array, the writeable storage array store a kind of look-up table (LUT) of function.The use of programmable computing unit
In two stages: setup phase and calculation stages.In setup phase, needing for the LUT of required function to be loaded into according to user can
It writes in array；In calculation stages, the value of basic function is obtained by searching for LUT.Due to using writeable array, even if with a batch
Different functions also may be implemented in secondary chip.Moreover, for based on the programmable gate that program storage (MTP) array is repeated several times
Array, due to that can load the LUT of different functions to MTP array in different periods, which is able to achieve restructural
It calculates.
In addition to may be programmed computing unit, programmable gate array also contains multiple programmable logic cells and reconfigurable interconnection.
Programmable logic cells selectively realize a kind of logical operation from a logical operation library；The reconfigurable interconnection property of can choose
Realize one of a variety of connections.During the realization of complicated function, complicated function is first broken down into multiple basic functions.
Then corresponding programmable computing unit is set for each basic function, achieves corresponding basic function.Finally, passing through
Programmable logic cells and reconfigurable interconnection are set, realize required complicated function.
Correspondingly, the present invention proposes a kind of programmable gate array (400), it is characterised in that contains: multiple includes that one can compile
The programmable computing unit (100AA-100AD) of journey computing unit (100), programmable computing unit (100) are writeable containing one
Storage array (110), the writeable storage array (110) store at least partly look-up table (LUT) of a basic function；It is multiple to include
The programmable logic cells (200AA-200AD) of one programmable logic cells (200), the programmable logic cells are from a logic
A kind of logical operation is selectively realized in operation library；It is multiple this be may be programmed into computing unit (100AA-100AD) and this to compile
The selectively coupled reconfigurable interconnection (300) of journey logic unit (200AA-200AD)；By may be programmed computing unit to this
(100AA-100AD), the programmable logic cells (200AA-200AD) and the reconfigurable interconnection (300) are programmed to realize
One complicated function, the complicated function are a kind of combinations of the basic function.
The present invention also proposes a kind of programmable gate array (400), it is characterised in that contains: semi-conductive substrate (0)；It is multiple
Programmable computing unit (100AA-100AD) including a programmable computing unit (100), programmable computing unit (100)
Containing a writeable storage array (110), which stores at least partly look-up table of a basic function
(LUT)；Multiple includes the programmable logic cells (200AA-200AD) of a programmable logic cells (200), this may be programmed and patrols
It collects unit and selectively realizes a kind of logical operation from a logical operation library；It is multiple that this be may be programmed into computing unit (100AA-
100AD) and the selectively coupled reconfigurable interconnection (300) of the programmable logic cells (200AA-200AD)；By that can be compiled to this
Journey computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and the reconfigurable interconnection (300) carry out
To realize a complicated function, which is a kind of combination of the basic function for programming；Writeable storage array (110) base
In the first transistor (0t1), which is based on second transistor (0t2), first and second crystal
Pipe (0t1,0t2) is formed in the semiconductor substrate (0).
Detailed description of the invention
Fig. 1 is a kind of symbol of programmable computing unit.
Fig. 2 is a kind of substrate circuitry layout of programmable computing unit.
Fig. 3 is a kind of layout of programmable gate array.
Fig. 4 indicates a kind of two service life of restructural gate array.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection is realized；Fig. 5 B discloses a kind of patrolling for programmable logic cells realization
Collect operation library.
Fig. 6 is a kind of layout of this kind of programmable gate array specific implementation.
Fig. 7 is a kind of sectional view of programmable gate array.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific embodiment
Fig. 1 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, it includes setting signal 125 that end CFG, which is arranged,.When setting signal 125 is " writing ", list is calculated programmable
The LUT of basic function needed for being written in member 100.When setting signal 125 is " reading ", read from programmable computing unit 100
Value in LUT.Fig. 2 is a kind of circuit arrangement map of programmable computing unit 100.In this embodiment, LUT is stored at least one
In a writeable storage array 110.The circuit further includes the peripheral circuit of writeable storage array 110: X-decoder 15 and Y-decoder
(including reading circuit) 17 etc..Writeable storage array 110 can be RAM or ROM.The example of RAM includes SRAM, DRAM etc.；ROM
Example include OTP(one-time programming), MTP(more times programming) etc..Wherein, MTP includes EPROM, EEPROM, flash memory etc..
Fig. 3 indicates a kind of programmable gate array 400.It contains regularly arranged programmable module 400A and programmable module
400B etc..Each programmable module (such as 400A), which is contained multiple programmable computing units (such as 100AA-100AD) and be may be programmed, patrols
It collects unit (such as 200AA-200AD).Programmable computing unit (such as 100AA-100AD) and programmable logic cells (such as
Contain programmable channel 320,340 between 200AA-200AD)；Between programmable module 400A and programmable module 400B,
Contain programmable channel 310,330,350.Programmable channel 310-350 contains multiple reconfigurable interconnections 300.For being familiar with ability
It, can also be using the design such as sea of gates (sea-of-gates) other than programmable channel for the professional person in domain.
Fig. 4 indicates two service life 620 and 660 of restructural gate array 400.It is two that first service life 620, which is divided to,
Stage: setup phase 610 and calculation stages 630.In setup phase 610, being needed according to user will be relevant to a basic function
Look-up table is loaded into MTP array 110；In calculation stages 630, corresponding LUT is searched in MTP array 110 to obtain the base
The value of this function.Similarly, the second service life 660 also contains identical setup phase 650 and calculation stages 670.It is restructural
Calculate be particularly suitable for SIMD(single-instruction multiple-data stream (SIMD)) data processing.Once LUT is loaded into MTP times in setup phase 610
After column 110, mass data can be sent into programmable computing unit 100 and handled, and obtain higher processing speed.
There are many example application of SIMD, as, to the same operation of multiple pixels or vector operation, used in scientific algorithm in image procossing
Extensive parallel computing etc..In addition, programmable gate array can also be may be programmed the pipelining of the calculating in computing unit,
To further increase throughput.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection 300 is able to achieve.The reconfigurable interconnection 300 and United States Patent (USP) 4,
The reconfigurable interconnection disclosed in 870,302 is similar.It uses a kind of connection type of following link libraries: a) interconnection line 302/304
It is connected, interconnection line 306/308 is connected, but 302/304 is not attached to 306/308；B) interconnection line 302/304/306/308 is homogeneous
Even；C) interconnection line 306/308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306/308；D) interconnection line 302/304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302/304；E) interconnection line 302,304,306,306 is not attached to.?
In this specification, the symbol "/" between two interconnection lines indicates that two interconnection lines are connected, the symbol between two interconnection lines
", " indicate that two interconnection lines are not attached to.
Fig. 5 B discloses a kind of logical operation library that programmable logic cells 200 are able to achieve.It is input data that it, which inputs A and B,
210,220, output C are output data 230.What is disclosed in the programmable logic cells 200 and United States Patent (USP) 4,870,302 compiles
Journey logic unit is similar.It may be implemented at least one of following logical operation libraries: C=A, A logic NOT, A displacement, AND (A,
B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B), arithmetic add A+B, arithmetic to subtract A-B etc..Programmable logic cells
200 can also be containing sequential circuit elements such as register, triggers, with the operation such as assembly line of practising.
Fig. 6 is a kind of specific implementation of programmable gate array 400, it is for realizing a complicated function: e=a.sin(b)+
c.cos(d).Reconfigurable interconnection 300 is using the representation in Fig. 5 A in programmable channel 310-350: there is dot in crosspoint
Reconfigurable interconnection indicate cross spider be connected, crosspoint without dot reconfigurable interconnection indicate cross spider be not attached to, disconnection can
Programming connection indicates that the interconnection line disconnected is divided into two mutual disjunct interconnection line segments.In this embodiment, it may be programmed and calculate
Unit 100AA is arranged to log (), and calculated result log (a) is sent to the first input of programmable logic cells 200AA.
Programmable computing unit 100AB is arranged to log [sin ()], and calculated result log [sin (b)] is sent to programmable logic
The second input of unit 200AA.Programmable logic cells 200AA is arranged to " arithmetic adds ", calculated result log (a)+log
[sin (b)] is sent to programmable computing unit 100BA.Programmable computing unit 100BA is arranged to exp (), calculates knot
Fruit exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to the first input of programmable logic cells 200BA.Similarly,
By setting appropriate, computing unit 100AC, 100AD, programmable logic cells 200AC, programmable computing unit may be programmed
The result c of 100BC.Cos (d) is sent to the second input of programmable logic cells 200BA.Programmable logic cells 200BA quilt
It is set as " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent to output e.It is obvious that being set by changing
It sets, programmable gate array 400 can also realize other complicated functions.
Fig. 7 is a kind of sectional view of programmable gate array 400, it contains regularly arranged programmable module 400A etc..It can
Programming module 400A contains programmable computing unit 100AA and programmable logic cells 200AA etc..Programmable computing unit
Writeable storage array 110 in 100AA is based on the first transistorlike 0t1, and transistorlike 0t1 is suitble to complete store function.It can
Logic circuit in programmed logic unit 200AA is based on the second transistorlike 0t2, and transistorlike 0t2 is suitble to complete logic function
Energy.Two transistorlike 0t1,0t2 are both formed in single crystal semiconductor substrate 0, they are intercoupled by interconnection line 0i.Due to can
Program calculation unit 100AA and programmable logic cells 200AA is based on transistor 0t1,0t2, they can be by traditional
Cmos process flow is formed, and does not need to develop new technique, therefore programmable gate array proposed by the present invention (400) is with very short
R&D cycle and splendid manufacturability.Moreover, because transistor 0t1 is single-crystal transistor, computing unit may be programmed
Writeable storage array 110 in 100AA has faster speed, is suitble to the realization of high-performance calculation.
This specification is by taking field programmable gate array (FPGA) as an example.In FPGA, wafer will complete all process steps (including
All programmable computing unit, programmable logic cells and reconfigurable interconnection).It, can be by the way that programmable connect be arranged at programming scene
Fetch the function of defining FPGA.The example of above-mentioned FPGA can easily be generalized to traditional programmable gate array.In tradition
In programmable gate array, wafer is only semi-finished, i.e., wafer production is only completed programmable computing unit and programmable logic cells, but
Reconfigurable interconnection is not completed.After the function of chip determines, programmable channel 310-350 is customized by backend process.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of programmable gate array (400), it is characterised in that contain:
Multiple includes the programmable computing unit (100AA-100AD) of a programmable computing unit (100), the programmable calculating
Unit (100) contains a writeable storage array (110), which stores a basic function at least partly
Look-up table (LUT)；
Multiple includes the programmable logic cells (200AA-200AD) of a programmable logic cells (200), the programmable logic
Unit selectively realizes a kind of logical operation from a logical operation library；
It is multiple that this be may be programmed into computing unit (100AA-100AD) and the programmable logic cells (200AA-200AD) selectivity
The reconfigurable interconnection (300) of coupling；
By to this may be programmed computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and this can compile
Journey connection (300) is programmed to realize a complicated function, which is a kind of combination of the basic function.
2. programmable gate array (400) according to claim 1, it is further characterized in that: the writeable storage array (110) is
One-time programming memory (OTP).
3. programmable gate array (400) according to claim 1, it is further characterized in that: the writeable storage array (110) is
Multiple programmable memory (MTP).
4. programmable gate array (400) according to claim 1, it is further characterized in that: its use process includes a setting
Stage (610) needs the LUT by a function to be loaded into writeable storage array (110) in the setup phase (610) according to user
In.
5. programmable gate array (400) according to claim 1, it is further characterized in that: its use process includes a use
Stage (630) searches corresponding LUT in writeable storage array (110) in the service stage (630) to obtain the function
Value.
6. a kind of programmable gate array (400), it is characterised in that contain:
Semi-conductive substrate (0)；
Multiple includes the programmable computing unit (100AA-100AD) of a programmable computing unit (100), the programmable calculating
Unit (100) contains a writeable storage array (110), which stores a basic function at least partly
Look-up table (LUT)；
Multiple includes the programmable logic cells (200AA-200AD) of a programmable logic cells (200), the programmable logic
Unit selectively realizes a kind of logical operation from a logical operation library；
It is multiple that this be may be programmed into computing unit (100AA-100AD) and the programmable logic cells (200AA-200AD) selectivity
The reconfigurable interconnection (300) of coupling；
By to this may be programmed computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and this can compile
Journey connection (300) is programmed to realize a complicated function, which is a kind of combination of the basic function；
The writeable storage array (110) is based on the first transistor (0t1), which is based on the second crystal
It manages (0t2), first and second transistor (0t1,0t2) is formed in the semiconductor substrate (0).
7. programmable gate array (400) according to claim 6, it is further characterized in that: the writeable storage array (110) is
One-time programming memory (OTP).
8. programmable gate array (400) according to claim 6, it is further characterized in that: the writeable storage array (110) is
Multiple programmable memory (MTP).
9. programmable gate array (400) according to claim 6, it is further characterized in that: its use process includes a setting
Stage (610) needs the LUT by a function to be loaded into writeable storage array (110) in the setup phase (610) according to user
In.
10. programmable gate array (400) according to claim 6, it is further characterized in that: its use process includes a use
Stage (630) searches corresponding LUT in writeable storage array (110) in the service stage (630) to obtain the function
Value.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710980620.XA CN109687864A (en) | 2017-10-19 | 2017-10-19 | Programmable gate array containing programmable computing unit |
| US15/793,920 US10084453B2 (en) | 2016-03-05 | 2017-10-25 | Configurable computing array |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
| US16/693,370 US10848158B2 (en) | 2016-02-13 | 2019-11-24 | Configurable processor |
| US17/065,604 US11128302B2 (en) | 2016-02-13 | 2020-10-08 | Configurable processor doublet based on three-dimensional memory (3D-M) |
| US17/065,632 US11128303B2 (en) | 2016-02-13 | 2020-10-08 | Three-dimensional memory (3D-M)-based configurable processor singlet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710980620.XA CN109687864A (en) | 2017-10-19 | 2017-10-19 | Programmable gate array containing programmable computing unit |
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| CN109687864A true CN109687864A (en) | 2019-04-26 |
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| CN201710980620.XA Pending CN109687864A (en) | 2016-02-13 | 2017-10-19 | Programmable gate array containing programmable computing unit |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574632A (en) * | 2003-05-21 | 2005-02-02 | 阿尔特拉公司 | Programmable logic devices with stabilized configuration cells for reduced soft error rates |
| CN1652324A (en) * | 2004-02-06 | 2005-08-10 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| CN1720616A (en) * | 2003-01-08 | 2006-01-11 | 国际商业机器公司 | High performance embedded dram technology with strained silicon |
| US20070097751A1 (en) * | 2005-10-31 | 2007-05-03 | Popoff Gregory A | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same |
| CN101924068A (en) * | 2009-06-11 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | Resistance storage and manufacturing method of integrated circuit comprising same |
| CN102446547A (en) * | 2010-10-06 | 2012-05-09 | 旺宏电子股份有限公司 | Cross-point self-aligned reduced cell size phase change memory |
| CN103367406A (en) * | 2012-03-30 | 2013-10-23 | 美国博通公司 | Integrated circuit (IC) including first memory cell transistor of read only memory (ROM) array and manufacturing method thereof |
| CN104037131A (en) * | 2013-03-08 | 2014-09-10 | 飞思卡尔半导体公司 | Technique of using thermal oxide for gate dielectric for select gate and partial replacement gate |
| CN104321967A (en) * | 2012-05-25 | 2015-01-28 | 株式会社半导体能源研究所 | Programmable logic device and semiconductor device |
| CN107154798A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional writable memory |
-
2017
- 2017-10-19 CN CN201710980620.XA patent/CN109687864A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720616A (en) * | 2003-01-08 | 2006-01-11 | 国际商业机器公司 | High performance embedded dram technology with strained silicon |
| CN1574632A (en) * | 2003-05-21 | 2005-02-02 | 阿尔特拉公司 | Programmable logic devices with stabilized configuration cells for reduced soft error rates |
| CN1652324A (en) * | 2004-02-06 | 2005-08-10 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| US20070097751A1 (en) * | 2005-10-31 | 2007-05-03 | Popoff Gregory A | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same |
| CN101924068A (en) * | 2009-06-11 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | Resistance storage and manufacturing method of integrated circuit comprising same |
| CN102446547A (en) * | 2010-10-06 | 2012-05-09 | 旺宏电子股份有限公司 | Cross-point self-aligned reduced cell size phase change memory |
| CN103367406A (en) * | 2012-03-30 | 2013-10-23 | 美国博通公司 | Integrated circuit (IC) including first memory cell transistor of read only memory (ROM) array and manufacturing method thereof |
| CN104321967A (en) * | 2012-05-25 | 2015-01-28 | 株式会社半导体能源研究所 | Programmable logic device and semiconductor device |
| CN104037131A (en) * | 2013-03-08 | 2014-09-10 | 飞思卡尔半导体公司 | Technique of using thermal oxide for gate dielectric for select gate and partial replacement gate |
| CN107154798A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional writable memory |
Non-Patent Citations (1)
| Title |
|---|
| 刘文松 等: "SoC设计和测试技术：理论与实践", vol. 1, 东南大学出版社, pages: 110 - 111 * |
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Address after: No.16, 34th floor, building 2, No.88, Jitai fifth road, high tech Zone, Chengdu, Sichuan, 640041 Applicant after: ChengDu HaiCun IP Technology LLC Address before: B-36, 6 Yongfeng Road, Chengdu, Sichuan 610041 Applicant before: ChengDu HaiCun IP Technology LLC |