CN109698694A - Programmable computing array - Google Patents
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- CN109698694A CN109698694A CN201710989881.8A CN201710989881A CN109698694A CN 109698694 A CN109698694 A CN 109698694A CN 201710989881 A CN201710989881 A CN 201710989881A CN 109698694 A CN109698694 A CN 109698694A
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- 238000007620 mathematical function Methods 0.000 claims abstract 8
- 239000000758 substrate Substances 0.000 claims description 24
- 238000003860 storage Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 description 39
- 238000009825 accumulation Methods 0.000 description 14
- 238000004364 calculation method Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 241000193935 Araneus diadematus Species 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 244000089409 Erythrina poeppigiana Species 0.000 description 1
- 235000009776 Rathbunia alamosensis Nutrition 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
Abstract
The present invention proposes a kind of programmable computing array based on three-dimensional writable memory (3D-W).It contains a programmable computing unit array, an array of programmable logic cells and multiple reconfigurable interconnections.Each programmable computing unit contains at least one 3D-W array, which stores the look-up table (LUT) of a mathematical function.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technique
Programmable gate array belongs to semicustom integrated circuit, i.e., by backend process or field programming, realizes to logic electricity
The customization on road.United States Patent (USP) 4,870,302 discloses a kind of programmable gate array.It contains multiple programmable logic cells
(configurable logic element or configurable logic block) and reconfigurable interconnection
(configurable interconnect or programmable interconnect).Wherein, programmable logic cells exist
Realize displacement, logic NOT, AND(logical AND to the property of can choose under setting signal control), OR(logic sum), NOR(and non-),
NAND(and non-), XOR(exclusive or) ,+(arithmetic adds) ,-functions such as (arithmetic subtracts)；Reconfigurable interconnection can be under setting signal control
Selectively realize the functions such as connection, the disconnection between two interconnection lines.
Currently, many applications all refer to the calculating of complicated function.Complicated function typically contains multiple independents variable, it is basic
A kind of combination of function.Basic function contains one or a small amount of independent variable, and example includes surmounting function, such as index (exp), right
Number (log), trigonometric function (sina, cos) etc..In order to guarantee to execute speed, performance application requirement realizes complexity with hardware
Function.In existing programmable gate array, complicated function to solidify computing unit by realizing.These solidifications calculate single
Member is a part of stone (hard block), and circuit has been cured, cannot reconfigure to it.It is obvious that solidification meter
Further applying for programmable gate array will be limited by calculating unit.In order to overcome this difficulty, the present invention is by programmable gate circuit
Concept makes to solidify computing unit programmable.Particularly, programmable gate circuit in addition to containing programmable logic cells with
Outside, also containing programmable computing unit.Realize any one of many kinds of function to the programmable computing unit property of can choose.
Summary of the invention
The main object of the present invention is to promote programmable gate circuit in the application in complex mathematical computations field.
It is a further object of the present invention to provide a kind of programmable gate circuits, and not only its logic function can be customized, meter
Calculating function can also be customized.
A kind of it is a further object of the present invention to provide computing capabilitys more flexible, more powerful programmable gate array.
A kind of it is a further object of the present invention to provide chip areas smaller, the lower programmable gate array of cost.
In order to realize that these and other purpose, the present invention propose a kind of based on three-dimensional writable memory (three-
Dimensional writable memory, referred to as 3D-W) programmable computing array.It is single that it contains a programmable calculating
Element array, an array of programmable logic cells and multiple reconfigurable interconnections.Each programmable computing unit contains at least one
3D-W array, the 3D-W array store a kind of look-up table (LUT) of function.It may be programmed the use of computing unit in two stages:
Setup phase and calculation stages.In setup phase, need for the LUT of required function to be loaded into 3D-W array according to user；?
Calculation stages obtain the value of basic function by searching for LUT.Due to using 3D-W array, even if with a batch of chip
Different functions may be implemented.Moreover, for based on the three-dimensional programmable calculating that program storage (3D-MTP) array is repeated several times
Array, due to that can load the LUT of different functions to 3D-MTP array in different periods, which is able to achieve can
Reconstruction calculations.
In addition to may be programmed computing unit, programmable computing array also contains multiple programmable logic cells and programmable company
It connects.During realization, complicated function is first broken down into multiple basic functions.Then it is corresponded to for the setting of each basic function
Programmable computing unit, achieve corresponding basic function.Finally, passing through setting programmable logic cells and programmable company
It connects, realizes required complicated function.
Realize that programmable computing array there are many advantages using 3D-W.Firstly, since 3D-W memory capacity is big, it can be with
Store biggish LUT.Secondly, may be implemented three-dimensionally integrated between 3D-W array, it is consequently belonging to different programmable computing units
3D-W array can be stacked together, with Substrate Area needed for the programmable computing array of reduction.Finally, due to 3D-W gusts
Column do not account for Substrate Area substantially, and programmable logic cells and/or reconfigurable interconnection can integrate below 3D-W array, in this way may be used
With Substrate Area needed for being further reduced programmable computing array.
Correspondingly, the present invention proposes a kind of programmable computing unit (100), it is characterised in that contain: one contains transistor
Semiconductor substrate (0)；Three-dimensional writable memory (3D-W) array (110) of one be stacked in the semiconductor substrate (0), should
3D-W array (110) stores at least partly look-up table (LUT) of a function；One setting signal (125), when the setting signal
(125) be " writing " when, the 3D-W array (110) is written into the value of a function；When the setting signal (125) is " reading ", from this
The value of the function is read in 3D-W array (110).
The present invention also proposes a kind of programmable computing array (400) for realizing a complicated function, it is characterised in that contains: one
Programmable computing unit array (100AA-100AD) containing at least one programmable computing unit (100), the programmable calculating are single
At least partly look-up table of first (100) containing three-dimensional writable memory (3D-W) array (110) and one basic function of storage
(LUT)；One contains the array of programmable logic cells (200AA-200AD) of an at least programmable logic cells (200), this can be compiled
Journey logic unit selectively realizes a kind of logical operation from a logical operation library；It is multiple that this be may be programmed into computing unit array
With the reconfigurable interconnection (300) of array of programmable logic cells coupling；Programmable computing array (400) are by that can compile this
Journey computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and the reconfigurable interconnection (300) carry out
To realize the complicated function, which is a kind of combination of the basic function for programming.
Detailed description of the invention
Fig. 1 is a kind of sectional view of three-dimensional writable memory (3D-W).
Fig. 2 is a kind of symbol of programmable computing unit.
Fig. 3 is the substrate circuitry layout of the first programmable computing unit.
Fig. 4 is a kind of layout of programmable computing array.
Fig. 5 indicates a kind of two service life of restructural gate array.
Fig. 6 A discloses a kind of link library that reconfigurable interconnection is realized；Fig. 6 B discloses a kind of patrolling for programmable logic cells realization
Collect operation library.
Fig. 7 A is the substrate circuitry layout of second of programmable computing unit；Fig. 7 B is to may be programmed computing unit in Fig. 4
The sectional view of 100AA-100AD.
Fig. 8 is a kind of layout of programmable computing array specific implementation.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific embodiment
Fig. 1 is a kind of sectional view of three-dimensional writable memory (3D-W).3D-W is one kind of three-dimensional storage (3D-M),
The information of storage uses the typing of electrical programming mode.According to the number that it can be programmed, 3D-W is divided into three-dimensional one-time programming memory again
(3D-OTP) and three-dimensional repeatedly programmable memory (3D-MTP).Wherein, 3D-OTP energy one-time programming, 3D-MTP can overprograms.
Common 3D-W includes 3D-XPoint(three dimensional intersection lattice array memory), 3D-RRAM(three-dimensional electric impedance memory), 3-D
Memristor(three-dimensional hinder storage), 3D-OTP(three-dimensional one-time programming memory) etc..
3D-W 10 is formed in the substrate circuitry layer 0K on substrate 0 containing one.Accumulation layer 16A be stacked on substrate circuitry 0K it
On, accumulation layer 16B is stacked on accumulation layer 16A.Substrate circuitry layer 0K contains the peripheral circuit of accumulation layer 16A, 16B, it is wrapped
Including transistor 0t and its interconnection line 0i(includes 0M1-0M2).Wherein, transistor 0t is formed in semi-conductive substrate 0；Interconnection line
0i contains interconnection line layer 0M1-0M3.Each accumulation layer (such as 16A) contains a plurality of first address wire (such as 2a, in the y-direction), a plurality of
Second address wire (such as 1a, in the x-direction) and multiple 3D-P store first (such as 1aa).Accumulation layer 16A, 16B passes through contact channel respectively
Hole 1av, 3av are coupled with substrate 0.
In a 3D-W, each accumulation layer contains multiple 3D-W arrays.3D-W array is that own in an accumulation layer
Have shared the set of the storage member of at least one address wire.In a 3D-W array, all address wires be it is continuous, not with
Different 3D-W arrays share any address wire.In addition, a 3D-W chip contains multiple 3D-W modules.Each 3D-W module includes
All accumulation layers in 3D-W, top accumulation layer contains only a 3D-W array, and the projection of 3D-W array on substrate is determined
Determine the boundary of 3D-W module.
3D-W storage member 1aa contains one layer of programming film 12 and a layer diode film 14.Programming film 12 can be antifuse film,
For 3D-OTP；It is also possible to other multiple programming films, is used for 3D-MTP.Diode film 14 has following generalized character:
Under read voltage, resistance is smaller；When applied voltage be less than read voltage or it is contrary with read voltage when, resistance is larger.Two
Pole pipe film can be P-i-N diode, be also possible to metal oxide (such as TiO2) diode etc..
Fig. 2 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, it includes setting signal 125 that end CFG, which is arranged,.When setting signal 125 is " writing ", list is calculated programmable
The LUT of basic function needed for being written in member 100.When setting signal 125 is " reading ", read from programmable computing unit 100
Value in LUT.
Fig. 3 is the layout of the substrate circuitry 0K of the first programmable computing unit 100.Since 3D-W array is stacked on lining
Above the circuit 0K of bottom, not in the substrate, therefore projection of the 3D-W array on substrate 0 is only represented by dashed line.In this embodiment,
LUT is stored at least one 3D-W array 110.Substrate circuitry 0K includes the peripheral circuit of 3D-W array 110: its X-decoder
15, Y-decoder (including reading circuit) 17 and Z decoder 19 etc..
Fig. 4 indicates a kind of programmable computing array 400.It contains regularly arranged programmable module 400A and programmable mould
Block 400B etc..Each programmable module (such as 400A) is containing multiple programmable computing units (such as 100AA-100AD) and may be programmed
Logic unit (such as 200AA-200AD).Programmable computing unit (such as 100AA-100AD) and programmable logic cells (such as
Contain programmable channel 320,340 between 200AA-200AD)；Between programmable module 400A and programmable module 400B,
Contain programmable channel 310,330,350.Programmable channel 310-350 contains multiple reconfigurable interconnections 300.For being familiar with ability
It, can also be using the design such as sea of gates (sea-of-gates) other than programmable channel for the professional person in domain.
Fig. 5 indicates two service life 620 and 660 of restructural gate array 400.It is two that first service life 620, which is divided to,
Stage: setup phase 610 and calculation stages 630.In setup phase 610, being needed according to user will relevant to first function the
One look-up table is loaded into 3D-MTP array 110；In calculation stages 630, corresponding LUT is searched in 3D-MTP array 110
Obtain the value of first function.Similarly, the second service life 660 also contains identical setup phase 650 and calculation stages 670.
Reconfigurable Computation is particularly suitable for SIMD(single-instruction multiple-data stream (SIMD)) data processing.Once LUT is loaded into setup phase 610
After 3D-MTP array 110, mass data can be sent into programmable computing unit 100 and handled, and obtain higher place
Manage speed.There are many example application of SIMD, as in image procossing to multiple pixels it is same operation or vector operation, scientific algorithm
Used in extensive parallel computing etc..In addition, programmable computing array can also be may be programmed the calculating in computing unit
Pipelining, to further increase throughput.
Fig. 6 A discloses a kind of link library that reconfigurable interconnection 300 is able to achieve.The reconfigurable interconnection 300 and United States Patent (USP) 4,
The reconfigurable interconnection disclosed in 870,302 is similar.It uses a kind of connection type of following link libraries: a) interconnection line 302/304
It is connected, interconnection line 306/308 is connected, but 302/304 is not attached to 306/308；B) interconnection line 302/304/306/308 is homogeneous
Even；C) interconnection line 306/308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306/308；D) interconnection line 302/304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302/304；E) interconnection line 302,304,306,306 is not attached to.?
In this specification, the symbol "/" between two interconnection lines indicates that two interconnection lines are connected, the symbol between two interconnection lines
", " indicate that two interconnection lines are not attached to.
Fig. 6 B discloses a kind of logical operation library that programmable logic cells 200 are able to achieve.It is input data that it, which inputs A and B,
210,220, output C are output data 230.What is disclosed in the programmable logic cells 200 and United States Patent (USP) 4,870,302 compiles
Journey logic unit is similar.It may be implemented at least one of following logical operation libraries: C=A, A logic NOT, A displacement, AND (A,
B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B), arithmetic add A+B, arithmetic to subtract A-B etc..Programmable logic cells
200 can also be containing sequential circuit elements such as register, triggers, with the operation such as assembly line of practising.
Fig. 7 A is the layout of second of programmable computing unit 100.Since 3D-W array 110 does not account for Substrate Area, because
This programmable logic cells 200 can integrate below 3D-W array 110, and at least partly be covered by 3D-W array 110.Except this
Except, reconfigurable interconnection can also be also integrated into 110 lower section of 3D-W array, and at least partly covered by 3D-W array 110.Institute
There are these measures that can reduce the chip area of programmable computing array 400.
Fig. 7 B is the sectional view that may be programmed computing unit 100AA-100AD in Fig. 4.In order to be further reduced programmable calculating
The chip area of array 400 can carry out three-dimensionally integrated 3D-W array in programmable computing unit 100AA to 3D-W array
110AA(stores the LUT A of the first basic function, is located at accumulation layer 16A) (direction+z) is stacked on substrate circuitry 0K, it can compile
3D-W array 110AB(in journey computing unit 100AB stores the LUT B of the second basic function, is located at accumulation layer 16B) it is stacked on
On 3D-W array 110AA (direction+z), the 3D-W array 110AC(that may be programmed in computing unit 100AC stores the basic letter of third
Several LUT C is located at accumulation layer 16C) (direction+z) is stacked on 3D-W array 110AB, it may be programmed in computing unit 100AD
3D-W array 110AD(store the 4th basic function LUT D, be located at accumulation layer 16D) be stacked on 3D-W array 110AC
(direction+z).Meanwhile programmable logic cells or reconfigurable interconnection can be also integrated in substrate circuitry 0K, by 3D-W array
110AA-210AD is at least partly covered.
Fig. 8 is a kind of specific implementation of programmable computing array 400, it is for realizing a complicated function: e=a.sin(b)+
c.cos(d).Reconfigurable interconnection 300 is using the representation in Fig. 6 A in programmable channel 310-350: there is dot in crosspoint
Reconfigurable interconnection indicate cross spider be connected, crosspoint without dot reconfigurable interconnection indicate cross spider be not attached to, disconnection can
Programming connection indicates that the interconnection line disconnected is divided into two mutual disjunct interconnection line segments.In this embodiment, it may be programmed and calculate
Unit 100AA is arranged to log (), and calculated result log (a) is sent to the first input of programmable logic cells 200AA.
Programmable computing unit 100AB is arranged to log [sin ()], and calculated result log [sin (b)] is sent to programmable logic
The second input of unit 200AA.Programmable logic cells 200AA is arranged to " arithmetic adds ", calculated result log (a)+log
[sin (b)] is sent to programmable computing unit 100BA.Programmable computing unit 100BA is arranged to exp (), calculates knot
Fruit exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to the first input of programmable logic cells 200BA.Similarly,
By setting appropriate, computing unit 100AC, 100AD, programmable logic cells 200AC, programmable computing unit may be programmed
The result c of 100BC.Cos (d) is sent to the second input of programmable logic cells 200BA.Programmable logic cells 200BA quilt
It is set as " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent to output e.It is obvious that being set by changing
It sets, programmable computing array 400 can also realize other complicated functions.
This specification is by taking field programmable gate array (FPGA) as an example.In FPGA, wafer will complete all process steps (including
All programmable computing unit, programmable logic cells and reconfigurable interconnection).It, can be by the way that programmable connect be arranged at programming scene
Fetch the function of defining FPGA.The example of above-mentioned FPGA can easily be generalized to traditional programmable computing array.It is passing
It unites in programmable computing array, wafer is only semi-finished, i.e., wafer production is only completed programmable computing unit and programmable logic list
Member, but do not complete reconfigurable interconnection.After the function of chip determines, programmable channel 310-350 is customized by backend process.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of programmable computing unit (100), it is characterised in that contain:
One semiconductor substrate (0) containing transistor；
Three-dimensional writable memory (3D-W) array (110) of one be stacked in the semiconductor substrate (0), the 3D-W array (110)
Store at least partly look-up table (LUT) of a mathematical function；
When the setting signal (125) is " writing " the 3D-W array is written in the value of one mathematical function by one setting signal (125)
(110)；When the setting signal (125) is " reading ", from the value for reading the mathematical function in the 3D-W array (110).
2. programmable computing unit (100) according to claim 1, it is further characterized in that: the 3D-W is three-dimensional primary volume
Journey memory (3D-OTP).
3. programmable computing unit (100) according to claim 1, it is further characterized in that: the 3D-W is three-dimensional repeatedly volume
Journey memory (3D-MTP).
4. programmable computing unit (100) according to claim 1, it is further characterized in that: the 3D-MTP is 3D-
At least one of XPoint, 3D-RRAM and 3D-memristor.
5. a kind of programmable computing array (400) for realizing a complex mathematical function, it is characterised in that contain:
One contains the programmable computing unit array (100AA-100AD) of at least one programmable computing unit (100), this is programmable
At least portion of the computing unit (100) containing three-dimensional writable memory (3D-W) array (110) and one basic mathematical function of storage
Divide look-up table (LUT)；
One contains the array of programmable logic cells (200AA-200AD) of an at least programmable logic cells (200), this is programmable
Logic unit selectively realizes a kind of logical operation from a logical operation library；
Multiple reconfigurable interconnections (300) that this may be programmed to computing unit array and array of programmable logic cells coupling；
Programmable computing array (400) are by may be programmed computing unit (100AA-100AD), the programmable logic cells to this
(200AA-200AD) and the reconfigurable interconnection (300) are programmed to realize the complex mathematical function, which is
A kind of combination of the basic mathematical function.
6. programmable computing array (400) according to claim 5, it is further characterized in that: the programmable computing unit battle array
Column (100AA-100AD) contain the first and second 3D-W arrays (110AA, 110AB) being stacked on semi-conductive substrate (0),
2nd 3D-W array (110AB) is stacked on above the first 3D-W array (110AA).
7. programmable computing array (400) according to claim 6, it is further characterized in that: 3D-W gusts of the first or second
Column (110AA or 110AB) are stacked on above the programmable logic cells (200).
8. programmable computing array (400) according to claim 7, it is further characterized in that: 3D-W gusts of the first or second
Arrange (110AA or 110AB) covering at least partly programmable logic cells (200).
9. programmable computing array (400) according to claim 6, it is further characterized in that: 3D-W gusts of the first or second
Column (110AA or 110AB) are stacked on above the reconfigurable interconnection (300).
10. programmable computing array (400) according to claim 7, it is further characterized in that: 3D-W gusts of the first or second
Arrange (110AA or 110AB) covering at least partly reconfigurable interconnection (300).
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710989881.8A CN109698694A (en) | 2017-10-23 | 2017-10-23 | Programmable computing array |
| US15/793,912 US10075168B2 (en) | 2016-03-05 | 2017-10-25 | Configurable computing array comprising three-dimensional writable memory |
| US16/055,170 US20180353985A1 (en) | 2016-03-05 | 2018-08-06 | Configurable Computing Array Implementing Math Functions with Multiple Input Variables |
| US16/121,653 US10456800B2 (en) | 2016-03-05 | 2018-09-05 | Configurable computing array comprising configurable computing elements |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
| US16/693,370 US10848158B2 (en) | 2016-02-13 | 2019-11-24 | Configurable processor |
| US17/065,632 US11128303B2 (en) | 2016-02-13 | 2020-10-08 | Three-dimensional memory (3D-M)-based configurable processor singlet |
| US17/065,604 US11128302B2 (en) | 2016-02-13 | 2020-10-08 | Configurable processor doublet based on three-dimensional memory (3D-M) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710989881.8A CN109698694A (en) | 2017-10-23 | 2017-10-23 | Programmable computing array |
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| Publication Number | Publication Date |
|---|---|
| CN109698694A true CN109698694A (en) | 2019-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710989881.8A Pending CN109698694A (en) | 2016-02-13 | 2017-10-23 | Programmable computing array |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154798A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional writable memory |
| CN107154797A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | The programmable gate array of reservoir is recorded based on three-dimensional print |
-
2017
- 2017-10-23 CN CN201710989881.8A patent/CN109698694A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154798A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | Programmable gate array based on three-dimensional writable memory |
| CN107154797A (en) * | 2016-03-05 | 2017-09-12 | 杭州海存信息技术有限公司 | The programmable gate array of reservoir is recorded based on three-dimensional print |
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Application publication date: 20190430 |