CN108540126A - Programmable gate array based on three-dimensional writable memory - Google Patents
Programmable gate array based on three-dimensional writable memory Download PDFInfo
- Publication number
- CN108540126A CN108540126A CN201710122749.7A CN201710122749A CN108540126A CN 108540126 A CN108540126 A CN 108540126A CN 201710122749 A CN201710122749 A CN 201710122749A CN 108540126 A CN108540126 A CN 108540126A
- Authority
- CN
- China
- Prior art keywords
- programmable
- arrays
- gate array
- programmable gate
- computing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
Abstract
It can only realize that the defect of programming in logic, the present invention propose a kind of based on three-dimensional writable memory to make up traditional gate array（3D‑W）Programmable gate array.It contains multiple programmable computing units, and each programmable computing unit contains at least one 3D W arrays, which stores a kind of look-up table of basic complicated calculations（LUT）.The use of programmable computing unit is in two stages：Setup phase and calculation stages.In setup phase, being needed according to user will be in required basic complicated calculations LUT storage to 3D W arrays；In calculation stages, basic complicated calculations are realized by searching for the numerical value of LUT.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technology
Programmable gate array belongs to semicustom integrated circuit, and multiple programmable logic cells are arranged on a single die
Array format realizes the customization to logic circuit then by backend process or field programming.United States Patent (USP) 4,870,302
Disclose a kind of field programmable gate array（FPGA）.It contains multiple programmable logic cells（configurable logic
Array or configurable logic element）And reconfigurable interconnection（programmable interconnect）.Its
In, programmable logic cells can selectively realize displacement, logic NOT, AND under setting signal control（Logical AND）、OR
（Logic sum）、NOR（With it is non-）、NAND（With it is non-）、XOR（Exclusive or）、+（Arithmetic adds）、-（Arithmetic subtracts）Etc. functions；Reconfigurable interconnection
The functions such as connection, the disconnection between two interconnection lines can be selectively realized under setting signal control.It is existing programmable
Gate array can only realize programming in logic, and simple arithmetic at most can be achieved（Such as addition and subtraction）Programming, i.e., same hardware setting believe
Number control is lower can selectively realize different logics（Or simple arithmetic）Function.Regrettably, existing programmable gate array
Row still cannot achieve the programming of complicated calculations, i.e., same hardware can selectively realize different answer under setting signal control
Miscellaneous calculating（Such as index, logarithm, sin, cos）Function.
Invention content
The main object of the present invention is same hardware can selectively realize different complicated meters under setting signal control
Calculate function.
It is a further object of the present invention to provide the programmable gate arrays that required complicated calculations can be arranged in a kind of user.
It is a further object of the present invention to provide a kind of programmable gate arrays that computing capability is more flexible.
It is a further object of the present invention to provide a kind of programmable gate arrays that computing capability is more powerful.
It is another object of the present invention to strengthen the computing capability of traditional gate array and FPGA.
In order to realize that these and other purpose, the present invention propose a kind of based on three-dimensional writable memory（3D-W）Compile
Journey gate array.It contains multiple programmable computing units, and each programmable computing unit contains at least one 3D-W arrays, should
3D-W arrays store a kind of look-up table of basic complicated calculations（LUT）.The use of programmable computing unit is in two stages：Setting
Stage and calculation stages.In setup phase, needed required basic complicated calculations LUT storages to 3D-W arrays according to user
In；In calculation stages, basic complicated calculations are realized by searching for the numerical value of LUT.Due to using 3D-W arrays, same hardware
（Programmable computing unit）It can selectively realize different basic complicated calculations functions.In the present invention, complicated calculations are
Refer to the calculating in addition to addition and subtraction, including the calculating such as index, logarithm, sin, cos.
In addition to may be programmed computing unit, programmable gate array also contains multiple programmable logic cells.During realization,
Each complicated calculations is first broken down into multiple basic complicated calculations.Then each basic complicated calculations are directed to, setting is corresponding
Programmable computing unit achieves corresponding basic complicated calculations.Finally, by the way that programmable logic cells are arranged and may be programmed
Connection, completes required complicated calculations.
Realize that programmable gate array there are many advantages using 3D-W.Firstly, since 3D-W memory capacity is big, it can be deposited
Store up larger LUT.Secondly, three-dimensionally integrated, therefore 3D-W battle arrays of different programmable computing unit may be implemented between 3D-W arrays
Row can be stacked together, to reduce the Substrate Area needed for programmable gate array.Finally, due to which 3D-W arrays are substantially not
Substrate Area is accounted for, programmable logic cells and/or reconfigurable interconnection can be integrated in below 3D-W arrays, in this way can be further
Reduce the Substrate Area needed for programmable gate array.
Correspondingly, the present invention proposes a kind of programmable gate array, it is characterised in that contains multiple programmable computing units, packet
It includes；First programmable computing unit, the first programmable computing unit contain at least first three-dimensional writable memory（3D-W）Battle array
Row, the first 3D-W arrays store the look-up table of first function（LUT）；Second programmable computing unit, the second programmable meter
It calculates unit and contains at least the 2nd 3D-W arrays, the 2nd 3D-W arrays store the LUT of second function；This first and the second function
For different functions.
Description of the drawings
Fig. 1 is a kind of three-dimensional writable memory（3D-W）Sectional view.
Fig. 2 is a kind of symbol of programmable computing unit.
Fig. 3 is the substrate circuitry layout of the first programmable computing unit.
Fig. 4 is a kind of layout of programmable gate array.
Fig. 5 A indicate a kind of a variety of connection types of reconfigurable interconnection；Fig. 5 B indicate a kind of a variety of of programmable logic cells
Logic function
Fig. 6 A are the substrate circuitry layouts of second of programmable computing unit；Fig. 6 B are to may be programmed computing unit in Fig. 4
The sectional view of 100AA-100AD.
Fig. 7 is a kind of layout of programmable gate array specific implementation.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.In the present specification, "/" indicates the relationship of "and/or".
Specific implementation mode
Fig. 1 is a kind of three-dimensional writable memory（3D-W）Sectional view.3D-W is three-dimensional storage（3D-M）One kind,
The information of storage may be used electric mode and program typing.According to the number that it can be programmed, 3D-W is divided into be deposited for three-dimensional one-time programming
Reservoir（3D-OTP）With three-dimensional multiple programmable memory（3D-MTP）.Wherein, 3D-OTP can be programmed once, and 3D-MTP can program more
It is secondary.
Accumulation layer 16A, 16B that the 3D-W contains a substrate circuitry layer 0K and multiple stackings thereon and is stacked with.Lining
Bottom circuit layer 0K contains the peripheral circuit of accumulation layer, it includes transistor 0t and its interconnection line 0i.Wherein, transistor 0t is formed in
In semi-conductive substrate 0；Interconnection line 0i contains interconnection line layer 0M1-0M3.Each accumulation layer（Such as 16A）Contain multiple bit lines（Such as
2a, in the y-direction）, wordline（Such as 1a, in the x-direction）With storage member（Such as 16Aaa）.Each accumulation layer（Such as 16A）Contain multiple 3D-W
Array.All address wires are continuous in one 3D-W array, not with same accumulation layer（Such as 16A）In other 3D-W arrays
Shared address wire.Accumulation layer（Such as 16A）By contacting access opening（Such as 1av）It is coupled with substrate 0.
3D-W storages member 16Aaa contains one layer of programming film 12 and a layer diode film 14.It can be antifuse to program film 12
Film is used for 3D-OTP；It can also be other multiple programming films, be used for 3D-MTP.Diode film 14 has following generalized character：
Under read voltage, resistance is smaller；When applied voltage be less than read voltage or it is opposite with read voltage direction when, resistance is larger.
Diode film can be P-i-N diode, can also be metal oxide（Such as TiO2）Diode etc..
Fig. 2 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, setting end CFG includes setting data 125.When it is " writing " that data 125, which are arranged, can be calculated programmable
The LUT of basic complicated calculations needed for being written in unit 100.It, can be from programmable computing unit when it is " reading " that data 125, which are arranged,
The value in LUT is read in 100, to realize set basic complicated calculations, and generates corresponding output data 135.
Fig. 3 is the layout of the substrate circuitry 0K of the first programmable computing unit 100.Since 3D-W arrays are stacked on lining
Above the circuit 0K of bottom, not in the substrate, therefore projection of the 3D-W arrays on substrate 0 is only represented by dashed line.In this embodiment,
LUT is stored at least one 3D-W arrays 110.Substrate circuitry 0K includes the peripheral circuit of 3D-W arrays 110：Its X-decoder
15, Y-decoder+reading circuit 17 and Z decoders 19 etc..
Fig. 4 indicates a kind of programmable gate array 300.It is programmable single that it contains regularly arranged A groups programmable unit, B groups
Member, etc..Every group of programmable unit（Such as A groups）Contain multiple programmable computing units（Such as 100AA, 100AB, 100AC, 100AD
Deng）And programmable logic cells（Such as 200AA, 200AB, 200AC, 200AD）.In programmable computing unit and programmable logic
There is programmable channel 320,340 etc. between unit.Between the groups, also contain programmable channel 310,330,330 etc..For ripe
It knows for the professional person of this field, other than programmable channel, sea of gates can also be used（sea-of-gates）Isotype.
Two ways is programmed with to programmable channel.A kind of mode is similar to traditional programmable gate array, and wafer is only
Produce programmable channel（Or sea of gates）Before and hoard.After the function of programmable gate array determines, programmable channel
310-350 is customized by backend process.Another way is similar to traditional field programmable gate array（FPGA）, all can
Programming channel is made of reconfigurable interconnection.Wafer will complete all process steps（Including reconfigurable interconnection）And cut encapsulation chip.
Programming scene can define the function of programmable gate array by the way that reconfigurable interconnection is arranged.
Fig. 5 A indicate a kind of a variety of connection types of reconfigurable interconnection.The reconfigurable interconnection and United States Patent (USP) 4,870,302
The reconfigurable interconnection of middle disclosure is similar.The reconfigurable interconnection has one kind of following several connection types：a）Interconnection line 302,304
It is connected, interconnection line 306,308 is connected, but 302,304 are not attached to 306,308；b）Interconnection line 302,304,306,308 is homogeneous
Even；c）Interconnection line 306,308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306,308；d）Interconnection line 302,304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302,304；e）Interconnection line 302,304,306,306 is not attached to.It is right
In being familiar with for the professional person of this field, the reconfigurable interconnection of other forms is also adoptable.
Fig. 5 B indicate a kind of a variety of logic functions of programmable logic cells 200.Its input A and B be input data 210,
220, output C are output data 230.The programmable logic cells 200 programmable are patrolled with what is disclosed in United States Patent (USP) 4,870,302
It is similar to collect unit.At least one of following several logical operations may be implemented in the programmable logic cells 200：C=A, A logics
Logical operations and the simple arithmetic such as non-, A displacements, AND (A, B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B)
Operation A+B, A-B etc..Programmable logic cells 200 can also contain the sequential circuit elements such as register, trigger, with stream of practising
The operations such as waterline.For the professional person for being familiar with this field, the programmable logic cells 200 of other forms are also that can be used
's.
Fig. 6 A are the layouts of second of programmable computing unit 100.Since 3D-W arrays 110 do not account for Substrate Area, because
This programmable logic cells 200 can be integrated in 110 lower section of 3D-W arrays, and at least partly be covered by 3D-W arrays 110.Except this
Except, reconfigurable interconnection can also be also integrated into 110 lower section of 3D-W arrays, and at least partly covered by 3D-W arrays 110.Institute
There are these measures that can reduce the chip area of programmable gate array 300.
Fig. 6 B are the sectional views that may be programmed computing unit 100AA-100AD in Fig. 4.Since three can be carried out to 3D-W arrays
Dimension is integrated, may be programmed the 3D-W arrays 110AA in computing unit 100AA（Store LUT A, accumulation layer 16A）It may be stacked on substrate
On circuit 0K（The directions+z）, may be programmed the 3D-W arrays 110AB in computing unit 100AB（Store LUT B, accumulation layer 16B）
It may be stacked on 3D-W arrays 110AA（The directions+z）, may be programmed the 3D-W arrays 110AC in computing unit 100AC（Storage
LUT C, accumulation layer 16C）It may be stacked on 3D-W arrays 110AB（The directions+z）, may be programmed the 3D-W in computing unit 100AD
Array 110AD（Store LUT D, accumulation layer 16D）It may be stacked on 3D-W arrays 110AC（The directions+z）.At the same time it can also incite somebody to action
Programmable logic cells 200AA-200AD is integrated in substrate circuitry 0K, is at least partly covered by 3D-W arrays 110AA-210AD
Lid.The chip area of programmable gate array 300 will be further reduced in all these measures.
Fig. 7 is a kind of specific implementation of programmable gate array, it is for realizing a complicated calculations：e=a.sin(b)+c.cos
(d).In programmable channel, crosspoint has the reconfigurable interconnection of dot to indicate that cross spider is connected, crosspoint compiling without dot
Journey connection indicates that cross spider is not attached to, the reconfigurable interconnection of disconnection indicate the interconnection line disconnected be divided into two mutually it is disjunct mutually
Line section.In this embodiment, it may be programmed computing unit 100AA and be arranged to log (), result of calculation log (a) is sent to
The first input of programmable logic cells 200AA.Programmable computing unit 100AB is arranged to log [sin ()], calculates knot
Fruit log [sin (b)] is sent to the second input of programmable logic cells 200AA.Programmable logic cells 200AA is arranged to
" arithmetic adds ", result of calculation log (a)+log [sin (b)] are sent to programmable computing unit 100BA.Programmable computing unit
100BA is arranged to exp (), result of calculation exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to programmable logic
The first input of unit 200BA.Similarly, by setting appropriate, programmable computing unit 100AC, 100AD, it may be programmed and patrol
Collect the result c of unit 200AC, programmable computing unit 100BC.Cos (d) is sent to the second of programmable logic cells 200BA
Input.Programmable logic cells 200BA is arranged to " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent
To output e.It is obvious that by changing its setting, programmable gate array 300 can also realize other complicated calculations functions.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to the form and details of the present invention
It is modified, this does not interfere the spirit of their application present invention.Therefore, in addition to the spirit according to appended claims,
The present invention does not answer any way limited.
Claims (10)
1. a kind of programmable gate array, it is characterised in that containing multiple programmable computing units, including：
First programmable computing unit, the first programmable computing unit contain at least first three-dimensional writable memory（3D-W）Battle array
Row, the first 3D-W arrays store the look-up table of first function（LUT）；
Second programmable computing unit, the second programmable computing unit contain at least the 2nd 3D-W arrays, the 2nd 3D-W gusts
The LUT of row storage second function；
This first and the second function be different functions.
2. programmable gate array according to claim 1, it is further characterized in that containing：
Multiple programmable logic cells, each programmable logic cells optionally realize Different Logic and/or arithmetic function；
First reconfigurable interconnection, at least partly described programmable computing unit pass through second reconfigurable interconnection and at least partly institute
Programmable logic cells are stated selectively to be electrically coupled.
3. programmable gate array according to claim 2, it is further characterized in that containing：
Multiple input；
Second reconfigurable interconnection, at least partly described input pass through the third reconfigurable interconnection and at least partly described programmable meter
It calculates unit and/or at least partly described programmable logic cells is selectively electrically coupled.
4. programmable gate array according to claim 2, it is further characterized in that containing：
Multiple outputs；
Third reconfigurable interconnection, at least partly described output pass through the 4th reconfigurable interconnection and at least partly described programmable meter
It calculates unit and/or at least partly described programmable logic cells is selectively electrically coupled.
5. programmable gate array according to claim 1, it is further characterized in that：The first and second 3D-W arrays are three
Tie up one-time programming memory（3D-OTP）.
6. programmable gate array according to claim 1, it is further characterized in that：The first and second 3D-W arrays are three
Tie up multiple programmable memory（3D-MTP）.
7. programmable gate array according to claim 2, it is further characterized in that：It is programmable that the 3D-W arrays are stacked on this
Above logic circuit.
8. programmable gate array according to claim 7, it is further characterized in that：The 3D-W arrays covering at least partly should
Programmable logic circuit.
9. programmable gate array according to claim 1, it is further characterized in that：2nd 3D-W arrays be stacked on this first
Above 3D-W arrays.
10. programmable gate array according to claim 9, it is further characterized in that：2nd 3D-W arrays cover this first
3D-W arrays.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710122749.7A CN108540126A (en) | 2017-03-03 | 2017-03-03 | Programmable gate array based on three-dimensional writable memory |
| US15/450,049 US9838021B2 (en) | 2016-03-05 | 2017-03-06 | Configurable gate array based on three-dimensional writable memory |
| US15/784,077 US10116312B2 (en) | 2016-03-05 | 2017-10-13 | Configurable gate array based on three-dimensional writable memory |
| US15/793,912 US10075168B2 (en) | 2016-03-05 | 2017-10-25 | Configurable computing array comprising three-dimensional writable memory |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
| US16/693,370 US10848158B2 (en) | 2016-02-13 | 2019-11-24 | Configurable processor |
| US17/065,604 US11128302B2 (en) | 2016-02-13 | 2020-10-08 | Configurable processor doublet based on three-dimensional memory (3D-M) |
| US17/065,632 US11128303B2 (en) | 2016-02-13 | 2020-10-08 | Three-dimensional memory (3D-M)-based configurable processor singlet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710122749.7A CN108540126A (en) | 2017-03-03 | 2017-03-03 | Programmable gate array based on three-dimensional writable memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108540126A true CN108540126A (en) | 2018-09-14 |
Family
ID=63489139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710122749.7A Pending CN108540126A (en) | 2016-02-13 | 2017-03-03 | Programmable gate array based on three-dimensional writable memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108540126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698692A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Using two-sided integrated programmable gate array |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07209772A (en) * | 1994-01-25 | 1995-08-11 | Konica Corp | Image processing method and device for color output |
| CN1401140A (en) * | 2000-08-14 | 2003-03-05 | 矩阵半导体公司 | Dense arrays and charge storage devices, and methods for making same |
| CN1474283A (en) * | 2003-08-04 | 2004-02-11 | 深圳大学 | Information hidden encrypting/decrypting method and device based on virtual imaging |
| US20050071401A1 (en) * | 2001-07-30 | 2005-03-31 | Ati Technologies, Inc. | Method and system for approximating sine and cosine functions |
| CN101266463A (en) * | 2008-04-29 | 2008-09-17 | 江南大学 | Fuzzy controller based on FPGA |
| CN103094249A (en) * | 2011-10-31 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Three dimensional integrated circuit connection structure and method |
| CN105487812A (en) * | 2014-10-01 | 2016-04-13 | 三星电子株式会社 | Method for supporting in-memory processing and memory module |
| CN105958995A (en) * | 2016-04-27 | 2016-09-21 | 北京时代民芯科技有限公司 | Circuit and method for fast starting FPGA |
-
2017
- 2017-03-03 CN CN201710122749.7A patent/CN108540126A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07209772A (en) * | 1994-01-25 | 1995-08-11 | Konica Corp | Image processing method and device for color output |
| CN1401140A (en) * | 2000-08-14 | 2003-03-05 | 矩阵半导体公司 | Dense arrays and charge storage devices, and methods for making same |
| US20050071401A1 (en) * | 2001-07-30 | 2005-03-31 | Ati Technologies, Inc. | Method and system for approximating sine and cosine functions |
| CN1474283A (en) * | 2003-08-04 | 2004-02-11 | 深圳大学 | Information hidden encrypting/decrypting method and device based on virtual imaging |
| CN101266463A (en) * | 2008-04-29 | 2008-09-17 | 江南大学 | Fuzzy controller based on FPGA |
| CN103094249A (en) * | 2011-10-31 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Three dimensional integrated circuit connection structure and method |
| CN105487812A (en) * | 2014-10-01 | 2016-04-13 | 三星电子株式会社 | Method for supporting in-memory processing and memory module |
| CN105958995A (en) * | 2016-04-27 | 2016-09-21 | 北京时代民芯科技有限公司 | Circuit and method for fast starting FPGA |
Non-Patent Citations (1)
| Title |
|---|
| YI-CHUNG CHEN等: "A Look Up Table design with 3D bipolar RRAMs", 《17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698692A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Using two-sided integrated programmable gate array |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11711082B2 (en) | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells | |
| US11869847B2 (en) | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits | |
| CN109616463A (en) | Chip-packaging structure | |
| CN106374912B (en) | A kind of logical operation circuit and operating method | |
| CN104424134B (en) | A kind of storage arrangement and its manufacture method | |
| CN105070735B (en) | Three-dimensional resistive memory and its operating method | |
| CN105097019A (en) | Semiconductor devices and related programming methods | |
| CN107154798A (en) | Programmable gate array based on three-dimensional writable memory | |
| JPS58153A (en) | Device for deciding wiring route | |
| CN102682848B (en) | Storage arrangement, memory card, solid-state drive, system and operational approach thereof | |
| CN110010612A (en) | Memory device with three-dimensional structure | |
| US20090164203A1 (en) | Non-volatile memory compiler | |
| CN104733041A (en) | Nonvolatile memory device and method of erasing nonvolatile memory device | |
| CN107093463B (en) | Array of bit-level cells, compound advanced memory and computer system | |
| CN101447230A (en) | Programming methods for nonvolatile memory | |
| CN107154797A (en) | The programmable gate array of reservoir is recorded based on three-dimensional print | |
| CN109872734A (en) | Dynamic distributed power control circuit | |
| CN106373609A (en) | Memory system including semiconductor memory device and operating method thereof | |
| CN107845400A (en) | Resistance-change memory device and for operating its circuit and method | |
| CN107134295A (en) | Memory diagnostic system | |
| CN105264775B (en) | Multidigit full adder and its operating method based on resistive device | |
| Zulehner et al. | A staircase structure for scalable and efficient synthesis of memristor-aided logic | |
| CN108540126A (en) | Programmable gate array based on three-dimensional writable memory | |
| CN102479919A (en) | Flux programmed multi-bit magnetic memory | |
| JP2010015328A (en) | Memory/logic conjugate system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.16, 34th floor, building 2, No.88, Jitai fifth road, high tech Zone, Chengdu, Sichuan, 640041 Applicant after: ChengDu HaiCun IP Technology LLC Address before: B-36, 6 Yongfeng Road, Chengdu, Sichuan 610041 Applicant before: ChengDu HaiCun IP Technology LLC |
|
| CB02 | Change of applicant information |