CN104037131A - Technique of using thermal oxide for gate dielectric for select gate and partial replacement gate - Google Patents

Technique of using thermal oxide for gate dielectric for select gate and partial replacement gate Download PDF

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Publication number
CN104037131A
CN104037131A CN201410061231.3A CN201410061231A CN104037131A CN 104037131 A CN104037131 A CN 104037131A CN 201410061231 A CN201410061231 A CN 201410061231A CN 104037131 A CN104037131 A CN 104037131A
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China
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layer
region
logic
polysilicon layer
control grid
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M·D·霍尔
M·D·施罗夫
F·K·小巴克尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority claimed from US13/790,004 external-priority patent/US9087913B2/en
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN104037131A publication Critical patent/CN104037131A/en
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

The invention relates to a technique of using a thermal oxide for a gate dielectric for a select gate and a partial replacement gate. A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and a barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and the barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and the control gate and defines a select gate location laterally adjacent to the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and the polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Description

The gate dielectric of selecting grid and part to replace grid is used to thermal oxide
Technical field
The disclosure is usually directed to nonvolatile memory, more specifically to integrating nonvolatile memory and logic transistor on same integrated circuit.
Background technology
A lot of semiconductor device comprise or embed the nonvolatile memory with other transistor types on same integrated circuit (IC).The manufacture craft of different crystal tubing type may be not identical, requires technique to be integrated.For example, for integrated NVM and CMOS (complementary metal oxide semiconductors (CMOS)), CMOS technique can be modified to include makes NVM memory cell and supports the necessary processing step of device.
Flash memory NVM is embedded in SOC (system on a chip) (SoC) integrated circuit that for example has CMOS logical circuit conventionally.Flash memory NVM may comprise the floating grid containing polysilicon, or use comprise nanocrystal or ONO(oxide-nitride thing-oxide) charge storage layer of layer.。Memory cell may also comprise control grid, and described control grid comprises polysilicon, metal or both.In addition, may wish to use high k(in logic transistor wherein k refer to the dielectric constant of material) gate dielectric.Integrating nonvolatile memory cell and have the logic transistor of metal gates and high k gate dielectric may require a lot of additional process steps on same integrated circuit.
Needed is that a kind of technology integrating method is effectively to embed metal gates/high k dielectric medium logic transistor to NVM cell array.
Brief description of the drawings
The present invention do not illustrate and limited by accompanying drawing by way of example, and similarly reference symbol represents identical element in the accompanying drawings.Element explanation in accompanying drawing is for easy and clear, not necessarily draws in proportion.
Fig. 1, according to an embodiment, is the cross section of the semiconductor device in a stage of work in-process;
Fig. 2 is the cross section at the semiconductor device of Fig. 1 of a subsequent stage of processing;
Fig. 3 is the cross section at the semiconductor device of Fig. 2 of a subsequent stage of processing;
Fig. 4 is a part that has shown more in detail the semiconductor device showing in Fig. 3;
Fig. 5 is the cross section at the semiconductor device of Fig. 3 of a subsequent stage of processing;
Fig. 6 is the cross section at the semiconductor device of Fig. 5 of a subsequent stage of processing;
Fig. 7 is the cross section at the semiconductor device of Fig. 6 of a subsequent stage of processing;
Fig. 8 is the cross section at the semiconductor device of Fig. 7 of a subsequent stage of processing;
Fig. 9 is the cross section at the semiconductor device of Fig. 8 of a subsequent stage of processing;
Figure 10 is the cross section at the semiconductor device of Fig. 9 of a subsequent stage of processing;
Figure 11 is the cross section at the semiconductor device of Figure 10 of a subsequent stage of processing;
Figure 12 is the cross section at the semiconductor device of Figure 11 of a subsequent stage of processing;
Figure 13 is the cross section at the semiconductor device of Figure 12 of a subsequent stage of processing;
Figure 14 is the cross section at the semiconductor device of Figure 13 of a subsequent stage of processing;
Figure 15 is the cross section at the semiconductor device of Figure 14 of a subsequent stage of processing;
Figure 16 is the cross section at the semiconductor device of Figure 15 of a subsequent stage of processing;
Figure 17 is the cross section at the semiconductor device of Figure 16 of a subsequent stage of processing; And
Figure 18 is the cross section at the semiconductor device of Figure 17 of a subsequent stage of processing.
Embodiment
On the one hand, integrated integrated NVM and the logic on single integrated circuit effectively of non-volatile memories (NVM) unit and logic transistor.This integrated technology utilizes thermal oxide for selecting grid and part to replace the gate dielectric of grid with the metal gates of acquisition logical device.Can understand better by reference to accompanying drawing and description below.
Semiconductor substrate described in the invention can be any Semiconductor substrate with end face that can thermal oxidation.
What Fig. 1 showed is semiconductor device 10.Described device has Semiconductor substrate 16, be positioned at NVM region 12 on a part or the part of substrate 16, be positioned at the logic region 14 on a part or the part of substrate 16 and be positioned at the hard mask layer 18 on substrate 16.In same substrate 16 or on, can also have other region.The technique that is used to form unity logic transistor and single NVM unit will show and be by other transistor forming in these regions and the demonstration of memory cell in accompanying drawing subsequently.Hard mask layer 18 can be nitride and can approximately 100 dusts thick.Other material and thickness also can be used.
What Fig. 2 showed is at the semiconductor device 10 after NVM region 12 removes hard mask layer 18.The mask not showing is used to carry out this etching.
What Fig. 3 showed is on the NVM region 12 on substrate 16 and mask layer 18 on logic region 14 on semiconductor device 10 after deposited charge accumulation layer 20.
What Fig. 4 showed is more detailed charge storage layer 20.Charge storage layer 20 has the dielectric layer 22 that is positioned on substrate 16, is multiplely positioned at the nanocrystal 24 of the nanocrystal that comprises demonstration 28 on dielectric layer 22 and is positioned on dielectric layer 22 and is positioned on nanocrystal 24 or around the dielectric layer 26 of nanocrystal 24.Preferably oxide of dielectric layer 22 and 26.Dielectric layer 22 be wherein electric charge by wherein flow into nanocrystal 24 for programming dielectric layer and nanocrystal 24 and raceway groove between gate dielectric.Dielectric layer 26 is that electric charge flows out the wherein dielectric layer for wiping from nanocrystal 24.Nanocrystal 24 preferably silicon can stand step of thermal oxidation subsequently.
What Fig. 5 showed is on the charge storage layer 20 in NVM region 12 and logic region 14, to form a kind of grid material 30 semiconductor device afterwards.Can the have an appointment thickness of 800-1000 dust of grid material 30.Grid material 30 can be metal.Described metal can provide benefit on polysilicon.Polysilicon also can be used.Grid material 30 can also be the stacking of electric conducting material.Described electric conducting material can comprise metal and polysilicon.
What Fig. 6 showed is the semiconductor device 10 after etching grid material 30 and charge storage layer 20.Except patterning grid material 30, do not need grid material 30 to make any change, but result is the control grid 32 as functional structure in NVM region 12.Grid material 30, charge storage layer 20 and hard mask layer 18 remove the end face of substrate 16 are exposed in logic region 14 from logic region 14.The top section of substrate 16 is also exposed in NVM region 12, the part existing except controlling grid 32.
What Fig. 7 showed is on the described expose portion of NVM region 12 and logic region 14 and control the semiconductor device 10 after forming dielectric layer 21 on grid 32.Dielectric layer 21 on substrate 16 is by heat growth and can be called as thermal oxide layer, and wherein it is with hot oxide skin(coating) of growing instead of the oxide skin(coating) of deposition.The dielectric layer 21 of controlling on grid is also oxide, but major part is the oxide skin(coating) of deposition.Therefore, dielectric layer 21 can be called as oxide skin(coating) 21.The oxide skin(coating) 21 of controlling on grid 32 forms with anisotropic etching subsequently by first depositing conformal oxide layer, and wherein this anisotropic etching has formed sidewall spacer and removed conformal oxide layer from substrate 16 around controlling grid 32.Then carry out step of thermal oxidation, this causes oxide skin(coating) 21 to be grown on substrate 16.The growth of the oxide skin(coating) 21 on substrate 16 is to carry out at relatively high temperature; If metal level was previously formed, this temperature is greater than the temperature that may cause damaging metal level.Consequently the oxide skin(coating) 21 on substrate 16 is gate-dielectrics high-quality and the selection grid that effectively conduct will be formed.Oxide skin(coating) 21 can be than thicker on substrate 16 on control grid 32, and on control grid 32, it is almost all deposited and only growth slightly, and it can only be grown on substrate 16.On layer 23 oxide skin(coating) 21 being formed in NVM region 12 and logic region 14 of polysilicon.Polysilicon layer 23 is thicker than oxide skin(coating) 21, but thinner than the highly significant ground of controlling grid 32.During the processing of logic region 14, the effect that layer 23 plays hard mask, and aspect protection oxide skin(coating) 21 particular importance, at this, it is positioned on substrate 16 and plays the effect of the gate-dielectric of the selection grid that will be formed.
What Fig. 8 showed is the semiconductor device 10 after removing oxide skin(coating) 21 and polysilicon layer 23 from logic region 14 and depositing high k dielectric layer 34 and metal level 35, and wherein said metal level 35 arranges the work function that plays the logic transistor that will be formed the effect of layer.
What Fig. 9 showed is the semiconductor device 10 after removing high k dielectric layer 34 and metal level 35 from NVM region 12.
What Figure 10 showed is the semiconductor device 10 after forming polysilicon layer 36, and wherein it is obtained by deposit spathic silicon layer, and polysilicon layer merges with polysilicon layer 23 in NVM region 12, but only on metal level 35, deposits in logic region 14.Result is exactly thicker than on logic region 14 of interior polysilicon layer 36 in NVM region 12.
What Figure 11 showed is to carry out planarization on layer 36, for example chemico-mechanical polishing (CMP) has the plane form of the height identical with the height of controlling grid 32 semiconductor device 10 afterwards so that layer 36 is arranged in, and wherein polysilicon layer 23 and 36 merges to simple layer.CMP process can be above that first deposition of sacrificial layer, to support protrusion, and reduces the possibility of the local fault in protrusion place thus.
What Figure 12 showed is the semiconductor device 10 after the photoresist 38 that forms patterning, wherein the photoresist 38 of patterning has the Part I in NVM region 12 on control grid 32, and described control grid 32 has the first side wall 39 that extends to limit selection grid away from the first side wall 33 of controlling grid 32.The Part I of the photoresist 38 of the patterning in NVM region 12 has the second sidewall 41 substantially aliging with oxide skin(coating) 21, the second sidewall 37 at this oxide skin(coating) 21 along control grid 32.The second sidewall 37 of controlling grid 32 is relative with the first side wall 33 of controlling grid 32.The horizontal breadth of oxide skin(coating) 21 along the sidewall of controlling grid 32 is at least preferably the twice of the alignment tolerance of the second sidewall 41 of the photoresist 38 in NVM region 12, the second sidewall 41 of the photoresist 38 in NVM region 12 is neither positioned at control not also to be positioned on grid 32 on polysilicon layer 36 but only along controlling on the oxide skin(coating) 21 of the second sidewall 37 of grid 32.The photoresist 38 of patterning has the Part II that is used to the grid that limits logic transistor in logic region 14.
What Figure 13 showed is the photoresist of patterning 38 is carried out to etching as mask so that the Part I of the polysilicon layer 36 in NVM region 12 adjacent to the control grid 32 in NVM region 12 and make the Part II of polysilicon layer 36 be positioned at logic region 14 semiconductor device 10 afterwards, wherein said Part I is to select grid and can be called as to select grid 61, and described Part II can be called as dummy grid 63.What also remove is the part that the photoresist not being patterned 38 of oxide skin(coating) 21 covers.Oxide skin(coating) 21 can be retained in to be controlled on grid 32.During technique subsequently, dummy grid 63 will be substituted by a kind of metallic stuffing.In alternate embodiment, patterning selects the step of grid and pseudo-logic gate in independent step, to complete.
What Figure 14 showed is at formation sidewall spacer and carries out the semiconductor device 10 injecting for after forming transistor in typical mode, the sidewall spacer 40 that this causes polysilicon layer 36 and controls the surrounding of the Part I of grid 32, snap in fact the regions and source/drain 44 in the substrate 16 of the first side wall of selecting grid 61, snap in fact the regions and source/drain 46 of the second sidewall of controlling grid 32, around the sidewall spacer 42 of dummy grid 63, snap in fact the regions and source/drain 48 of the first side wall of dummy grid 63, and snap in fact the regions and source/drain 50 of the second sidewall of dummy grid 63.After forming source/drain, grid and regions and source/drain can be by silication (silicided) by use traditional handicraft.Sidewall spacer 40 and 42 can additionally have the lining between grid and sept.In alternate embodiment, the formation of regions and source/drain 44 and 46 can separate with the formation of regions and source/drain 48 and 50.
What Figure 15 showed is to form then CMP semiconductor device 10 afterwards of interlayer dielectric (ILD) 52 by deposition.Therefore Figure 15 has shown that ILD52 has some parts around sidewall spacer 40 and 42.CMP causes selecting grid 61, control grid 32 and dummy grid to be exposed.During sidewall spacer 40 and 42 forms, CMP has removed the little gap area that may be formed between the top section of selecting grid 61 and controlling grid 32.
What Figure 16 showed is on NVM region 12, to form hard mask layer 43 and remove subsequently the semiconductor device 10 after dummy grid 63.Hard mask layer 43 can comprise silicon nitride.Removing of dummy grid 63 can complete in the situation that there is no mask.Hard mask layer 43 can deposit by covering (blanket deposition) and form, and then removes the part on logic region of this covering deposition.Removing at the end face of sidewall spacer 42 inner sides and metal level 35 of dummy grid 63 left opening 45, and this metal level 35 is that the work function exposing arranges layer.
What Figure 17 showed is the semiconductor device 10 after the grid material 56 that forms filling opening 45, and this opening 45 is to form by the dummy grid 63 that removes shown in Figure 16.Grid material 56 can be certain combination of metal or metal and polysilicon.
What Figure 18 showed is the semiconductor device 10 after carrying out CMP.Result is that hard mask layer 43 and grid material 56 are removed in NVM region 12, and is removed in the logic region 14 of grid material 56 on ILD52.This makes to have left logic gate 56 in the logic region 14 in the opening 45 of sidewall spacer 42 inner sides that is contained in Figure 16 demonstration.This causes the NVM unit having had in NVM region 12 and the logic transistor having had in logic region 14.
Therefore the effective means that forms NVM memory cell and logic transistor is implemented.Wherein gate dielectric can be hot growth or high k, and grid can be polysilicon or metal, and accumulation layer can be polysilicon or metal nanocrystal.In alternate embodiment, accumulation layer can be nitride.
Should be appreciated that at present a kind of method of making logic transistor and making non-volatile memories (NVM) unit in the logic region of substrate in the NVM region of described substrate that discloses, described method is included in formation on the substrate in described NVM region and covers the control grid on charge storage layer.Described method is also included on the described substrate in described NVM region, heat growth containing oxygen dielectric layer on described substrate on described control grid and in described logic region.Described method also comprise remove from described logic region described containing oxygen dielectric layer.Described method is also included in and on the described substrate in described logic region, forms high k gate dielectric.Described method is also included on the described high k gate dielectric in described logic region and forms barrier layer.Form polysilicon layer the containing on oxygen dielectric layer and the described barrier layer in described logic region of described heat growth that described method is also included in described NVM region.Described method also comprises polysilicon layer described in complanation.Described method is also included in the described polysilicon layer in described NVM region and controls on grid and forms the first mask layer (masking layer), and wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region.Described method is also included on the described polysilicon layer in described logic region and forms the second mask layer, and wherein said the second mask layer defines logic gate position in described logic region.Described method also comprises that described the first mask layer of use is to remove the expose portion of the described polysilicon layer in described NVM region, and the Part I of wherein said polysilicon layer is retained in described selection gate location and sentences formation selection grid.Described method also comprises that described the second mask layer of use is to remove the expose portion of the described polysilicon layer in described logic region, and the Part II of wherein said polysilicon layer is retained in described logic gate position.Described method is also included in described NVM region and described logic region and forms dielectric layer, and wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described polysilicon layer.Described method also comprises described in complanation that dielectric layer is to expose the described Part II of described polysilicon layer.Described method also comprises that the described Part II that removes described polysilicon layer is to cause opening in described logic gate position, and wherein said opening has exposed described barrier layer.The described step that described method can be considered to form described the first mask layer is performed described the first mask layer is located immediately on described control grid, and the first edge of described the first mask layer extends transverse to described polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid.Described method can be considered to form protective layer on described selection grid in described NVM region and described control grid, and wherein said protective layer has exposed described logic region.Described method can also be included in form described heat growth containing before the described step of oxygen dielectric layer, on the sidewall of described control grid, form oxide spacer.Described method can be considered to the part that described the first mask layer and described the second mask layer are the mask layers of identical patterns, and wherein uses described the first mask layer to remove the expose portion of the described polysilicon layer in described NVM region and to use described the second mask layer to be performed with the described step of the expose portion that removes the described polysilicon layer in described logic region simultaneously.Described method can be considered to described barrier layer and comprise that work function arranges metal.Described method can be considered to form on the described substrate in described NVM region wherein the described step that overlays on the described control grid on described charge storage layer and be included on the described substrate in described NVM region and described logic region and form described charge storage layer; On described charge storage layer in described NVM region and described logic region, form the second polysilicon layer; Described in patterning, the second polysilicon layer and described charge storage layer to form described control grid and to remove described the second polysilicon layer and described charge storage layer from described logic region in described NVM region.Described method can be considered to after forming described selection grid, and the part containing oxygen dielectric layer of described heat growth is between described selection grid and described control grid.Described method can be considered at described the first and second mask layers of use with after removing the described step of expose portion of the described polysilicon layer in described NVM region and described logic region, described method also comprises: laterally forming the first regions and source/drain and form the second regions and source/drain in the horizontal described substrate adjacent to described control grid in the described substrate adjacent to described selection grid, make described selection grid and described control grid between described the first and second regions and source/drain; And in the horizontal described substrate adjacent to the first side wall of the described Part II of described polysilicon layer, form the 3rd regions and source/drain and laterally forming the 4th regions and source/drain in the described substrate adjacent to the second sidewall of the described Part II of described polysilicon layer.Described method can be considered to using described the first and second mask layers with after removing the described step of expose portion of the described polysilicon layer in described NVM region and described logic region, and described method also comprises and forms around the first side wall sept of the lateral wall of described selection grid and described control grid and form around the second sidewall spacer of the described Part II of described polysilicon layer.Described method can also be included in from described logic region remove described heat growth containing before the described step of oxygen dielectric layer, form the second polysilicon layer in containing on oxygen dielectric layer of described heat growth, wherein said polysilicon layer is formed on described the second polysilicon layer, and the described step containing oxygen dielectric layer that removes described heat growth also comprises from described logic region and removes described the second polysilicon layer.The described step that described method can be considered to form described high k gate dielectric and form described barrier layer is included on the described substrate in described the second polysilicon layer and the described logic region in described NVM region and forms described high k gate dielectric; On described high k gate dielectric in described NVM region and described logic region, form described barrier layer; And remove described high k gate dielectric and described barrier layer from described NVM region.Described method can be considered to described charge storage layer and comprise at least one in nanocrystal or nitride.Described method can be considered to remove described polysilicon layer described Part II with after described logic gate position causes the described step of described opening, described method is also included in and in described opening on the described barrier layer on the described protective layer in described NVM region and in described logic region, forms logic gate layer; And logic gate layer is to cause logic gate in described logic gate position described in complanation, wherein said complanation has removed described protective layer from described NVM region.
Also disclosed is a kind of method of making logic transistor and making non-volatile memories (NVM) unit in the logic region of substrate in the NVM region of described substrate.Described method is included on the described substrate in described NVM region and forms the control grid covering on charge storage layer, and wherein said control grid comprises polysilicon.Described method is also included on the sidewall of described control grid and forms oxide spacer.Described method is also included on the described substrate in described NVM region, heat growth containing oxygen dielectric layer on described substrate on described control grid and in described logic region.Described method also comprise remove from described logic region described containing oxygen dielectric layer.Described method is also included in and on the described substrate in described logic region, forms high k gate dielectric.Described method is also included on the described high k gate dielectric in described logic region and forms barrier layer.Form polysilicon layer the containing on oxygen dielectric layer and the described barrier layer in described logic region of described heat growth that described method is also included in described NVM region.Described method also comprises polysilicon layer described in complanation, wherein said heat growth comprise containing oxygen dielectric layer the sidewall sections of placing along the sidewall of described control grid.Described method is also included in the described polysilicon layer in described NVM region and controls on grid and forms the first mask layer, wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region, wherein said the first mask layer is located immediately on described control grid, and the first edge of described the first mask layer extends transverse to described polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid.Described method is also included on the described polysilicon layer in described logic region and forms the second mask layer, and wherein said the second mask layer defines logic gate position in described logic region.Described method also comprises that described the first mask layer of use is to remove the expose portion of the described polysilicon layer in described NVM region, and the Part I of wherein said polysilicon layer is retained in described selection gate location and sentences formation selection grid.Described method also comprises that described the second mask layer of use is to remove the expose portion of the described polysilicon layer in described logic region, and the Part II of wherein said polysilicon layer is retained in described logic gate position.Described method is also included in described NVM region and described logic region and forms dielectric layer, and wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described polysilicon layer.Described method also comprises described in complanation that dielectric layer is to expose the described Part II of described polysilicon layer.Described method is also included on described selection grid in described NVM region and described control grid and forms protective layer, and wherein said protective layer has exposed described logic region.Described method also comprises that the described Part II that removes described polysilicon layer is to cause opening in described logic gate position, and wherein said opening has exposed described barrier layer.Described method is also included in formation logic gate layer in the described opening on the described barrier layer on the described protective layer in described NVM region and in described logic region.Described method also comprises that logic gate layer is to cause logic gate in described logic gate position described in complanation, and wherein said complanation has removed described protective layer from described NVM region.Described method can also be included in from described logic region remove described heat growth containing before the described step of oxygen dielectric layer, described heat growth form the second polysilicon layer containing on oxygen dielectric layer, and the described step containing oxygen dielectric layer that wherein removes described heat growth also comprises from described logic region and removes described the second polysilicon layer.The described step that described method can be considered to form described high k gate dielectric and form described barrier layer is included on the described substrate in described the second polysilicon layer and the described logic region in described NVM region and forms described high k gate dielectric; On described high k gate dielectric in described NVM region and described logic region, form described barrier layer; And remove described high k gate dielectric and described barrier layer from described NVM region.Described method can be considered at the mask layer that uses described patterning with after removing the described step of expose portion of described polysilicon layer and form the described step of described protective layer in described NVM region and described logic region before, described method is also included in laterally and forms the first regions and source/drain and laterally forming the second regions and source/drain in the described substrate adjacent to described control grid, make described selection grid and described control grid between described the first and second regions and source/drain in the described substrate adjacent to described selection grid; In the horizontal described substrate adjacent to the first side wall of the described Part II of described polysilicon layer, form the 3rd regions and source/drain and laterally forming the 4th regions and source/drain in the described substrate adjacent to the second sidewall of the described Part II of described polysilicon layer; And form around the first side wall sept of the lateral wall of described selection grid and described control grid.Described method can also be considered to described barrier layer and comprise that work function arranges metal.
Also disclosed is a kind of method of making logic transistor and making non-volatile memories (NVM) unit in the logic region of substrate in the NVM region of described substrate.Described method is included on the described substrate in described NVM region and forms the control grid overlaying on charge storage layer, and wherein said control grid comprises that polysilicon and described charge storage layer comprise at least one in nanocrystal or nitride.Described method be also included on the described substrate on described substrate in described NVM region and described control grid and in described logic region, form heat growth containing oxygen dielectric layer.Form the first polysilicon layer the containing on oxygen dielectric layer of described heat growth that described method is also included in described NVM region and described logic region.Described method also comprise remove from described logic region described containing oxygen dielectric layer and described the first polysilicon layer.Described method is also included on the described substrate on described first polysilicon layer in described NVM region and in described logic region and forms high k gate dielectric.Described method is also included on the described high k gate dielectric in described NVM region and described logic region and forms barrier layer.Described method also comprises from described NVM region and removes described high k gate dielectric and described barrier layer.Described method is also included on the described barrier layer on described first polysilicon layer in described NVM region and in described logic region and forms the second polysilicon layer.Described method also comprises the second polysilicon layer described in complanation, wherein said heat growth comprise containing oxygen dielectric layer the sidewall sections of placing along the sidewall of described control grid.Described method is also included in the described polysilicon layer in described NVM region and controls on grid and forms the first mask layer, wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region, wherein said the first mask layer is located immediately on described control grid, and the first edge of described the first mask layer extends transverse to described polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid.Described method is also included on described the second polysilicon layer in described logic region and forms the second mask layer, and wherein said the second mask layer defines logic gate position in described logic region.Described method also comprises that described the first mask layer of use is to remove the expose portion of described the second polysilicon layer in described NVM region, and the Part I of wherein said the second polysilicon layer is retained in described selection gate location and sentences formation selection grid.Described method also comprises that described the second mask layer of use is to remove the expose portion of described the second polysilicon layer in described logic region, and the Part II of wherein said the second polysilicon layer is retained in described logic gate position.Described method is also included in described NVM region and described logic region and forms dielectric layer, and wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described the second polysilicon layer.Described method also comprises described in complanation that dielectric layer is to expose the described Part II of described the second polysilicon layer.Described method is also included on described selection grid in described NVM region and described control grid and forms protective layer, and wherein said protective layer has exposed described logic region.Described method also comprises that the described Part II that removes described the second polysilicon layer is to cause opening in described logic gate position, and wherein said opening has exposed described barrier layer.Described method is also included in formation logic gate layer in the described opening on the described barrier layer on the described protective layer in described NVM region and in described logic region.Described method also comprises that logic gate layer is to cause logic gate in described logic gate position described in complanation, and wherein said complanation has removed described protective layer from described NVM region.
Although description of the invention, with reference to specific embodiment, is stated as the claims of enclosing, and without departing from the present invention, can carry out various amendments and variation.For example, various sizes can be different from those descriptions.Therefore, it is illustrative instead of restrictive that specification and accompanying drawing are considered to, and all such modifications are will list in the scope of the invention.About specific embodiment, any benefit, advantage or solution described in the invention is not intended to be interpreted as primary, essential or requisite feature or the element of any or all protection range.
In addition, word used herein " a " or " an " (" one " or " one ") are restricted to one or more.And; importing phrase used in claims should not be interpreted as implying that as " at least one " and " one or more " other claimed element of introducing by indefinite article " a " or " an " (" one " or " one ") limits any specific rights of the claimed element that contains this introducing and requires to disclose only to contain the element in the of, even import phrase " one or more " or " at least one " and indefinite article for example " a " or " an " (" one " or " one ") when same claim comprises.The use of definite article is also like this.
Except as otherwise noted, using term is element for distinguishing arbitrarily these term descriptions as " first " and " second ".Therefore, these terms not necessarily represent other order of priority of time or these elements.

Claims (20)

1. the method for making logic transistor and making non-volatile memories NVM unit in the logic region of substrate in the non-volatile memories NVM region of described substrate, comprising:
On described substrate in described NVM region, form the control grid overlaying on charge storage layer;
What on the described substrate on the described substrate in described NVM region and described control grid and in described logic region, formation heat was grown contains oxygen dielectric layer;
From described logic region remove described heat growth containing oxygen dielectric layer;
On described substrate in described logic region, form high k gate dielectric;
On described high k gate dielectric in described logic region, form barrier layer;
Form polysilicon layer the containing on the described barrier layer on oxygen dielectric layer and in described logic region of described heat growth in described NVM region;
Polysilicon layer described in complanation;
On described polysilicon layer in described NVM region and control grid, form the first mask layer, wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region;
On described polysilicon layer in described logic region, form the second mask layer, wherein said the second mask layer defines logic gate position in described logic region;
Remove the expose portion of the described polysilicon layer in described NVM region with described the first mask layer, the Part I of wherein said polysilicon layer is retained in described selection gate location and sentences formation selection grid;
Remove the expose portion of the described polysilicon layer in described logic region with described the second mask layer, the Part II of wherein said polysilicon layer is retained in described logic gate position;
In described NVM region and described logic region, form dielectric layer, wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described polysilicon layer;
Described in complanation, dielectric layer is to expose the described Part II of described polysilicon layer; And
Remove the described Part II of described polysilicon layer to cause opening in described logic gate position, wherein said opening has exposed described barrier layer.
2. method according to claim 1, the step that wherein forms described the first mask layer is performed and makes:
Described the first mask layer is located immediately on described control grid, and
The first edge of described the first mask layer extends transverse to described polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid.
3. method according to claim 1, also comprises:
On described selection grid in described NVM region and described control grid, form protective layer, wherein said protective layer has exposed described logic region.
4. method according to claim 1, also comprises:
Form described heat growth containing before the step of oxygen dielectric layer, on the sidewall of described control grid, form oxide spacer.
5. method according to claim 1, the part that wherein said the first mask layer and described the second mask layer are the mask layers of identical patterns, and wherein remove the expose portion of the described polysilicon layer in described NVM region with described the first mask layer and be performed simultaneously by the step that described the second mask layer removes the expose portion of the described polysilicon layer in described logic region.
6. method according to claim 1, wherein said barrier layer comprises that work function arranges metal.
7. method according to claim 1, wherein forms the step that overlays on the described control grid on described charge storage layer and comprises on the described substrate in described NVM region:
On described substrate in described NVM region and described logic region, form described charge storage layer;
On described charge storage layer in described NVM region and described logic region, form the second polysilicon layer; And
Described in patterning, the second polysilicon layer and described charge storage layer to form described control grid and to remove described the second polysilicon layer and described charge storage layer from described logic region in described NVM region.
8. method according to claim 1, wherein, after forming described selection grid, the part containing oxygen dielectric layer of described heat growth is between described selection grid and described control grid.
9. method according to claim 1, wherein, remove the step of expose portion of the described polysilicon layer in described NVM region and described logic region with described the first and second mask layers after, described method also comprises:
Laterally forming the first regions and source/drain and form the second regions and source/drain in the horizontal described substrate adjacent to described control grid in the described substrate adjacent to described selection grid, make described selection grid and described control grid between described the first and second regions and source/drain; And
In the horizontal described substrate adjacent to the first side wall of the described Part II of described polysilicon layer, form the 3rd regions and source/drain and laterally forming the 4th regions and source/drain in the described substrate adjacent to the second sidewall of the described Part II of described polysilicon layer.
10. method according to claim 9, wherein, remove the step of expose portion of the described polysilicon layer in described NVM region and described logic region with described the first and second mask layers after, described method also comprises:
Form around the first side wall sept of the lateral wall of described selection grid and described control grid and form around the second sidewall spacer of the described Part II of described polysilicon layer.
11. methods according to claim 1, also comprise:
Remove from described logic region described heat growth containing before the step of oxygen dielectric layer, described heat growth form the second polysilicon layer containing on oxygen dielectric layer, wherein said polysilicon layer is formed on described the second polysilicon layer, and
The step containing oxygen dielectric layer that wherein removes described heat growth also comprises from described logic region and removes described the second polysilicon layer.
12. methods according to claim 11, the step that wherein forms described high k gate dielectric and the described barrier layer of formation comprises:
On described substrate on described the second polysilicon layer in described NVM region and in described logic region, form described high k gate dielectric;
On described high k gate dielectric in described NVM region and in described logic region, form described barrier layer; And
Remove described high k gate dielectric and described barrier layer from described NVM region.
13. methods according to claim 1, wherein said charge storage layer comprises at least one in nanocrystal or nitride.
14. methods according to claim 3, wherein remove described polysilicon layer described Part II with after described logic gate position causes the step of described opening, described method also comprises:
Within described opening on described barrier layer on described protective layer in described NVM region and in described logic region, form logic gate layer; And
Described in complanation, logic gate layer is to cause logic gate in described logic gate position, and wherein said complanation has removed described protective layer from described NVM region.
15. 1 kinds of methods of making logic transistor and making non-volatile memories NVM unit in the logic region of substrate in the non-volatile memories NVM region of described substrate, comprising:
On described substrate in described NVM region, form the control grid overlaying on charge storage layer, wherein said control grid comprises polysilicon;
On the sidewall of described control grid, form oxide spacer;
What on the described substrate on the described substrate in described NVM region, on described control grid and in described logic region, heat was grown contains oxygen dielectric layer;
From described logic region remove described heat growth containing oxygen dielectric layer;
On described substrate in described logic region, form high k gate dielectric;
On described high k gate dielectric in described logic region, form barrier layer;
On the described described barrier layer containing on oxygen dielectric layer and in described logic region in described NVM region, form polysilicon layer;
Polysilicon layer described in complanation, the wherein said oxygen dielectric layer that contains comprises the sidewall sections being positioned at along the sidewall of described control grid;
On described polysilicon layer in described NVM region and control grid, form the first mask layer, wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region, wherein:
Described the first mask layer is located immediately on described control grid, and the first edge of described the first mask layer extends transverse to described polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid;
On described polysilicon layer in described logic region, form the second mask layer, wherein said the second mask layer defines logic gate position in described logic region;
Remove the expose portion of the described polysilicon layer in described NVM region with described the first mask layer, the Part I of wherein said polysilicon layer is retained in described selection gate location and sentences formation selection grid;
Remove the expose portion of the described polysilicon layer in described logic region with described the second mask layer, the Part II of wherein said polysilicon layer is retained in described logic gate position;
In described NVM region and described logic region, form dielectric layer, wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described polysilicon layer;
Described in complanation, dielectric layer is to expose the described Part II of described polysilicon layer;
On described selection grid in described NVM region and described control grid, form protective layer, wherein said protective layer has exposed described logic region;
Remove the described Part II of described polysilicon layer to cause opening in described logic gate position, wherein said opening has exposed described barrier layer;
Within described opening on described barrier layer on described protective layer in described NVM region and in described logic region, form logic gate layer; And
Described in complanation, logic gate layer is to cause logic gate in described logic gate position, and wherein said complanation has removed described protective layer from described NVM region.
16. methods according to claim 15, also comprise:
Described in removing from described logic region, containing before the step of oxygen dielectric layer, form the second polysilicon layer in containing on oxygen dielectric layer of described heat growth, and
Described in wherein removing, also comprise from described logic region and remove described the second polysilicon layer containing the step of oxygen dielectric layer.
17. methods according to claim 16, the step that wherein forms described high k gate dielectric and the described barrier layer of formation comprises:
On described substrate on described the second polysilicon layer in described NVM region and in described logic region, form described high k gate dielectric;
On described high k gate dielectric in described NVM region and in described logic region, form described barrier layer; And
Remove described high k gate dielectric and described barrier layer from described NVM region.
18. methods according to claim 15; before wherein forming the step of described protective layer after the step of expose portion that removes described polysilicon layer with the mask layer of described patterning and in described NVM region and described logic region, described method also comprises:
Laterally forming the first regions and source/drain and form the second regions and source/drain in the horizontal described substrate adjacent to described control grid in the described substrate adjacent to described selection grid, make described selection grid and described control grid between described the first and second regions and source/drain;
In the horizontal described substrate adjacent to the first side wall of the described Part II of described polysilicon layer, form the 3rd regions and source/drain and laterally forming the 4th regions and source/drain in the described substrate adjacent to the second sidewall of the described Part II of described polysilicon layer; And
Form around the first side wall sept of the lateral wall of described selection grid and described control grid.
19. methods according to claim 15, wherein said barrier layer comprises that work function arranges metal.
20. 1 kinds of methods of making logic transistor and making non-volatile memories NVM unit in the logic region of substrate in the non-volatile memories NVM region of described substrate, comprising:
On described substrate in described NVM region, form the control grid overlaying on charge storage layer, wherein said control grid comprises that polysilicon and described charge storage layer comprise at least one in nanocrystal or nitride;
What on the described substrate on the described substrate in described NVM region and described control grid and in described logic region, formation heat was grown contains oxygen dielectric layer;
Form the first polysilicon layer the containing on oxygen dielectric layer of described heat growth in described NVM region and described logic region;
From described logic region remove described heat growth containing oxygen dielectric layer and described the first polysilicon layer;
On described substrate on described the first polysilicon layer in described NVM region and in described logic region, form high k gate dielectric;
On described high k gate dielectric in described NVM region and in described logic region, form barrier layer;
Remove described high k gate dielectric and described barrier layer from described NVM region;
On described barrier layer on described the first polysilicon layer in described NVM region and in described logic region, form the second polysilicon layer;
The second polysilicon layer described in complanation, the oxygen dielectric layer that contains of wherein said heat growth comprises the sidewall sections being positioned at along the sidewall of described control grid;
On described polysilicon layer in described NVM region and control grid, form the first mask layer, wherein said the first mask layer defines the laterally selection gate location adjacent to described control grid in described NVM region, wherein:
Described the first mask layer is located immediately on described control grid, and the first edge of described the first mask layer extends transverse to described the second polysilicon layer to limit the laterally described selection gate location adjacent to described control grid in described NVM region from described control grid;
On described the second polysilicon layer in described logic region, form the second mask layer, wherein said the second mask layer defines logic gate position in described logic region;
Remove the expose portion of described the second polysilicon layer in described NVM region with described the first mask layer, the Part I of wherein said the second polysilicon layer is retained in described selection gate location and sentences formation selection grid;
Remove the expose portion of described the second polysilicon layer in described logic region with described the second mask layer, the Part II of wherein said the second polysilicon layer is retained in described logic gate position;
In described NVM region and described logic region, form dielectric layer, wherein said dielectric layer is formed on the described Part II of described selection grid, described control grid and described the second polysilicon layer;
Described in complanation, dielectric layer is to expose the described Part II of described the second polysilicon layer;
On described selection grid in described NVM region and described control grid, form protective layer, wherein said protective layer has exposed described logic region;
Remove the described Part II of described the second polysilicon layer to cause opening in described logic gate position, wherein said opening has exposed described barrier layer;
Within described opening on described barrier layer on described protective layer in described NVM region and in described logic region, form logic gate layer; And
Described in complanation, logic gate layer is to cause logic gate in described logic gate position, and wherein said complanation has removed described protective layer from described NVM region.
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Application publication date: 20140910