CN109684653A - Programmable gate array encapsulation containing programmable computing unit - Google Patents
Programmable gate array encapsulation containing programmable computing unit Download PDFInfo
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- CN109684653A CN109684653A CN201710996864.7A CN201710996864A CN109684653A CN 109684653 A CN109684653 A CN 109684653A CN 201710996864 A CN201710996864 A CN 201710996864A CN 109684653 A CN109684653 A CN 109684653A
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- 238000005538 encapsulation Methods 0.000 title abstract description 15
- 238000003860 storage Methods 0.000 claims abstract description 12
- 230000006870 function Effects 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 241000193935 Araneus diadematus Species 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
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- 235000009776 Rathbunia alamosensis Nutrition 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention proposes a kind of programmable gate array encapsulation, it contains at least one programmable computing chip and a programmable logic chip.Programmable computing chip contains multiple programmable computing units, and each programmable computing unit contains a writeable storage array, which stores the look-up table (LUT) of a basic function.Programmable computing chip and programmable logic chip vertical stacking, and be electrically coupled by chip chamber connection.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to programmable gate array.
Background technique
Programmable gate array belongs to semicustom integrated circuit, i.e., by backend process or field programming, realizes to logic electricity
The customization on road.United States Patent (USP) 4,870,302 discloses a kind of programmable gate array.It contains multiple programmable logic cells
(configurable logic element or configurable logic block) and reconfigurable interconnection
(configurable interconnect or programmable interconnect).Wherein, programmable logic cells exist
Realize displacement, logic NOT, AND(logical AND to the property of can choose under setting signal control), OR(logic sum), NOR(and non-),
NAND(and non-), XOR(exclusive or) ,+(arithmetic adds) ,-functions such as (arithmetic subtracts)；Reconfigurable interconnection can be under setting signal control
Selectively realize the functions such as connection, the disconnection between two interconnection lines.
Currently, many applications all refer to the calculating of complicated function.Complicated function typically contains multiple independents variable, it is basic
A kind of combination of function.Basic function contains one or a small amount of independent variable, and example includes surmounting function, such as index (exp), right
Number (log), trigonometric function (sina, cos) etc..In order to guarantee to execute speed, performance application requirement realizes complexity with hardware
Function.In existing programmable gate array, complicated function to solidify computing unit by realizing.These solidifications calculate single
Member is a part of stone (hard block), and circuit has been cured, cannot reconfigure to it.It is obvious that solidification meter
Further applying for programmable gate array will be limited by calculating unit.In order to overcome this difficulty, the present invention is by programmable gate circuit
Concept makes to solidify computing unit programmable.Particularly, programmable gate circuit in addition to containing programmable logic cells with
Outside, also containing programmable computing unit.Realize any one of many kinds of function to the programmable computing unit property of can choose.
Summary of the invention
The main object of the present invention is to promote programmable gate circuit in the application in complex mathematical computations field.
It is a further object of the present invention to provide a kind of programmable gate circuits, and not only its logic function can be customized, meter
Calculating function can also be customized.
A kind of it is a further object of the present invention to provide computing capabilitys more flexible, more powerful programmable gate array.
A kind of it is a further object of the present invention to provide chip areas smaller, the lower programmable gate array of cost.
In order to realize that these and other purpose, the present invention propose a kind of programmable gate array encapsulation.It contains at least one
Programmable computing chip and a programmable logic chip.Programmable computing chip contains programmable computing unit array, may be programmed
Logic chip contains array of programmable logic cells.Gate array encapsulation also contains multiple reconfigurable interconnections, these programmable companies
It connects and is distributed in programmable computing chip and/or programmable logic chip.Each programmable computing unit contains at least one can
Storage array is write, which stores a kind of look-up table (LUT) of function.The use of programmable computing unit is divided to two
Stage: setup phase and calculation stages.In setup phase, needed the LUT of required function being loaded into writeable array according to user
In；In calculation stages, the value of basic function is obtained by searching for LUT.Due to using writeable array, even if with a batch of core
Different functions also may be implemented in piece.Moreover, for the programmable gate array based on multiplicating program storage (MTP) array,
Due to that can load the LUT of different functions to MTP array in different periods, which is able to achieve Reconfigurable Computation.
In addition to may be programmed computing unit, programmable gate array encapsulation is also containing multiple programmable logic cells and the company of may be programmed
It connects.Programmable logic cells selectively realize a kind of logical operation from a logical operation library；Reconfigurable interconnection can choose
Property realize it is a variety of connection one of.During the realization of complicated function, complicated function is first broken down into multiple basic
Function.Then corresponding programmable computing unit is set for each basic function, achieves corresponding basic function.Most
Afterwards, by setting programmable logic cells and reconfigurable interconnection, required complicated function is realized.
Correspondingly, the present invention proposes a kind of programmable gate array encapsulation (400), it is characterised in that contains: one containing multiple
The programmable computing chip (100W) of programmable computing unit (100AA-100AD), the programmable computing unit (100AA-
100AD) contain at least one writeable storage array (110), which stores a basic function at least partly
Look-up table (LUT)；One contains the programmable logic chip (200W) of multiple programmable logic cells (200AA-200AD), this can
Programmed logic unit (200AA-200AD) contains an at least programmable logic cells (200), the programmable logic cells (200)
A kind of logical operation is selectively realized from a logical operation library；It is multiple that this be may be programmed into computing unit (100AA-100AD)
The reconfigurable interconnection (300) selectively coupled with the programmable logic cells (200AA-200AD)；By to the programmable calculating
Unit (100AA-100AD), the programmable logic cells (200AA-200AD) and the reconfigurable interconnection (300) be programmed with
Realize a complicated function, which is a kind of combination of the basic function；The programmable computing chip (100W) and
The programmable logic chip (200W) is electrically coupled by chip chamber connection (160).
Detailed description of the invention
Fig. 1 is a kind of symbol of programmable computing unit.
Fig. 2 is a kind of substrate circuitry layout of programmable computing unit.
Fig. 3 is a kind of layout of programmable gate array.
Fig. 4 indicates a kind of two service life of restructural gate array.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection is realized；Fig. 5 B discloses a kind of patrolling for programmable logic cells realization
Collect operation library.
Fig. 6 is a kind of layout of this kind of programmable gate array specific implementation.
Fig. 7 is a kind of perspective view of programmable gate array encapsulation.
Fig. 8 A-8C is the sectional view of three kinds of programmable gate arrays encapsulation.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific embodiment
Fig. 1 is a kind of symbol of programmable computing unit 100.Its input terminal IN includes input data 115, output end OUT
Including output data 135, it includes setting signal 125 that end CFG, which is arranged,.When setting signal 125 is " writing ", list is calculated programmable
The LUT of basic function needed for being written in member 100.When setting signal 125 is " reading ", read from programmable computing unit 100
Value in LUT.Fig. 2 is a kind of circuit arrangement map of programmable computing unit 100.In this embodiment, LUT is stored at least one
In a writeable storage array 110.The circuit further includes the peripheral circuit of writeable storage array 110: X-decoder 15 and Y-decoder
(including reading circuit) 17 etc..Writeable storage array 110 can be RAM or ROM.The example of RAM includes SRAM, DRAM etc.；ROM
Example include OTP(one-time programming), MTP(more times programming) etc..Wherein, MTP includes EPROM, EEPROM, flash memory etc..
Fig. 3 indicates a kind of programmable gate array 400.It contains regularly arranged programmable module 400A and programmable module
400B etc..Each programmable module (such as 400A), which is contained multiple programmable computing units (such as 100AA-100AD) and be may be programmed, patrols
It collects unit (such as 200AA-200AD).Programmable computing unit (such as 100AA-100AD) and programmable logic cells (such as
Contain programmable channel 320,340 between 200AA-200AD)；Between programmable module 400A and programmable module 400B,
Contain programmable channel 310,330,350.Programmable channel 310-350 contains multiple reconfigurable interconnections 300.For being familiar with ability
It, can also be using the design such as sea of gates (sea-of-gates) other than programmable channel for the professional person in domain.
Fig. 4 indicates two service life 620 and 660 of restructural gate array 400.It is two that first service life 620, which is divided to,
Stage: setup phase 610 and calculation stages 630.In setup phase 610, being needed according to user will be relevant to a basic function
Look-up table is loaded into MTP array 110；In calculation stages 630, corresponding LUT is searched in MTP array 110 to obtain the base
The value of this function.Similarly, the second service life 660 also contains identical setup phase 650 and calculation stages 670.It is restructural
Calculate be particularly suitable for SIMD(single-instruction multiple-data stream (SIMD)) data processing.Once LUT is loaded into MTP times in setup phase 610
After column 110, mass data can be sent into programmable computing unit 100 and handled, and obtain higher processing speed.
There are many example application of SIMD, as, to the same operation of multiple pixels or vector operation, used in scientific algorithm in image procossing
Extensive parallel computing etc..In addition, programmable gate array can also be may be programmed the pipelining of the calculating in computing unit,
To further increase throughput.
Fig. 5 A discloses a kind of link library that reconfigurable interconnection 300 is able to achieve.The reconfigurable interconnection 300 and United States Patent (USP) 4,
The reconfigurable interconnection disclosed in 870,302 is similar.It uses a kind of connection type of following link libraries: a) interconnection line 302/304
It is connected, interconnection line 306/308 is connected, but 302/304 is not attached to 306/308；B) interconnection line 302/304/306/308 is homogeneous
Even；C) interconnection line 306/308 is connected, and interconnection line 302,304 is not attached to, and is not also connected with 306/308；D) interconnection line 302/304
It is connected, interconnection line 306,306 is not attached to, and is not also connected with 302/304；E) interconnection line 302,304,306,306 is not attached to.?
In this specification, the symbol "/" between two interconnection lines indicates that two interconnection lines are connected, the symbol between two interconnection lines
", " indicate that two interconnection lines are not attached to.
Fig. 5 B discloses a kind of logical operation library that programmable logic cells 200 are able to achieve.It is input data that it, which inputs A and B,
210,220, output C are output data 230.What is disclosed in the programmable logic cells 200 and United States Patent (USP) 4,870,302 compiles
Journey logic unit is similar.It may be implemented at least one of following logical operation libraries: C=A, A logic NOT, A displacement, AND (A,
B), OR (A, B), NAND (A, B), NOR (A, B), XOR (A, B), arithmetic add A+B, arithmetic to subtract A-B etc..Programmable logic cells
200 can also be containing sequential circuit elements such as register, triggers, with the operation such as assembly line of practising.
Fig. 6 is a kind of specific implementation of programmable gate array 400, it is for realizing a complicated function: e=a.sin(b)+
c.cos(d).Reconfigurable interconnection 300 is using the representation in Fig. 5 A in programmable channel 310-350: there is dot in crosspoint
Reconfigurable interconnection indicate cross spider be connected, crosspoint without dot reconfigurable interconnection indicate cross spider be not attached to, disconnection can
Programming connection indicates that the interconnection line disconnected is divided into two mutual disjunct interconnection line segments.In this embodiment, it may be programmed and calculate
Unit 100AA is arranged to log (), and calculated result log (a) is sent to the first input of programmable logic cells 200AA.
Programmable computing unit 100AB is arranged to log [sin ()], and calculated result log [sin (b)] is sent to programmable logic
The second input of unit 200AA.Programmable logic cells 200AA is arranged to " arithmetic adds ", calculated result log (a)+log
[sin (b)] is sent to programmable computing unit 100BA.Programmable computing unit 100BA is arranged to exp (), calculates knot
Fruit exp { log (a)+log [sin (b)] }=a.Sin (b) is sent to the first input of programmable logic cells 200BA.Similarly,
By setting appropriate, computing unit 100AC, 100AD, programmable logic cells 200AC, programmable computing unit may be programmed
The result c of 100BC.Cos (d) is sent to the second input of programmable logic cells 200BA.Programmable logic cells 200BA quilt
It is set as " arithmetic adds ", a.Sin (b) and c.Cos (d) is added herein, and final result is sent to output e.It is obvious that being set by changing
It sets, programmable gate array 400 can also realize other complicated functions.
Fig. 7 is a kind of perspective view of programmable gate array encapsulation 400.It contains a programmable computing chip 100W and one can
Programmed logic chip 200W.Programmable computing chip 100W is formed in computing chip substrate 100S, it contains multiple programmable
Computing unit 100AA-100BB.Each programmable computing unit 100 contains a writeable storage array 110, it is for storing a base
The look-up table (LUT) of this function.Programmable logic chip 200W is formed in logic chip substrate 200S, it contains multiple compile
Journey logic unit 200AA-200BB, each programmable logic cells 200 selectively realize that one kind is patrolled from a logical operation library
Collect operation.Programmable computing chip 100W is electrically coupled by multiple chip chambers connection 160 with programmable logic chip 200W.Chip
Between connection 160 can be microbonding point (micro-bump) or penetrate silicon wafer channel (TSV).Programmable gate array encapsulation 400 also contains
There are multiple reconfigurable interconnections, a part of reconfigurable interconnection is located in programmable computing chip 100W, another part reconfigurable interconnection
In programmable logic chip 200W.
Fig. 8 A- Fig. 8 C is the sectional view of three kinds of programmable gate array encapsulation 400, they are a kind of multi-chip package
(multi-chip package, referred to as MCP).Wherein, the programmable gate array encapsulation 400 in Fig. 8 A is containing there are two separating cores
Piece: programmable computing chip 100W and programmable logic chip 200W.Chip 100W, 200W are stacked in package substrate 110 simultaneously
In same encapsulating shell 130.Microbonding point (micro-bump) 116 provides for them to be electrically coupled, and chip chamber connection 160 is played
Effect.In the present embodiment, it may be programmed computing chip 100W to be stacked on programmable logic chip 200W；Meanwhile programmable meter
It calculates chip 100W to be reversed, and is stacked Face to face with programmable logic chip 200W.In other embodiments, it can compile
Journey computing chip 100W can not be reversed；Or, programmable logic chip 200W is stacked on programmable computing chip 100W.
Programmable gate array encapsulation 400 in Fig. 8 B contains programmable computing chip 100W, programmable logic chip 200W
With silicon plate (interposer) 120.Silicon plate 120 penetrates silicon wafer channel (TSV) 118 containing multiple, it makes programmable calculating
Being electrically coupled between chip 100W and programmable logic chip 200W is more easy, and there is more freedom in when design, radiates simultaneously
It is be more good.This embodiment also contains multiple microbonding points 116, it constitutes chip chamber with TSV 118 and connect 160.
Programmable gate array encapsulation 400 in Fig. 8 C contains the programmable meter of a programmable logic chip 200W and at least two
Calculate chip 100W, 100W`.These chips 200W, 100W and 100W` are separation, and are located in same encapsulating shell 130.Wherein,
Chip 100W` is stacked on chip 100W, and chip 100W is stacked on chip 200W.Chip 200W, 100W and
It is coupled between 100W` by TSV 118 and microbonding point 116.It is obvious that Fig. 8 C ratio Fig. 8 A has bigger memory capacity.It is similar
Ground, in this embodiment, TSV 118 constitute chip chamber with microbonding point 116 and connect 160.
It is beneficial that programmable gate array encapsulates 400 pairs of manufacturing process angles.Due to programmable computing chip 100W and may be programmed
Logic chip 200W is different chips, constitutes the memory transistor of programmable computing chip 100W and constitutes programmable logic chip
The logic transistor of 200W is respectively formed on various substrates (100S, 200S), their manufacturing process can be separately optimized.It can compile
Journey computing chip 100W can use carrier of any type of writable memory as LUT, as SRAM, DRAM, MRAM,
FRAM, OTP, NOR flash memory, nand flash memory etc.；Programmable logic chip 200W can contain any type of programmable logic electricity
Road.It is formed on single crystal semiconductor substrate 100S due to may be programmed the writeable storage array in computing chip 100W, speed is very
Fastly.Further, since microbonding point (or penetrating silicon wafer channel) 160 is large number of and length is shorter, may be programmed computing chip 100W and
Bandwidth between programmable logic chip 200W is higher.
This specification is by taking field programmable gate array (FPGA) as an example.In FPGA, wafer will complete all process steps (including
All programmable computing unit, programmable logic cells and reconfigurable interconnection).It, can be by the way that programmable connect be arranged at programming scene
Fetch the function of defining FPGA.The example of above-mentioned FPGA can easily be generalized to traditional programmable gate array.In tradition
In programmable gate array, wafer is only semi-finished, i.e., wafer production is only completed programmable computing unit and programmable logic cells, but
Reconfigurable interconnection is not completed.After the function of chip determines, programmable channel 310-350 is customized by backend process.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of programmable gate array encapsulates (400), it is characterised in that contain:
One contains the programmable computing chip (100W) of multiple programmable computing units (100AA-100AD), the programmable calculating
Unit (100AA-100AD) contains at least one writeable storage array (110), which stores a basic letter
Several at least partly look-up tables (LUT)；
One contains the programmable logic chip (200W) of multiple programmable logic cells (200AA-200AD), the programmable logic
Unit (200AA-200AD) contains an at least programmable logic cells (200), and the programmable logic cells (200) are from a logic
A kind of logical operation is selectively realized in operation library；
It is multiple that this be may be programmed into computing unit (100AA-100AD) and the programmable logic cells (200AA-200AD) selectivity
The reconfigurable interconnection (300) of coupling；
By to this may be programmed computing unit (100AA-100AD), the programmable logic cells (200AA-200AD) and this can compile
Journey connection (300) is programmed to realize a complicated function, which is a kind of combination of the basic function；
The programmable computing chip (100W) connects (160) thermocouple by chip chamber with the programmable logic chip (200W)
It closes.
2. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: it is at least partly described to compile
Journey connection (300) is located in the programmable computing chip (100W).
3. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: it is at least partly described to compile
Journey connection (300) is located in the programmable logic chip (200W).
4. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: the programmable computing chip
(100W) and programmable logic chip (200W) vertical stacking.
5. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: the writeable storage array
It (110) is RAM or ROM.
6. programmable gate array according to claim 5 encapsulates (400), it is further characterized in that: the ROM is one-time programming
Memory (OTP) or repeatedly programmable memory (MTP).
7. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: the reconfigurable interconnection (300)
For microbonding point (micro-bump) or penetrate silicon wafer channel (TSV).
8. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: its use process includes one
Setup phase (610) needs the LUT by a function to be loaded into writeable storage array in the setup phase (610) according to user
(110) in.
9. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that: its use process includes one
Service stage (630) searches corresponding LUT in writeable storage array (110) in the service stage (630) to obtain the letter
Several values.
10. programmable gate array according to claim 1 encapsulates (400), it is further characterized in that containing: at least two can be compiled
Journey computing chip (100W, 100W`), the programmable computing chip (100W, 100W`) and the programmable logic chip
(200W) is electrically coupled by chip chamber connection (160).
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710996864.7A CN109684653B (en) | 2017-10-19 | 2017-10-19 | Programmable gate array package containing programmable computing units |
| US15/793,968 US20180048317A1 (en) | 2016-03-05 | 2017-10-25 | Configurable Computing-Array Package |
| US16/059,023 US10312917B2 (en) | 2016-03-05 | 2018-08-08 | Configurable computing array for implementing complex math functions |
| US16/121,653 US10456800B2 (en) | 2016-03-05 | 2018-09-05 | Configurable computing array comprising configurable computing elements |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
| US16/199,178 US20190115921A1 (en) | 2016-03-05 | 2018-11-24 | Configurable Computing-Array Package |
| US16/199,204 US20190115920A1 (en) | 2016-03-05 | 2018-11-25 | Configurable Computing-Array Package Implementing Complex Math Functions |
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