TW202145463A - A non-volatile programmable logic device based on multi-chip package - Google Patents

Abstract

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Description

Non-volatile Programmable Logic Driver Based on Multi-Chip Package Structure

This application claims U.S. Provisional Application No. 62/983,634, filed on February 29, 2020, entitled "Non-volatile Programmable Logic Driver Based on Multi-Chip Package Structure". In addition, it is a continuation-in-part of US Application No. 16/601,834 filed on October 15, 2019, and US Application No. 16/601,834 is a US application filed on December 14, 2017 A continuation of case No. 15/841,326, which has US Patent No. 10,489,544, which claims US Patent No. 15/841,326 filed on December 14, 2016 U.S. Provisional Application No. 62/433,806, the invention of which is entitled "Logical Drive", and U.S. Provisional Application No. 15/841,326 asserts that U.S. Provisional Application No. 62/448,924, filed on January 20, 2017, which The title of the invention of the case is "Method of Forming a Logical Drive and a Memory Drive", and the US Application No. 15/841,326 claims the US Provisional Application No. 62/533,788 filed on July 18, 2017, the title of the invention of the case For "Logic Drivers Constructed on Standard Commercialized FPGAIC Chips" and that U.S. Application No. 15/841,326 claims U.S. Provisional Application No. 62/545,556, filed on August 15, 2017, whose invention is entitled " Logic Drivers Based on Standard Commercialized FPGAIC Chips".

The present invention relates to a logic operation chip package, a logic driver package, a logic operation chip device, a logic operation chip module, a logic driver, a logic operation hard disk, a logic driver hard disk, a logic driver solid state hard disk , a Field Programmable Gate Array (FPGA) logic operation hard disk or a Field Programmable Gate Array logic driver (hereinafter referred to as a logic driver, which means that the following specification refers to a logic operation chip package, a logic driver package , a logic operation chip device, a logic operation chip module, a logic operation hard disk, a logic driver hard disk, a logic driver solid state hard disk, a Field Programmable Gate Array (FPGA) logic operation hard disk Or a field programmable logic gate array logic driver, all referred to as logic driver), the logic driver of the present invention includes a plurality of FPGA integrated circuit (IC) chips, one or more non-volatile memories for the purpose of field programming IC chips, more specifically, a plurality of commercial standard FPGA IC chips and a plurality of non-volatile memory IC chips are used to form a commercial standard logic driver, when field programming, the commercial standard logic driver can be used in different applications superior.

FPGA semiconductor IC chips have been used to develop an innovative application or low volume application or business requirement. When an application or business requirement expands to a certain amount or a certain period of time, semiconductor IC suppliers usually regard the application as an Application Specific IC (ASIC) chip or a Customer Owned Tool IC chip (Customer). -OwnedTooling (COT) IC chip), the conversion from FPGA chip design to ASIC chip or COT chip, is because the existing FPGAIC chip has a specific application, and the existing FPGAIC chip is compared to an ASIC chip or COT chip is (1) Requires larger size semiconductor wafers, lower manufacturing yield and higher manufacturing costs; (2) higher power consumption; (3) lower performance. As semiconductor technology evolves to the next process generation technology (eg, to less than 30 nanometers (nm) or 20 nanometers (nm)) in accordance with Moore's Law, it is necessary to design an ASIC chip or a COT chip once. The cost of non-recurring engineering (NRE) is very expensive (eg more than 5 million US dollars, or even more than 10 million US dollars, 20 million US dollars, 50 million US dollars or 100 million US dollars) US dollars). Such an expensive NRE cost reduces or even stops the application of advanced IC technology or new process generation technology in innovation or application. Therefore, in order to easily realize the progress in semiconductor innovation, it is necessary to develop a new manufacturing with continuous innovation and low manufacturing cost. method or technique.

The present invention discloses a commercial standard logic driver. The commercial standard logic driver is a multi-chip package used to achieve computing and/or processing functions through field programming. The chip package includes several FPGA IC chips and one or more programmable chips. Non-volatile memory IC chips used in different logic operations. The difference between the two is that the former is a computing/processor with logic operation function, while the latter is a data storage device with memory function. This commercial standard The non-volatile memory IC chip used in the logical drive is similar to using a commercial standard solid state storage hard disk (or drive), a data storage hard disk, a data storage floppy disk, a universal serial bus (Universal Serial Bus (USB) ) flash memory disk (or drive), a USB drive, a USB memory stick, a flash memory disk or a USB memory.

The present invention further discloses a method for reducing the cost of NRE, and the method realizes innovation and application on semiconductor IC chips through commercialized standard logic drivers. Persons, users or developers with innovative ideas or innovative applications need to purchase this commercial standard logical drive and a development or writing software source code or program that can write (or load) this commercial standard logical drive for Realize his/her innovative idea or innovative application. Compared with the method realized by developing an ASIC chip or COTIC chip, the realized method provided by the present invention can reduce the NRE cost by more than 2.5 times or more than 10 times. For advanced semiconductor technologies or next-generation technologies (eg, to less than 30 nanometers (nm) or 20 nanometers (nm)), the cost of NRE for ASIC wafers or COT wafers increases substantially, for example, by more than US$500 10,000 yuan, even more than 10 million yuan, 20 million yuan, 50 million yuan or 100 million yuan. 16nm technology or process generations such as ASIC chips or COTIC chips require masks in excess of $2 million, $5 million or $10 million if logic drivers are used to achieve the same or similar Innovations or applications can reduce this NRE cost by less than $10 million, or even less than $5 million, $3 million, $2 million, or $1 million. The present invention stimulates innovation and reduces barriers to innovation in implementing IC chip designs and barriers to using advanced IC processes or next process generations, such as using more advanced IC process technologies than 30nm, 20nm or 10nm , as shown in Figure 36.

Another aspect of the present invention provides an "open innovation platform", which enables creators to easily and cost-effectively use technologies from the IC technology generation advanced in 20nm on semiconductor wafers through the logic driver of the present invention, and through the logic driver of the present invention. use logical drives to execute or realize their ideas or inventions in advanced technology generations such as those of 16nm, 10nm, 7nm, 5nm or 3nm, where such ideas or inventions include: (i) innovative algorithms or Computational, processing, learning and/or inferencing architectures, (ii) in the 1990s, creators or inventors could design IC chips and use 1µm, 0.8µm, 1µm, 0.8µm in semiconductor foundries for hundreds of thousands of dollars , 0.5µm, 0.35µm, 0.18µm or 0.13µm technology generation technology to realize their ideas or inventions, semiconductor manufacturing companies are companies with fewer products and own semiconductor manufacturing plants, semiconductor manufacturing companies provide manufacturing services to their customers, Their clients are companies without factories, which include: (i) IC design companies that design and own IC chips; (ii) systems companies that design and own systems, (iii) IC chip design independent designs and own IC chips, The IC manufacturing facility was what was called a "common innovation platform" at the time, however, when technology generations migrated and progressed to more advanced technology generations than 20nm or 10nm, such as ICs that advanced 16nm, 10nm, 7nm, 5nm or 3nm The technology of the manufacturing technology generation, only a few large system vendors or IC design companies (non-public innovators or inventors) can afford the development costs required by semiconductor IC manufacturing foundries, which use these advanced generations of development and implementation The cost is about more than 5 million US dollars. Today's semiconductor IC foundries are no longer a "public innovation platform", but only become a "club innovation platform" for club innovators or inventors, and the logic proposed by the present invention Drivers (including standard commercial field programmable gate array (FPGA) integrated circuit chips (standard commercial FPGA IC chips)) can provide public creators with a return to the same "common innovation platform" for the semiconductor IC industry in the 1990s , creators can execute or implement their creations or inventions by writing software programs using the standard commercial logic drivers of the present invention and using common programming languages at a cost of less than $500K or $300K, where common programming languages such as is a programming language such as C, Java, C++, C#, Scala, Swift, Matlab, AssemblyLanguage, Pascal, Python, VisualBasic, PL/SQL or JavaScript, where creators can use their own standard logic drivers or they can The data center or cloud rents standard commercial logical drives for development or to implement their creations or inventions, as shown in Figure 36 .

Another aspect of the present invention provides an innovative platform of the inventors, the innovative platform includes (a) a plurality of logic drivers in a data center or cloud, wherein the logic drivers include semiconductor IC process technology nodes using the first 20nm technology node Manufactured multiple standard commercial FPGAIC chips (in FPGA/HBMCSPs packages). (b) The innovator's device and the plurality of users' devices that communicate with the Internet or the Internet on a data center or cloud, where the innovator can use a common programming language in the data center or cloud via the Internet or the Internet To program complex logic drivers to develop and write software programs to realize his innovations (inventions) (including algorithms, architectures and/or applications), commonly used programming languages include C, Java, C++, C#, Scala, Swift, Matlab, AssemblyLanguage, Pascal, Python, VisualBasic, PL/SQL or JavaScript and other programming languages, (c) after programming some logic drivers, the innovator or multiple users can use the programmed software via the Internet or the Internet Logic drives are used in their innovations (including algorithms, architectures and/or applications), where such innovations include: (i) computationally, computationally, learning and/or inferentially innovative algorithms or architectures, and/or (ii) innovative and/or specific applications.

The present invention discloses a method for changing the industrial model of an existing logic ASIC chip or COT chip into a commercialized logic IC chip industry model, such as the existing commercialized Dynamic Random Access Memory (DRAM) chip industry model or Is the commercial flash memory IC chip industry model, through standardized commercial logic drivers. For the same innovation or new application, standard commercial logic drivers can be used as an alternative to ASIC chips or COTIC chips. Standard commercial logic drivers should be comparable to existing ASIC chips or COTIC chips in terms of performance, power consumption, engineering and manufacturing costs. good or the same. Existing logic ASIC chip or COTIC chip design, manufacture and/or production companies (including fabless IC chip design and production companies, IC fabs or build-to-order (can be product-free), companies and/or), vertical Companies that integrate IC chip design, manufacture and production) can become similar to existing commercial DRAM companies, flash memory IC chip design, manufacture and production companies, flash USB stick or drive companies, flash solid state drives or hard disks A company that designs, manufactures and produces. Existing logic computing ASIC chip or COTIC chip design companies and/or manufacturing companies (including fabless IC chip design and production companies, IC fabs or build-to-order manufacturing (can be no product) companies, vertically integrated IC chip design, manufacturing companies and production companies) may change the company's business model to: (1) design, manufacture and/or sell standard commercial FPGAIC chips; and/or (2) design, manufacture and/or sell standard Commercial logical drives. Individuals, users, clients, software developers The application developer can purchase this commercial standard logic driver and write the source code of the software for programming his/her desired application, for example, in artificial intelligence (Artificial Intelligence, AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (Internet Of Things, IOT), virtual reality (VR), augmented reality (AR), automotive electronic graphics processing (GP). The logic driver can write chips that perform functions such as graphics chips, baseband chips, Ethernet chips, wireless chips (eg, 802.11ac), or artificial intelligence chips. This logic driver can alternatively be programmed to perform artificial intelligence, machine learning, deep learning, big data database storage or analysis, Internet of Things (IOT), virtual reality (VR), augmented reality (AR), automotive electronics Graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) functions or any combination of them.

The present invention further discloses a way to change the existing logic ASIC chip or COT chip hardware industry model to a software industry model through commercialized standard logic drivers. On the same innovation and application, the standard commercial logic driver should be better or the same as the existing ASIC chip or COTIC chip in terms of performance, power consumption, engineering and manufacturing cost, so the commercial standard logic driver can be used as a replacement for designing ASIC chips or COTIC chips plan. Existing design companies or suppliers of ASIC chips or COTIC chips can become software developers or suppliers, and become the following industrial models: (1) Become a software company to conduct software research and development or software sales for its own innovations and applications, Then let the customer or user install the software in the commercial standard logic drive owned by the customer or user; and/or (2) is still a hardware company that sells the hardware without designing and producing ASIC chips or COTIC chips . For innovative or new applications, self-developed software can be installed in one or more non-volatile memory IC chips in standard commercial logic drives sold, and then sold to their customers or users. They can also write software source code in a standard commercial logic driver (that is, install the software source code in a non-volatile memory IC chip in a standard commercial logic driver) as desired, such as in Artificial Intelligence (AI) , machine learning, deep learning, big data database storage or analysis, Internet of Things (Internet Of Things, IOT), virtual reality (VR), augmented reality (AR), automotive electronic graphics processing (GP). The logic driver can write chips that perform functions such as graphics chips, baseband chips, Ethernet chips, wireless chips (eg, 802.11ac), or artificial intelligence chips. This logic driver can alternatively be programmed to perform artificial intelligence, machine learning, deep learning, big data database storage or analysis, Internet of Things (IOT), virtual reality (VR), augmented reality (AR), automotive electronics Graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) functions or any combination of them.

The present invention further discloses a transformation of the existing system design, system manufacturing and/or system product industry via standard commercial logic drivers into a commercial system/product industry, such as the current commercial DRAM industry and the flash memory industry. Existing systems, computers, processors, smart phones or electronic instruments or devices can be turned into a standard commercial hardware company with memory drives and logical drives as the main hardware. The memory drive may be a hard disk, a flash drive (pen drive) and/or a solid-state drive. The logical drivers disclosed in the present invention may have a sufficient number of output/input terminals (I/Os) to support (support) the I/Os portion of the programming of all or most applications. For example, perform one of the following functions or a combination of the following functions: artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IOT), virtual reality (VR), Augmented reality (AR), automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) and other functions. A logical driver may include: (1) Software or application developers can download application software or programming code to connect or couple to the I/Os of the logical driver via I/O ports or connectors for programming or configuration The logical drive; (2) I/Os that are executed or used by the user, the user is connected or coupled to the I/Os of the logical drive through one or more external I/Os or connectors to execute instructions, such as generating and making a Microsoft wordfile, a presentation file or a spreadsheet. External I/Os or connectors of external components are connected or coupled to corresponding logic drivers. 4 connectors, one or more Ethernet network connectors, one or more audio source or serial ports, such as RS-232 connectors or COM (communication) connectors, wireless transceiver I/Os and ( or) Bluetooth transceiver I/Os, external I/Os connected or coupled to corresponding logical drive I/Os may include Serial Advanced Technology Attachments for communication, connection or coupling to memory drives , SATA) connector or external link (PeripheralComponentsInterconnectexpress, PCIe) connector. These I/Os for communication, connection or coupling can be provided, located, assembled or connected to (or to) a substrate, a flexible or rigid board, such as a Printed Circuit Board (PCB), a A silicon substrate with a connection circuit structure, a metal substrate with a connection circuit structure, a glass substrate with a connection circuit structure, a ceramic substrate with a connection circuit structure, or a flexible substrate with a connection circuit structure. The logic driver is packaged in a process similar to flip-chip through tin bumps, copper pillars or copper bumps or gold bumps or chip-on-film (COF) used in LCD driver packaging technology. ) packaging process, the logic driver is arranged on the substrate, flexible board or hard board. Existing systems, computers, processors, smart phones or electronic instruments or devices can become: (1) a company that sells standard commercial hardware. For the purposes of the present invention, this type of company is still a hardware company, while the (2) The system or application software developed by the user is installed in the user's own standard commercial hardware. For the present invention, this type of company is a software company (3) Install system or application software or program developed by a third party in standard commercial hardware and sell software download hardware. For the present invention, this type of company is a hardware company.

The present invention further discloses a commercial standard FPGA IC chip used as a commercial standard logic driver. This commercial standard FPGAIC chip is designed and manufactured using advanced semiconductor technology or next-generation process, enabling it to have a small die size and advantageous manufacturing yields, such as 30 nanometers (nm), 20nm or 10nm more advanced or equivalent, or smaller or the same semiconductor advanced process. The dimensions of the commercial standard FPGAIC chips are between 400 millimeters square (mm ² ) and 9 mm ^{2 ,} between 225 mm ² and 9 mm ^{2 ,} between 144 mm ² and 16 mm ^{2 ,} between 100 mm ² and 16 mm 2 between ^2, between 50 mm and 16mm ² 75 ² mm in mm or between ² and 16mm ^2. The transistors manufactured by advanced semiconductor technology or new generation process can be a FINField-Effect-Transistor (FINFET), a Gate-all-around (GAA) FET, Silicon wafer on insulator (Silicon-On-Insulator (FINFETSOI)), GAA field effect transistor on insulator (GAAFETonSilicon-On-Insulator (GAAFETSOI)), thin film fully depleted silicon wafer on insulator (FDSOI) MOSFET ), thin-film partially depleted silicon wafers on insulators (Partially Depleted Silicon-On-Insulator (PDSOI)), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or conventional MOSFETs. This commercial standard FPGAIC die may only be able to communicate with other die within the logic driver, where the input/output circuits of the commercial standard FPGAIC die may only require small input/output drivers (complex I/O drivers) or input/output receivers receivers (I/O complex receivers), and small (or no) electrostatic discharge (Electrostatic Discharge (ESD)) devices. The drive capability, load, output capacitance, or input capacitance of this I/O driver, I/O receiver, or I/O circuit is between 0.1 picofarads (pF) and 10 pF, between 0.1 pF and 5 pF, Between 0.1 pF and 3 pF or between 0.1 pF and 2 pF, or less than 10 pF, less than 5 pF, less than 3 pF, less than 2 pF or less than 1 pF. The size of the ESD device is between 0.05pF and 10pF, between 0.05pF and 5pF, between 0.05pF and 2pF, or between 0.05pF and 1pF, or less than 5pF, less than 3pF, less than 2pF , less than 1pF or less than 0.5pF. For example, a bi-directional (or tri-state) input/output pad or circuit may include an ESD circuit, a receiver, and a driver, with an output capacitance or input capacitance ranging from 0.1pF to 10pF, 0.1pF between 5 pF or between 0.1 pF and 2 pF, or less than 10 pF, less than 5 pF, less than 3 pF, less than 2 pF or less than 1 pF. All or most of the control and/or input/output circuits or units are external to or not included in a commercial standard FPGAIC die (e.g., off-logic-drive I/O circuits), meaning a large input/output circuit used to communicate with circuits or components of an external logic driver), but may be included in another dedicated control chip, a dedicated input/output chip, or dedicated control and input in the same logic driver. Within a commercial standard FPGAIC die, the minimum (or none) area is used to set up control or input/output circuits, eg, less than 15%, 10%, 5%, 2%, 1%, 0.5%, or 0.1% within an output/output die The area system is used to set the control or input/output circuit, or the minimum (or no) transistor system in the commercial standard FPGAIC chip is used to set the control or input/output circuit, for example, the number of transistors is less than 15%, 10%, 5% , 2%, 1%, 0.5%, or 0.1% are used to set up control or input/output circuits, or all or most of the area of a commercial standard FPGAIC die is used in (i) logic blocks, cells, or component sets , which includes a logic gate matrix, an arithmetic unit or operating unit, and/or a look-up table (Look-Up-Tables, LUTs) and a multiplexer (multiplexer); and (or) (ii) programmable interconnections line (programmable interactive connection line). For example, more than 85%, more than 90%, more than 95%, more than 98%, more than 99%, more than 99.5%, more than 99.9% of the commercial standard FPGA IC chip area is used to set up logic blocks, cells or components and programmable interactions Connection lines, or all or most of the transistor system in a commercial standard FPGA IC chip are used to configure logic blocks, cells or elements and/or programmable interconnection lines, such as more than 85% transistors, more than 90% transistors , greater than 95%, greater than 98%, greater than 99%, greater than 99.5%, greater than 99.9% are used to set logic blocks, cells or elements and/or programmable interconnect lines.

Complex logic blocks, cells or elements include (i) a matrix of complex logic gates including Boolean logic drivers such as NAND circuits, NOR circuits, AND circuits and/or OR circuits; (ii) complex computing units such as adders circuits, multiplexers, shift registers, floating point circuits and multiplying and/or dividing circuits; (iii) LUTs and multiplexers. Additionally, Boolean logic drivers, logic gate functions, certain calculations, operations or processing may be performed via LUTs and/or complex multiplexers. LUTs can store or memorize processing results or computational logic gate results, operation results, decision process or operation results, event results or activity results. For example, LUTs can store or memorize data or results in static random access memory cells (SRAM cells). A plurality of static random access memory (SRAM) cells can be distributed in the FPGA chip, and are close to or close to the multiplexers within the corresponding logic blocks, cells or elements. In addition, the complex SRAM cells can be arranged in an SRAM matrix in a certain area or location within the FPGA chip. In order to distribute the complex selection multiplexers of the logical blocks, cells or elements in the FPGA chip, the complex SRAM cell matrix is aggregated Or an SRAM cell that includes a plurality of LUTs, which can be arranged in one or a plurality of SRAM matrices in certain complex regions in the FPGA wafer; for the purpose of distributing the location of the logic blocks, cells, or components in the FPGA wafer for a plurality of selections For the processor, each SRAM matrix can aggregate or include SRAM cells of a complex number of LUTs. The data stored or latched in each SRAM cell can be input into the multiplexer for selection. Each SRAM cell can include 6 transistors (6TSRAM), the 6 transistors include 2 transfer (write) transistors and 4 data latch transistors, of which 2 transfer transistor systems are used for writing Data to 2 nodes for storage or latching of 4 data latch transistors. Each SRAM cell can include 5 transistors (5TSRAM), the 6 transistors include 1 transfer (write) transistor and 4 data latch transistors, of which 1 transfer transistor system is used for writing Data to 2 nodes of storage or latching of 4 data latch transistors, one of the two latch points of the 4 data latch transistors in a 5T or 6T SRAM cell is connected or coupled to the multiplexer. Data stored in 5T or 6T SRAM cells are used as LUTs. When a set of data, request or condition is input, the multiplexer will select to store or memorize the corresponding data (or result) in the LUTs according to the input data, request or condition. The 4-input NAND gate circuit described below can be used as an example of the implementation of an operator including complex LUTs and complex multiplexers: The 4-input NAND gate circuit includes 4 inputs and 16 (or 2 ⁴ A) may correspond to the output (result), an operator performs a 4-input NAND operation via a plurality of LUTs and a plurality of multiplexers, including (i) 4 inputs; (ii) a storable and memory 16 may correspond to the output ( results) of the LUTs; (iii) a multiplexer designed to select the correct (corresponding) output based on a particular 4-input data set (eg, 1,0,0,1); (iv) an output. Generally speaking, an operator includes n inputs, a ^{LUT for storing or memorizing 2 n} corresponding data and results, and a LUT for selecting the correct (corresponding) ) output multiplexer.

The complex programmable interconnection lines in the commercial standard FPGAIC chip include a plurality of crosspoint switches located in the middle of the complex programmable interconnection lines, for example, n metal lines are connected to the input terminals of the complex crosspoint switches, and m metal lines are connected to the input terminals of the complex crosspoint switches. The lines are connected to the output terminals of a plurality of cross-point switches, wherein the cross-point switches are located between the n metal lines and the m metal lines. Such crosspoint switches are designed so that each n metal line can be connected programmatically to any m metal line. type transistor and a p-type transistor, one of the n-metal lines can be connected to the source terminals of the opposing pairs of n-type and p-type transistors in the pass/fail circuit, and one of them The m metal lines are connected to the drains of the opposing pairs of n-type transistors and p-type transistors in the pass/pass circuit, and the connected or disconnected state (pass or fail) of the cross-point switch is stored by Or the data (0 or 1) latched in an SRAM cell is controlled, a plurality of SRAM cells can be distributed in the FPGA chip, and each 5T or 6T SRAM cell is located at or close to the corresponding cross-point switch. In addition, the SRAM cells may be arranged in an SRAM matrix in certain blocks of the FPGA, wherein the SRAM cells are aggregated or include a plurality of SRAM cells for controlling the corresponding cross-point switches at the distribution positions. Additionally, the SRAM cells may be arranged in one of the complex SRAM matrices within certain complex blocks of the FPGA, where each SRAM matrix aggregates or includes complex SRAM cells for controlling corresponding crosspoint switches at distributed locations. The gates of both n-type transistors and p-type transistors in the crosspoint switch are connected to two storage nodes or latch nodes. Each SRAM cell may include six transistors (6TSRAM), including two transfer ( Write) transistors and 4 data latch transistors, of which 2 transfer transistor systems are used to write programming source codes or data to the 2 storage nodes of the 4 data latch transistors. In addition, each SRAM cell may include 5 transistors (5TSRAM), including a transfer (write) transistor and 4 data latch transistors, of which one transfer transistor system is used to write programming source code or Data to 2 storage nodes of 4 data latch transistors, 2 storage nodes of 4 data latch transistors in 5TSRAM or 6TSRAM are respectively connected to the gates of the n-type transistors in the pass/non-pass switch circuit and the gate of the p-type transistor. It is stored on the node where the 5TSRAM cell and the 6TSRAM cell are connected to the cross-point switch, and the stored data is used to program the connection state or disconnection state between the two metal lines. When the data is latched in the 5TSRAM or 6TSRAM two storage nodes are programmed as [1,0] (can be defined as 1 for storage in an SRAM cell), where the "1" node is connected to the n-type transistor gate and the "0" node is connected to the p-type transistor gate When it is extremely high, the pass/no pass circuit is in an "open" state, that is, the two metal lines are connected to the two nodes of the pass/no pass circuit. When data is latched in 5TSRAM or 6TSRAM, the two storage nodes are programmed as [0,1] (which can be defined as 0 for storage in SRAM cells), where the "0" node is connected to the gate of the n-type transistor, When the "1" node is connected to the gate of the p-type transistor, the pass/no pass circuit is in the "off" state, that is, the two metal lines are disconnected from the two nodes of the pass/no pass circuit. Since commercial standard FPGA IC chips include regular and repeating gate matrices or blocks, cells or elements, LUTs and multiplexers or programmable interconnects, just like commercial standard DRAM chips, NAND flash IC chips, Processes with wafer areas greater than 50 mm ² or 80 mm ² have very high yields, eg greater than 70%, 80%, 90% or 95%.

In addition, each cross-point switch includes, for example, a pass/no pass circuit with a switch buffer (switch buffer or switch buffer), and the switch buffer includes a two-stage inverter, a control N- MOS cell and a control P-MOS cell, one of the n-metal lines is connected to the common (connected) gate terminal of an input stage inverter with/without a buffer in the circuit, and one of the m-metal lines is connected to The common (connected) drain terminal of an output stage inverter that passes/does not pass through the buffer in the circuit, the output stage inverter is formed by stacking a control P-MOS and a control N-MOS, wherein the control P-MOS is in the The top (between Vcc and the source of the P-MOS of the output stage inverter), while the control N-MOS is at the bottom (between Vss and the source of the N-MOS of the output stage inverter). The connection state or non-connection state (pass or fail) of the cross-point switch is controlled by the data (0 or 1) stored in the 5TSRAM cell or the 6TSRAM cell. Multiple SRAM cells can be distributed in the FPGA chip, and each 5T or 6TSRAM cell is controlled by the data (0 or 1). The unit is located at or near the corresponding crosspoint switch. In addition, 5TSRAM cells or 6TSRAM cells may be arranged in 5TSRAM cells or 6TSRAM cell matrices in certain blocks of the FPGA, wherein the 5TSRAM cells or 6TSRAM cell matrices are aggregated or include a plurality of 5TSRAM cells or 6TSRAM cells for controlling the distribution of Corresponding crosspoint switch. In addition, 5TSRAM cells or 6TSRAM cells may be arranged in a matrix of 5TSRAM cells or 6TSRAM cells within many complex blocks of the FPGA, wherein each 5TSRAM cell or 6TSRAM cell matrix aggregates or includes a plurality of 5TSRAM cells or 6TSRAM cells for control in distributed locations on the corresponding crosspoint switch. The gates of both the control N-MOS transistor and the control P-MOS transistor within the crosspoint switch are connected or coupled to the two latch nodes of the 5TSRAM cell or the 6TSRAM cell, respectively. One of the latch nodes of the 5TSRAM cell or the 6TSRAM cell is connected or coupled to the control N-MOS transistor gate in the switch buffer circuit, and the other latch nodes of the 5TSRAM cell or the 6TSRAM cell are connected to the switch buffer. The gate of the control P-MOS transistor in the circuit. Stored on the node where the 5TSRAM cell and the 6TSRAM cell are connected to the cross-point switch, and the stored data is used to program the connection or disconnection between the two metal lines. When the data is stored in the 5TSRAM or 6TSRAM cell data "1" , when the latch node of "1" is connected to the gate of the control N-MOS transistor, and the other latch nodes of "0" are connected to the gate of the control P-MOS transistor, this pass/fail circuit (switch Buffer) allows data from the input end to pass to the output end, that is, the connection state between the two metal lines and the two nodes of the pass/non-pass circuit (essentially). When the data is stored in the 5TSRAM or 6TSRAM, it is programmed to "0" , where the latch node of "0" is connected to the gate of the control N-MOS transistor, and the other latch nodes of "1" are connected to the gate of the control P-MOS transistor, the complex control N-MOS transistor and The complex control P-MOS transistor is in the "off" state, and the data cannot pass from the input end to the output end, that is, the two metal lines and the two nodes of the pass/no pass circuit are in a disconnected state.

In addition, the cross-point switch may include, for example, a plurality of multiplexers and a plurality of switch buffers, and the multiplexer of the cross-point switch may select one n input data from the n input metal lines according to the data stored in the 5TSRAM cell and the 6TSRAM cell, And output the selected input data to the switch buffer, the switch buffer decides whether to pass or not pass the data output from the multiplexer to the output terminal of the switch buffer according to the data stored in the 5TSRAM cell and the 6TSRAM cell A metal line of the switch buffer includes a two-level inverter (buffer), a control N-MOS transistor and a control P-MOS transistor, wherein the data selected from the multiplexer is connected (input) to the common (connected) gate terminal of an input stage inverter of the buffer, and one of the metal wires is connected to the common (connected) drain terminal of an output stage inverter of the buffer, the output stage inverter being It is formed by stacking a control P-MOS and a control N-MOS, where the control P-MOS is at the top (between Vcc and the source of the P-MOS of the output stage inverter), and the control N-MOS is at the bottom ( between Vss and the source of the N-MOS of the output stage inverter). The connection state or disconnection state (pass or fail) of the switch buffer is controlled by the data (0 or 1) stored in the 5TSRAM cell or the 6TSRAM cell, and a latch node in the 5TSRAM cell and the 6TSRAM cell is connected or coupled to the control N-MOS transistor gate of the switch buffer circuit, and other latch nodes within the 5TSRAM cell and 6TSRAM cell are connected or coupled to the control P-MOS transistor gate of the switch buffer circuit, eg, a complex metal The line A and the plurality of metal lines B are respectively intersected and connected at an intersection, wherein the metal line A is divided into a metal line A1 segment and a metal line A2 segment respectively, and the metal line B is respectively divided into a metal line B1 segment and a metal line B2 segment, which intersect. The point switch can be set at the cross point, the cross point switch includes 4 pairs of multiplexers and switch buffers, each multiplexer has 3 input terminals and 1 output terminal, that is, each multiplexer can be stored in a 5TSRAM unit according to And the 2-bit data in the 6TSRAM cell selects one of the 3 input terminals as the output terminal. Each switch buffer receives the data output from the corresponding multiplexer and decides whether to pass or fail the received data according to the data stored in the third 5TSRAM unit and the third 6TSRAM unit. The point switch is set between the metal line A1 segment, the metal line A2 segment, the metal line B1 segment and the metal line B2 segment. The cross point switch includes 4 pairs of multiplexers/switch buffers: (1) The first multiplexer The three input terminals may be the metal line A1 segment, the metal line B1 segment and the metal line B2 segment. For the multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "0" and "0", the first The multiplexer selects the segment A1 of the metal line as the input end, and the segment A1 of the metal line is connected to the input end of a first switch buffer. For the first switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A1 segment is input to the metal line A2 segment. For the first switch buffer, if the 5TSRAM cell and the 6TSRAM cell When the bit data stored in the cell is "0", the data of the metal line A1 segment cannot pass to the metal line A2 segment. For the first multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "1" and "0", the first multiplexer selects the metal line B1 segment, and the metal line B1 segment is connected to the first switch The input end of the buffer, for the first switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B1 segment is input to the metal line A2 segment, for the first switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line B1 segment cannot pass to the metal line A2 segment. For the first multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "0" and "1", the first multiplexer selects the metal line B2 segment, and the metal line B2 segment is connected to the first switch The input end of the buffer, for the first switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B2 segment is input to the metal line A2 segment, for the first switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line B2 segment cannot pass to the metal line A2 segment. (2) The three input terminals of the first multiplexer may be the metal line A2 segment, the metal line B1 segment and the metal line B2 segment. For the second multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0" and "0", the second multiplexer selects the segment A2 of the metal line as the input end, and the segment A2 of the metal line is connected to the input end of a second switch buffer. For the second switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A2 segment is input to the metal line A1 segment. For the second switch buffer, if the 5TSRAM cell and the 6TSRAM cell When the bit data stored in the cell is "0", the data of the segment A2 of the metal line cannot pass to the segment of the metal line A1. For the second multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "1" and "0", the second multiplexer selects the metal line B1 segment, and the metal line B1 segment is connected to the second switch The input end of the buffer, for the second switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B1 segment is input to the metal line A1 segment, for the second switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line B1 segment cannot pass to the metal line A1 segment. For the second multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "0" and "1", the second multiplexer selects the metal line B2 segment, and the metal line B2 segment is connected to the second switch The input end of the buffer, for the second switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B2 segment is input to the metal line A1 segment, for the second switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line B2 segment cannot pass to the metal line A1 segment. (3) The three input terminals of the third multiplexer may be the metal line A1 segment, the metal line A2 segment and the metal line B2 segment. For the second multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0" and "0", the third multiplexer selects the segment of the metal line A1 as the input end, and the segment of the metal line A1 is connected to the input end of a third switch buffer. For the third switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A1 segment is input to the metal line B1 segment. For the third switch buffer, if the 5TSRAM cell and the 6TSRAM cell When the bit data stored in the cell is "0", the data of the metal line A1 segment cannot pass to the metal line B1 segment. For the third multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "1" and "0", the third multiplexer selects the metal line A2 segment, and the metal line A2 segment is connected to the third switch The input end of the buffer, for the third switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A2 segment is input to the metal line B1 segment, for the third switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data in the metal line A2 segment cannot pass to the metal line B1 segment. For the third multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "0" and "1", the third multiplexer selects the metal line B2 segment, and the metal line B2 segment is connected to the third switch The input end of the buffer, for the third switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B2 segment is input to the metal line B1 segment, for the third switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line B2 segment cannot pass to the metal line B1 segment. (4) The three input terminals of the fourth multiplexer may be the metal line A1 segment, the metal line A2 segment and the metal line B1 segment. For the fourth multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0" and "0", the fourth multiplexer selects the segment of the metal line A1 as the input end, and the segment of the metal line A1 is connected to the input end of a fourth switch buffer. For the fourth switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A1 segment is input to the metal line B2 segment. For the fourth switch buffer, if the 5TSRAM cell and the 6TSRAM cell When the bit data stored in the cell is "0", the data of the metal line A1 segment cannot pass to the metal line B2 segment. For the fourth multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "1" and "0", the fourth multiplexer selects the metal line A2 segment, and the metal line A2 segment is connected to the fourth switch The input end of the buffer, for the fourth switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line A2 segment is input to the metal line B2 segment, for the fourth switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data of the metal line A2 segment cannot pass to the metal line B2 segment. For the fourth multiplexer, if the 2-bit data stored in the 5TSRAM cell and the 6TSRAM cell are "0" and "1", the fourth multiplexer selects the metal line B1 segment, and the metal line B1 segment is connected to the fourth switch The input end of the buffer, for the fourth switch buffer, if the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "1", the data of the metal line B1 segment is input to the metal line B2 segment, for the fourth switch buffer. , If the bit data stored in the 5TSRAM cell and the 6TSRAM cell is "0", the data in the metal line B1 segment cannot pass to the metal line B2 segment. In this case, the crosspoint switch is bidirectional, and the crosspoint switch has 4 pairs of multiplexer/switch buffers, each pair of multiplexer/switch buffers is stored in 3 pairs of 5TSRAM cells and 6TSRAM cells Bit data control, a total of 12-bit data of 5TSRAM cells and 6TSRAM cells are required for the crosspoint switch. The 5TSRAM cells and the 6TSRAM cells can be distributed on the FPGA chip and located at or near the corresponding crosspoint switch. and/or switching buffers. In addition, 5TSRAM cells and 6TSRAM cells can be arranged in 5TSRAM cells and 6TSRAM cell matrices in certain blocks of the FPGA, wherein the 5TSRAM cells and 6TSRAM cells are aggregated or include a plurality of 5TSRAM cells and 6TSRAM cells. The multiplexer and/or switch buffer of the crosspoint switch. In addition, the 5TSRAM cells and the 6TSRAM cells can be arranged in one of the complex SRAM matrices in some complex blocks of the FPGA, wherein each 5TSRAM cell and 6TSRAM cell matrix aggregates or includes plural 5TSRAM cells and 6TSRAM cells for controlling the The multiplexers and/or switch buffers of the corresponding crosspoint switches at the distribution locations.

The programmable interconnection lines of commercial standard FPGA chips include one (or a plurality of) multiplexers located among (or between) interconnecting metal lines. Select one metal interconnect wire to connect to the output of the multiplexer. For example, if the number of metal interconnect wires is n=16, 5TSRAM cells and 6TSRAM cells with 4-bit data need to be connected to 16 inputs of the multiplexer. and connect or couple the selected metal interconnect to a metal interconnect connected to the output of the multiplexer, select a data from the 16 inputs to couple, pass or Connect to the metal wire connected to the output of the multiplexer.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the multi-chip package includes a commercial standard multiple FPGA IC chips and one or more non-volatile memory IC chips, wherein the non-volatile memory IC chips are used for For using the logic calculation and/or operation functions required for programming in different applications, the commercial standard complex FPGAIC chips are respectively bare chip type, single chip package or complex chip package, and each commercial standard complex FPGAIC chip can have a common standard Features or specifications; (1) Logic blocks, cells or elements include: (i) system gates with a number greater than or equal to 2M, 10M, 20M, 50M or 100M, (ii) a number greater than or equal to 64K, 128K, 512K, 1M, 4M or 8M logic units or elements, (iii) hard cores (hard macros) include, for example, digital signal processing (DSP) segments (elements) (slices), graphics processing units (graphic process units, (GPU) ) hard core, microcontroller unit (MCU) hard core, multiplexer hard core, multiplier hard core, addition hard core, arithmetic logic unit (arithmeticlogic) hard core, shift (shift) circuit hard core, Comparison circuit hard cores, floating-point computing hard cores, register or flip-flop hard cores, and/or I/O interface hard cores, each of which is made by having fixed hard wiring (fixed hardwiring) to design, compile and implement circuits, and/or (iv) have memory blocks with a bit number equal to or greater than 1M, 10M, 50M, 100M, 200M or 500M; (2) connected to each logic The number of inputs of blocks, units or elements or operators may be greater than or equal to 4, 8, 16, 32, 64, 128 or 256; (3) Power supply voltage: this voltage may be between 0.1 volts (V) to 8V between 0.1V and 6V, between 0.1V and 2.5V, between 0.1V and 2V, between 0.1V and 1.5V, or between 0.1V and 1V; (4) I/O pads on the chip layout , location, quantity and function. Since FPGA wafers are commercial standard IC wafers, FPGA wafers can be greatly reduced in design or product quantity, and therefore, the use of expensive masks or mask sets required in advanced semiconductor technology manufacturing can be greatly reduced. For example, it can be reduced to 3 to 20 sets of masks, 3 to 10 sets of masks, or 3 to 5 sets of masks for a particular technology, so NRE and manufacturing expenditure can be greatly reduced. For a small number of wafer designs or products, the manufacturing process can be adjusted or optimized through a small number of designs and products to achieve very high wafer fabrication yields. This approach is similar to the current advanced commercial standard DRAM, or NAND flash memory design and manufacturing process. Additionally, wafer inventory management becomes simple and efficient, resulting in shorter and more cost-effective FPGA wafer lead times.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package comprising a plurality of commercial standard FPGA IC chips and one or more non-volatile memory IC chips, wherein the non-volatile memory IC chips are used for use The logic calculation and/or operation functions required to be programmed for different applications, and the plurality of commercial standard FPGAIC chips are respectively bare chip type, single chip package or multiple chip package, and commercial standard logic drivers may have common standard features or specifications; logic A block, cell or element includes: (i) a number of system gates greater than or equal to 8M, 40M, 80M, 200M or 400M, (ii) a number greater than or equal to 256K, 512K, 2M, 4M, 16M or 32M Logic units or components, (iii) hard cores (hardmacros), for example, include digital signal processing (DSP) segments (components) (slices), graphics processing unit (graphic process unit, (GPU)) hard cores, microcontroller units (microcontrollerunit (MCU)) hard core, multiplexer hard core, multiplier hard core, addition hard core, arithmetic logic unit (arithmeticlogic) hard core, shift (shift) circuit hard core, comparison circuit hard core, floating point ( floating-point) computing hard cores, register or flip-flop hard cores, and/or I/O interface hard cores, where each hard core is designed, compiled and implemented by having fixed hardwiring Implemented circuits, and/or (iv) have memory blocks with a number of bits equal to or greater than 40M, 200M, 400M, 800M or 2G; (2) Supply voltage: this voltage can be between 0.1V and 12V, 0.1V to 7V, 0.1V to 3V, 0.1V to 2V, 0.1V to 1.5V, or 0.1V to 1V; (3) I/O pads in commercial standard logic drivers Layout, location, number, and function of a multi-die package where logic drivers may include I/O pads, metal posts, or bumps, connected to one or more (2, 3, 4, or more) USB ports, a or IEEE single-level package volatile memory driver 4 ports, one or more Ethernet ports, one or more audio source ports or serial ports such as RS-32 or COM ports, wireless transceiver I/O connections port, and/or Bluetooth signal transceiver port, etc. Logical drives may also include I/O pads, metal posts or bumps that communicate, connect or couple to memory disks, connect to SATA ports, or PCIs ports. Since logical drives can be produced in commercial standards, the product Inventory management becomes simple and efficient, resulting in shorter and more cost-effective logical drive lead times.

In another aspect, the present invention discloses commercialized standard logic drivers in a multi-chip package that includes a dedicated control chip designed to implement and manufacture various semiconductor technologies, including legacy or mature technologies such as non- Before, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm. Alternatively, this dedicated control wafer may use prior semiconductor technology, such as advanced or equal to, below or equal to 40 nm, 20 nm or 10 nm. This dedicated control chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology to commercialize a standard FPGAIC chip package within the same logic driver superior. The transistors used in the dedicated control chip can be FINFETs, GAAFETs, fully depleted silicon-on-insulator (FDSOI) MOSFETs, partially depleted silicon-on-insulator MOSFETs or conventional MOSFETs. The transistors used in the dedicated control die can be different from the commercial standard FPGAIC die package used in the same logic driver, eg the dedicated control die uses conventional MOSFETs, but the commercial standard FPGAIC die package in the same logic driver can be Use FINFET transistors or GAAFET transistors; or use FDSOIMOSFETs for dedicated control chips, but commercial standard FPGAIC chip packages within the same logic driver can use FINFET or GAAFET transistors. The functions of this dedicated control chip are: (1) downloading the programming software source code from the non-volatile IC chip in the external logic driver; (2) from the non-volatile IC chip (such as NAND or NOR flash memory) in the logic driver body IC chip) download programming software source code, data or information to switches (including pass-no pass switch gates and/or multiplexers) on programmable interconnects on commercial standard FPGA chips used in logic drivers 5TSRAM cells and 6TSRAM cells; and/or downloading programming software source code, data or information from a non-volatile IC chip (such as a NAND or NOR flash memory IC chip) within a logic drive to commercial use in logic drives 5TSRAM cells and 6TSRAM cells of programmable logic circuits, cells or blocks (including LUTs and/or multiplexers) that implement programmable logic operations/functions on standard FPGA chips. Alternatively, programmable software source code, data or information or result values from a non-volatile IC chip within a logic driver can be accessed into programmable interconnects or programmable logic operations/functions on a commercial standard FPGA chip. Programming logic circuits, cells or blocks of 5TSRAM cells and 6TSRAM cells can be preceded by a buffer or driver in a dedicated control chip. The driver of the dedicated control chip can latch the source code, data, information or result value from the non-volatile chip and increase the bandwidth of the data. For example, the data bandwidth (in standard SATA) from a non-volatile chip is 1 bit, the driver can latch this 1-bit data in each complex SRAM cell in the driver, and store or latch the complex parallel SRAM unit and also increase the data bandwidth, such as equal to or greater than 4-bit bandwidth, 8-bit bandwidth, 16-bit bandwidth, 32-bit bandwidth or 64-bit bandwidth, another example, from non-volatile The data bit bandwidth of the chip is 32 bits (under standard PCIs), and the booster can increase the data bit bandwidth to be greater than or equal to 64 bits, 128 bits or 256 bits , the driver in the dedicated control chip can amplify the data signal from the non-volatile chip; (3) as an input/output signal of a user application; (4) power management.

Another aspect of the present invention discloses that a commercial standard logic driver in a multi-chip package further includes a dedicated I/O chip that can be designed and fabricated using a variety of semiconductor technologies, including legacy or mature Technology, eg, not prior to, equal to, above, below 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. This dedicated I/O chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology to commercialize a standard FPGAIC within the same logic driver on the chip package. The transistors used in the dedicated I/O die can be fully depleted silicon-on-insulator (FDSOI) MOSFETs, partially depleted silicon-on-insulator MOSFETs, or conventional MOSFETs. The transistors used in the dedicated I/O die can be different from the commercial standard FPGAIC die package used in the same logic driver, e.g. the dedicated I/O die uses conventional MOSFETs, but the commercial standard within the same logic driver FPGAIC chip packages can use FINFET transistors; or dedicated I/O chips use FDSOIMOSFETs, but commercial standard FPGAIC chip packages within the same logic driver can use FINFETs. The power supply voltage used by the dedicated I/O chip can be greater than or equal to 1.5V, 2V, 2.5V, 3V, 3.5V, 4V or 5V, while the power supply voltage used by a commercial standard FPGAIC chip within the same logic driver can be less than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V. The power supply voltage used in the dedicated I/O die can be different from the commercial standard FPGAIC die package within the same logic driver, for example, the dedicated I/O die may use a power supply voltage of 4V, while the commercial The power supply voltage used by standard FPGAIC chip packages is 1.5V, or the power supply voltage used by dedicated IC chips is 2.5V, while the power supply voltage used by commercial standard FPGAIC chip packages within the same logic driver is 0.75V. The oxide layer (physical) thickness of the gate of Field-Effect-Transistors (FETs) can be greater than or equal to 5nm, 6nm, 7.5nm, 10nm, 12.5nm or 15nm, and is used in commercial logic drivers. The gate oxide (physical) thickness in FETs in standard FPGAIC chip packages can be less than 4.5 nm, 4 nm, 3 nm or 2 nm. The gate oxide thickness of FETs used in a dedicated I/O die can be different from the gate oxide thickness of FETs in a commercial standard FPGAIC die package used in the same arithmetic driver, for example, in a dedicated I/O die FETs have a gate oxide thickness of 10nm, compared to 3nm for FETs in commercial standard FPGAIC chip packages used in the same series of computing drivers, or for FETs in dedicated I/O chips The thickness of the gate oxide is 2nm in the FETs in the commercial standard FPGAIC chip package used in the same series computing driver. The dedicated I/O chip provides complex input terminals, complex output terminals and ESD protectors for logic drivers. This dedicated I/O chip provides: (i) huge complex drivers, complex receivers or I/O circuits for communication with the outside world ; (ii) Small complex drivers, complex receivers or I/O circuits for communicating with complex chips within a logic driver. Complex drivers, complex receivers, or I/O circuits for communication with the outside world whose drive capability, load, output capacitance, or input capacitance is greater than that of a small complex driver, complex receiver in a logic driver, or communication with a complex chip in a logic driver I/O circuit used. Complex drivers, complex receivers or I/O circuits for communication with the outside world have drive capability, load, output capacitance or input capacitance between 2pF and 100pF, 2pF and 50pF, 2pF and 30pF, 2pF and Between 20pF, between 2pF and 15pF, between 2pF and 10pF, between 2pF and 5pF, or greater than 2pF, 5pF, 10pF, 15pF or 20pF. The drive capability, load, output capacitance or input capacitance of a small complex driver, complex receiver or I/O circuit for communicating with complex chips within a logic driver can be between 0.1pF and 10pF, 0.1pF and 5pF , between 0.1pF and 2pF, or less than 10pF, 5pF, 3pF, 2pF or 1pF. The ESD protector size on a dedicated I/O die is larger than that in a commercial standard FPGAIC die in the same logic driver, and the ESD protector size in a large dedicated I/O die can be between 0.5pF and Between 20pF, 0.5pF and 15pF, 0.5pF and 10pF, 0.5pF and 5pF, or 0.5pF and 2pF, or greater than 0.5pF, 1pF, 2pF, 3pF, 5pF or 10pF, for example, a Bidirectional I/O (or tri-state) pads, I/O circuits that can be used in large I/O drivers or receivers, or I/O circuits used to communicate with the outside world (other than logic drivers) can include An ESD circuit, a receiver and a driver with input capacitance or output capacitance may be between 2pF and 100pF, between 2pF and 50pF, between 2pF and 30pF, between 2pF and 20pF, between 2pF and 15pF , between 2pF and 10pF or between 2pF and 5pF, or greater than 2pF, 5pF, 10pF, 15pF or 20pF. For example, a bidirectional I/O (or tri-state) pad, I/O circuitry may be used in a small I/O driver or receiver, or I/O circuitry used to communicate with multiple chips within a logic driver may include An ESD circuit, a receiver, and a driver with input capacitance or output capacitance may be between 0.1pF and 10pF, between 0.1pF and 5pF, between 0.1pF and 2pF, or less than 10pF, 5pF, 3pF, 2pF or 1pF.

Dedicated I/O chips (or multiple chips) in a multi-chip package in standard commercial logic drivers may include a buffer and/or driver circuit for: downloading programming software source code from a non-volatile IC chip within the logic driver, Data, information or result values to programmable interconnect 5TSRAM cells and 6TSRAM cells (switches including pass-through switch gates and multiplexers) and/or programmable logic circuits, cells, Components or blocks (including LUTs and multiplexers). Programmable software source code, data, information, or result values from non-volatile IC chips within the logic driver are obtained into 5TSRAM cells and 6TSRAM cells and/or bits in programmable interconnects on commercial standard FPGA chips. Programmable logic circuits, cells, elements or blocks on a standard commercial FPGAIC die can previously be routed through a buffer or driver in a dedicated I/O die. Drivers for dedicated I/O chips can latch data from non-volatile chips and increase data bandwidth. For example, the data bandwidth (in standard SATA) from a non-volatile chip is 1 bit, the driver can latch this 1-bit data in each complex SRAM cell in the driver, and store or latch the complex parallel SRAM unit and at the same time increase the data bandwidth, such as equal to or greater than 4-bit bandwidth, 8-bit bandwidth, 16-bit bandwidth, 32-bit bandwidth or 64-bit bandwidth, another example, from non-volatile The data bit bandwidth of the chip is 32 bits (under standard PCIs), and the booster can increase the data bit bandwidth to be greater than or equal to 64 bits, 128 bits or 256 bits , the driver in the dedicated I/O chip can amplify the data signal from the non-volatile chip.

Dedicated I/O die (or dies) in a multi-die package in commercial standard logic drives that include I/O circuits or pads (or micro-copper metal posts or bumps) as connections or couplings to one or more USB port, one or more IEEE1394 single-level package volatile memory driver 4 port, one or more Ethernet port, one or more audio source port or serial port, such as RS-232 or COM connection port, wireless signal transceiving I/Os and/or Bluetooth signal transceiving port, this dedicated I/O chip includes a plurality of I/O circuits or a plurality of pads (or a plurality of micro-copper metal pillars or bumps) as connections or couplings Connect to SATA ports or PCIs ports for communication, connection or coupling to memory drives.

Another aspect of the present invention discloses that a commercial standard logic driver in a multi-chip package further includes a dedicated control chip and a dedicated I/O chip. The dedicated control chip and the dedicated I/O chip provide functions as described above on a single chip As disclosed, this dedicated control chip and dedicated I/O chip can be designed to be implemented and fabricated using a variety of semiconductor technologies, including older or mature technologies, such as less advanced than, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm. The dedicated control chip and dedicated I/O chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology within the same logical drive Commercially available on standard FPGAIC chip packages. The transistors used in the dedicated control chips and dedicated I/O chips can be FINFETs, GAAFETs, FDSOIMOSFETs, partially depleted silicon insulator MOSFETs or conventional MOSFETs. The transistors used in the dedicated control chips and dedicated I/O chips can be from The commercial standard FPGAIC chip package used in the same logic driver is different, for example, the dedicated control chip and the dedicated I/O chip use conventional MOSFETs, but the commercial standard FPGAIC chip package in the same logic driver can use FINFET transistors or GAAFET transistors, or dedicated control chips and dedicated I/O chips use FDSOIMOSFETs, while commercial standard FPGAIC chip packages within the same logic driver can use FINFETs or GAAFETs for multiple small I/O chips within the I/O chip. The O circuit, that is, the small driver or receiver, and the large I/O circuit, that is, the large driver or receiver can all apply the specifications and contents of the dedicated control chip and the dedicated I/O chip disclosed above.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver comprising a plurality of commercial standard FPGA IC chips and one or more non-volatile IC chips, through field programming for use in various applications The required logic, computing and/or processing functions, wherein one or more non-volatile memory IC chips include one (or more) NAND flash chips, and/or a NOR flash chip in bare die type or chip package type Flash chips, each NAND flash chip may have a standard memory density, capacity or size greater than or equal to 64Mb, 512Mb, 1Gb, 4Gb, 16Gb, 128Gb, 256Gb or 512Gb, where "b" stands for bit, each (or Multiple) NOR flash chips with standard memory density, content or size greater than or equal to 1Mb, 4Mb, 16Mb, 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 4Gb or 16Gb, where "b" stands for bit, NAND flash Flash chips may be designed and manufactured using advanced NAND flash technology or next-generation process technology, eg, technology advanced at or equal to 45nm, 28nm, 20nm, 16nm and/or 10nm, where advanced NAND flash technology may be included in Single-level storage (Single Level Cells (SLC)) technology or multi-level storage (multiple level cells (MLC)) technology (for example, dual Layer storage (DoubleLevelCellsDLC) or triple storage (tripleLevelcellsTLC)). A 3DNAND structure may include a stack of layers (or levels) of multiple NAND memory cells, such as stacks of greater than or equal to 4, 8, 16, 32 NAND memory cells, one (or more) non-volatile memory IC chips including the above or below The disclosed NAND flash chips and/or NOR flash chips, and the non-volatile memory IC chips are used in logic drivers to: (a) store data or information for FPGA chips configured in the logic drivers , the NAND flash chip and/or NOR flash chip in the logic driver is used as a logic circuit (including the result values for LUTs and the multiplexer used to configure the logic circuit) stored in the FPGA chip in the logic driver data to select the resulting value from the corresponding LUTs) configuration data, and/or the FPGA chip's programming code stored in the logic driver for the switches (including those used to control pass/fail gates and multiplexing in the switches) (b) storing data or information required for the operation of the FPGA chip in the logic driver, wherein the FPGA chip has been configured with a specific operation or function, in one embodiment, the logic driver may include a NOR A flash chip and a NAND flash chip, wherein the NOR flash chip is used for storing data or information for configuring the FPGA chip, and the NAND flash chip is used for storing data or information for the operation of the FPGA chip.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver comprising a plurality of commercial standard FPGA IC chips and one or more non-volatile IC chips, through field programming for use in various applications Logic, computing and/or processing functions required where one or more non-volatile memory IC chips include one (or more) NAND flash chips in bare die or chip package style, commercial standard logic drivers can be Has a non-volatile chip or a plurality of non-volatile chips with a memory density, capacity or size greater than or equal to 8MB, 64MB, 128GB, 512GB, 1GB, 4GB, 16GB, 64GB, 256GB or 512GB, where "B" represents 8 bits.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver comprising a plurality of commercial standard FPGAIC chips, a dedicated I/O chip, a dedicated control chip, and one or more non-volatile memories IC chips, used through field programming to use logic, computing and/or processing functions required by various applications, communication between multiple chips in a logic driver and between the logic driver and the outside or outside (outside the logic driver) The disclosure of the communication is as follows: (1) The dedicated I/O chip can directly communicate with other chips or chips in the logic driver, and the dedicated I/O chip can also directly communicate with external circuits or external circuits (besides the logic driver) directly Communication, dedicated I/O chip includes two types of complex I/O circuits, one type has large driving capacity, large load, large output capacitance or large input capacitance as an external circuit or external circuit other than logic driver Communication, and another type with small drive capability, small load, small output capacitance or small input capacitance can directly communicate with other chips or multiple chips in the logic driver; (2) Multiple FPGAIC chips can directly communicate with logic Communication with other chips or multiple chips in the driver, but not with external circuits or external circuits outside the logic driver, wherein the I/O circuits in the plurality of FPGAIC chips can indirectly communicate with external circuits or external circuits outside the logic driver via dedicated The I/O circuit communication in the I/O chip, wherein the drive capability, load, output capacitance or input capacitance of the I/O circuit in the dedicated I/O chip is significantly larger than that of the I/O circuit in the complex FPGAIC chip, where the complex FPGAIC I/O circuits in the die (eg, output or input capacitance less than 2pF) are connected or coupled to large I/O circuits in the dedicated I/O die (eg, input or output capacitance greater than 3pF) as AND logic (3) The dedicated control chip can directly communicate with other chips or multiple chips in the logic driver, but does not communicate with external circuits or external circuits outside the logic driver, among which the dedicated control chip The I/O circuit in the chip can communicate indirectly with the external circuit outside the logic driver or the external circuit via the I/O circuit in the dedicated I/O chip, wherein the driving capability of the I/O circuit in the dedicated I/O chip, The load, output capacitance or input capacitance is significantly larger than the I/O circuit in the dedicated control chip. In addition, the dedicated control chip can communicate directly with other chips or multiple chips in the logic driver, and can also communicate with external circuits outside the logic driver or outside circuit communication; (4) one or more non-volatile memory IC chips can communicate directly with other chips or multiple chips in the logic driver, but not with external circuits or external circuits outside the logic driver, one or more of which are not An I/O circuit in the volatile memory IC chip can communicate indirectly with external circuits outside the logic driver or external circuits via the I/O circuit in the dedicated I/O chip, wherein The drive capability, load, output capacitance, or input capacitance of the I/O circuit in the dedicated I/O chip is significantly greater than that of the non-volatile memory IC chip in the I/O circuit, in addition, one or more non-volatile memory IC chips It can communicate directly with other chips or multiple chips in the logic driver, and can also communicate with external circuits or external circuits outside the logic driver. The above "object X communicates directly with object Y" means that object X (eg, the first chip in the logical driver) communicates or couples directly with object Y without going through or through any chip in the logical driver. The above "object X does not communicate directly with object Y" means that object X (eg, the first chip in a logical drive) can communicate or couple indirectly with object Y via a plurality of chips in any chip in the logical drive, and "Object X does not communicate with Object Y" means that Object X (eg, the first chip in a logical drive) does not communicate or couple with Object Y directly or indirectly.

Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver includes a plurality of commercial standard FPGA IC chips, a dedicated control chip and a dedicated I/O chip, and one or more non-volatile memory ICs Chips, programmed in the field to use the logic, computation and/or processing functions required by various applications, communication between multiple chips within a logic driver and external circuits outside each chip within the logic driver and the logic driver or The communication between external circuits is as follows: (1) The dedicated control chip and the dedicated I/O chip communicate directly with other chips or multiple chips in the logic driver, and can also communicate with external circuits or external circuits outside the logic driver. , this dedicated control chip and dedicated I/O chip include two types of complex I/O circuits, one type has large driving capacity, large load, large output capacitance or large input capacitance as a connection with logic driver. External circuit or external circuit communication, and another type with small drive capability, small load, small output capacitance or small input capacitance can communicate directly with other chips or multiple chips in the logic driver; (2)) Complex FPGAIC The chip can communicate directly with other chips or multiple chips in the logic driver, but not with external circuits or external circuits outside the logic driver, wherein the I/O circuits in the plurality of FPGAIC chips can indirectly communicate with external circuits outside the logic driver. The circuit or external circuit passes through the I/O circuit in the dedicated control chip and the dedicated I/O chip, wherein the drive capacity, load, output capacitance or input capacitance of the I/O circuit in the dedicated control chip and the dedicated I/O chip is significantly greater than I/O circuits in a plurality of FPGAIC chips, wherein the I/O circuits in a plurality of FPGAIC chips; (3) One or more non-volatile memory IC chips can communicate directly with other chips in a logic driver or a plurality of chips, but Do not communicate with external circuits or external circuits other than the logic driver, wherein an I/O circuit in one or more non-volatile memory IC chips can indirectly communicate with the external circuits or external circuits other than the logic driver through a dedicated control chip and The I/O circuit communication in the dedicated I/O chip, in which the drive capability, load, output capacitance or input capacitance of the dedicated control chip and the I/O circuit in the dedicated I/O chip are significantly greater than the non-volatile in the I/O circuit In addition, one or more non-volatile memory IC chips can communicate directly with other chips or chips in the logic driver, and can also communicate with external circuits or external circuits outside the logic driver. The descriptions "object X communicates directly with object Y", "object X does not communicate directly with object Y" and "object X does not communicate with object Y" have been disclosed and defined in the content of the preceding paragraphs. have the same meaning.

Another aspect of the present invention discloses a development kit or tool, as a user or developer using (via) a commercial standard logic driver to implement an innovative technology or application technology, a user or developer with innovative technology, new application concepts or ideas Users can purchase commercial standard logic drives and use corresponding development kits or tools for development, or software source code, data or programs are loaded into a plurality of non-volatile memory chips in commercial standard logic drives to implement other (or her) innovative technology or application concept idea, a standard commercial logic driver in a multi-chip package structure comprising a plurality of standard commercial FPGA IC chips and one (or more) non-volatile IC chips, one (or more) of which A) non-volatile IC chip including a NAND flash chip or/and a NOR flash chip in bare chip format or multi-chip flash memory package format, user's software source code, data, information, instructions or programs (related to innovation or application) is loaded and stored into one (or more) non-volatile IC chips in standard commercial logic drivers, and can be downloaded or coupled to programmable interconnects (switches include pass/no-go switches) Programmable logic circuits, cells, elements or blocks (including LUTs) in 5T or 6T SRAM cells of gates and multiplexers and/or downloaded or coupled to standard commercial FPGA IC chips in standard commercial logic drivers and multiplexers), provides an alternative to current ASICIC chip design, manufacturing, and business by incorporating FPGA chips and non-volatile IC chips in a one-chip package structure in standard commercial logic drivers, with load and Chip packages in logic drives storing software source code, data, information, instructions or programs (relating to innovative technologies or applications) can be sold as an ASICIC chip.

Another aspect of the present invention discloses a logic driver type in a multi-chip package, and the logic driver type further includes an innovative ASIC chip or COT chip (hereinafter referred to as IAC) as an intellectual property (IP) circuit, special application ( , ApplicationSpecific (AS)) circuits, analog circuits, mixed-signal (mixed-modesignal) circuits, radio frequency (RF) circuits and (or) transceivers, receivers, transceiver circuits, etc. IAC wafers can be designed for implementation and fabrication using a variety of semiconductor technologies, including older or mature technologies, such as less than, equal to, above, below 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. This IAC wafer can be used earlier than or equal to, less than or equal to 40 nm, 20 nm or 10 nm. This IAC chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on a commercial standard FPGAIC chip package within the same logic driver . This IAC chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on a commercial standard FPGAIC chip package within the same logic driver . The transistors used in the IAC wafers can be FINFETs, GAAFETs, FDSOIMOSFETs, PDSOIMOSFETs or conventional MOSFETs. The transistors used in the IAC die can be different from the commercial standard FPGAIC die packages used in the same logic driver, eg the IAC die uses conventional MOSFETs, but the commercial standard FPGAIC die packages within the same logic driver can use FINFETs Transistors; or IAC chips use FDSOIMOSFETs, but commercial standard FPGAIC chip packages within the same logic driver can use FINFETs or GAAFETs. IAC wafers can be designed for implementation and fabrication using a variety of semiconductor technologies, including older or mature technologies such as less than, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm, and NRE costs are Cheaper to design and manufacture than existing or conventional ASIC or COT wafers using advanced IC processes or next process generations, eg less advanced technologies than 30nm, 20nm or 10nm technologies. Designing an existing or conventional ASIC chip or COT chip using advanced IC process or next process generation, for example, more than US$5 million, US$10 million, US$2,000 compared to 30nm, 20nm or 10nm technology design 10,000 yuan or even more than US$50 million or US$100 million. 16nm technology or process generation such as ASIC chips or COTIC chips requires masks in excess of $2 million, $5 million or $10 million if logic drivers (including IAC chips) are used. Designs implementing the same or similar innovations or applications, and using older or less advanced technology or process generations can reduce this NRE cost by less than $10 million, $7 million, $5 million, USD 3 million or USD 1 million.

For the same or similar innovative technologies or applications, the NRE cost of developing IAC chips can be reduced by more than 2 times, 5 times, 10 times, 20 times or 30 times compared to the development of existing conventional logic operation ASICIC chips and COTIC chips.

Another aspect of the present invention discloses that a logic driver type in a multi-chip package may include a single dedicated control and IAC chip (hereinafter referred to as DCIAC chip) that integrates the functions of the dedicated control chip and the IAC chip. The DCIAC chip now includes control circuits, intellectual property circuits , special application (AS) circuits, analog circuits, mixed-signal circuits, RF circuits and/or signal transmission circuits, signal transceiver circuits, etc. DCIAC chips can be designed and manufactured using various semiconductor technologies, including old or mature ones. Technology, eg, not prior to, equal to, above, below 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. In addition, DCIAC wafers can be used earlier than or equal to, less than or equal to 40 nm, 20 nm or 10 nm. This DCIAC chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on multiple commercial standard FPGAIC chips within the same logic driver . The transistors used in the DCIAC die can be FINFETs or GAAFETs, FDSOIMOSFETs, partially depleted silicon insulator MOSFETs or conventional MOSFETs, the transistors used in the DCIAC die can be different from the commercial standard FPGAIC die packages used in the same logic driver For example, DCIAC chips use conventional MOSFETs, but commercial standard FPGAIC chip packages within the same logic driver may use FINFET transistors, while commercial standard FPGAIC chip packages within the same logic driver may use FINFETs or GAAFETs. Or DCIAC chips use FDSOIMOSFETs, while commercial standard FPGAIC chip packages within the same logic driver can use FINFETs or GAAFETs. DCIAC wafers can be designed for implementation and fabrication using a variety of semiconductor technologies, including older or mature technologies such as less than, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm, and NRE costs are Cheaper to design and manufacture than existing or conventional ASIC or COT wafers using advanced IC processes or next process generations, eg less advanced technologies than 30nm, 20nm or 10nm technologies. Designing an existing or conventional ASIC chip or COT chip using advanced IC process or next process generation, for example, more than US$5 million, US$10 million, US$2,000 compared to 30nm, 20nm or 10nm technology design 10,000 yuan or even more than US$50 million or US$100 million. This NRE cost can be reduced by less than US$10 million, US$7 if the same or similar innovations or applications are implemented using logic driver (including DCIAC chip) designs, and using older or less advanced technology or process generations $1 million, $5 million, $3 million, or $1 million. For the same or similar innovative technologies or applications, the NRE cost of developing DCIAC chips can be reduced by more than 2 times, 5 times, 10 times, 20 times or 30 times compared to the development of existing conventional logic operation ASICIC chips and COTIC chips.

Another aspect of the present invention discloses that the logic driver type in the multi-chip package may include a single dedicated control, control and IAC chip (hereinafter referred to as DCDI/OIAC chip) that integrates the functions of the dedicated control chip, dedicated I/O chip and IAC chip, DCDI/OIAC chips include control circuits, intellectual property circuits, special application (AS) circuits, analog circuits, mixed-signal circuits, RF circuits and/or signal transmission circuits, signal transceiver circuits, etc. DCDI/OIAC chips can use various semiconductor technologies Designed to be implemented and manufactured, including older or mature technologies such as not advanced, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm. DCDI/OIAC wafers can be designed for implementation and fabrication using a variety of semiconductor technologies, including older or mature technologies, such as not advanced, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm, in addition, DCDI/OIAC wafers can be used first at or equal to, below or equal to 40 nm, 20 nm or 10 nm. This DCIAC chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on multiple commercial standard FPGAIC chips within the same logic driver . The transistors used in the DCDI/OIAC die can be FINFETs or GAAFETs, FDSOIMOSFETs, partially depleted silicon-insulator MOSFETs or conventional MOSFETs, the transistors used in the DCDI/OIAC die can be from commercial standards used in the same logic driver FPGAIC chips are packaged differently, for example DCDI/OIAC chips use conventional MOSFETs, but commercial standard FPGAIC chip packages within the same logic driver can use FINFET transistors or GAAFET transistors, or DCDI/OIAC chips use FDSOIMOSFETs, while Commercially available standard FPGAIC chip packages within the same logic driver can use FINFETs. DCDI/OIAC wafers can be designed for implementation and fabrication using a variety of semiconductor technologies, including older or mature technologies such as not advanced, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm, and NRE The cost is cheaper than existing or conventional ASIC or COT chips to design and manufacture using advanced IC process or next process generation, eg more advanced technology than 30nm, 20nm or 10nm technology. Designing an existing or conventional ASIC chip or COT chip using advanced IC process or next process generation, for example, more than US$5 million, US$10 million, US$2,000 compared to 30nm, 20nm or 10nm technology design 10,000 yuan or even more than US$50 million or US$100 million. For example, 16nm technology or process generation of ASIC chips or COTIC chips will cost more than US$2 million, US$5 million or US$10 million for masks, if logic drivers (including DCDI/OIAC wafers) designed to implement the same or similar innovations or applications, and the use of older or less advanced technology or process generations can reduce this NRE cost by less than $10 million, $7 million, $5 million USD, USD 3 million or USD 1 million. For the same or similar innovative technologies or applications, the NRE cost of developing DCDI/OIAC chips can be reduced by more than 2 times, 5 times, 10 times, 20 times or 30 times compared to the development of existing conventional logic operation ASICIC chips and COTIC chips .

The present invention further discloses a way to change the existing hardware industry model of logic ASIC chips or COT chips into a software industry model through logic drivers. On the same innovation and application, the performance, power consumption, engineering and manufacturing cost of the logic driver should be better or the same as the existing conventional ASIC chips or conventional COTIC chips, and the design companies or suppliers of the existing ASIC chips or COTIC chips can be turned into software Developers or suppliers that only use older or less advanced semiconductor technology or process generations to design such IAC chips, DCIAC chips or DCDI/OIAC chips as above, disclosures in this regard may be (1) designed and owned by IAC chips, DCIAC chips or DCDI/OIAC chips; (2) procurement of multiple commercial standard FPGA chips and multiple commercial standard non-volatile memory chips in bare die or package form from third parties; (3) design and manufacture ( A third party that can outsource this manufacturing work to a manufacturing provider) contains its own IAC chip, DCIAC chip or DCI/OIAC chip logic driver; (3) Install in-house developed software to multiple In non-volatile memory IC chips in a plurality of non-volatile chips; and/or (4) sell pre-programmed logical drives to their customers, in which case they may still sell the hardware, the hardware ASICIC wafers or COTIC wafers that are not designed and fabricated using advanced semiconductor technologies, such as technologies that are more advanced than 30nm, 20nm or 10nm technologies. They can write software source code to program complex commercial standard FPGA chips in logic drivers for desired applications such as artificial intelligence (AI), machine learning, deep learning, big data database storage or analytics , Internet of Things (IOT), Virtual Reality (VR), Augmented Reality (AR), Automotive Graphics Processing (GP), Digital Signal Processing (DSP), Microcontroller (MC) or Central Processing Unit (CP) and other functions or any combination of them.

Another aspect of the present invention discloses that the logic driver type in a multi-chip package may include a plurality of commercial standard FPGA IC chips and one or more non-volatile IC chips, and further include a computing IC chip and/or a computing IC chip, such as using A CPU chip, a GPU chip, a DSP chip, a Tensor Processing Unit (TPU) chip and/or a special application processor chip (APU) designed and manufactured by advanced semiconductor technology or advanced generation technology, such as 30 nanometers (nm), 20 nm or 10 nm more advanced or equivalent, or smaller or same size semiconductor advanced process, or more advanced semiconductor advanced process than multiple FPGAIC chips used in the same logic driver. Such processing IC chips and computing IC chips may include: (1) CPU and DSP units; (2) CPU and GPU units; (3) DSP and GPU units; or (4) CPU, GPU and DSP units, processing IC chips and The transistor used in the computing IC chip may be FINFET or GAAFET, FINFETSOI or GAAFETSOI, FDSOIMOSFET, PDSOIMOSFET or a conventional MOSFET. In addition, the complex processing IC chip and the complex computing IC chip type may include a package type or incorporated in a logic driver, and the combination of the complex processing IC chip and the complex computing IC chip may include two types of chips, and the combination types are as follows: ( 1) One type of the complex processing IC chip and the complex computing IC chip is a CPU chip and the other type is a GPU chip; (2) One type of the complex processing IC chip and the complex computing IC chip is a CPU chip and the other type is DSP chip; (3) one type of the complex processing IC chip and the complex computing IC chip is a CPU chip and the other type is a TPU chip; (4) one type of the complex processing IC chip and the complex computing IC chip is a GPU chip and The other type is a DSP chip; (5) one type of the complex processing IC chip and the complex computing IC chip is a GPU chip and the other type is a TPU chip; (6) one type of the complex processing IC chip and the complex computing IC chip It is a DSP chip and another type is a TPU chip. In addition, complex processing IC chips and complex computing IC chip types may include packaged versions or incorporated within logic drivers, and combinations of complex processing IC chips and complex computing IC chips may include three types of chips, as follows: ( 1) One type of the complex processing IC chip and the complex computing IC chip is a CPU chip, the other type is a GPU chip, and the other type is a DSP chip type; (2) One type of the complex processing IC chip and the complex computing IC chip It is a CPU chip, the other type is a GPU chip, and the other type is a TPU chip type; (3) one type of the complex processing IC chip and the complex computing IC chip is a CPU chip, the other type is a DSP chip, and the other type is TPU chip type; (4) one type of complex processing IC chip and complex computing IC chip is a GPU chip, the other type is a DSP chip and the other type is a TPU chip type; or, a complex processing IC chip and a complex computing IC chip The combination may include: (1) a plurality of GPU chips, such as 2, 3, 4 or more than 4 GPU chips; (2) one or more CPU chips and one or more GPU chips; (3) one or more CPU chips and one or more DSP chips; (4) one or more CPU chips, one or more GPU chips and one or more DSP chips; (5) one or more CPU chips and/or one or more CPU chips and/or one or more TPU chips; (6) one or more CPU chips, one or more DSP chips and/or TPU chips, in all of the above alternatives, the logic driver may include one or more processing IC chips and a plurality of computing IC chips, and One or more high-speed, high-bandwidth cache SRAM chips or DRAM chips or NVM chips for high-speed parallel computing and/or computing functions. ) top-level interconnection structure (TopInterconnectionSchemein, onorofthelogicdrive (TISD)) transmission, such as logical drives including multiple GPU chips, such as 2, 3, 4 or more than 4 GPU chips, and multiple high-speed, high-bandwidth cache SRAM chips, DRAM chips Chip or NVM chip, wherein the communication between a GPU chip of the plurality of GPU chips and a chip of the plurality of SRAM chips, the plurality of DRAM chips or the NVM chips (wires or connecting wires that can be used for TISD) can be data bandwidth greater than or equal to 64K, 128K, 256K, 512K, 1024K, 2048K, 4096K, 8K or 16K, other examples are logic drivers may include multiple TPU chips, such as 2, 3, 4 or more than 4 TPU chips and multiple high-speed, high-bandwidth caches Communication between SRAM chips, DRAM chips or NVM chips, TPU chips, SRAM chips, DRAM chips or NVM chips can be used for TISD Metal lines or connecting lines, and the bit frequency of its data is greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, another example, the logic driver may include a plurality of FPGA chips, such as 2, 3, 4 or more than 4 multiple FPGA chips, and multiple high-speed, high-bandwidth cache SRAM chips, DRAM chips or NVM chips can be used for metal wires or connecting wires of TISD, and their data bit bandwidth is greater than or equal to 64K, 128K, 256K, 512K, 1024K, 2048K, 4096K, 8K or 16K.

(i) FPGA IC chips, computing chips and/or computing chips (such as CPU, GPU, DSP, APU, TPU and/or ASIC chips) and; (ii) communication in high-speed and high-bandwidth SRAM, DRAM or NVM chips, The connection or coupling is through (via) the TISD in the logic driver, wherein the logic driver as disclosed and described above is connected and communicated in a manner similar or similar to the internal circuits in the same chip. In addition, (i) FPGAIC chips, computing chips and/or computing chips (such as CPU, GPU, DSP, APU, TPU and/or ASIC chips) and; (ii) high-speed and high-bandwidth SRAM, DRAM or NVM chips Communication, connection or coupling is through (via) the TISD in the logical driver, wherein the logical driver is as disclosed and described above, and its connection and communication can use small complex I/O drivers or small complex receivers, small complex I/O The drive capability, load, output capacitance or input capacitance of an O driver, small complex receiver or complex I/O circuit can be between 0.01pF and 10pF, between 0.05pF and 5pF, between 0.01pF and 2pF Occasionally between 0.01pF and 1pF, or less than 10pF, 5pF, 3pF, 2pF, 1pF, 0.5pF or 0.01pF, for example, a bidirectional I/O (or tristate) pad, I/O Circuits can be used in small complex I/O drivers, complex receivers or complex I/O circuits and logic drivers in high-speed, high-bandwidth logic-input and memory-chip communications, and can include an ESD circuit, a receiver and a driver with an input capacitance or an output capacitance that may be between 0.01pF and 10pF, between 0.05pF and 5pF, between 0.01pF and 2pF, or between 0.01pF and 1pF, or less than 10pF , 5pF, 3pF, 2pF, 1pF, 0.5pF or 0.1pF.

A computing IC chip or a computing IC chip or a chip in a logic driver provides a fixed metal interconnect (off-field programming) for use in (field programmable) functions, processors, and operations, and these commercial standard FPGA IC chips provide (1 ) programmable metal interaction (field programmable) using (field programmable) functions, processors and operations and (2) fixed metal interaction using (non-field programmable) functions, processors and operations. Once the field programmable metal interconnects in the FPGAIC die are programmed, the FPGAIC die can be manipulated to provide powerful functions and operations in applications, such as providing Artificial Intelligence (AI), Machine Learning, Deep Learning, Big Data Database Storage or Analysis, Internet of Things (Internet Of Things, IOT), Virtual Reality (VR), Augmented Reality (AR), Automotive Electronic Graphics Processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) or any combination thereof.

Another aspect of the present invention discloses commercial standard FPGA IC chips used in logic drivers, commercial standard FPGA chips designed and manufactured using advanced semiconductor technology or advanced generation technology, eg, more advanced than 30 nanometers (nm), 20 nm or 10 nm Or equivalent, or smaller or the same advanced semiconductor process, a plurality of commercial standard FPGAIC chips by disclosing the steps of the manufacturing process in the following paragraphs:

(I) Provide a semiconductor substrate (such as a silicon substrate) or a silicon-on-insulator (SOI) substrate, wherein the form and size of the wafer are, for example, 8 inches, 12 inches or 18 inches, plural The transistor is formed on the surface of the substrate by advanced semiconductor technology or new generation technology wafer process technology. The transistor may be FINFET or GAAFET, FINFETSOI or GAAFETSOI, FDSOIMOSFET, PDSOIMOSFET or conventional MOSFET;

(II) A first interconnection structure (First Interconnection Scheme, onor of the Chip (FISC)) is formed on the surface of the substrate (or chip) or on the level containing transistors through a wafer process. The FISC includes a plurality of interconnect metal layers. There is an intermetal dielectric layer between the plurality of interconnect metal layers. The FISC structure can be formed by performing a single damascene copper process and/or a dual damascene copper process, for example, an The metal lines in the interconnect metal layer can be formed through a single damascene copper process. The following steps are as follows: (1) Provide a first insulating dielectric layer (which can be an intermetal dielectric layer on the exposed via metal layer or The top surface of the exposed metal pads, metal lines or interconnecting lines), the topmost layer of the first insulating dielectric layer can be, for example, a low dielectric constant (LowK) dielectric layer, such as a carbon-based silicon oxide ( SiOC) layer; (2) depositing a second insulating dielectric layer on the entire wafer or on the first insulating dielectric layer and on the first insulating dielectric layer, such as by chemical vapor deposition (Chemical Vapor Deposition (CVD)) method On the exposed via metal layer or the exposed metal pads, a second insulating dielectric layer is formed by (a) depositing a bottom distinguishing etch stop layer, such as a carbon-based silicon nitride (SiON) layer, on the first insulating layer exposing the via metal layer or the exposed metal pads on the topmost surface of the dielectric layer and in the first insulating dielectric layer; (b) then depositing a low-k dielectric layer on the bottom distinguishing etch stop layer, For example, a SiOC layer, the dielectric constant of this low-k dielectric material is smaller than that of silicon oxide material, the SiOC layer and the SiON layer can be deposited by CVD, the material of the first insulating dielectric layer and the second insulating dielectric layer of FISC Including an inorganic material, or a compound including silicon, nitrogen, carbon and (or) oxygen; (3) then forming trenches or openings in the second insulating dielectric layer, through the following steps: (a) coating, exposing, forming a plurality of trenches or a plurality of openings in a photoresist layer; (b) forming trenches or a plurality of openings in the second insulating dielectric layer by etching, and then removing the photoresist layer; (4) then depositing a The adhesive layer is on the entire wafer, including in the trenches or openings of the second insulating dielectric layer, for example, by sputtering or CVD to form a titanium (Ti) or titanium nitride (TiN) layer (thickness). (5) Next, a seed layer for electroplating is formed on the adhesion layer, such as sputtering or CVD to form a copper seed layer (the thickness of which is, for example, between 3 nanometers (nm) to 50 nanometers); between 200nm); (6) then electroplating a copper layer (the thickness of which is, for example, between 10nm to 3000nm, between 10nm and 1000nm, between 10nm and 500nm) on the copper seed layer; (7) ) and then use the Chemical-MechanicalProcess (CMP)) remove the metal (Ti or TiN/Cu seed layer/electroplated copper layer) outside the trenches or openings in the second insulating dielectric layer until the top surface of the second insulating dielectric layer is exposed, remaining in the The metal in the trenches or openings in the second insulating dielectric layer is used as a metal plug (metal plug), metal wire or metal connection wire of the interconnect metal layer in the FISC.

In another example, the metal lines and connecting lines of the interconnecting metal layers of the FISC and the metal plugs of the intermetal dielectric layer of the FISC can be formed by a dual damascene copper process. The steps are as follows: (1) Provide a first insulating dielectric layer to form On the surface of the exposed metal lines and connecting lines or metal pads, the topmost layer of the first insulating dielectric layer, such as a SiCN layer or a silicon nitride (SiN) layer; (2) forming a dielectric layer including a plurality of insulating dielectric layers The electrical stack is on the topmost layer of the first insulating dielectric layer and on the exposed metal lines and connecting lines or metal pad surfaces, the dielectric stack from bottom to top includes forming (a) a bottom low-k dielectric layer , such as a SiOC layer (used as a plug dielectric layer or an intermetal dielectric layer); (b) an intermediate etch stop layer, such as a SiCN layer or SiN layer; (c) a low-k SiOC top layer (used as a (d) a top-side differentiated etch stop layer, such as a SiCN layer or a SiN layer. All insulating dielectric layers (SiCN layer, SiOC layer or SiN layer) can be formed by CVD deposition; (3) forming trenches, openings or through holes in the dielectric stack, the steps include: (a) coating , exposing and developing a first photoresist layer within a trench or opening in the photoresist layer, then (b) etching the exposed top differentiated etch stop layer and top low-k SiOC layer and stopping in the middle differentiated etch stop layer ( SiCN layer or SiN layer), forming trenches or top openings in the dielectric stack, the formed trenches or top openings form metal lines and connecting lines in the interconnect metal layer through the subsequent dual damascene copper process; ( c) then, coating, exposing and developing a second photoresist layer and forming openings and holes in the second photoresist layer; (d) etching the exposed intermediate etch stop layer (SiCN layer or SiN layer), and The bottom low-k SiOC layer and the metal lines and connecting lines that stop in the first insulating dielectric layer form bottom openings or holes in the bottom of the dielectric stack, and the formed bottom openings or holes pass through the subsequent dual damascene copper process Forming a metal plug in an intermetal dielectric layer with a trench or top opening in the top of the dielectric stack overlapping a bottom opening or hole in the bottom of the dielectric stack, the top opening or hole having a larger size than the bottom opening or hole Larger, in other words, from the top view, bottom openings and holes in the bottom of the dielectric stack are surrounded by top trenches or openings in the dielectric stack; (4) forming metal lines, connecting lines and Metal plug, the steps are as follows: (a) depositing an adhesion layer on the wafer, including on the dielectric stack and in the etched trench or tip in the top of the dielectric stack, and in the dielectric stack Bottom openings or holes in the bottom, for example, by sputtering or CVD deposition of a Ti layer or a TiN layer (the thickness of which is, for example, between 1 nm and 50 nm); (b) Next, depositing a seed layer for electroplating on the adhesion layer, For example, a copper seed layer is deposited by sputtering or CVD (its thickness is, for example, between 3 nm and 200 nm); (c) then, a copper layer is electroplated on the copper seed layer (its thickness is, for example, between 20 nm and 6000 nm, 10 nm to 3000 nm or 10 nm to 1000 nm); (d) then, use CMP to remove unwanted metal (Ti layer or cavities) outside the trenches or top openings and inside the bottom openings or holes in the dielectric stack. TiN layer/copper seed layer/electroplated copper layer) until the top surface of the dielectric stack is exposed. The metal remaining in the trenches or top openings is used as metal lines or connecting lines in the interconnect metal layer, while the bottom openings or holes in the IMD layer are used as metal plugs for connecting metal plugs Above and below metal wires or connecting wires. In a single damascene process, the copper electroplating process steps and the CMP process steps can form metal lines or connecting lines in the interconnect metal layer, and then the copper electroplating process steps and the CMP process steps are performed again to form metal plugs in the IMD layer. On the interconnect metal layer, in other words, in a single damascene copper process, the copper electroplating process step and the CMP process step can be performed twice for forming metal lines or connecting lines in the interconnect metal layer and forming metal The metal plug in the inter-dielectric layer is on the interconnect metal layer. In the dual damascene process, the copper electroplating process steps and the CMP process steps are performed only once for forming the metal lines or connecting lines in the metal layer of the interconnection lines and forming the metal plugs in the intermetal dielectric layer on the metallization lines of the interconnection lines under the layer. A single damascene copper process or a dual damascene copper process can be used repeatedly to form metal lines or connecting lines in the interconnect metal layer and form metal plugs in the intermetal dielectric layer to form multiple interconnect metal layers in FISC Metal lines or connecting lines in layers and metal plugs in intermetal dielectric layers, FISC may include 4 to 15 layers of metal lines or connecting lines or 6 to 12 layers of metal lines or connecting lines in a plurality of interconnecting line metal layers.

The metal lines or connecting lines in the FISC are connected or coupled to the underlying transistors. The thickness of the metal lines or connecting lines in the FISC formed by the single damascene process or the bi-directional damascene process is between 3nm and 500nm, Between 10nm and 1000nm, or the thickness is less than or equal to 5nm, 10nm, 30nm, 50nm, 100nm, 200nm, 300nm, 500nm or 1000nm, and the width of the metal lines or connecting lines in FISC is, for example, between 3nm and 500nm between 10nm to 1000nm, or narrower than 5nm, 10nm, 30nm, 50nm, 100nm, 200nm, 300nm, 500nm or 1000nm, the thickness of the intermetal dielectric layer is, for example, between 3nm to 500nm, Between 10nm and 1000nm, or with thickness less than or equal to 5nm, 10nm, 30nm, 5 can be used for 0nm, 100nm, 200nm, 300nm, 500nm or 1000nm, the metal wire or connecting wire in FISC can be used as programmable interconnection wire .

(III) Depositing a passivation layer on the entire wafer and on the FISC structure, the passivation layer is used to protect the transistor and the FISC structure from moisture or contamination in the external environment, such as sodium free particles . The protective layer includes a free particle capture layer such as SiN layer, SiON layer and/or SiCN layer, the thickness of the free particle capture layer is greater than or equal to 100nm, 150nm, 200nm, 300nm, 450nm or 500nm, forming openings in the protective layer Inside, the upper surface of the topmost layer of the FISC is exposed.

(IV) forming a second interconnection scheme (SecondInterconnectionSchemein, onoroftheChip (SISC)) on the FISC structure, the SISC includes a plurality of interconnection metal layers, and a metal interlayer between each layer of the plurality of interconnection metal layers Electrical layers, and optionally including an insulating dielectric layer on top of the protective layer and between the bottommost interconnect metal layer of the SISC and the protective layer, then the insulating dielectric layer is deposited over the entire wafer, including the protective layer In the opening in the upper and protective layers, the 67 can have a planarization function, and a polymer material can be used as an insulating dielectric layer, such as polyimide, benzocyclobutene (BenzoCycloButene (BCB)), poly Para-xylene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the material of the insulating dielectric layer of SISC includes organic material, such as a polymer or material compound Including carbon, the polymer layer can be formed by spin coating, screen printing, dripping or injection molding. The metal plug is formed in the process, that is, the photosensitive photoresist polymer layer is coated and exposed through a mask, and then developed and etched to form a plurality of openings in the polymer layer and in the photosensitive photoresist insulating dielectric layer. The opening in the protective layer overlaps the opening in the protective layer and exposes the surface of the topmost metal layer of the FISC. In some applications or designs, the size of the opening in the polymer layer is larger than the opening in the protective layer, and the upper surface of the protective layer is partially exposed by openings in the polymer, then the photosensitive photoresist polymer layer (insulating dielectric layer) is cured at a temperature, for example, 100°C or higher, 125°C, 150°C, 175°C, 200°C, 225°C °C, 250°C, 275°C, or 300°C, followed in some cases by an emboss copper process on the cured polymer layer and the FISC topmost interconnects exposed within the cured polymer layer openings Line metal layer surface or protective layer surface exposed in the cured polymer layer opening: (a) First deposit an adhesive layer over the cured polymer layer across the wafer, and the topmost FISC interaction in the cured polymer layer opening The surface of the metal layer of the connection wire or the surface of the protective layer exposed in the opening of the cured polymer layer, for example, a Ti layer or a TiN layer (the thickness of which is, for example, between 1 nm and 50 nm) is deposited by sputtering or CVD; ( b) then depositing a seed layer for electroplating on the adhesion layer, eg by sputtering or CVD deposition (the thickness of which is eg between 3 nm and 200 nm); (c) coating, exposing and developing the photoresist layer on On the copper seed layer, trenches or openings are formed in the photoresist layer through subsequent processes, which are used to form the metal lines or connecting lines of the interconnected metal layer in the SISC, wherein the trenches (openings) in the photoresist layer. ) part can be combined with the cured polymer layer within the The entire area of the openings overlaps, the metal plugs in the openings of the cured polymer layer through a subsequent process; the copper seed layer is exposed at the bottom of the trenches or openings; (d) a copper layer (with a thickness of, for example, 0.3 µm to 20µm, 0.5µm to 5µm, 1µm to 10µm, 2µm to 20µm) on the copper seed layer at the bottom of patterned trenches or openings in the photoresist layer; (e ) remove the remaining photoresist layer; (f) remove or etch the copper seed layer and the adhesion layer not under the electroplated copper layer, the relief metal (Ti(TiN)/copper seed layer/electroplated copper layer) remains Or remain in the opening of the cured polymer layer for use as a metal plug in the insulating dielectric layer and a metal plug in the protective layer; and the relief metal (Ti(TiN)/copper seed layer/electroplated copper layer) remains Or the location of trenches or openings remaining in the photoresist layer (where the photoresist layer will be removed after the electroplated copper layer is formed) for interconnecting metal lines or connecting lines of the metal layers. The process of forming the insulating dielectric layer and its openings, and the metal plugs and interconnecting wires in the insulating dielectric layer are formed by the raised copper process. The metal lines or connecting lines of the metal layer can be repeated to form multiple interconnections in SISC Line metal layers, where the insulating dielectric layer is used as an intermetal dielectric layer between a plurality of interconnecting wire metal layers in SISC, and in the insulating dielectric layer (now within the intermetal dielectric layer) The metal plug is used to connect or couple the metal wires or connecting wires on the upper and lower layers of the metal layer of the multiple interconnecting wires. The electrical layer has a plurality of openings exposing the upper surface of the topmost interconnection wire metal layer. The SISC may include, for example, 2 to 6 layers of interconnection wire metal layers or 3 to 5 layers of interconnection wire metal layers. The metal lines or connecting lines of the interconnect metal layer have an adhesive layer (such as a Ti layer or a TiN layer) and a copper seed layer located only at the bottom of the metal lines or connecting lines, but not on the sidewalls of the metal lines or connecting lines. In FISC, a plurality of interconnected metal layers of metal lines or connecting lines have an adhesive layer (eg, a Ti layer or a TiN layer) and a copper seed layer located on the bottom and sidewalls of the metal lines or connecting lines.

The interconnecting metal lines or connecting lines of the SISC are connected or coupled to the interconnecting metal lines or connecting lines of the FISC, or to the transistors in the wafer via metal plugs in openings in the protective layer, the metal lines or connecting lines of the SISC. Thickness between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, between 1µm and 10µm, or between 2µm and 10µm, or thickness greater than or equal to 0.3 µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, and the metal line or connecting line width of SISC is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 1µm. Between 5µm, 1µm to 10µm, or 2µm to 10µm, or widths greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, or 3µm. The thickness of the IMD layer is, for example, between 0.3 µm and 20 µm, between 0.5 µm and 10 µm, between 1 µm and 5 µm, between 1 µm and 10 µm, or between 2 µm and 10 µm , or the thickness is greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, the metal wires or connecting wires of SISC are used as programmable interactive connecting wires.

(v) forming micro copper pillars or bumps (i) in the upper surface of the topmost interconnect metal layer of the SISC and within exposed openings in the insulating dielectric layer in the SISC, and (or) (ii) in the topmost SISC on the top insulating dielectric layer. Micro copper pillars or bumps are formed by performing the copper relief process disclosed and described in the above paragraphs, wherein the steps of the copper relief process are as follows: (a) depositing an adhesive layer on the entire wafer or in the SISC structure on the topmost dielectric layer, and in the openings in the topmost insulating dielectric layer, for example, by sputtering or CVD deposition of a layer of Ti or TiN (the thickness of which is, for example, between 1 nm and 50 nm); (b) Then deposit a seed layer for electroplating on the adhesion layer, such as sputtering or CVD to deposit a copper seed layer (the thickness of which is, for example, between 3 nm and 300 nm or between 3 nm and 200 nm); (c) coating, Expose and develop a photoresist layer; form a plurality of openings or holes in the photoresist layer for subsequent procedures to form micro metal pillars or bumps, exposing (i) the topmost top of the bottom of the opening in the topmost insulating layer of the SISC Interconnecting the upper surface of the metal layer of the wire; and (ii) exposing the SISC topmost insulating dielectric layer region or annular portion, the region bounding the opening in the topmost insulating dielectric layer; (d) then, electroplating a copper layer (whose thickness is, for example, between 3 µm and 60 µm, between 5 µm and 50 µm, between 5 µm and 40 µm, between 5 µm and 30 µm, between 3 µm and 20 µm, or between 5 µm and 15µm) on the copper seed layer in the patterned openings or holes of the photoresist layer; (e) remove the remaining photoresist layer; (f) remove or etch the copper seed layer and the adhesion layer not under the electroplated copper layer; The remaining or retained metal is used as micro copper pillars or bumps.

The micro copper pillars or bumps are connected or coupled to the interconnection metal lines or lines of the SISC and the interconnection metal lines or lines of the FISC, and to the chip through metal plugs in the openings in the topmost insulating dielectric layer of the SISC in the transistor. The heights of the micro metal pillars or bumps are between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 20µm. Between 5µm and 15µm or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm or 3µm, the maximum diameter of the cross-section of the micro metal post or bump (such as the diameter of a circle or a square or the diagonal length of a rectangle) e.g. between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, Between 5µm and 15µm or between 3µm and 10µm, or less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the nearest metal pillar or bump of the micro metal pillar or bump Spatial distance between 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 5µm Between 15µm or 3µm to 10µm, or less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

(VI) dicing the wafer to obtain a plurality of separate commercial standard FPGA chips, the plurality of commercial standard FPGA chips sequentially from bottom to top respectively include: (i) a transistor layer; (ii) FISC; (iii) a protective layer; (iv) the SISC layer and (v) the micro copper pillars or bumps, the height of the top layer of the topmost insulating dielectric layer of the SISC is, for example, between 3 μm and 60 μm, between 5 μm and 50 μm, between 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 15µm, or 3µm to 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm or 3µm.

Another aspect of the present invention provides a fan-out interconnection technology (FOIT) for fabricating or manufacturing a logic driver according to the multi-chip packaging technology and process. The process steps are as follows:

(1) Provide a chip carrier, support, molding material or substrate, and a plurality of IC chips and packages; then place, fix or adhere a plurality of IC chips and package them on the chip carrier, support, molding material or substrate, the chip carrier, The holder, potting material or substrate can be wafer type (with a diameter of 8", 12" or 18" wafers), or a square or rectangular panel type (with a width or length greater than or equal to 20cm, 30cm) , 50cm, 75cm, 100cm, 150cm, 200cm or 300cm), the material of the wafer carrier, holder, potting material or substrate can be silicon material, metal material, glass material, plastic material, polymer material, epoxy-base polymer material or epoxy based compound material. The plurality of IC chips and packages disclosed and described above can be disposed, fixed or adhered on a chip carrier, support, potting material or substrate, wherein the plurality of IC chips and packages include a plurality of commercial standard FPGA IC chips, a plurality of non-volatile I/O chips or packages, dedicated control chips, multiple dedicated I/O chips, dedicated control and I/O chips, IAC, DCIAC and/or DCDI/OIAC chips, all of which are located in multiple logic drivers and are Micro copper pillars or bumps are arranged on the upper surface of the micro copper pillars or bumps, and the upper surface of the micro copper pillars or bumps has a level above the level of the upper surface of the topmost insulating dielectric layer of the plurality of chips, and its height is, for example, between 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 15µm, or 3µm to 10µm time, or greater than or equal to 30µm, 20µm, 15µm, 5µm or 3µm, when the plurality of wafers are set, fixed or adhered on a wafer carrier, support, potting material or substrate, the surface or side of the wafer with the plurality of transistors is oriented, The backside of the silicon substrate of the plurality of chips (the side that does not have the plurality of transistors) is disposed, fixed or adhered on the chip carrier, the holder, the potting material or the substrate facing down.

(II) Filling the gaps between the plurality of wafers and covering the plurality of wafers with a material, resin or compound, such as by spin coating, screen printing or dripping or casting, the casting method includes Pressure casting mold (using upper and lower molds) or pouring casting mold (using dripping method), the material, resin or compound can be a polymer material, such as polyimide, benzocyclobutene, Parylene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone (silicone), this polymer can be, for example, photosensitive polyimide/PBOPIMEL provided by Japan Asahi Kasei Company ™, epoxy resin-based casting compound, resin or sealant provided by NagaseChemteX, Japan, which material, resin or compound is applied (via coating, printing, dripping or casting) to wafer carriers, supports, castings Above the material or substrate and on the plurality of wafers to a level, such as (i) filling the gaps of the plurality of wafers; (ii) covering the top of the plurality of wafers; (iii) filling the micro copper pillars on the plurality of wafers or gaps between bumps; (iv) covering the upper surfaces of micro-copper pillars or bumps on a plurality of wafers, the materials, resins and compounds can be cured or cross-linked by heating to a specific temperature, The specific temperature is, for example, higher than or equal to 50°C, 70°C, 90°C, 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C, and the material can be a polymer Or pour the mold material, use CMP polishing or grinding to fully expose the surface of the used material, resin or compound to the upper surface of all micro-bumps or pillars on the plurality of wafers. The wafer carrier, support, potting material or substrate may then: (i) After the CMP process and before forming the top interconnect structure (TISD) on the logic driver, the wafer carrier, support, potting material or substrate may be removed , where the TISD will be disclosed below; (ii) the chip carrier, support, potting material or substrate remains in wafer or panel form during subsequent steps of manufacturing the logic drive, after all process steps of producing or fabricating the logic drive The wafer carrier, support, potting material or substrate is removed, or (iii) is retained as part of the finalized and separated logic drive product, and the wafer carrier, support, potting material or substrate can be removed in a manner such as a CMP process, a polishing process, a wafer back grinding process, or, in a wafer or panel process, a CMP process, a polishing process, a wafer back grinding process to remove part of the wafer or panel to make it thinner, in all After the wafer or panel process is completed, the wafer or panel can be separated into a plurality of individual logic drivers by dicing.

(III) Forming a top interconnect structure (TISD) on the logic driver through a wafer or panel process on the planarization material, resin or compound and on the exposed upper surface of the micro metal pillars or bumps, the TISD includes a plurality of metal layers , with an inter-metal dielectric layer between each metal layer, and optionally including an insulating dielectric layer on the planarizing material, resin or compound layer and on the bottom of the planarizing material, resin or compound layer and the TISD Between the metal layers of the terminal interconnects, the metal lines or interconnects of the multiple interconnect metal layers in TISD are located above the plurality of wafers and extend horizontally across the edges of the plurality of wafers. In other words, the metal lines or interconnects pass through the logic The gap between the plurality of chips of the driver, the plurality of interconnecting wires in the TISD, the metal wires or connecting wires of the metal layer connect or couple the circuits of two or more chips of the logic driver, the steps of TISD formation are as follows: TISD insulation The dielectric layer is then deposited over the entire wafer, including on the top surface of the planarizing material, resin or compound layer and the exposed top surface of the micro copper pillars or bumps. The insulating dielectric layer has the function of planarizing, and a polymer material can be Insulating dielectric layers for TISD, such as polyimide, benzocyclobutene, parylene, epoxy base material or compound, photosensitive epoxy SU-8, elastomer or silicone ), the material used for the insulating dielectric layer of TISD includes organic materials, such as a polymer, or a material compound including carbon, and the polymer layer can be formed by spin coating, screen printing, dripping or injection molding , the material of the polymer can be a photosensitive material, which can be used for patterning openings in the photogroup layer to form metal plugs in the subsequent process, that is, coating the photosensitive photoresist polymer layer and exposing it through a photomask , and then develop and etch to form a plurality of openings in the polymer layer, openings in the photosensitive photoresist insulating dielectric layer and the exposed upper surface of the micro copper pillars or bumps, micro copper pillars on the plurality of chips in the logic driver or the exposed top surfaces of the bumps overlap, in some applications or designs, the opening size in the polymer layer is smaller than the size of the top surface of the microcopper pillars or bumps, in other applications or designs, in the polymer layer The size of the openings in the layer is larger than the size of the upper surface of the micro copper pillars or bumps, the openings in the polymer layer expose the upper surface of the planarizing material, resin or compound layer, followed by the photosensitive photoresist polymer layer (insulating dielectric layer). ) curing at a temperature, for example above 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C, followed by a relief ( emboss) copper process openings in the cured polymer layer on or over the insulating dielectric layer of the TISD and on or over the exposed upper surface of the micro-copper pillars or bumps in the openings in the cured polymer layer On or over the exposed upper surface of the planarizing material, resin or compound in: (a) first deposit an adhesive layer over the cured polymer layer of the entire wafer, and a plurality of openings in the cured polymer layer The exposed upper surface of the micro-copper pillars or bumps in the, in some cases, an adhesion layer may be deposited in the plurality of openings in the cured polymer layer The upper surface of the exposed planarization material, resin or compound, for example, via Sputtering, CVD deposition of a Ti layer or a TiN layer (the thickness of which is between 1 nm and 50 nm, for example); (b) then depositing a seed layer for electroplating on the adhesion layer, such as by sputtering or CVD deposition way (the thickness of which is, for example, between 3 nm and 400 nm or between 3 nm and 200 nm); (c) coating, exposing and developing a photoresist layer on the copper seed layer, and forming trenches or The opening is in the photoresist layer, which is used to form the metal lines or connecting lines of a plurality of interconnected metal layers in TISD, wherein the trench (opening) part in the photoresist layer can be with the entire area of the opening in the cured polymer layer Overlapping, metal plugs in the cured polymer layer openings via a subsequent procedure; copper seed layers exposed at the bottom of the trenches or openings; (d) followed by electroplating of a copper layer (with a thickness between, for example, 0.3µm to 20µm) , 0.5µm to 5µm, 1µm to 10µm, 2µm to 10µm) on the copper seed layer at the bottom of patterned trenches or openings in the photoresist layer; (e) removed The remaining photoresist layer; (f) remove or etch the copper seed layer and the adhesion layer not under the electroplated copper layer, the relief metal (Ti(TiN)/copper seed layer/electroplated copper layer) remains or remains in In openings in the cured polymer layer for use as metal plugs in the insulating dielectric layer; and trenches where the raised metal (Ti(TiN)/copper seed layer/electroplated copper layer) remains or remains in the photoresist layer Or the location of the openings (wherein the photoresist layer will be removed after the formation of the electroplated copper layer) is used for the metal lines or connecting lines of the plurality of interconnecting metal layers in TISD, the process of forming the insulating dielectric layer and the plurality of openings, and The copper relief process is used to form the plurality of metal plugs and the plurality of interconnection lines in the insulating dielectric layer. The metal lines or connecting lines in the metal layer can be repeated to form the plurality of interconnection line metal layers. In TISD, the insulating dielectric An electrical layer is deposited in the interconnect metal layers and between interconnects, wherein the top portion of the insulating dielectric layer is used as an intermetal dielectric layer between two interconnect metal layers in TISD, and a plurality of metal plugs in the top portion of the insulating dielectric layer (now in the intermetal dielectric layer) for connecting or coupling the metal lines or connecting lines of the two plurality of interconnected metal layers in the TISD, the insulating dielectric The bottom part of the layer is used as a dielectric layer between the interconnecting lines in the same interconnecting metal layer of TISD, which means that the metal lines or connecting lines of the interconnecting metal layer are located at the bottom of the insulating dielectric layer. , the metal layer of the topmost plurality of interconnecting lines of the TISD is covered by the topmost insulating dielectric layer of the TISD, and the topmost insulating dielectric layer has a plurality of openings in the insulating dielectric layer and exposes the upper surface of the metal layer of the topmost plural interconnecting lines , TISD can include 2 to 6 layers of complex interconnection wire gold Metal layers or 3 to 5 layers of multiple interconnecting metal layers, the interconnecting metal lines or interconnecting lines in TISD have an adhesive layer (such as a Ti layer or a TiN layer) and a copper seed layer only at the bottom, not at the bottom On the sidewalls of the metal lines or connecting lines, the interconnecting metal lines or connecting lines of the FISC have an adhesive layer (eg, a Ti layer or a TiN layer) and a copper seed layer on the bottom and sidewalls of the metal lines or connecting lines.

TISD interconnecting metal lines or connecting lines are connected or coupled to a plurality of SISC interconnecting metal lines or connecting lines, FISC interconnecting metal lines or connecting lines and/or logic drivers through micro-metal pillars or bumps on a plurality of wafers The transistors on the wafer, the plurality of wafers are surrounded by resin material or compound filling the gaps between the plurality of wafers, the surface of these wafers is also covered with resin material or compound, the thickness of metal wires or connecting lines in TISD is, for example, between 0.3µm to 30µm, 0.5µm to 20µm, 1µm to 10µm, or 0.5µm to 5µm, or thicker than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, the width of metal lines or connecting lines in TISD is for example between 0.3µm and 30µm, between 0.5µm and 20µm, between 1µm and 10µm, or between 0.3µm and 30µm. Between 0.5µm and 5µm, or the width is greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, the thickness of the IMD layer of TISD is, for example, 0.3µm to 30µm, 0.5µm to 20µm, 1µm to 10µm, or 0.5µm to 5µm, or thicker than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, the metal lines or connecting lines of the metal layer of the multiple interconnection lines in TISD can be used for the multiple programmable interconnection lines.

(IV) Forming a plurality of copper pillars or bumps on the topmost insulating dielectric layer in the TISD through the copper embossing process disclosed above, and in the plurality of openings of the topmost insulating dielectric layer in the TISD On the exposed upper surface of the topmost plurality of interconnected metal layers, the process steps are as follows: (a) deposit t72 on the topmost insulating dielectric layer of the TISD of the entire wafer or panel, and the topmost insulating dielectric layer in the TISD The exposed upper surface of the metal layers of the interconnecting lines in the plurality of openings, such as sputtering or CVD deposition of a Ti layer or TiN layer (the thickness of which is, for example, between 1 nm and 200 nm or between 5 nm and 50 nm); (b) then depositing a seed layer for electroplating on the adhesion layer, such as sputtering or CVD deposition of a copper seed layer (the thickness of which is, for example, between 3 nm and 400 nm or between 10 nm and 200 nm); (c) ) Through the processes of coating, exposure and development, patterned openings and holes in the photoresist layer and exposing the copper seed layer to form copper pads, the openings in the photoresist layer are insulated from the tops of the openings in the TISD Overlapping of dielectric layers, and an annular block of copper pillars or bumps surrounding (TISD) top-most insulating dielectric layer openings that can extend from the top-most insulating dielectric layer to TISD ; (d) followed by electroplating of a copper layer (with a thickness of, for example, between 1 µm and 50 µm, between 1 µm and 40 µm, between 1 µm and 30 µm, between 1 µm and 20 µm, between 1 µm and 10µm, 1µm to 5µm, or 1µm to 3µm) on the copper seed layer within the opening of the photoresist layer; (e) remove the remaining photoresist; (f) remove or etch The copper seed layer and the adhesion layer not under the electroplated copper layer, the remaining metal layer is used as a plurality of copper pillars or bumps, and the plurality of copper pillars or bumps can be used for connection or coupling to a plurality of chips of logic drivers, such as It is a dedicated I/O chip to external circuits or components other than logic drivers. The height of the plurality of copper pillars or bumps is, for example, between 5µm and 120µm, between 10µm and 100µm, and between 10µm and 60µm. between 10µm and 40µm or between 10µm and 30µm, or greater than, higher than or equal to 50µm, 30µm, 20µm, 15µm or 10µm, the largest diameter in cross-sectional view of a plurality of copper pillars or bumps (e.g. diameter of a circle or diagonal of a square or rectangle) e.g. between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, between 10µm Between 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the minimum space (gap) between the nearest copper pillars or bumps is, for example, between 5µm and 120µm, between 10µm to 100µm, 10µm to 60µ m, 10µm to 40µm or 10µm to 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, copper bumps or copper metal pillars can be used for logic drivers The driver is flip-chip packaged on a substrate, flex board or motherboard, similar to the flip-chip assembly chip packaging technology or Chip-On-Film (COF) packaging technology used in LCD driver packaging technology, such as a substrate, flex board or motherboard. It can be used on a printed circuit board (PCB), a silicon substrate with an interconnect structure, a metal substrate with an interconnect structure, a glass substrate with an interconnect structure, a ceramic substrate with an interconnect structure, or a A flexible board with an interconnecting wire structure, a substrate, a flexible board or a motherboard may include a plurality of metal bonding pads or bumps on its surface, the plurality of metal bonding pads or bumps having a solder layer on its top surface for soldering A flow or thermal bonding process bonds a plurality of copper pillars or bumps on the logic driver package, the plurality of copper pillars or bumps being arranged on the front surface of the logic driver package with a Ball-Grid-Array (BGA) A layout in which a plurality of copper pillars or bumps in the peripheral area are used for signal I/Os, and the power/ground (P/G) I/Os near the central area, and the signal bumps can form a ring (circle) in the peripheral area The shape area is along the boundary of the logic driver driver package, such as 1 circle, 2 circles, 3 circles, 4 circles, 5 circles or 6 circles, and the spacing of the complex signal I/Os in the circle area can be smaller than the power/ Ground (P/G) I/Os on or near the center area of the logic driver package.

Alternatively, a plurality of solder bumps may be formed on or over the topmost insulating dielectric layer in the TISD through a copper relief/solder process, and the topmost plurality of interconnection metal layers within the plurality of openings of the topmost insulating dielectric layer in the TISD are exposed On the upper surface, the process steps are as follows: (a) depositing an adhesive layer on or above the topmost insulating dielectric layer in the TISD on the entire wafer or panel, and the topmost multiple interconnections in the plurality of openings of the topmost insulating dielectric layer in the TISD The exposed upper surface of the wire metal layer, such as sputtering or CVD deposition of a Ti layer or TiN layer (the thickness of which is, for example, between 1 nm and 200 nm or between 5 nm and 50 nm); (b) Then deposit a layer for electroplating The seed layer is on the adhesion layer, for example, by sputtering or CVD deposition of a copper seed layer (the thickness of which is, for example, between 3 nm and 400 nm or between 10 nm and 200 nm); (d) by coating, exposing and developing and other processes, patterned multiple openings and holes in the photoresist layer and exposed the copper seed layer for the formation of subsequent multiple solder bumps, openings in the photoresist layer and openings in the topmost insulating dielectric layer in the TISD and the opening in the topmost insulating dielectric layer extends to a region of the topmost insulating dielectric layer in the TISD or an annular region surrounding the opening in the topmost insulating dielectric layer; (d) then electroplating a copper barrier layer ( Its thickness is, for example, between 1 µm and 50 µm, between 1 µm and 30 µm, between 1 µm and 20 µm, between 1 µm and 10 µm, between 1 µm and 5 µm, or between 1 µm and 3 µm. between) on the copper seed layer in the opening of the photoresist layer; (e) then electroplating a solder layer (with a thickness of, for example, between 1 µm and 150 µm, between 1 µm and 120 µm, between 5 µm and 120 µm) , 5µm to 100µm, 5µm to 75µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, between 5µm and 10µm or between 1µm and 3µm) on the electroplated copper barrier layer within the opening of the photogroup layer; (f) remove the remaining photoresist; (g) remove or etch the remaining photoresist Copper seed layer and adhesion layer under electroplated copper barrier layer and electroplated solder layer; (h) Reflow solder layer to form multiple solder bumps, remaining metal (Ti layer (or TiN layer)/Cu seed layer/resistor layer) Barrier copper layer/solder layer) through the solder flow process and used as a plurality of solder bumps, the material of the plurality of solder bumps can be lead-free solder, the lead-free solder in commercial applications can include tin alloys, copper metal, silver Metal, bismuth metal, indium metal, zinc metal, antimony metal, or other metals, such as lead-free solder can include tin-silver-copper solder, tin-silver solder, or tin-silver-copper-zinc solder, for multiple solder bumps For multiple chips connected or coupled to logic drivers, such as dedicated I/O chips, to external circuits or components other than logic drivers, the height of the plurality of solder bumps is, for example, between 5µm and 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or greater than, higher than, or Equal to 75µm, 50µm, 30µm, 20µm, 15µm or 10µm, the height of the solder bump is the distance from the topmost insulating dielectric layer in the TISD to the top surface of the solder bump, the largest diameter in the cross-sectional view of the plurality of solder bumps ( e.g. diameter of a circle or diagonal of a square or rectangle) e.g. between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 5µm and 100µm Between 10µm and 60µm, between 10µm and 40µm, between 10µm and 30µm, or greater than or equal to 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, between the nearest solder bumps The minimum space (gap) is, for example, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between Between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, multiple solder bumps can be used for logic driver driver flip-chip packaging on substrates, flex boards or motherboards, similar to those used in LCDs In the driver packaging technology, the chip packaging technology of flip chip assembly or the Chip-On-Film (COF) packaging technology, the solder bump packaging process may include a solder flow with or without solder flux (solder flux) ) or reflow process, substrates, flex boards or motherboards can be used, for example, on printed circuit boards (PCBs), a silicon substrate with interconnecting line structures, a metal substrate with interconnecting line structures, a A glass substrate with a wire structure, a ceramic substrate with an interconnected wire structure, or a flexible board with an interconnected wire structure, a plurality of solder bumps are arranged on the bottom surface of the logic driver package with a Ball-Grid-Array (Ball-Grid-Array (Ball-Grid-Array) BGA)) layout, in which a plurality of solder bumps in the peripheral area are used for signal I/Os, and the power/ground (P/G) I/Os near the central area, the signal bumps can form a ring in the peripheral area ( The circle)-shaped area is close to the boundary of the logic driver driver package, such as 1 circle, 2 circles, 3 circles, 4 circles, 5 circles or 6 circles, the spacing of the complex signal I/Os in the circle area can be smaller than the power / Ground (P/G) I/Os spacing.

Alternatively, gold bumps may be formed on or over the topmost insulating dielectric layer of the TISD via a gold embossing process, and on the exposed topmost interconnection line metal layer within the plurality of openings in the topmost insulating dielectric layer in the TISD The surface, the process steps are as follows: (a) deposit t72 on the topmost insulating dielectric layer of the TISD of the entire wafer or panel, and a plurality of interconnecting metal layers in the plurality of openings of the topmost insulating dielectric layer in the TISD The exposed upper surface is, for example, sputtered or CVD deposited a layer of Ti or TiN (the thickness of which is, for example, between 1 nm and 200 nm or between 5 nm and 50 nm); (b) a seed layer for electroplating is then deposited on the On the adhesion layer, for example, a gold seed layer is deposited by sputtering or CVD (the thickness of which is, for example, between 1 nm and 300 nm or between 1 nm and 50 nm); (c) through the processes of coating, exposure and development, A plurality of openings and holes are patterned in the photoresist layer and the gold seed layer is exposed for the subsequent process to form gold bumps. The openings in the photoresist layer overlap with the top insulating dielectric layer in the openings in the TISD, and can be extended An area from the opening on the topmost insulating dielectric layer to the topmost insulating dielectric layer of the TISD or an annular area surrounding the opening in the topmost insulating dielectric layer; (d) then electroplating a gold layer (with a thickness such as dielectric between 3µm and 40µm, between 3µm and 30µm, between 3µm and 20µm, between 3µm and 15µm, or between 3µm and 10µm) gold seed layer within the opening of the photoresist layer (f) remove the remaining photoresist; (g) remove or etch the gold seed layer and the adhesion layer not under the electroplated gold layer, the remaining metal layer (Ti layer (or TiN layer)/gold seed layer) / electroplating gold layer) is used as gold bumps that can be used to connect or couple to a plurality of chips of logic drivers, such as dedicated I/O chips, to external circuits or components outside the logic drivers, The height of the plurality of gold bumps is, for example, between 3 µm and 40 µm, between 3 µm and 30 µm, between 3 µm and 20 µm, between 3 µm and 15 µm, or between 3 µm and 10 µm, or less than , less than or equal to 40µm, 30µm, 20µm, 15µm or 10µm, the largest diameter in the cross-sectional view of the plurality of gold bumps (for example, the diameter of a circle or the diagonal of a square or rectangle), for example, between 3µm and 40µm , 3µm to 30µm, 3µm to 20µm, 3µm to 15µm, or 3µm to 10µm, or less than or equal to 40µm, 30µm, 20µm, 15µm or 10µm, closest to gold Minimum space (gap) between pillars or gold bumps, for example, between 3µm to 40µm, 3µm to 30µm, 3µm to 20µm, 3µm to 15µm, or 3µm Between 10µm, or less than or equal to 40µm, 30µm, 20µm, 15µ m or 10µm, multiple gold bumps can be used for logic driver driver flip chip packaging on substrates, flex boards or motherboards, similar to flip chip packaging used in LCD driver packaging technology or Chip-On-Film (COF ) packaging technology, substrates, flexible boards or motherboards such as printed circuit boards (PCBs), a silicon substrate with interconnecting line structures, a metal substrate with interconnecting line structures, a glass substrate with interconnecting line structures 2. A ceramic substrate containing an interconnecting line structure or a flexible board containing an interconnecting interconnecting line structure. When a plurality of gold bumps use COF technology, the plurality of gold bumps are bonded to a flexible circuit filmortape by thermocompression bonding. .), the multiple gold bumps used in the COF package have a very high number of I/Os in a small area, and the spacing between each gold bump is less than 20µm, and the multiple gold bumps in the area around the 4 sides of the logic driver package Bumps or I/Os are used for complex signal input or output, such as a 10nm-wide square logic driver package with two turns (rings) (or two rows) along the 4 sides of the logic driver package, such as greater than or equal to 5000 I/Os (15µm pitch between gold bumps), 4000 I/Os (20µm pitch between gold bumps), or 2500 I/Os (15µm pitch between gold bumps), The rationale for using 2 turns or two rows along the logical drive package boundary is because when a single layer of the logical drive package is used on a single-sided metal wire or connection line, fan-out connections can be easily made from the logical drive package. ), when the multiple metal pads of the flexible circuit board have a gold layer or a solder layer on the topmost surface, when the multiple metal pads of the flexible circuit board have a gold layer on the topmost surface, the gold layer-to-gold layer hot pressing can be used Bonded COF assembly technology, when the multiple metal pads of the flexible circuit board have a solder layer on the topmost surface, the COF assembly technology of thermocompression bonding from the gold layer to the solder layer can be used, and the plurality of gold bumps are arranged on the logic driver package. The front surface of the device has a Ball-Grid-Array (BGA) layout, where gold bumps in the peripheral area are used for signal I/Os, and power/ground (P/G) I near the center area /Os, the signal bumps can form a ring (circle) in the peripheral area along the boundary of the logic driver package, such as 1 circle, 2 circles, 3 circles, 4 circles, 5 circles or 6 circles, complex signal I The pitch of /Os may be smaller in the annular area than the pitch of power/ground (P/G) I/Os near the center area or near the center area of the logic driver driver package.

TISDs in a single-level packaged logic driver may: (a) include an interconnection network or structure of metal lines or bonds within the TISD of a single-level packaged logic driver for connecting or coupling to a plurality of Transistor, FISC, SISC, and/or micro-copper pillars or bumps of an FPGAIC chip in a single-level package logic driver to SISC and/or micro-copper pillars in another FPGAIC chip package within the same single-level package logic driver or Bumps, FISCs, and transistors, interconnecting nets or structures of metal lines or connecting lines within TISDs can be through multiple metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps on the TISD) Blocks) connect multiple circuits or multiple components outside or outside of a single-layer packaged logic driver, and the interconnecting network or structure of metal lines or connecting lines within the TISD may be a mesh line or structure for multiple signals, power or ground power supply ; (c) Interconnecting metal lines or connecting lines within a TISD including a single-level package logic driver may pass through a plurality of metal pillars or bumps (copper pillars or bumps, solder bumps, or solder bumps in the TISD) of the single-level package logic driver; The gold bumps on the TISD are connected or coupled to the outside of the single-level package logic driver or to multiple circuits or multiple components outside. In this case, for example, the plurality of metal pillars or bumps may be connected to the plurality of I/O circuits in the plurality of dedicated I/O die in the single-level package logic driver, which in this case, the plurality of I/O circuits The /O circuit can be a large I/O circuit, such as a bidirectional I/O (or tri-state) pad, the I/O circuit includes an ESD circuit, a receiver and a driver, and has an input capacitor or an output capacitor that can be Between 2pF and 100pF, between 2pF and 50pF, between 2pF and 30pF, between 2pF and 20pF, between 2pF and 15pF, between 2pF and 10pF, or between 2pF and 5pF, or greater than 2pF, 5pF, 10pF, 15pF or 20pF; (d) Interconnected nets or structures of metal lines or connecting lines included in TISDs in single-level package logic drivers for connecting multiple transistors, FISCs, SISCs and/or single level package logic drivers Micro-copper pillars or bumps of an FPGAIC chip within the same single-level package logic driver to another FPGAIC chip package within the same single-level package and/or multiple transistors, FISC, SISC, but not connected to the single-level package Circuits or components outside or outside the logic driver, no metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps on TISD) connected or coupled in a single-level package logic driver A plurality of I/O circuits connected to a plurality of FPGA chip packages in a single-level package logic driver, the I/O circuit in this case may be a small I/O circuit, such as a bidirectional I/O (or tri-state) The pad, I/O circuit includes an ESD circuit, receiver and driver, and has an input capacitance or an output capacitance between 0.1pF and 10pF, between 0.1pF and 5pF, between 0.1pF and 2pF, or less than 10pF, 5pF, 3pF, 2pF or 1pF; (e) an interconnecting network or structure of metal lines or connecting lines included in a TISD in a single-level packaged logic driver for connecting or coupling to a single-level packaged logic driver; Micro-copper pillars or bumps of the IC die, but not connected to or outside the single-level package logic driver circuit or component, that is, without the metal pillars or bumps in the single-level package logic driver ( An interconnection network or structure in which copper pillars or bumps, solder bumps, or gold bumps on a TISD are connected to metal lines or connecting lines in a TISD, in which case the metal lines or connecting lines in a TISD The interconnection network or structure can be connected or coupled to the micro copper pillars or bumps of the FPGAIC chip in the complex transistor, FISC, SISC and/or single level package logic driver without passing through any I/O of the FPGAIC chip circuit.

(V) dicing the completed wafer or panel, including separating and slicing through a material or structure between two adjacent logic drivers, the material (eg, polymer) filling a plurality of pieces between two adjacent logic drivers The wafers are separated or diced into individual logical driver units.

The wafers are turned up and the above-mentioned FOIT with TISD is formed, while a polymer material, resin or compound is filled into the gaps between the wafers and covers the surfaces of the wafers. Alternatively, the above-mentioned FOIT with TISD is formed with the wafers facing down, while a polymer material, resin or compound is filled into the gaps between the wafers and covers the surfaces of the wafers. In the step (I) of forming the FOIT with the above TISD, the wafers may be placed, fixed or attached to the carrier, support, potting material or substrate with the surface or side of the wafer with transistors facing down, and then A polymer material, resin or compound is filled into the gaps between the wafers and covers the surfaces of the wafers, as in step (II) above. The carrier, support, potting material, or substrate can then be removed to expose the upper surface of the wafers (the front side with the transistors and the upper surface of the micro-metal pads, metal posts or bumps of the wafers exposure), then, TISD is formed on the upper surfaces of the chips and on or over the upper surfaces of the micro-metal pads, metal pillars or bumps through a wafer or panel process, the disclosure of the TSID is as disclosed above TISD content is the same.

Another aspect of the present invention provides that the logic driver includes a plurality of single-level packaging logic drivers, and each single-level packaging logic driver in the multi-chip package is disclosed in the above description. 7, 8 or more than 8, the type of which is (1) flip-chip packaging on a printed circuit board (PCB), high-density fine metal wire PCB, BGA substrate or flexible circuit board; or (2) stacking package (Package-on -Package (POP)) technology, in which a single-layer packaging logical driver is packaged on top of other single-layer packaging logical drivers. This POP packaging technology, for example, can be applied to Surface Mount Technology (SMT).

Another aspect of the present invention provides a method for a single-level packaging logic driver suitable for stacking POP packaging technology. The process steps and specifications of the single-level packaging logic driver for POP packaging are the same as the logical driver FOIT described in the above paragraphs, except that in Form through-package vias (TPVS) or through-polymer vias (ThoughtPolymerVias, TPVS) between the gaps of the plurality of chips of the logic driver, and/or the peripheral area of the logic driver package and the logic driver inside the wafer boundary. TPVS is used to connect or couple circuits or components on top of the logic driver to the back of the logic driver package. Single-level packaged logic drivers with TPVs can be used to stack logic drivers. The single-level packaged logic drivers can be standard type or standard size, such as The single-level package logic driver can have a square or rectangular shape with a certain width, length and thickness. An industry standard can set the diameter (size) or shape of the single-level package logic driver. For example, the standard shape of the single-level package logic driver can be Square, the width of which is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and the thickness is greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm , 2mm, 3mm, 4mm or 5mm. Alternatively, the standard shape of a single-level package logic driver may be a rectangle with a width greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm and a length greater than or equal to 3mm, 5mm, 7mm , 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm or 50mm with a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm . Logic drivers with TPVs are formed by forming copper pillars or bumps on a chip carrier, support, potting material or substrate by placing, fixing or adhering a plurality of IC chips and packaging on the chip carrier, support, potting material or substrate. , the process steps of FOIT to form a logic driver package, to form a plurality of copper pillars or bumps (used as TPVS) on or over a chip carrier, support, molding material or substrate, and the process steps are: (a) Provide a chip carrier , holder, potting material or substrate and a plurality of IC chips and packages, the chip carrier, holder, potting material or substrate may be in wafer type (wafers with diameters of 8", 12" or 18"), or Square or rectangular panel type (the width or length of which is greater than or equal to 20cm, 30cm, 50cm, 75cm, 100cm, 150cm, 200cm or 300cm), the material of the chip carrier, bracket, casting material or substrate can be silicon, metal material, glass material, plastic material, polymer material, epoxy-based polymer material or epoxy-based compound material. The wafer or panel has a basic insulating layer thereon, the basic insulating layer may include a silicon oxide layer, a silicon nitride layer and/or a polymer layer; (b) depositing an insulating dielectric layer The basic insulating layer of the entire wafer or panel On the layer, the insulating dielectric layer can be a polymer material, such as polyimide, benzocyclobutene (BenzoCycloButene (BCB)), parylene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the bottommost polymer insulating dielectric layer can be formed by spin coating, screen printing, dripping or molding, and the insulating dielectric layer can be formed by: (A) through a non-photosensitive material or a photosensitive material, and without a plurality of openings in the polymer insulating dielectric layer; or (B) alternatively, the polymer material can be a photosensitive material and can be used as a photoresist layer and For patterning the openings in the photoresist layer, the metal plugs (used as the bottoms of copper pillars or bumps, that is, the bottom of TPVS) formed by subsequent process steps are in the photoresist layer (polymer layer), that is The photosensitive polymer layer is coated, exposed through a mask, then developed and etched to form a plurality of openings in the photosensitive polymer layer, and the plurality of openings in the photosensitive insulating dielectric layer expose the upper surface of the base insulating layer. A non-photosensitive polymer layer or a photosensitive polymer layer can be used as the insulating dielectric layer in option (A) or option (B), and then cured at a temperature, eg above 100°C, 125°C, 150°C , 175°C, 200°C, 225°C, 250°C, 275°C or 300°C, the thickness of the cured polymer is, for example, between 2 µm and 50 µm, between 3 µm and 50 µm, between 3 µm and 30 µm. , between 3µm and 20µm or between 3µm and 15µm, or with a thickness greater than or equal to 2µm, 3µm, 5µm, 10µm, 20µm or 30µm; (c) perform a copper relief process to form micro copper pillars or bumps Blocks as TPVs, for options (A) or (B): (i) deposit an adhesive layer on or over the insulating dielectric layer of the entire wafer or panel (for options (A) and (b)) and cure the polymer The upper surface of the base insulating layer exposed at the bottom of the plurality of openings in the material layer (for option (B)), for example, a Ti layer or a TiN layer (the thickness of which is, for example, between 1 nm and 50 nm) is deposited by sputtering or CVD. (ii) then depositing a seed layer for electroplating on the adhesion layer, for example by sputtering or CVD deposition (the thickness of which is, for example, between 3 nm and 300 nm or between 10 nm and 120 nm); (iii) After coating, exposing, and developing the photoresist layer, the copper seed layer is exposed in the plurality of openings or holes in the photoresist layer, and the plurality of openings or holes in the photoresist layer can be patterned to form subsequent micro copper pillars or bumps. (B) Option, the openings and holes in the photoresist layer overlap the openings in the insulating dielectric layer, and may extend the opening of T67 to an area or an annular area surrounding the opening in the insulating dielectric layer, which The width of the annular region is between 1µm and 15µm, between 1µm and 10µm, between 1µm and 5µm, for options (A) or (B), the width of the openings or holes in the photoresist layer. The location is in the gap between the dice within the logical driver, and/or outside the logic driver package peripheral area and the edge of the dice within the logical driver (the dice may be placed, attached, or fixed in a later process) ); (v) then electroplating a copper layer (with a thickness of, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm) on the copper seed layer in patterned openings or holes in the photoresist layer; (e) shifting Remove the remaining photoresist layer; (f) remove or etch the copper seed layer and the adhesion layer not under the electroplated copper. For option (A) the remaining or remaining metal (Ti layer (or TiN layer) Cu seed layer/electroplated copper layer) in the photoresist layer (at which point the photoresist layer has been removed) at positions within the plurality of openings or holes , used as copper pillars or bumps (TPVs), for option (B) the remaining or reserved metal (Ti layer (or TiN layer) Cu seed layer / electroplated copper layer) in the photoresist layer (at which point the photoresist layer has been At the position of the plurality of openings or holes in the removed), as the main part of the plurality of copper pillars or bumps (TPVS); and the remaining or retained metal (Ti layer (or TiN layer) Cu seed layer/electroplating copper layer) in the insulating Inside the openings of the dielectric layer, used as the bottom portion of the pillars or bumps (TPVS), for options (A) and (B), the height of the pillars or bumps (from the top surface of the insulating dielectric layer) The distance to the upper surface of the plurality of copper pillars or bumps) is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, and between 5µm and 120µm. Between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, between 10µm and 30µm, or greater than, greater than or equal to 50µm, 30µm, 20µm, 15µm or 5µm, plural copper The largest diameter in the cross-sectional view of the column or bump (for example, the diameter of a circle or the diagonal of a square or rectangle) is, for example, between 5 µm and 120 µm, between 10 µm and 100 µm, between 10 µm and 60 µm. between 10µm and 40µm, between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the smallest space (gap) between the nearest copper pillars or bumps ), for example, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 60µm, 50µm , 40µm, 30µm, 20µm, 15µm or 10µm.

A wafer or panel with an insulating dielectric layer and a plurality of copper pillars or bumps (TPVS) is used for a chip carrier, a support, a potting material or a substrate, and then the above disclosure and description are used to form a logic driver, and all processes for forming a logic driver As disclosed and described above, some of the process steps are again listed below: (2) to form the above-mentioned logic driver, using a resin material or compound to (i) fill the gaps between the plurality of chips; (ii) cover the plurality of chips upper surface; (iii) filling the gaps between the micro copper pillars or bumps on the plurality of chips; (iv) covering the upper surface of the micro copper pillars or bumps on the plurality of chips; (v) filling the wafer or panel or the gaps between the copper pillars or bumps (TPVs) above; (vi) cover the upper surface of the copper pillars or bumps on or over the wafer or panel, use a CMP process, a grinding process to planarize the applied material, The surface of the resin or compound to a level to (i) the upper surface of all micro metal pillars or bumps on the wafer; (ii) the upper surface of all copper pillars or bumps (TPVs) on or over the wafer or panel , all exposed. The TISD structure is then formed on the planar surface of the planarizing material, resin or compound, and is connected or coupled to the exposed upper surface of a plurality of on-chip micro metal pillars or bumps, and/or a plurality of copper on or over the wafer or panel The top surface of the pillar or bump (TPVS), as disclosed and described above. Then a plurality of copper pillars or bumps, a plurality of solder bumps, and gold bumps are formed on or over the TISD for connecting or coupling to the metal lines or connecting lines in the plurality of interconnection line metal layers of the TISD, as disclosed above and Illustratively, copper pillars or bumps are used for metal plugs (TPVs) on or over wafers or panels, and on flat surfaces of cured or cross-linked planarizing materials, resins, or compounds. ) to connect or couple to circuits, interconnect layer metal structures, metal pads, metal posts or bumps and/or components on the backside of a logic driver package, chip carrier, support, potting material or substrate Can be: (i) removed after the CMP process and before forming the top interconnect structure on or over the logical drivers; (ii) retained throughout the process steps and removed after the process is complete. The wafer carrier, support, pot material or substrate can be removed via a lift-off process, a CMP process or a backgrinding process. After the wafer carrier, support, pot material or substrate is removed, for option (A), the insulating dielectric layer and The adhesion layer (assuming that the side with transistors of the IC chips is facing up) on the bottom surface of the TPVS can be removed by a CMP process or a back grinding process, exposing the bottom surface of the copper seed layer or the electroplating of the copper pillars or bumps The copper layer (meaning that the insulating dielectric layer is removed in its entirety), for option (B), the bottom portion of the insulating dielectric layer (assuming the The adhesive layer on the bottom surface of the TPVS can be removed by a CMP process or a back grinding process to expose the bottom portion of the plurality of copper pillars or bumps (note: the bottom of the plurality of copper pillars or bumps is metal plugs in the openings of the insulating dielectric layer); that is, the process of removing the insulating dielectric layer is carried out until the copper seed layer or electroplating at the bottom of the plurality of copper pillars or bumps (in the openings of the insulating dielectric layer) The copper is exposed, and in option (B), the remaining portion of the insulating dielectric layer becomes part of the completed logic driver on the bottom of the logic driver package, and the surface of the copper seed layer or the remaining portion of the insulating dielectric layer is located within the opening of the remaining insulating dielectric layer. The electroplated copper layer is exposed, for option (A) or (B), the exposed bottom surface of the copper seed layer or the electroplated copper layer of the plurality of copper pillars or bumps forms the plurality of copper pads on the backside of the logic driver for connection or coupling To transistors, circuits, interconnect metal structures, metal pads, metal pillars or bumps and/or on the front side (or top side) of the logic driver, still assuming the front side of the IC chip with transistors facing up), a stacked logic driver can be formed by the following process steps: (i) providing a first single-level package logic driver, the first single-level package logic driver being a discrete or wafer or panel type having a plurality of copper Pillars or bumps, solder bumps or gold bumps face down, and their exposed TPVs on copper pads (IC chips face down); (ii) POP stacked package via surface mount or flip chip packaging , a second separate single-layer package logic driver is provided on top of the provided first single-layer package logic driver, and the surface mount process is similar to the SMT technology used in the packaging of multiple components on the PCB, by printing a solder layer or solder paste, or flux on the copper pads of the photoresist layer, followed by flip chip packaging, connecting or coupling copper pillars or bumps, solder bumps, or gold bumps of the logic driver in a second separate monolayer package to the first The solder or solder paste on the copper pads of the TPVS of the single-layer packaged logic driver is packaged through a flip-chip packaging process, which is similar to the POP technology used in IC stacking technology, connected or coupled to a second separate single layer A plurality of copper pillars or bumps, a plurality of solder bumps or a plurality of gold bumps on the packaged logic driver to copper pads on the TPVS of the first single-level packaged logic driver, a third separate single-level packaged logic driver may be flip-chip encapsulated A plurality of copper pads exposed by the TPVS assembled, connected or coupled to the second single-level package logic driver, the POP stack packaging process can be repeated for assembling more discrete single-level package logic drivers (eg, more than or equal to n discrete single-level package logic drives, where n is greater than or equal to 2, 3, 4, 5, 6, 7, 8) to form a complete stacked logic drive, when the first single-level package logic drive is of the discrete type, They can be a first flip chip package assembled to a carrier or substrate, such as a PCB, or a BGA board, and then a POP process is performed to form a plurality of stacked logic drivers in the carrier or substrate type, and then the carrier or substrate is cut. In order to generate a plurality of separate stacked logic drivers, when the first single-level package logic driver is still in the form of a wafer or a panel, the wafer or panel can be directly used as a carrier or substrate when the POP stacking process is performed to form a plurality of stacked logic drivers. , and then the wafer or panel is diced and separated to produce a plurality of separated stacks to complete the logic driver.

Another aspect of the present invention provides a method for a single-level package logic driver suitable for stacked POP assembly technology. The single-level package logic driver for POP package assembly follows the same process steps and specifications as the multiple FOITs described in the preceding paragraphs, except that the formation of The bottom layer interconnect structure (Bottom Interconnection Scheme, onor of the logic drive (BISD)) in (or on) the logic drive at the bottom of the single-level package logic drive and the gap between the plurality of chips in the logic drive through through-package or through-polymer (TPVS) , and/or in the area surrounding the logic driver package and at the die boundaries within the logic driver, the BISD is formed on a die carrier, support, potting material, or substrate, and the BISD includes a plurality of metal lines, connections within a plurality of interconnect metal layers Lines or metal planes, and prior to disposing, adhering or securing the wafer carrier, support, potting material or substrate, the same or similar process steps can be used to form the TISD disclosed above, the TPVS is formed on or over the BISD, and the same or similar process steps are used to form The process steps of forming multiple metal pillars or bumps (multiple copper pillars or bumps, multiple solder bumps or gold bumps) on TISD, BISD provides additional interconnection wire metal layer connection layer on the bottom or back of the logic driver package, and provide exposed metal pads or copper pads on the area array on the bottom of the single-level package logic driver, the location of which is included directly under the plurality of IC chips in the logic driver, TPVS is used to connect or couple above the logic driver Multiple circuits or elements (eg TISD) to multiple circuits or elements (eg BISD) on the backside of the logic driver package, a single level package logic driver with FPGA die 0 can be used to stack the logic drivers, this single level package logic driver However, standard type or standard size, such as a single-layer packaged logic driver can have a square or rectangular shape with a certain width, length and thickness, and/or the position of the plurality of copper pads has a standard layout, an industry standard can set a single-layer The diameter (dimension) or shape of the packaged logic driver, for example, the standard shape of a single-layer packaged logic driver may be a square, and its width is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and have a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm. Alternatively, the standard shape of a single-level package logic driver may be a rectangle with a width greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm and a length greater than or equal to 3mm, 5mm, 7mm , 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm or 50mm with a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm . Logic drivers with BISD and TPVs are formed by forming a plurality of metal lines, bonding lines or metal planes on a plurality of interconnecting line metal layers provided by a wafer carrier, support, potting material or substrate for placement, attachment or adhesion A plurality of IC chips, or packaged on a logic driver, and then a plurality of copper pillars or bumps (TPVS) are formed on the BISD, and the chip carrier, support, molding material or substrate with BISD and TPVS is used in the FOIT process, wherein FOIT Process The process of forming BISD and a plurality of copper pillars or bumps (used as TPVS) on or over a chip carrier, support, potting material or substrate as described in Process Step (1) for Forming FOIT in Logic Driver Packages The steps are: (a) providing a chip carrier, support, molding material or substrate and a plurality of IC chips or packages, and the chip carrier, support, molding material or substrate can be in the form of a wafer (for example, a diameter of 8 inches, 12 inch or 18-inch wafer), or square panel type or rectangular panel type (for example, width or length greater than or equal to 20 centimeters (cm), 30cm, 50cm, 75cm, 100cm, 150cm, 200cm or 300cm), the chip carrier , The material of bracket, molding material or substrate can be silicon material, metal material, ceramic material, glass material, steel metal material, plastic material, polymer material, epoxy resin base polymer material or epoxy resin base compound material, There is a base insulating layer on the wafer or panel, and the base insulating layer may include a silicon oxide layer, a silicon nitride layer and/or a polymer layer; (b) depositing a bottommost insulating dielectric layer on the entire wafer; On the circle or panel and on the base insulating layer, the bottommost insulating dielectric layer may be a polymer material, such as polyimide, benzocyclobutene (BCB), parylene, epoxy Resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the bottommost polymer insulating dielectric layer can be formed by spin coating, screen printing, dripping or casting Forming, the polymer material can be a photosensitive material, which can be used for patterning openings in the photogroup layer to form metal plugs in a subsequent process, that is, coating the photosensitive photoresist polymer layer and passing through a photomask. Exposure, followed by development and etching to form a plurality of openings in the polymer layer, the plurality of openings in the bottommost photosensitive insulating dielectric layer expose the upper surface of the base insulating layer, and the bottommost photosensitive polymer layer (insulating dielectric layer) layer) at a temperature, for example above 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C, the thickness of the cured bottommost polymer layer depends on between 3µm and 50µm, between 3µm and 30µm, between 3µm and 20µm, or between 3µm and 15µm, or greater than (thicker than) or equal to 3µm, 5µm, 10µm, 20µm or 30µm; ( c ) perform an emboss copper process to form metal plugs in the plurality of openings of the cured bottommost polymer insulating dielectric layer, and to form the plurality of metal lines, connecting lines or Metal Planes: (i) Deposition of an adhesive layer over the entire wafer or panel on the bottommost insulating dielectric layer and on the exposed upper surface of the bottom base insulating layer with multiple openings in the cured bottommost polymer layer, for example by sputtering Plating method, CVD deposition of a Ti layer or a TiN layer (the thickness of which is between 1 nm and 50 nm, for example); (ii) Then deposit a seed layer for electroplating on the adhesion layer, such as by sputtering or CVD deposition (The thickness is, for example, between 3 nm and 300 nm or between 10 nm and 120 nm); (iii) by coating, exposing and developing the photoresist layer, exposing the copper seed layer to a plurality of trenches and openings in the photoresist layer or on the bottom of the hole, while the trenches, openings or holes in the photoresist layer can be used to form a plurality of metal lines, connecting lines or metal planes that interconnect the metal layer at the bottommost end, wherein the grooves in the photoresist layer are formed. The slot, opening or hole may overlap with the opening in the bottommost insulating dielectric layer and may extend the opening of the bottommost insulating dielectric layer; (iv) then electroplating a copper layer (with a thickness of, for example, between 5µm and 80µm) between, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 3µm to 20µm, 3µm to 15µm, or 3µm to 10µm ) patterning trench openings or holes in the photoresist layer; (v) removing the remaining photoresist layer; (vi) removing or etching the copper seed layer and the adhesion layer not under the electroplated copper layer, which Intra-patterned trench openings or holes where the metal (Ti(TiN)/Cu seed layer/Copper electroplating) remains or remains in the photoresist layer (note: the photoresist layer has now been cleared), which is used as a BISD A plurality of metal lines, connecting lines or metal planes of the bottommost interconnected metal layer, and this metal (Ti(TiN)/copper seed layer/electroplated copper layer) remains or remains on the bottommost insulating dielectric layer. The opening is used as the metal plug of the bottommost insulating dielectric layer of BISD, the process of forming the bottommost insulating dielectric layer and its plurality of openings, and the raised copper process is used to form the metal plug on the metal layer of the interconnection line The bottommost plurality of metal lines, connecting lines or metal planes and in the bottommost insulating dielectric layer can be repeated to form a metal layer of a plurality of interconnecting line metal layers in the BISD; wherein the bottommost insulating dielectric is repeated Layers are used as the IMD layer between the multiple interconnect metal layers of the BISD and the metal plug in the bottommost insulating dielectric layer (now within the IMD layer) for connecting or coupling the BISD A plurality of metal lines, connecting lines or metal planes between the metal layers of the two plural interconnecting lines, that is, above and below the metal plug, the topmost interconnecting line metal layer of the BISD covers a topmost insulating dielectric layer of a BISD, The topmost insulating dielectric layer has a plurality of openings to expose B On the upper surface of the topmost interconnect metal layer of the ISD, the positions of the plurality of openings in the topmost insulating dielectric layer are located outside the boundaries of the plurality of chips in the surrounding area of the logic driver package and the logic driver (the plurality of chips are arranged, Attached or fixed in a subsequent process), a CMP process can be performed next to planarize the upper surface of the BISD (that is, planarize the topmost insulating dielectric layer that has been cured), and then form a plurality of copper pillars as TPVS or Before the bump process, the BISD can include 1 to 6 layers of multiple interconnect metal layers or 2 to 5 layers of multiple interconnect metal layers. The BISD multiple metal lines, interconnect lines or metal plane interconnect lines have an adhesive layer ( For example, Ti layer or TiN layer) and copper seed layer are only located at the bottom, but not on the sidewalls of metal lines or connecting lines. The interconnecting metal lines or connecting lines of FISC have adhesive layers (such as Ti layer or TiN layer) and copper seeds. The layers are located on the sidewalls and bottoms of the metal lines or connecting lines.

The thickness of the plurality of metal lines, connecting lines or metal planes of BISD is, for example, between 0.3 µm and 40 µm, between 0.5 µm and 30 µm, between 1 µm and 20 µm, between 1 µm and 15 µm, and between 1 µm and 15 µm. Between 1µm and 10µm or between 0.5µm and 5µm, or thicker (greater than) or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, 7µm or 10µm, BISD metal line or connecting line width For example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm, or between 0.5µm and 5µm , or wider than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, 7µm or 10µm, the IMD thickness of BISD is, for example, between 0.3µm and 50µm, between 0.5µm and 0.5µm 30µm, 0.5µm to 20µm, 1µm to 10µm, or 0.5µm to 5µm, or thicker than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm or 5µm, BISD The height or thickness of the metal plug in the bottommost insulating dielectric layer is, for example, between 3 µm and 50 µm, between 3 µm and 30 µm, between 3 µm and 20 µm, or between 3 µm and 15 µm, Or the thickness is greater than or equal to 3µm, 5µm, 10µm, 20µm or 30µm, the metal plane is in the metal layer of the BISD's multiple interconnecting wire metal layer, and can be used as the power supply/ground plane of the power supply, and/or as a heat sink or diffuser for heat dissipation, where the metal is thicker, for example, between 5µm and 50µm, between 5µm and 30µm, between 5µm and 20µm, or between 5µm and 15µm, or the thickness Greater than or equal to 5µm, 10µm, 20µm or 30µm, power/ground planes, and/or heat sinks or heat spreaders can be arranged in BISD's interconnecting wire metal layers in a staggered or cross pattern, such as a layout design In the form of a fork shape.

After the BISD is formed, a plurality of copper pillars or bumps (as TPVS) are formed on or above the topmost insulating dielectric layer of the BISD or chip carrier, support, molding material or substrate through the above-disclosed raised copper process, the topmost in the BISD The opening of the insulating dielectric layer exposes the upper surface of the topmost interconnecting wire metal layer, and the process steps are as follows: (a) deposit t72 on the topmost insulating dielectric layer of the BISD of the entire wafer or panel, and the topmost insulating dielectric layer in the BISD The exposed upper surface of the interconnecting metal layer in the plurality of openings of the top insulating dielectric layer, such as sputtering or CVD deposition of a Ti layer or TiN layer (the thickness of which is, for example, between 1 nm and 200 nm or between 5 nm and 50 nm. (b) then depositing a seed layer for electroplating on the adhesion layer, such as sputtering or CVD deposition of a copper seed layer (the thickness of which is, for example, between 3 nm and 400 nm or between 10 nm and 200 nm) ); (c) through the processes of coating, exposing and developing, patterning a plurality of openings and holes in the photoresist layer and exposing the copper seed layer to form a plurality of copper pillars or bumps (TPVS), in the photoresist layer The opening overlaps with the top insulating dielectric layer in the opening in the BISD, and can extend from the opening on the topmost insulating dielectric layer to an area of the topmost insulating dielectric layer in the BISD or an annular area surrounding the topmost insulating dielectric layer in the BISD. opening, the width of the annular region is between 1µm and 15µm, between 1µm and 10µm, or between 1µm and 5µm, and the positions of the plurality of openings and holes in the photoresist layer are located in the logic driver In the gap between the plurality of chips, and/or in the logic driver peripheral area and the boundary periphery of the plurality of chips in the logic driver (the plurality of chips are placed, attached or fixed in the subsequent process); (d) then electroplating a copper layer (The thickness is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm between 10µm and 30µm) on the copper seed layer within the opening of the photoresist layer; (e) remove the remaining photoresist layer; (f) remove or etch the copper not under the electroplated copper layer The seed layer and the adhesive layer, the remaining metal layer (Ti layer (or TiN layer) / copper seed layer / electroplated copper layer) or the metal layer remaining on the multiple openings and holes of the photoresist layer are used as multiple copper layers Pillars or bumps (TPVs), the height of the distinguishing etch stop layer 12h (from the upper surface of the insulating dielectric layer to the upper surface of the plurality of copper pillars or bumps) is, for example, between 5µm to 300µm, 5µm to 5µm 200µm, 5µm to 150µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or its height is higher than or Equal to 50µm, 30µm, 20µm, 15µm or 5µm, different etching The maximum diameter (eg, the diameter of a circle or the diagonal of a square or rectangle) in the cross-sectional view of the stop layer 12h is, for example, between 5 µm and 300 µm, between 5 µm and 200 µm, and between 5 µm and 150 µm. , 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or greater than or equal to 150µm, 100µm, 60µm , 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the minimum space (gap) between the nearest copper metal pillars or bumps, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or greater than or equal to 150µm , 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

The wafer or panel with BISD and copper pillars or bumps (TPVS) is then used as a plurality of IC chips and packages to form the logic driver in the above disclosure and description, and all the processes for forming the logic driver are the same as the above disclosure and description, Some of the process steps are listed again below: in process step (II) to form the above-mentioned logic drivers, resin materials or compounds are used to (i) fill the gaps between the plurality of chips; (ii) cover the upper surfaces of the plurality of chips; ( iii) fill in the gaps between the micro copper pillars or bumps on the plurality of chips; (iv) cover the upper surface of the micro copper pillars or bumps on the plurality of chips; (v) fill in the plural numbers on or above the wafer or panel gaps between copper pillars or bumps (TPVs); (vi) covering the upper surface of a plurality of copper pillars or bumps on or over a wafer or panel, using CMP procedures, grinding procedures to planarize the application of materials, resins or compounds Surface to a level to (i) the upper surface of all the plurality of micro-bumps or metal pillars on the plurality of wafers; (ii) the upper surface of all the plurality of copper pillars or bumps (TPVs) on or over the wafer or panel, all covered by exposure. As disclosed and described above, the plurality of copper pillars or bumps are located on or over the wafer or panel, and on the flat surface of the cured or cross-linked planarizing material, resin or compound, the plurality of copper pillars or bumps are used for Metal plugs (TPVs) to connect or couple circuits on the front side of the logic driver package structure, inter-connect layer metal structures (eg TISD), copper metal pillars or bumps, solder bumps, gold bumps, metal contacts Pads to circuits, interconnect layer metal structures (eg BISD), copper pads, metal posts or bumps, and/or components located on the backside of the logic driver package structure, chip carriers, supports, potting materials or substrates may be : (i) removed after the CMP process and prior to forming the top interconnect structure on or over the logical drivers; (ii) retained throughout the process steps and removed after the process is complete. The wafer carrier, support, potting material or substrate can be removed by a lift-off process, a CMP process or a back grinding process. After the wafer carrier, support, potting material or substrate is removed, the bottom portion of the bottommost insulating dielectric layer ( Assuming the IC chip has transistors face up) can be removed via a CMP process or a back grinding or polishing process to expose the metal plugs in the openings in the bottommost insulating dielectric layer, meaning the bottommost insulating The removal process of the bottom portion of the dielectric layer is performed until the electroplated copper layer or copper seed layer of the metal plug in the opening of the bottommost insulating dielectric layer is exposed, and the remaining portion of the insulating dielectric layer becomes the completed logic driver. A portion is located on the bottom of the logic driver package, and the surface of the copper seed layer or the exposed surface of the electroplated copper layer located within the remaining bottommost insulating dielectric layer openings can be designed or laid out as a matrix of pad areas located on the logic driver. On the back side, the pads in the peripheral area are used as signal pads, and the pads in the central area are used as power supply/ground reference (P/G) pads, located between the lower positions of the IC chip. The pads can be directly placed or attached to the carrier, bracket, potting material or substrate, and the signal pads on the peripheral area can form a ring along the edge of the bottom of the logic driver package structure, or 2, 3, 4, 5 or 6 rings, the spacing between the signal pads on the peripheral area can be smaller than the spacing between the P/G pads on the bottom center area of the logic driver package structure, on the back of the logic driver The exposed copper pads on the top or bottom surface can be connected to the TPVs, so the copper pads and TPVs can be used as the TPVs on the front side of the logic driver package structure (the top side, still assuming the side of the IC die with the transistors is facing up). connections or couplings between some transistors, circuits, interconnect metal structures (such as TISD), metal pads, metal posts or bumps, and interconnect metal structures (such as BISD) on the backside of the logic driver package structure , connection or coupling between metal pads, metal posts or bumps.

The BISD interconnection metal lines or connecting lines of the single-level package logic driver are used in: (a) for connecting or coupling the plurality of copper pads on the bottom surface (back side) of the single-level package logic driver. Copper pillars to corresponding TPVs; and metal lines connected or coupled to TISDs located on (or front side) of the single-level package logic driver through corresponding TPVs on the bottom surface of the single-level package logic driver, a plurality of copper pads or connecting lines, thus connecting or coupling the plurality of copper pads to the plurality of transistors, FISC, SISC and micro copper pillars or bumps in the plurality of IC chips on the upper side of the single layer package logic driver; (b) connecting or coupling the single layer The plurality of copper pads on the bottom surface of the packaged logic driver are connected to the corresponding TPVS, and through the corresponding TPVS, the plurality of copper pads on the bottom surface of the single-level packaged logic driver are connected or coupled to the upper side (front side) of the single-level packaged logic driver. Metal lines or connecting lines of TISD, TISD can be connected or coupled to a plurality of metal pillars or bumps on the TISD, so a plurality of copper pads on the back of the single-level package logic driver are connected or coupled to the front side of the single-level package logic driver (c) directly connecting or coupling the plurality of copper pads of the first FPGA die located in the single-level package logic driver to the plural number of copper pads of the second FPGA die located in the single-level package logic driver Copper pads, via an interconnection net or structure of metal lines or connecting lines within the BISD, the interconnection net or structure can be connected or coupled to the TPVS of the single layer package logic driver; (d) Directly connected or coupled to the single layer A copper pad under the FPGA chip in the packaged logic driver is connected to other copper pads and another copper pad under the same FPGA chip through an interconnection network or structure using metal wires or connecting wires in the BISD. An interconnection net or structure may be connected to the TPVS coupled to the single level package logic driver; (e) a power or ground plane and a heat sink or diffuser for heat dissipation.

Another aspect of the present invention provides a non-volatile programmable logic driver (a non-volatile programmable logic driver) constructed according to the above disclosed non-volatile programmable logic driver, in a multi-chip package structure (according to the above disclosed FOIT package structure) The non-volatile programmable logic driver in ) includes a plurality of standard commercial FPGA IC chips and one (or more) non-volatile IC chips, wherein the one (or more) non-volatile IC chips include a bare-type or multi-chip A NAND flash chip and/or a NOR flash chip of the package structure type, in one embodiment, the non-volatile programmable logic drive device in the multi-chip package structure (according to the FOIT package structure disclosed above) only includes one Standard commercial FPGA IC chip and a non-volatile IC chip, wherein the non-volatile IC chip includes a NAND flash chip and/or a NOR flash chip of a bare die type or a multi-chip package structure type, with innovative or application concepts or The user or developer of the idea can purchase the programmable logic drive device, develop or write software source code, data or programs loaded into the non-volatile IC chip of the non-volatile programmable logic drive device for realizing their innovation or Application concepts or ideas, the user's software source code, data, information, instructions or programs (related to innovative or applied concepts or ideas) loaded in the non-volatile IC chip of the non-volatile programmable logic drive device can be packaged through FOIT The TISD of the structure is downloaded to the 5T or 6T SRAM cells and/or the programmable interconnects (switches include pass-through switch gates and multiplexers) on standard commercial FPGAIC chips in non-volatile programmable logic drivers. Program logic circuits, cells, elements or blocks (including LUTs and multiplexers).

A non-volatile programmable logic driver (non-volatile programmable logic driver) may include a dedicated I/O chip or a dedicated control and I/O chip together with an FPGA chip and a non-volatile memory IC chip, wherein the dedicated I/O chip or Dedicated Control and I/O Chip As disclosed above, in a non-volatile programmable logic drive device, the dedicated I/O chip or between the dedicated control and I/O chip and the FPGA chip and the non-volatile memory IC chip The communication or electrical coupling between the non-volatile programmable logic driving device and the external circuit outside the non-volatile programmable logic driving device is as disclosed and described above. Note that, as disclosed and described above, a dedicated I/O chip or a dedicated control and I/O chip includes large I/O circuits for communication or electrical functions with external circuits other than the non-volatile programmable logic drive device Coupling and including a small I/O circuit for communication or electrical coupling with the small I/O circuit of the FPGA IC chip and the non-volatile memory IC chip, the large I/O circuit and the small I/O circuit The O circuit is as disclosed and described above.

The non-volatile programmable logic driver (non-volatile programmable logic driver) may include HBM memory chips (such as HBMDRAM, SRAM, MRAM or RRMIC chips) and dedicated I/O chips or dedicated control and I/O chips, FPGA chips along with non-volatile memory IC chips, wherein HBM memory chips (eg, HBMDRAM, SRAM, MRAM, or RRMIC chips) as disclosed and described above, HBM memory chips, dedicated I/O chips, or dedicated control and I/ The communication or electrical coupling between the O chip, the FPGA chip and the non-volatile memory IC chip, as disclosed and explained above, the non-volatile programmable logic driving device and the external circuits other than the non-volatile programmable logic driving device The communication or electrical coupling between them is as disclosed and explained above, as disclosed and explained above, as disclosed and explained above, dedicated I/O chips or dedicated control and I/O chips include large I/O circuits For communication or electrical coupling with external circuits other than non-volatile programmable logic drivers, and includes small I/O circuits for communication with FPGA IC chips, HBM memory chips, and non-volatile memory IC chips The communication or electrical coupling between the small I/O circuits, the large I/O circuits and the small I/O circuits are as disclosed and described above.

The FPGAIC chip in a non-volatile programmable logic driver device (non-volatile programmable logic driver) may include an on-chip security circuit for design security, the on-chip security circuit for preventing unintentional Copying, using or reverse engineering, the on-chip security circuitry on an FPGA IC chip in a non-volatile programmable logic drive device provides an on-chip bitstream based on a decryption key stored in a dedicated memory unit on the FPGAIC chip (bitstream) decryption, the decrypted on-chip bitstream (bitstream) is stored in the non-volatile memory chip of the non-volatile programmable logic drive device, and is used to configure the FPGAIC chip of the non-volatile programmable logic drive device, encrypted The on-chip bitstream input from the non-volatile memory chip into the FPGAIC chip for programmable interconnects (switches including pass-through switch gates and multiplexers) and/or on the FPGAIC chip programmable logic circuits, cells, elements or blocks (including LUTs and multiplexers) in which encrypted on-chip bitstreams can be secured on-chip via a decryption key stored in decryption memory cells The circuit is decrypted, a user-generated key can be created from a true random source, and the FPGAIC chip in the non-volatile programmable logic drive device stores the encryption key in the non-volatile memory of the FPGAIC chip. Bulk cells, where on-chip non-volatile memory cells may include a floating gate MOS transistor, MRAM or RRAM. Alternatively, the FPGAIC chip in the non-volatile programmable logic drive device stores the encryption key in a dedicated RAM cell on the FPGAIC chip, where the dedicated RAM cell can be backed up via a small external connection power supply. Alternatively, an e-fuse or anti-fuse on the FPGAIC chip can be used to store the encryption key, and the e-fuse or anti-fuse can be programmed to be non-volatile The electronic fuse (e-fuse) includes a plurality of fuses, and each fuse has an interconnected metal wire or a metal wire of the connecting wire in the FISC or SISC of the FPGAIC chip (as disclosed and described above). One of the narrow necks, in programming of non-volatile storage, selects the fuse to be cut or destroyed by applying a high current through the fuse, the impedance fuse includes a plurality of fuses, each fuse having a thin oxide window Located between two contacts or electrodes, in non-volatile memory programming, by applying a high voltage between the two contacts or electrodes to destroy the oxide in the thin oxide window, the encryption key can be accessed through a Special ports/ports are programmed on the device, the on-chip security circuit performs operations to decrypt the incoming bit stream during configuration, the non-volatile programmable logic drives the device with encryption logic using 128, 256, 512 or 1024 bit encryption keys (depending on the on-chip security circuit).

Non-volatile IC memory chips and FPGA IC chips in a chip package structure in a non-volatile programmable logic drive provide an alternative to current ASICIC chip design, manufacture and business. The chip package structure has: (i) loading and storing software source code, data, information, instructions or programs (related to innovation or application) in a non-volatile IC memory chip, and (ii) on-chip with decryption/encryption FPGAIC chips with meta-flow functionality (based on on-chip security circuits) can be sold and used like ASICIC chips.

The stacked logic driver can be formed using the same or similar process steps as disclosed above, for example, by the following process steps: (i) providing a first single-level package logic driver with TPVs and BISD, wherein the single-level package logic driver is a split chip type Or still in wafer or panel format with copper pillars or bumps, solder bumps or gold bumps down, and copper pads exposed on top of the BISD; (ii) POP stacked package , a second separate single-level package logic driver (also with TPVS and BISD) can be provided on top of the first single-level package logic driver by surface mount and/or flip chip method, and the surface mount process is similarly used SMT technology where multiple component packages are placed on a PCB, for example by printing a layer of solder or solder paste, or flux on exposed copper pad surfaces, followed by flip chip packaging, connecting or coupling on a second separate single-level package logic driver The plurality of copper pillars or bumps, the plurality of solder bumps or the plurality of gold bumps to the first single-level package logic driver exposes the solder layer, solder paste or flux on the plurality of copper pads, and connects or couples the plurality of Copper pillars or bumps, solder bumps or gold bumps on the surface of the copper pads of the first single-level package logic driver, wherein the flip chip packaging process is similar to the POP packaging technology used in IC stacking technology, here Note that copper pillars or bumps, solder bumps, or gold bumps on the second separate single-level package logic driver to bond to the copper pad surfaces of the first single-level package logic driver can be placed directly After the plurality of IC dies are positioned over the location of the first single-level package logic driver; an underfill material may be filled in the gap between the first single-level package logic driver and the second single-level package logic driver, the third separate single-level package logic driver Layer-packaged logic drivers (also with TPVS and BISD) can be flip-chip connected to the exposed surface of the TPVS coupled to the second single-level packaged logic driver, and the POP stack package process can be repackaged for multiple separate single-level packaged logic drivers (The number is, for example, greater than or equal to n discrete single-level package logic drivers, where n is greater than or equal to 2, 3, 4, 5, 6, 7, or 8) to form a completed stacked logic driver, when the first single-level package logic driver is Logic drivers are separate types, they can be assembled to a carrier or substrate, such as a PCB or BGA board, in a first flip-chip package, and then a POP process is performed, and in the carrier or substrate type, a plurality of stacked logic drivers are formed, and then The carrier or substrate is diced to generate multiple separations to complete the stacked logic drivers. When the first single-layer packaged logic drivers are still in the wafer or panel type, the wafers or panels can be directly separated when the POP stacking process is performed to form the multiple stacked logic drivers. Used as a carrier or substrate for the POP stacking process, the wafer or panel is then diced and separated to produce a plurality of separate stacks to complete the logic driver.

Another aspect of the present invention provides several alternative interconnections for the TPVS of a single-level packaged logic driver: (a) The TPV can be used as a via to connect another single-level packaged logic driver above and below another single-level packaged logic driver Another single-level package logic driver is not connected or coupled to the FISC, SISC or miniature copper pillars or bumps on any IC die of the single-level package logic driver, in which case the formation of a stacked structure, From bottom to top are: (i) copper pads (metal plugs in the bottommost insulating dielectric layer in BISD); (ii) multiple stacked interconnect layers and metal plugs in the dielectric layers of TISD; (iii) TPV layers; (iv) multiple stacked interconnect layers and metal plugs within the dielectric layers of the TISD; (v) metal metal pillars or bumps; (b) TPVs are stacked as in (a) the structure through the TISD Through TPV (through TPV) of metal lines or connecting lines, but connected or coupled to FISC, SISC or micro copper pillars or bumps on one or more IC chips of a single-level package logic driver; (c) TPV only Stacked on the bottom, but not on the top, in this case, the formation of the TPV connection structure, from bottom to top, respectively: (i) copper pads (metal plugs of the bottommost insulating dielectric layer in BISD); ( ii) A plurality of stacked interconnect layers and metal plugs in the dielectric layer of the BISD; (iii) TPV; (iv) The top of the TPV passes through the TISD multiple trenches or multiple open holes in the multiple interconnect metal layers and metal layers in the electrical layer Plug connection or coupling to FISC, SISC or micro copper pillars or bumps on one or more IC chips of single level package logic driver, no metal metal pillars or bumps directly on top of TPV and connected or coupled to TPV ; (v) metal metal pillars or bumps (on TISD) connected or coupled to the top of the TPV, but where one of the metal metal pillars or bumps is not directly on the top surface of the TPV; (d) TPV connection structure form, from bottom to top, (i) a copper pad (metal plug of the bottommost insulating dielectric layer in the BISD) directly under the IC die of the single-level package logic driver; (ii)) a copper pad on the BISD Pads, pillars or bumps are connected or coupled to the bottom of the TPV (in the gaps between the dies or in the peripheral area where no dies are placed) through a plurality of interconnecting wire metal layers and metal plugs within the dielectric layer of the BISD; (iii) TPVs; (iv) The upper TPVs are connected or coupled to FISCs on one or more IC chips of single-level packaged logic drivers through a plurality of interconnecting wire metal layers and metal plugs within the insulating dielectric layer of the TISD , R94, or micro copper pillars or bumps; (v) metal metal pillars or bumps (on TISD) are connected or coupled to the top of the TPV and are not located directly above the TPV; (e) the TPV connection structure is Formed, from bottom to top: (i) copper pads (the bottommost insulating dielectric in BISD) (ii) copper pads connected or coupled to the bottom of the TPV (which is located in the gap between the dies or is not provided with a die) Peripheral area) through a plurality of interconnecting wire metal layers and metal plugs in the dielectric layer of BISD; (iii) TPV; (iv) The top of the TPV is through a plurality of interconnecting wire metal layers and metal plugs in the dielectric layer of TISD The plugs are connected or coupled to FISC, SISC, or micro copper pillars or bumps on one or more IC chips of a single-level packaged logic driver, the plurality of interconnect metal layers and metal plugs within the dielectric layer of the TISD include a single layer One of the interconnecting nets or structures of metal lines or connecting lines within the TISD of the packaged logic driver for connecting or coupling transistors, FISCs, SISCs, and/or miniature copper pillars or bumps of FPGAIC chips, or packaged in A plurality of FPGAIC chips within a single-level packaged logic driver, but the interconnection nets or structures are not connected or coupled to a plurality of circuits or elements outside the single-level packaged logic driver, that is, a plurality of metal pillars within the single-level packaged logic driver or bumps (copper pillars or bumps, solder bumps, or gold bumps) to the interconnection network or structure of metal lines or connection lines within the TISD, so there are no metal pillars for single-level package logic drivers Or bumps (copper pillars or bumps, solder bumps or gold bumps) are connected or coupled to the top of the TPV.

Another aspect of the present invention discloses that the logic driver type in a multi-chip package may further include one or more dedicated programmable SRAM (DPSRAM) chips, the DPSRAM includes a plurality of 5TSRAM cells or 6TSRAM cells and a plurality of cross-point switches, and is used as a plurality of Interconnect programming between circuits or a plurality of interconnecting wires of a plurality of commercial standard FPGA chips, the plurality of programmable interconnecting wires including the interconnecting wires or wires of the TISD located between the plurality of commercial standard FPGA chips, which have A plurality of cross-point switch circuits of TISD and located in the middle of the interconnecting metal lines or connecting lines, such as n metal lines or connecting lines of TISD input to a cross-point switching circuit, and m metal lines or connecting lines of TISD from the switch The circuit output, the cross-point switch circuit is designed so that each of the n wires or connections of the TISD can be programmed to connect to any one of the m wires or connections of the TISD The line, cross-point switch circuits can be controlled via, for example, programming source code for SRAM cells stored in a DPSRAM chip, which can include 6 transistors (6TSRAM) including two transfer (write) transistors and four data locks Storage transistors, of which 2 transfer (write) transistor systems are used to write programming source code or data to the 2 storage or latch nodes of the 4 data latch transistors. Alternatively, the SRAM cell may include 5 transistors (5TSRAM), including a transfer (write) transistor and 4 data latch transistors, of which one transfer transistor system is used to write programming source code or data to 2 storage or latch nodes of 4 data latch transistors, the storage (programming) data in 5TSRAM cells or 6TSRAM cells is used for "connected" or "unconnected" programming of TISD metal lines or connecting lines , the complex crosspoint switches are the same as those described in the complex commercial standard FPGAIC chips above, the details of the various types of complex crosspoint switches are disclosed or described in the paragraphs above for the complex FPGAIC chips, and the complex crosspoint switches may include: (1) n A paired circuit of type and p-type transistors; or (2) a plurality of multiplexers and a plurality of switch buffers, when the data latched in the 5TSRAM cell or the 6TSRAM cell is programmed at "1", an n-type and p-type paired The pass/no pass circuit of the transistor is switched to the "on" state, and the two metal lines or connecting lines of the TISD connected to the two ends of the pass/no pass circuit (respectively the source and drain of the paired transistor) are: In the connected state, and the data latched in the 5TSRAM cell or the 6TSRAM cell is programmed to "0", the pass/no pass circuit of a pair of n-type and p-type transistors switches to a "non-conducting" state, connecting to pass/no The two metal lines or connecting lines of the TISD passing through the two ends of the circuit (respectively the source and drain electrodes of the paired transistors) are not connected, or, when the data latched in the 5TSRAM cell or the 6TSRAM cell is programmed in "1" ", the control N-MOS transistor and the control P-MOS transistor in the switch buffer are switched to the "on" state, the data in the input metal line is turned on to the output metal line of the cross-point switch, and is connected to the cross The two metal lines or connecting lines of the TISD at the two terminals of the point switch are connected or coupled; when the data latched in the 5TSRAM cell or the 6TSRAM cell is programmed to "0", the control N-MOS circuit in the switch buffer The crystal and the control P-MOS transistor are switched to a "non-conducting" state, the data on the input metal line is not conducted to the output metal line of the cross-point switch, and the two metal lines of the TISD connected to the two terminals of the cross-point switch or Connection lines are not connected or coupled. The DPSRAM chip includes a plurality of 5TSRAM cells or 6TSRAM cells and a plurality of crosspoint switches, and the plurality of 5TSRAM cells or 6TSRAM cells and a plurality of crosspoint switches are used for the programmable interaction of the metal lines or connecting lines of the TISD between the plurality of commercial standard FPGA chips in the logic driver. Wires, alternatively, 5TSRAM cells or 6TSRAM cells and crosspoint switches Programmable interconnection of metal wires or wires for TISD between commercial standard FPGA chips in logic drivers and TPVS (eg, TPVS top surface) line, as described above in the same or similar disclosed method. The (programming) data stored in the 5TSRAM cell or the 6TSRAM cell is used to program the connection or disconnection between the two, for example: (i) the first metal line, connection line or net of the TISD is connected to an or One or more miniature copper pillars or bumps on the plurality of IC chips, and/or one or more metal pillars or bumps on or above the TISD connected to the logic driver, and (ii) the second metal line, connecting line of the TISD Or the mesh is connected or coupled to a TPV (eg, TPV top surface), as in the same or similar disclosed methods above. According to the above disclosure, TPVS is programmable, that is, the above disclosure provides programmable TPVS, programmable TPVS or can be used in programmable interconnects, including plural 5TSRAM cells on plural FPGA chips used in logic drivers or 6TSRAM cells and crosspoint switches, programmable TPVs can be programmed (via software) to (i) one or more of one or more IC chips connected or coupled to the logic driver or microcopper pillars or bumps (for this Metal lines or connecting lines connected to SISC and/or FISC, and/or transistors), and/or (ii) one or more metal connections on or above the TISD connected or coupled to the logic driver Pads, metal pillars, or bumps when copper pads on the backside of a logic drive (TPV bottom surface, bottom bottom surface of metal plugs located within the polymer layer of the bottom portion of the TPV, or bottom-most polymer for BISD The metal plug bottom surface in the layer is connected to the programmable TPV, the copper pad becomes a programmable copper pad, and the programmable copper pad on the backside of the logic driver can be programmed and connected or coupled through the programmable TPV to ( i) one or a plurality of miniature copper pillars or bumps on the front side of one or more IC chips (for this purpose connected to the SISC and/or the FISC) of the logical driver; and (or)(ii) the front side of the logical driver A plurality of metal pads, bumps or pillars on or above the TISD. Alternatively, the DPSRAM chip includes 5TSRAM cells or 6TSRAM cells and crosspoint switches, which can be used for metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps) on or over the TISDs of the logic driver Programmable interconnections of metal lines or connecting lines of TISD between blocks), and micro copper pillars or bumps on one or more IC chips of the logic driver, as the same or similar methods disclosed above. The data stored (or programmed) in a 5TSRAM cell or a 6TSRAM cell can be used for "connected" or "unconnected" programming between the two, for example: (i) the first metal line or connecting line of the TISD is connected to the logic One or more miniature copper pillars or bumps on one or more IC chips of the driver, and a plurality of metal metal pillars or bumps connected to the TISD, and (ii) a second metal line or connecting line of the TISD is connected or coupled A plurality of metal pads, studs, or bumps are connected to or above the TISD, as in the same or similar disclosed methods above. According to the above disclosure, the plurality of metal studs or bumps on or above the TISD are also programmable. In other words, the plurality of metal pads, studs or bumps on or above the TISD provided by the above disclosure of the present invention are programmable. Programmable metal pads, studs or bumps on or over TISD or can be used in programmable interconnects, including 5TSRAM cells or 6TSRAM cells and crosspoint switches on FPGA die for logic drivers, programmable The plurality of metal pads, studs or bumps can be programmed, connected or coupled to one or more IC chips of the logic driver (for this purpose connected to the metal lines or connecting lines of the SISC and/or the FISC, and/or a plurality of transistor) or a plurality of micro copper pillars or bumps.

DPSRAMs can be designed to be implemented and fabricated using a variety of semiconductor technologies, including older or mature technologies, such as less than, equal to, above, below 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. Or DPSRAM includes use first above or equal to, below or equal to 30nm, 20nm or 10nm. This DPSRAM can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on multiple commercial standard FPGAIC chips within the same logic driver. The transistors used in DPSRAMs can be FINFETGAAFETs, FDSOIMOSFETs, partially depleted silicon insulator MOSFETs or conventional MOSFETs. The transistors used in DPSRAMs can be different from commercial standard FPGAIC chip packages used in the same logic driver, such as DPSRAM Conventional MOSFETs are used, but commercial standard FPGAIC chip packages within the same logic driver can use FINFET transistors, or DPSRAM uses FDSOIMOSFETs, and commercial standard FPGAIC chip packages within the same logic driver can use FINFETs or GAAFETs.

Another aspect of the present invention provides a logic driver type in a multi-chip package further comprising one or more dedicated programmable interconnect and cache SRAM (DPCSRAM) chips, the DPCSRAM chips including (i) a plurality of 5TSRAM cells or 6TSRAM cells and a plurality of cross points Switches are used to program the interconnects of wires or interconnects in TISDs, thus programming interconnects between interconnects or circuits of commercial standard FPGA chips within logic drivers, and (ii) conventional 6T The plurality of SRAM cells are used for the cache memory, and the plurality of programmable interconnect lines and the plurality of cross-point switches in the plurality of 5T or 6T cells are as disclosed and described above. Alternatively, as in the same or similar methods disclosed above, the DPCSRAM chip includes a plurality of 5TSRAM cells or a plurality of 6TSRAM cells and a plurality of crosspoint switches, which can be used between a plurality of commercial standard FPGA chips in a logic driver and a TPVS (eg, a TPVS top surface) Programmable interconnection of TISD metal lines or connecting lines, the data stored (or programmed) in the 5TSRAM cell or the 6TSRAM cell can be used for "connected" or "unconnected" programming between the two, the same as above or Methods similar to those disclosed such as: (i) a first metal line or connecting line in a TISD, connected to one or a plurality of micro-copper pillars or bumps on one or more IC chips of a logic driver, on a TISD of a logic driver, or The upper one or more metal pads, studs, or bumps, and (ii) the TISD second metal line or connection line is connected or coupled to the TPV (eg, the top surface of the TPV), which is programmable according to the above disclosure, in other words In other words, the above disclosure provides programmable TPVS, programmable TPVS or can be used in programmable interconnects, including multiple 5TSRAM cells or 6TSRAM cells and multiple crosspoint switches on multiple FPGA chips for use in logic drivers, programmable TPVs Can be programmed (via software) to (i) one of one or more IC chips connected or coupled to the logic driver or a plurality of micro copper pillars or bumps (for this purpose connected to the metal lines of the SISC and/or the FISC or connecting lines, and (or) transistors), and (or) (ii) one or more metal pads, metal posts or bumps on or above the TISD connected or coupled to the logic driver, when located on The copper pads on the back of the logic drive (the bottom surface of the TPV, the bottom surface of the metal plug in the polymer layer in the bottom portion of the TPV, or the bottom surface of the metal plug in the bottommost polymer layer of the BISD) are connected to the Program the TPV, the copper pad becomes a programmable copper pad on or over the BISD, programmable metal pads, bumps or pillars on the backside of the logic driver can be programmed and connected or coupled to the programmable TPV (i) one or more IC chips (for this purpose connected to SISC and/or FISC metal lines or connecting lines, and/or multiple transistors) one or more micro copper pillars or bumps on the front side of the logic driver block; and/or (ii) a plurality of metal pads, bumps or pillars on or over the TISD on the front side of the logic drive. Alternatively, the DPCSRAM chip includes 5TSRAM cells or 6TSRAM cells and crosspoint switches, which can be used for metal pillars or bumps (copper pillars or bumps, solder bumps, or gold) on or over the TISDs of the logic driver. Programmable interconnection lines of metal lines or connecting lines of TISD between bumps), and one or more micro copper pillars or bumps on one or more IC chips of logic drivers, as the same or similar disclosed methods above . The data stored (or programmed) in the 5TSRAM cell or the 6TSRAM cell can be used for "connected" or "unconnected" programming between the two, for example: (i) TISD first metal line or connecting line is connected to the logic driver One or a plurality of micro-copper pillars or bumps on one or more IC chips of the To a plurality of metal pads, studs or bumps on or above the TISD, as described above in the same or similar disclosed methods. According to the above disclosure, the plurality of metal studs or bumps on or above the TISD are also programmable. In other words, the plurality of metal pads, studs or bumps on or above the TISD provided by the above disclosure of the present invention are programmable. Plural metal metal pillars or bumps or can be used in programmable interconnects, including plural 5TSRAM cells or 6TSRAM cells and plural crosspoint switches on plural FPGA chips used in logic drivers, programmable plural plural metal metal pillars or bumps One or more micro-copper pillars can be programmed, connected or coupled to the logic driver's one or more IC chips (for this purpose connected to the SISC's and/or FISC's metal lines or connecting lines, and/or the plurality of transistors) or bumps.

6TSRAM cells are used as cache memory for data latching or storage, which includes 2 transistors for bit and bit-bar data transfer, and 4 data latch transistors for a data lock Storage or storage node, the plurality of 6TSRAM cache memory cells provide 2 transfer transistors for writing data to the 6TSRAM cache memory cell and reading data from the 6TSRAM cache memory cell, and reading from the plurality of cache memory cells A sense amplifier is required for (amplifying or detecting) the data, in contrast, multiple 5TSRAM cells or 6TSRAM cells for programmable interconnects or for LUTS may not require a read step, and no sense amplifiers are required for Detecting data from SRAM cells, DPCSRAM chips include 6T complex SRAM cells used as cache memory to store data during operations or computations on the logic drive's complex chips, DPCSRAM chips can be designed and fabricated using a variety of semiconductor technologies, including older Or mature technology, such as not advanced above, equal to, above, below 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm. Or DPCSRAM wafers include use first above or equal to, below or equal to 30nm, 20nm or 10nm. This DPCSRAM chip can use semiconductor technology 1st, 2nd, 3rd, 4th, 5th, or more than 5th generation, or use more mature or advanced technology on multiple commercial standard FPGAIC chips within the same logic driver . The transistors used in the DPCSRAM die can be FINFETs, GAAFETs, FDSOIMOSFETs, partially depleted silicon insulator MOSFETs or conventional MOSFETs. The transistors used in the DPCSRAM die can be different from the commercial standard FPGAIC die packages used in the same logic driver For example, DPCSRAM chips use conventional MOSFETs, but commercial standard FPGAIC chip packages within the same logic driver can use FINFET transistors or GAAFET transistors, or DPCSRAM chips use FDSOIMOSFETs, while commercialized standard FPGAIC chip packages within the same logic driver Standard FPGAIC chip packages can use FINFET or GAAFET.

Another aspect of the present invention provides a wafer-type, panel-type standardized plurality of IC chips and packages in inventory or in a listing for subsequent formation of a commercialized standard logic driver process, as described and disclosed above, Standardized IC chips and packages include a fixed layout or design of copper pads and TPVS on the backside of the IC chips and packages, and if included in the IC chips and packages, the fixed design and/or layout of the BISD, the The TPVS and the plurality of copper pads in or on the IC chip and package are the same, if there are BISDs, design or BISD interconnection lines, such as the connection structure between the plurality of copper pads and the TPVS, each commercial standard plural number The IC chips and packages are the same, and the commercialized standard multiple IC chips and packages in the inventory and commodity list can then be used to form a commercialized standard logic driver through the above disclosure and description. The steps include: (1) placing, accommodating, Fixing or adhering a plurality of IC chips on a plurality of IC chips and packages, wherein the plurality of IC chips and packages have the surface of the chip (which has a plurality of transistors) or one side up; (2) Filling with a material, resin, or compound The gaps between the plurality of wafers, and for example in wafer or panel format are covered on the plurality of wafers by coating, printing, dripping or potting, using a CMP process to planarize the surface of the applied material, resin or compound to a The horizontal plane to the plurality of wafers on which all the plurality of micro-bumps or metal pillars are exposed; (3) the TISD is formed; and (4) the plurality of metal pillars or bumps on the TISD are formed, with a fixed layout or design of commercial standard carriers, brackets, Fillers or substrates can be customized for different applications through TISD different designs or layouts. Commercially available standard carriers, holders, molders or substrates with fixed layouts or designs can be coded or programmed by software for different applications Specifically customized and used, as described above, with data mounted or programmed in multiple 5TSRAM cells or 6TSRAM cells on multiple DPSRAM or DPCSRAM chips, available for programmable TPVs, with data mounted or programmed in multiple 5TSRAM cells or 6TSRAM cells on multiple FPGA chips Or can be used for programmable TPVs.

Another aspect of the present invention provides a commercial standard logic driver (eg, a single-level package logic driver) with a fixed design, layout or pinout, including: (i) a plurality of metal pillars or bumps (a plurality of copper pillars) on the front side or bumps, solder bumps, or gold bumps), and (ii) copper pads on the backside of commercial standard logic drivers (TPV bottom surface, metal plugs in the polymer layer on the bottom portion of the TPV) the bottom surface of the BISD, or the bottom surface of the metal plug in the bottommost polymer layer of the BISD), commercial standard logic drivers can be used in different applications, which can be used in different applications by software coding or programming, and use As described in the above disclosure and description, programming of multiple metal pillars or bumps and/or programmable multiple copper pads (through programmable TPVs) is performed. As mentioned above, for different applications, software can be downloaded, installed or programmed. The source code of the program is in multiple 5TSRAM cells or 6TSRAM cells of a DPSRAM or DCPRAM die to control multiple crosspoint switches in the same single-level package logic driver 6 or DCPRAM die in a commercial standard logic driver, or, for different Application, source code for downloading, installing or programming software programs in a logic driver of a commercial standard logic driver or a plurality of 5TSRAM cells or 6TSRAM cells of a plurality of FPGAIC chips in a commercial standard logic driver for controlling the same FPGAIC Multiple crosspoint switches of a chip, each commercial standard logic driver with multiple metal pillars or bumps and multiple copper pads of the same design, layout or pinout can be coded or programmed by software for a different application, purpose or function , where programmable can use programmable complex copper pads of logic drivers (via programmable TPVS), and/or programmable complex metal pillars or bumps.

Another aspect of the present invention provides a single-layer package or stacked logic driver, which includes a plurality of IC chips, a plurality of logic blocks, cells or elements (including LUTs, a plurality of multiplexers, a plurality of logic operation circuits, a plurality of logic operation gates, and ( or) complex computing circuits) and/or complex memory cells or arrays, the logic driver is immersed in a structure or environment with super rich interconnects, logical blocks, cells or elements (including LUTs, multiplexed devices, complex logic operation circuits, complex logic operation gates and/or complex calculation circuits) and/or complex memory cells or arrays within a complex commercial standard FPGA IC chip immersed in a programmable 3D immersive IC interconnection line Environment (IIIE); wherein (1) in the xy direction FISC, SISC, TISD and/or BISD provide an interconnecting wire structure or system for interconnecting or coupling in a single level package logic driver on the same FPGAIC die or in Logic blocks, cells or components and/or memory cells or matrices in different FPGAIC chips, interconnecting wire structures in the xy direction or interconnecting metal wires or interconnecting wires in the system can be programmed; (2) in BISD Metal structures on SISC include micro metal pillars or bumps on SISC or micro metal pillars or bumps, solder bumps or gold bumps on TISD, TPVs and/or copper pads, providing interconnection lines in the z-direction Structure or system for interconnecting or coupling logic blocks, cells or elements and/or memory cells or matrices in different FPGAIC chips of different single-level logic drivers in a stacked package logic driver, interconnection in the z-direction Interconnecting wires or interconnects in wire structures or systems can be programmed; at very low cost, programmable 3DIIIE provides a virtually unlimited number of transistors or complex logic blocks, cells or elements, interconnecting wires Or connecting lines and memory cells/switches, programmable 3DIIIE like or similar to the human mind: (i) complex transistors and/or complex logic blocks, cells or elements (including complex logic operation gates, logic operation circuits, Computational operating units, computational circuits, LUTs and/or multiplexers) and/or interconnecting wires, similar or similar neurons (cell bodies) or neurons; (ii) FISC or SISC metal wires or connecting wires It is similar or similar to dendrites (dendrities) connected to neurons (plural cell bodies) or plural nerve cells, and miniature metal pillars or bumps connected to plural receivers for plural logic blocks, cells or components in plural FPGAIC chips ( Postsynaptic cells whose complex inputs are similar or similar to synaptic terminals, including complex logic operation gates, logic operation circuits, computational operation units, computational circuits, LUTs, and/or complex multiplexers; Connection via FISC metal lines or connecting lines, SISC, TISD and/or BISD, multiple metal pillars or bumps, micro copper pillars included on SISC or bumps, metal pillars or bumps on TISD, TPVs, copper pads on BISD which resemble or resemble axons connected to neurons (cell bodies) or nerve cells, miniature Metal pillars or bumps connected to complex drivers or emitters for complex logic blocks, units or elements (including complex logic gates, logic operation circuits, computational operation units, computational circuits, LUTs and/or complex numbers) within a complex FPGAIC chip multiplexer), which resembles or resembles the complex number of pre-synaptic cells at the axon terminal.

Another aspect of the present invention provides a programmable 3DIIIE with similar or similar complex connections, interconnecting lines and/or complex human brain functions: (1) complex transistors and/or complex logic blocks, units or elements (including Complex logic operation gates, logic operation circuits, computing operation units, computing circuits, LUTs and (or) complex multiplexers) are similar or similar to neurons (complex cell bodies) or complex nerve cells; (2) complex interconnecting line structure and logical drive structures that resemble or resemble dendrites or axons connected to neurons (plural cell bodies) or multiple nerve cells, and the multiple interconnecting wire structures and/or logical drive structures include (i) Metal lines or connections for FISC, SISC, TISD, and BISD and/or (ii) micro copper pillars or bumps, metal pillars or bumps on TISD, TPVS, and/or copper on backside Pads, axon-like interconnecting wire structures and/or logic driver structures are connected to the drive output or emission output (a driver) of a logic operation unit or operating unit, which has a structure like a tree A structure comprising: (i) a trunk or stem connected to a logic operation unit or operation unit; (ii) a plurality of branches branching off from the backbone, the ends of each branch may be connected or coupled to other complex logic operation units or operations Cells, programmable complex crosspoint switches (multiple 5TSRAM cells or 6TSRAM cells/complex switches of a complex FPGAIC chip or/and a complex DPSRAM, or a complex DPCSRAM) to control the connection or disconnection of the trunk to each branch; (iii ) sub-branches branched out from the complex branch, and the end of each sub-branch can be connected or coupled to other complex logic operation units or operation units, programmable complex cross-point switches (complex FPGAIC chips or (and) complex DPSRAMs The plurality of 5TSRAM cells or 6TSRAM cells/switches, or the plurality of DPCSRAMs) are used to control the "connection" or "disconnection" between the trunk and each of its branches, a branch-like interconnect structure and/or the logic driver. The structure is connected to the receiving or sensing input of a logic operation unit or operating unit (a receiver), and the branch-like interconnect structure has a structure similar to that of a shrub: (i) a short trunk connected to a logic unit or operating unit; (ii) branching from the trunk, plural programmable switches (multiple 5TSRAM cells or 6TSRAM cells/complex switches of FPGAIC chips or (and) DPSRAMs, or DPCSRAMs) are used to control the trunk or its "connection" or "non-connection" between each branch, the plurality of dendritic-like interconnecting line structures are connected or coupled to the logic operation unit or operation unit, and the end of each branch of the dendritic-like interconnecting line structure is connected or ends of trunks or branches coupled to axon-like structures, logical The dendrimer-like interconnect structure of the driver may include a plurality of FISCs and SISCs of a plurality of FPGAIC chips.

Another aspect of the present invention provides a commercial standard memory drive, packaged or packaged drive, device, module, hard drive, hard drive, solid state drive or solid state drive (hereafter referred to as the drive) in a multi-chip package , including a number of commercial standard non-volatile memory IC chips for data storage. Even when the power of the drive is turned off, the data stored in the commercial standard non-volatile memory drive is still retained. The plurality of non-volatile memory IC chips include a plurality of NAND or NOR flash chips of a bare type or a package type, Alternatively, the plurality of non-volatile memory IC chips may include bare die type or packaged type non-volatile NVRAM. The plurality of IC chips may be Ferroelectric RAM (FRAM), magnetoresistive random access memory Magnetoresistive RAM (MRAM), Phase-change RAM (PRAM), commercial standard memory drives consisting of FOIT, which are used in the formation of commercial standard logical drives as described in the above paragraphs The process steps of FOIT are as follows: (1) Provide non-volatile memory IC chips, such as a plurality of commercial standard NAND or NOR flash IC chips, a chip carrier, support, mold filling material or substrate, and then place, fix or adhere a plurality of IC chips on a carrier, support, molder or substrate; each NAND flash chip can have a standard memory density, content or size greater than or equal to 64Mb, 512Mb, 1Gb, 4Gb, 16Gb, 64Gb, 128Gb, 256Gb or 512Gb, where "b" is a bit, each NOR flash IC chip can have a standard memory density, internal volume or size greater than or equal to 1Mb, 4Mb, 16Mb, 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 4Gb or 16Gb, where "b" is a bit, NAND flash chips can use advanced NAND flash technology or next generation process technology or design and manufacture, for example, technology advanced in or Equal to 45nm, 28nm, 20nm, 16nm and/or 10nm, where advanced NAND flash technology can include the use of a single monolayer in planar flash (2D-NAND) structures or three-dimensional flash (3DNAND) structures Single Level Cells (SLC) technology or multiple level cells (MLC) technology (eg, Double Level Cells DLC or triple Level Cells TLC). A 3D NAND structure may include stacked layers (or levels) of a plurality of NAND memory cells, eg, greater than or equal to 4, 8, 16, 32 stacked layers of NAND memory cells. Each of the plurality of NAND flash chips is packaged in the plurality of memory drivers, which may include micro-copper pillars or bumps disposed on the upper surface of the plurality of chips, and the upper surface of the micro-copper pillars or bumps has a level located on the top of the plurality of chips. Above the level of the upper surface of the topmost insulating dielectric layer, its height is, for example, between 3 µm and 60 µm, between 5 µm and 50 µm, between 5 µm and 40 µm, between 5 µm and 30 µm, Between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm, or 3µm, pluralities of chips set, housed, fixed or attached to pluralities of ICs On chips and packages, wherein the surface or side of the chip with the plurality of transistors is facing up; (2) the resin material or the The compound fills the gaps between the plurality of wafers and covers the surfaces of the plurality of wafers, and the surface of the application material, resin or compound is planarized using a CMP process to fully expose the upper surfaces of all the plurality of micro-bumps or metal pillars on the plurality of wafers; ( 3) Form a TISD structure on or above the planarized material, resin or compound through a wafer or panel process, and on the memory driver, and the exposed upper surface of the micro metal pillars or bumps; (4) Form a plurality of copper pillars or bumps Blocks, solder bumps, and gold bumps on TISD, dicing completed wafers or panels, including separating, slicing through a material or structure between two adjacent memory drivers, the material or compound (e.g. A plurality of wafers filled between two adjacent memory drives are separated or diced into individual memory drives.

Another aspect of the present invention provides a commercial standard memory driver in a multi-chip package, the commercial standard memory driver includes a plurality of commercial standard non-volatile memory IC chips, and the commercial standard non-volatile memory IC chips are more Including dedicated control chip, dedicated I/O chip or dedicated control chip and dedicated I/O chip for data storage, even when the power of the drive is turned off, the data stored in the commercial standard non-volatile memory drive is retained, plural The non-volatile memory IC chips include a bare-type or a package-type NAND or NOR flash chips, or the non-volatile memory IC chips can include a bare-type or a package-type non-volatile NVRAM Multiple IC chips, NVRAM can be Ferroelectric RAM (FRAM), Magnetoresistive RAM (MRAM), Phase-change RAM (PRAM), dedicated The functions of the control chip, the dedicated I/O chip, or the dedicated control chip and the dedicated I/O chip are for memory control and/or input/output, and the same or similar disclosures as described in the preceding paragraphs are used for logical drives , communication, connection or coupling between non-volatile memory IC chips such as multiple NAND or NOR flash chips, dedicated control chips, dedicated I/O chips, or dedicated control chips within the same memory driver and The description of the dedicated I/O chip is the same as or similar to the description (disclosure) in the above paragraph for the logic driver, and a plurality of commercial standard NAND or NOR flash IC chips may be used different from the dedicated control chip, the dedicated I/O chip or the IC manufacturing technology nodes or generations of dedicated control chips and dedicated I/O chips within the same memory driver, multiple commercial standard NAND or NOR flash IC chips include multiple small I/O circuits, and are used in memory drives. A dedicated control chip, a dedicated I/O chip, or a dedicated control chip and a dedicated I/O chip may include a plurality of large I/O circuits, as disclosed and described above for logic drivers, commercial standard memory drivers include dedicated control chips, Dedicated I/O chips, or dedicated control chips and dedicated I/O chips via FOIT, are fabricated using the same or similar multiple FOIT processes used to form the logical drivers, as disclosed and described in the preceding paragraphs.

Another aspect of the present invention provides a stacked non-volatile (eg, NAND or NOR flash) memory driver comprising, as disclosed and described above, a single-level packaged non-volatile memory driver with TPVS for use in a standard type (with Standard size) stacked non-volatile memory drivers, for example, single-layer packaging non-volatile memory drivers can have a square or rectangular shape with a certain width, length and thickness, an industry standard can set single-layer packaging non-volatile memory drivers The diameter (dimension) or shape of the volatile memory driver, for example, the standard shape of a single-layer packaged non-volatile memory driver can be a square, and its width is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm , 35mm or 40mm, and have a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm. Alternatively, the standard shape of a single-level packaged non-volatile memory driver may be a rectangle with a width greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm and a length greater than or equal to 3mm , 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm or 50mm, and its thickness is greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm , 4mm or 5mm. Stacked plural non-volatile memory chip drivers including, for example, 2, 5, 6, 7, 8, or more than 8 single-level packaged non-volatile memory drivers, similar to those disclosed and described above for forming stacked logic drivers can be used Or the same process to form, single-level packaged non-volatile memory drivers include TPVS for stacked packaging purposes, these process steps are used to form TPVS, the parts of the TPVS disclosed and described in the above paragraphs can be used for stacked logic drivers, while using The method of TPVS stacking (eg, the POP method) is as disclosed and described in the above paragraphs for stacked logical drives.

Another aspect of the present invention provides a commercial standard memory driver in a multi-chip package comprising a plurality of commercial standard plurality of volatile IC chips for data storage, wherein 137 comprises a plurality of DRAM chips in bare die or packaged form, commercial The standard DRAM memory driver is formed by FOIT. The above paragraphs can be used to disclose and describe the steps of forming a logic driver using the same or similar FOIT process. The process steps are as follows: (1) Provide commercial standard multiple DRAMIC chips and chip carriers and support , Fill molding material or substrate, and then set, fix or adhere a plurality of IC chips on a carrier, support, molder or substrate, each DRAM chip can have a standard memory density, internal volume or size greater than or equal to 64Mb, 512Mb , 1Gb, 4Gb, 16Gb, 64Gb, 128Gb, 256Gb or 512Gb, where "b" is a bit, DRAM flash chips can use advanced DRAM flash technology or next-generation process technology or design and manufacture, for example, technology advanced in or equal to 45nm, 28nm, 20nm, 16nm and/or 10nm, all DRAM chips are packaged in a plurality of memory drivers, which may include micro copper pillars or bumps disposed on the upper surface of the plurality of chips, micro copper pillars or The upper surface of the bump has a level above the level of the upper surface of the topmost insulating dielectric layer of the plurality of chips, and its height is, for example, between 3µm to 60µm, between 5µm and 50µm, and between 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 15µm, or 3µm to 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm or 3µm , the plurality of wafers are arranged, fixed or adhered on the carrier, support, mold filling device or substrate, wherein the surface or side of the wafer with the plurality of transistors is facing upward; (2) If there is, it can be obtained by the following methods, such as spin coating, mesh lithography, drop casting, or casting in wafer or panel formats, can utilize a material, resin, or compound to fill in the gaps between multiple wafers and cover the surfaces of multiple wafers, and use a CMP process to planarize the applied material, resin The surface of the compound or the surface of the compound to the upper surface of all the plurality of micro-bumps or metal pillars of all the plurality of chips is fully exposed; (3) Through the wafer or panel process, a TISD is formed on the planarization application material, resin or compound, and micro-metallic The exposed upper surface of the pillars or bumps; (4) forming copper pillars or bumps, solder bumps or gold bumps on the TISD; (5) dicing the completed wafer or panel, including via The material or structure between adjacent memory drives is separated and cut, and the plurality of wafers filled with the material or compound (eg, polymer) between two adjacent memory drives are separated or cut into individual memory drives.

Another aspect of the present invention provides a commercial standard memory driver in a multi-chip package, the commercial standard memory driver includes a plurality of commercial standard plural volatile IC chips, and the commercial standard plural volatile IC chip further includes a dedicated control chip , Dedicated I/O chip or dedicated control chip and dedicated I/O chip for data storage, plural volatile IC chips include a bare crystal type or a DRAM package type, dedicated control chip, dedicated I/O chip or dedicated control chip and dedicated I/O chips for memory driver functions for memory control and/or input/output, and the same or similar disclosures described in the preceding paragraphs for logic drivers, between DRAM chips The communication, connection, or coupling of, for example, multiple NAND flash chips, dedicated control chips, dedicated I/O chips, or dedicated control chips and dedicated I/O chips within the same memory driver as described in the preceding paragraph for logic The description (disclosure) in the driver is the same or similar, commercial standard complex DRAMIC chips can be manufactured using different IC manufacturing technology nodes or generations than dedicated control chips, dedicated I/O chips, or dedicated control chips and dedicated I/O chips, commercial Standard complex DRAM chips include multiple small I/O circuits, while dedicated control chips, dedicated I/O chips, or dedicated control chips and dedicated I/O chips used in memory drives may include multiple large I/O circuits, as described above For the disclosure and description of logical drives, commercial standard memory drives can be fabricated using the same or similar multiple COIP processes used to form logical drives, as disclosed and described in the preceding paragraphs.

Another aspect of the present invention provides a stacked volatile (eg, DRAM chip) memory driver comprising, as disclosed and described above, a plurality of single-level packaged volatile memory drivers with TPVS for use in standard-type (having a standard size) Stacked multiple non-volatile memory chip drivers, for example, multiple single-layer packaged volatile memory drivers can have a square or rectangular shape with a certain width, length and thickness, an industry standard can set multiple single-level packaged volatile memory drivers The diameter (dimension) or shape of the bulk driver, for example, the standard shape of a plurality of single-layer package volatile memory drivers can be square, and its width is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and have a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm. Alternatively, the standard shape of the plurality of single-layer packaged volatile memory drivers may be a rectangle with a width greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm and a length greater than or equal to 3mm , 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm or 50mm, and its thickness is greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm , 4mm or 5mm. Stacked volatile memory drivers include, for example, 2, 5, 6, 7, 8, or more than 8 pluralities of single-level package volatile memory drivers, similar or identical to those disclosed and described above for forming stacked logical drivers. Process formation, multiple single-level package volatile memory drivers include TPVS for stacked packaging purposes, these process steps are used to form TPVS, the portion of the TPVS disclosed and described in the above paragraphs can be used for stacked logic drivers, while the use of TPVS stacked logic drivers The method (eg, the POP method) is as disclosed and described for the stacked logical drives in the above paragraphs.

Another aspect of the present invention provides a stacked logic operation and volatile memory (eg, DRAM) driver comprising a plurality of single-level packaged logic drivers and a plurality of single-level packaged volatile memory drivers, each of which is disclosed and described above. The packaged logic driver and each of the plurality of single-level packaged volatile memory drivers may be located in a multi-chip package, and each of the single-level packaged logic drivers and each of the plurality of single-level packaged volatile memory drivers may be of the same standard type or have a standard Shape and size, as disclosed and described above, stacked logic operations and volatile memory drivers include, for example, 2, 3, 4, 5, 6, 7, 8 or greater than 8 single-level package logic drivers or multiple volatile Memory drivers can be formed using similar or identical processes as disclosed and described above for forming stacked logical drivers, and the stacking sequence from bottom to top can be: (a) all single-level package logical drivers on the bottom and all The plurality of single-level package volatile memory drivers are located on the top, or (b) the single-level package logic driver and the plurality of single-level package volatile drivers are stacked and interleaved sequentially from bottom to top: (i) the single-level package logic driver; ( ii) single-level package volatile memory driver; (iii) single-level package logic driver; (iv) single-level package volatile memory, etc., single-level package logic driver and multiple single-level package volatile memory driver are used for A plurality of stacked logical drivers and volatile memory drivers, each logical driver and volatile memory driver including TPVs for packaging purposes, the process steps for forming TPVS, as disclosed in the above paragraphs and related descriptions, and the use of TPVS stacked The method (eg, the POP method) is as disclosed and described in the above paragraphs.

Another aspect of the present invention provides stacked non-volatile (eg, NAND or NOR flash) and volatile (eg, DRAM) memory drivers including a single-level packaged non-volatile driver and a plurality of single-level packaged volatile memory drivers, each The single-level packaged non-volatile driver and each of the plurality of single-level packaged volatile memory drivers may be located in a multi-chip package, as disclosed and described in the preceding paragraphs, each of the single-level packaged volatile memory drivers and each of the single-level packaged volatile memory drivers Packaged non-volatile drivers may be of the same standard type or of standard shape and size, as disclosed and described above, stacked non-volatile and volatile memory drivers including, for example, 2, 5, 6, 7, 8, or greater than 8 in total A single-level package non-volatile memory driver or a plurality of single-level package volatile memory drivers may be formed using similar or identical processes as disclosed and described above for forming the stacked logic driver, and the bottom-to-top stacking sequence may be Either: (a) all PLP volatile memory drivers are on the bottom and all PLP non-volatile memory drivers are located on top, or (b) all PLP non-volatile memory The drivers are on the bottom and all the multiple single-level package volatile memory drivers are located on the top; (c) the single-level package non-volatile memory drivers and the multiple single-level package volatile drivers are stacked in sequence from bottom to top and staggered: (i ) single-level package volatile memory drivers; (ii) single-level package non-volatile memory drivers; (iii) single-level package volatile memory drivers; (iv) single-level package multiple non-volatile memory chips, etc. , single-level encapsulated non-volatile drivers and single-level encapsulated volatile memory drivers for stacking multiple non-volatile chips and volatile memory drivers, each logic driver and volatile memory driver included for packaging purposes TPVs and/or BISDs, the process steps for forming TPVS and/or BISDs are disclosed and related in the paragraphs above for stacking logical drivers, and methods for stacking TPVS and/or BISDs (such as the POP method) ) as disclosed and described in the paragraph above for stacking logical drives.

Another aspect of the present invention provides stacked logic non-volatile (eg, NAND or NOR flash) memory and volatile (eg, DRAM) memory drivers including a plurality of single-level packaged non-volatile drivers and a plurality of single-level packaged volatile memories The drivers may be located in a multi-chip package, as disclosed and described above, each single-level package non-volatile and each multiple single-level package volatile memory drivers The drivers may be of the same standard type or have a standard shape and size, as described above Disclosed and illustrated, stacked logic non-volatile (flash) memory and volatile (DRAM) memory drivers include, for example, 2, 3, 4, 5, 6, 7, 8 or more than 8 single-level package non-volatile A volatile memory driver or a plurality of single-level package volatile memory drivers can be formed using similar or identical processes as disclosed and described above for forming a stacked logical driver memory, and the stacking sequence from bottom to top is, for example: ( a) all single-level package volatile memory drivers on the bottom and all single-level package non-volatile memory drivers on top; (b) all single-level package non-volatile memory drivers on the bottom and all single-level package non-volatile memory drivers on the bottom The packaged volatile memory driver is on top, or (c) a single-level packaged non-volatile memory driver and a plurality of single-level packaged volatile memory drivers are stacked and staggered sequentially from bottom to top: (i) a single-level packaged volatile memory driver Drivers; (ii) Single-Encapsulated Non-Volatile Memory Drivers; (iii) Single-Encapsulated Volatile Memory Drivers; (iv) Single-Encapsulated Non-Volatile Memories, etc. Single-level package volatile memory drivers for single-level package logic drivers, multiple single-level package volatile memory drivers, and multiple single-level package volatile memory drivers for stacked logic operations Non-volatile and volatile memory drivers , each logical driver and flash memory driver includes TPVs for packaging purposes, and the process steps for forming the TPVS are as disclosed and described in the paragraphs above for stacking logical drivers, using the method of stacking TPVS (e.g. POP method) as disclosed and described in the paragraph above for stacking logical drives. Single-level packaged non-volatile memory drivers in stacked logic drivers include non-volatile memory IC chips including NAND flash chips and/or NOR flash chips, single-level packaged non-volatile memory drivers in stacked logic drivers The NAND flash chips and/or NOR flash chips in are used as: (a) to store data, information, codes or result values for FPGA chips configured in a single level package logic driver in a stacked logic driver. The NAND and/or NOR chips in the single-level packaged non-volatile memory driver in the stacked logic driver are used to store configuration data (a logic for the FPGA chip in the single-level packaged logic driver in the stacked logic driver circuits) (including result values for LUTs and multiplexers for configuring logic circuits to select result values from corresponding LUTs), and/or storing FPGA chips used in single-level packaging logic drivers in stacked logic drivers (b) store data or information for the operation of the FPGA chip in the single-level package logic driver in the stacked logic driver, note that The point is that the FPGA chip in option (b) has been configured with a specific operation or function. In one embodiment, the stacked logic driver may include a single-level package non-volatile memory driver including a NOR flash chip and a NAND flash chip, wherein the NOR flash chip functions as storage data or data for configuration in the The FPGA chip in the stacked logic driver is single-level packaged, and the NAND flash chip is used to store data or information for operation of the FPGA chip in the single-level packaged logic driver in the stacked logic driver.

Another aspect of the present invention provides systems, hardware, electronic devices, computers, processors, mobile phones, communication equipment, and/or robots, non-volatile (eg, NAND flash chips or NOR flash chips) having logical drivers. ) memory driver, and/or volatile (eg DRAM) memory driver, the logical driver may be a single level package logical driver or a stacked logical driver, as disclosed and described above, the non-volatile flash memory driver may be A single-level packaged non-volatile 147 or stacked non-volatile flash memory driver, as disclosed and described above, and a volatile DRAM memory driver can be a single-level packaged DRAM memory driver or a stacked volatile DRAM memory driver , as disclosed and described above, the logic driver, the non-volatile flash memory driver, and/or the volatile DRAM memory driver are arranged in a flip-chip package on a PCB substrate, a BGA substrate, a flexible circuit board, or a ceramic circuit substrate superior.

Another aspect of the present invention provides a logic and memory driver in a stacked package or device comprising a single level package logic driver and a single level package memory driver, the single level package logic driver as disclosed and described above, and including one or more FPGAs Chip, one or more non-volatile NAND flash memory chips or NOR flash memory chips, a plurality of DPSRAM or DPCSRAM, a dedicated control chip, a dedicated I/O chip, and/or a dedicated control chip and a dedicated I/O chip , the single-level package logic driver may further include one or more processing IC chips and multiple computing IC chips, such as one or more CPU chips, GPU chips, DSP chips and/or TPU chips, and the single-level package memory driver as disclosed above and description, and including one or more high-speed, high-bandwidth cache SRAM chips, one or more DRAM chips, or one or more NVM chips for high-speed parallel processing operations and/or computations, one or more high-speed, high-bandwidth NVMs may include MRAM or PRAM, single-level package logic driver As disclosed and described above, single-level package logic drivers are formed using FOIT technology for high-speed, high-bandwidth communication between multiple memory chips in single-level package memory drives, stacked metal plugs (within TISD) formed directly and vertically on or over micro-copper pillars or bumps, over SISC and over or over FISC of IC chips, metal pillars or bumps on the front side of logic drivers (IC chips have transistor side up) formed directly and vertically on or above the metal plugs of the TISD stack, multiple stack structures within the logic driver, each high-speed bit data, wide bit bandwidth bus ( bus) from top to bottom: (i) metal pillars or bumps on or over the TISD; (II) metal layers forming the stacked metal plug and TISD via the stacked metal plug; (iii) on the SISC and FISC or the micro copper pillars or bumps above, the number of stack structures per IC chip (ie, the data bit bandwidth between each logic IC chip and each high-speed, high-bandwidth memory chip) is equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K for high-speed, high-bandwidth parallel processing operations and/or computations, similarly, multiple stack structures are formed in single-level package memory drivers, single-level package logic drivers Flip chip assembled or packaged in a single-level package memory chip, its plurality of IC chips in a logic driver, its plurality of IC chips with the transistor side facing down, and a plurality of IC chips in a memory driver, its plurality of The side of the IC chip with the transistors faces up, so a micro copper/solder metal post or bump on the FPGA, CPU, GPU, DSP and/or TPU chips can be short-distance connected or coupled to the memory Micro-copper/solder metal pillars or bumps on bulk wafers, such as DRAM, SRAM or NVM, by: (i) in single-level packaging logic drivers (2) stacked metal plugs via stacked metal plugs and metal layers on TISD in single-level package logic drivers; (iii) a plurality of metal pads, studs or bumps on or below a TISD in a single-level package logic driver; (iv) a number of metal pads, studs or bumps on or above a TISD in a single-level package memory driver; ( v) Micro copper pads, studs or bumps on or over the SISC and/or FISCs, TPVs and/or BISDs for single level package logic drives for single level package logic drives and single level package memory drives , the stacked logic and memory drives or devices can be accessed from the upper side of the stacked logic and memory drives or devices (the backside of the single-level packaged logic one side down) and the underside (the backside of the single-level package memory driver, the side of the IC chips with the transistors in the single-level package memory driver is facing up) to communicate, connect, or couple to external Circuitry, alternatively, TPVs and/or BISDs can be omitted for single-level package logic drives, and stacked logic drives and memory drives or devices can be accessed from the back of the stacked logic drives and single-level package memory drives or devices The backside of the layer-packaged memory driver, the plurality of IC chips with transistors in the single-layer-packaged memory driver face up), communicates, connects or couples to a plurality of external circuits through the TPVS and/or BISD of the memory driver, Alternatively, TPVS and/or BISD can be omitted for single-level package memory drives, and stacked logical drives and memory drives or devices can be Backside, IC dies with transistors in the single level package logic driver facing up) communicate, connect or couple to external circuits or components through the BISD and/or TPVS within the single level package logic driver.

In all alternatives to logic drivers and memory drives or devices, a single-level package logic driver may include one or more processing IC chips and multiple computing IC chips and a single-level package memory driver, wherein the single-level package memory driver may Include one or more high-speed, high-bandwidth cache SRAM chips, DRAM or NVM chips (eg, MRAM or RRAM) for high-speed parallel processing and/or computation, for example, a single-level package logic driver may include multiple GPU chips, such as 2, 3, 4, or more than 4 GPU chips, and single-level package memory drives may include multiple high-speed, high-bandwidth cache SRAM chips, DRAM chips, or NVM chips, a TPU chip and a SRAM chip, DRAM chip, or NVM chip. Through the stack structure disclosed and described above, the data bit bandwidth of the communication system can be greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K. For another example, the logic driver can include a plurality of FPGAs Chips, such as 2, 3, 4, or more than 4 FPGA chips, and single-level package memory drivers may include multiple high-speed, high-bandwidth cache SRAM chips, DRAM chips, or NVM chips, a plurality of FPGA chips and a SRAM chip, The communication between DRAM chips or NVM chips is through the stack structure disclosed and described above, and the data bit bandwidth can be greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K.

A communication, connection or coupling system between a plurality of FPGAIC chips, processing and/or computing chips (such as CPU, GPU, DSP, APU, TPU and/or ASIC chips) and a high-speed, high-bandwidth SRAM, DRAM or NVM chip Through the stack structure as disclosed and described above, the communication or connection method is the same as or similar to a plurality of internal circuits in the same chip, or, (i) a plurality of FPGAIC chips, processing and/or computing chips (eg CPU, GPU) , DSP, APU, TPU, and/or ASIC chips), and (ii) a high-speed, high-bandwidth SRAM, DRAM, or NVM chip communicates, connects, or couples through a plurality of stacked structures as disclosed and described above, which Using a small complex I/O driver and/or complex receiver, the drive capability, load, output capacitance or input capacitance of a small complex I/O driver, small complex receiver or complex I/O circuit can be between 0.01pF and 0.01pF. Between 10pF, 0.05pF and 5pF, between 0.01pF and 2pF, or between 0.01pF and 1pF, or less than 10pF, 5pF, 3pF, 2pF, 1pF, 0.5pF or 0.01pF, for example, A bidirectional I/O (or tri-state) pad, I/O circuits can be used in small complex I/O drivers, complex receivers or complex I/O circuits used in logic drivers and memory stack drivers High-speed, high-speed Communication between a bandwidth logic driver and a plurality of memory chips includes an ESD circuit, a receiver and a driver, and has an input capacitance or an output capacitance that can be between 0.01pF and 10pF, 0.05pF and 5pF, between 0.01pF and 5pF. Between 0.01 pF and 2 pF or between 0.01 pF and 1 pF, or less than 10 pF, 5 pF, 3 pF, 2 pF, 1 pF, 0.5 pF or 0.1 pF.

Another aspect of the present invention discloses and provides a Fan-Out Interconnection Technology (FOIT) with TISD and TPVs for manufacturing a single-layer chip package structure, wherein the single-layer chip package structure can be used as A chiplet, the single-layer chip package structure (chiplet) is formed using process steps similar to the above disclosure and description for forming a multi-chip package structure with TISD and TPV, except:

(A) In step (I), the semiconductor IC chip is placed, fixed or attached to a carrier, support, molder or substrate, and can be a product or device of the same type of semiconductor IC chip in a batch process For example, semiconductor chips that use the same batch of wafers or panel processes may belong to only one of the following products or equipment: standard commercial FPGA chips, dedicated control chips, dedicated I/O chips, proprietary control and I/O chips /O chip, CPU chip, GPU chip, DSP chip, APU chip, TPU chip, DRAM memory chip, SRAM memory chip, MRAM memory chip, RRAM memory chip, analog IC chip, hybrid module IC chip or RFIC wafer.

(B) In step (V), the wafer or panel that has been processed is cut and divided to form a single chip package structure unit, wherein the single chip package structure unit only includes a semiconductor IC chip, TISD and TPVs.

There are matrix-type metal pads, bumps or metal posts at the bottom of the single chip package structure and under the TISD (the side of the front side of the semiconductor IC chip with transistors) of the single chip package structure, in which the semiconductor IC chips are connected or coupled. The metal pads, bumps or metal pillars can be positioned vertically below the semiconductor IC chip, and the upper surface of the TPVs of the single chip package structure can be used as a package-on-package assembly (POP assembly) for bonding the package structure to the package structure. metal pads, wherein the metal pads are located in the peripheral area on the front side of the single chip package structure (the side of the front side of the semiconductor IC chip with transistors), in one embodiment, the single chip package structure (or chiplet ) with a matrix type of solder bumps (with a height between 20µm and 100µm) or copper metal pillars with a solder layer (with a height between 20µm and 100µm) on the bottom side, in which the semiconductor IC chip is connected or coupled The solder bumps or copper metal pillars with the solder layer can be positioned vertically below the semiconductor IC chip, and the single chip package structure (or chiplet) has a matrix type of metal pads on the front side. Alternatively, the metal pads (having a thickness between 1 µm and 10 µm) of the matrix type can be formed on the front side of the single chip package structure, wherein the metal pads of the matrix type can be located on top of the TPVs and are vertically positioned Above the semiconductor IC chip, wherein the metal pads located vertically above the semiconductor IC chip include dummy metal pads, meaning not connected or coupled to the semiconductor IC chip.

The disclosed single chip package structure (or chiplet) can be used in a multi-chip package or a heterogeneous package structure (heterogeneous integration). between TISDs), copper metal pillars (with a height between 20µm and 100µm) with a solder layer on the perimeter area under the TISD, and metal pads on the perimeter area (including the exposed upper surface of the TPVs) Size, layout or location can have a standard. Alternatively, a single chip package structure (or chiplet) with solder bumps (with a height between 20µm and 100µm), copper metal pillars under the TISD and with a solder layer on the perimeter area (with a height of 20µm) between 100µm) and the size of the metal pads (with a thickness between 1µm and 10µm) in a matrix type vertically above a single chip package structure (or chiplet) with some dummy metal pads, Layout or location can have a standard.

Another aspect of the present invention discloses to provide a Fan-Out Interconnection Technology (FOIT) with TSID, BISD and TPVs for manufacturing a single chip package structure (or chiplet), wherein the single chip package structure can be Acting as a chiplet, the single chip package structure (or chiplet) is formed using process steps similar to those used to form the multi-chip package structure with TISD, BISD, and TPV in the above disclosure and description, except:

(A) In step (I), the semiconductor IC chip is placed, fixed or attached to a carrier, support, molder or substrate, and can be a product or device of the same type of semiconductor IC chip in a batch process For example, semiconductor chips that use the same batch of wafers or panel processes may belong to only one of the following products or equipment: standard commercial FPGA chips, dedicated control chips, dedicated I/O chips, proprietary control and I/O chips /O chip, CPU chip, GPU chip, DSP chip, APU chip, TPU chip, DRAM memory chip, SRAM memory chip, MRAM memory chip, RRAM memory chip, analog IC chip, hybrid module IC chip or RFIC wafer.

(B) In step (V), the wafer or panel that has been processed is cut and divided to form a single chip package structure unit, wherein the single chip package structure unit only includes a semiconductor IC chip, TISD, BISD and TPVs.

The single chip package structure has a matrix type of metal pads, bumps and pillars at the bottom and below the TISD (the side of the front side of the semiconductor IC chip with transistors), and has a matrix type of metal pads, bumps and The pillars are located at the bottom and above the BISD (the side of the backside of the semiconductor IC chip with transistors), and the positions of the matrix-type metal pads, bumps and pillars located below the TISD can be located vertically on the semiconductor IC chip. The metal pads, bumps and studs below and above the BISD can be positioned vertically above the semiconductor IC chip, and the metal pads, bumps and studs positioned above the BISD and above the semiconductor IC chip can be coupled To the semiconductor IC chip, the metal pads, bumps, and pillars above the BISD and above the semiconductor IC chip can be coupled to the transistors on the front side of the semiconductor IC chip via TPVs, and the metal pads, bumps, and pillars below the TIDS The bumps and studs can be coupled via TPVs to metal pads, bumps, and studs above the BISD, in one embodiment, a matrix of solder bumps (their height) on the single chip package structure (or chiplet) between 20µm and 100µm) or copper pillars with a solder layer (with a height of between 20µm and 100µm) located under the TISD, where the solder bumps or copper with a solder layer are connected or coupled to the semiconductor IC die The pillars can be positioned vertically below the semiconductor IC chip, and the metal pads of a matrix type of single chip package structure (or chiplet) are positioned above the BISD, wherein the metal pads coupled to the semiconductor IC chip via TPVs can be positioned vertically above the semiconductor IC chip. Above the IC die, the metal pads above the BISD can be coupled via TPVs to solder bumps or copper pillars with a solder layer below the TISD.

The disclosed single chip package structure (or chiplet) can be used in a multi-chip package or a heterogeneous package structure (heterogeneous integration). between), copper metal pillars (with a height between 20µm and 100µm) under the TISD and with a solder layer on the perimeter area, and metal pads (with a thickness between 1µm and 10µm) over the BISD .

Another aspect of the present invention discloses and provides a chip package structure for use as a non-volatile programmable device (a non-volatile programmable stacked logic driver), comprising: (a) a first chiplet (or a single chip package structure) ) includes an FPGAIC chip, and (b) a second chiplet (or single chip package structure) includes a non-volatile memory chip, wherein the first and second chiplets are formed in the manner disclosed above, the first chiplet The two chiplets can be stacked and packaged on (or over) the first chiplet using a POP packaging method in the same manner as disclosed above. Alternatively, the first chiplet can be stacked and packaged on (or over) the second chiplet using the POP packaging method, and the first and second chiplets can be one of the above-disclosed chiplets (or single-chip package structures): (a1) Chiplets (or single chip package structures) with TISDs and TPVs, with solder bumps or with solder copper pillars located below the TISDs and metal pads in the peripheral area above the TPVs; (a2 ) chiplets (or single chip package structures) with TISDs and TPVs, with solder bumps or with solder copper pillars below the TISD, metal pads above the TPVs and on the backside of the die (including dummy metal pads); (b) chiplets (or single chip package structures) with TISD, BISD and TPVs with solder bumps or solder copper pillars below the TISD and metal pads above the BISD. In one case, the second chiplet is positioned on (or over) the first chiplet, and the second chiplet with solder bumps or with solder copper pillars is packaged and bonded to the metal pads of the first chiplet. In another case, the first chiplet is positioned on (or over) the second chiplet, and the first chiplet with solder bumps or with solder copper pillars is packaged and bonded to the metal pads of the second chiplet. The contents of the solder bumps under the TISD or with the solder copper pillars and the metal pads over the BISD and TPVs are as disclosed above.

The non-volatile memory IC chip in the second chiplet of the chip package structure (POP package structure) includes a NAND flash chip or a NOR flash chip, and the NAND flash chip or NOR flash chip in the second chiplet The flash chip is used as: (a) to store data or data for the FPGAIC chip arranged in the first chiplet of the chip package structure, and the NAND flash chip or NOR flash chip in the second chiplet is used for Store the resulting values of the LUTs and configuration data for the multiplexer (associated with the LUTs of the FPGA chip in the first chiplet in the chip package structure), and/or store the first chiplet in the chip package structure (b) storing data for the operation of the FPGA chip in the first chiplet in the chip package structure or information, wherein the FPGAIC chip has been configured in (b) with a specific operation or function.

In one embodiment, the stacked logic driver may include a chiplet (including a NOR flash chip), a chiplet (including a NAND flash chip), and a chiplet (including an FPGAIC chip), where the NOR flash The flash chiplet is positioned above the FPGA chiplet, and the NAND flash chiplet is positioned above the NOR flash chiplet, which is used to store data or data for configuring the FPGAIC of the stacked logic driver The data or information of the chip, and the NAND flash chip is used to store the data or information of the operation of the FPGAIC chip of the stacked logic driver.

Another aspect of the present invention discloses and provides a non-volatile programmable logic driver (non-volatile programmable stacked logic driver) that needs to be constructed according to the logic driver disclosed and described above, in a stacked multi-chip package structure (according to the above disclosure A non-volatile programmable stacked logic driver constructed in a FOIT package structure with TISD, TPVs and/or BISD) includes a standard commercial FPGA IC chip (chiplet type disclosed above) and a non-volatile memory IC chip ( The chiplet type disclosed above), wherein the non-volatile memory IC chip includes a NAND flash chip or a NOR flash chip. Alternatively, the non-volatile memory IC chip can be a bare die type or a traditional package structure, wherein the traditional package structure can be a BGA package structure (wire bonding method or flip chip bonding method), a thin small outline package with lead frame structure (thin small outline package with lead frame) , TSOP) or chip-scale package (chip-scale package, CSP), the non-volatile memory chip or package structure is stacked on top of the FPGA chiplet. Alternatively, a non-volatile memory die or package structure is stacked under the FPGA die, and the non-volatile memory die in the non-volatile programmable logic driver is used to store data, to configure the FPGA die and/or to be used in Operation of an FPGA die in a non-volatile programmable logic driver.

Non-volatile Programmable Logic Drivers (Non-volatile Programmable Stacked Logic Drivers) may include dedicated I/O chips or chiplets of dedicated control and I/O chips stacked on top of FPGA chiplets and non-volatile memory IC chiplets. Together, where the dedicated I/O chip or the dedicated control and I/O chip is as disclosed above, the dedicated I/O chip or the dedicated control and I/O chip's chiplets are passed through and formed with the FPGA chiplet or non-volatile memory In the same way as chiplets, non-volatile programmable logic drivers are formed by stacking POPs, for example, from bottom to top: (i) FPGA chiplets; (ii) dedicated I/O chips or dedicated control and I/O chips. A chiplet of the O chip, (iii) a non-volatile memory chiplet. The communication or electrical coupling between the dedicated I/O chip or the dedicated control and I/O chip, the FPGA chip and the non-volatile memory chip in the non-volatile programmable logic driver is as disclosed above, The communication or electrical coupling between the non-volatile programmable logic driver and the external power is as disclosed above. In the logic driver disclosed above, the dedicated I/O chip or the dedicated control and I/O chip includes a large I/O circuit for communicating or electrically coupling with the external circuit of the non-volatile programmable logic driver, and is dedicated to the The I/O chip or the small I/O circuit of the dedicated control and I/O chip communicates or electrically couples with the FPGA IC chip with the small I/O circuit and the non-volatile memory IC chip for use in the logic driver. The contents of the large I/O circuit and the small I/O circuit are as disclosed above.

Non-volatile programmable logic drivers (non-volatile programmable stacked logic drivers) may include an HBM memory chiplet (eg including an HBMDRAM, SRAM, MRAM or RRMIC chip), FPGA chiplets, and nonvolatile memory IC chiplets. Chips are stacked together, wherein the HBM memory chiplet has a dedicated I/O chip or a dedicated control and I/O chip, the HBM memory chiplet (e.g. including an HBMDRAM, SRAM, MRAM or RRMIC chip) as described above It is disclosed that the method of forming a HBM memory chiplet (eg including a HBMDRAM, SRAM, MRAM or RRMIC chip) is the same as the above-mentioned method of forming an FPGA chiplet or a non-volatile IC memory chiplet. The non-volatile programmable logic drive device It is formed by POP stacking, for example, from bottom to top: (i) FPGA chiplets; (ii) HBM memory chiplets; (iii) dedicated I/O chips or dedicated control and I/O chips. chiplets; (iv) non-volatile memory chiplets. Disclosure of communication or electrical coupling between dedicated I/O chips or dedicated control and I/O chips, HBM memory chips, FPGA chips and non-volatile memory chips in a non-volatile programmable logic drive device The description is the same as the disclosure description of the above-mentioned logical drive. The disclosure of the communication or electrical coupling between the non-volatile programmable logic driver and the external circuit is the same as the disclosure of the above-mentioned logic driver. In the above disclosure of the logic driver, the dedicated I/O chip or the dedicated control and I/O chip includes a large I/O circuit for communicating or electrically coupling with the external circuit of the non-volatile programmable logic drive device , and the dedicated I/O chip or the small I/O circuit of the dedicated control and I/O chip communicates or electrically couples with the FPGAIC chip, HBM memory chip and non-volatile memory IC chip with small I/O circuit Then, the contents of the large I/O circuit and the small I/O circuit used in the logic driver are as disclosed above.

The FPGAIC chip in the non-volatile programmable logic driver (Non-volatile programmable stacked logic driver) may include an on-chip security circuit for security design, the on-chip security circuit is used for protection The data will not be intentionally copied or reverse engineered to obtain the data. On-chip bitstream decryption is provided by the on-chip security circuit of the FPGAIC chip in the non-volatile programmable logic drive device. The decryption of the metastream is performed according to a decryption key stored in the dedicated memory unit on the FPGAIC chip, and the encrypted bitstream is stored in the nonvolatile memory chip of the nonvolatile programmable logic driver and is Used as an FPGAIC chip configured in a non-volatile programmable logic driver, encrypted bitstreams from the non-volatile memory chip are input into the FPGAIC chip for programmable interconnect lines in the FPGAIC chip (switches include pass/fail switches, gates and multiplexers) and/or programmable logic circuits, cells or elements or blocks (including LUTs and multiplexers), where the incoming encrypted bit stream can be stored via on-chip security circuitry according to A decryption key in the dedicated memory unit performs decryption. A user-generated key can be created from a truly random source. The FPGAIC chip in the non-volatile programmable logic drive device internally stores the decryption key's non-volatile memory on the FPGAIC chip Among the bulk cells, the on-chip non-volatile memory cells may include a floating gate MOS transistor, MRAM or RRAM. Alternatively, the FPGAIC chip in the non-volatile programmable logic drive device stores the decryption key internally in a dedicated RAM unit of the FPGAIC chip, where the dedicated RAM unit can be backed up via a small externally connected battery. Alternatively, an electronic fuse or anti-fuse (e-fuseorananti-fuse) on the FPGAIC chip can be used as the decryption key, the e-fuse or anti-fuse programmed to store the decryption key non-volatile, the e-fuse comprising a plurality of fuses, Each fuse has a narrow neck in the metal connection line in the interconnection metal line of the FISC or SISC of the FPGAIC chip disclosed above. In programming for non-volatile storage, the selected fuse is cut and damaged by a high current flowing through the fuse. The anti-fuse includes a plurality of fuses, each fuse having a thin oxide window at two electrode terminals In between, in the programming of non-volatile storage, the selected fuse is connected, wherein the oxide in the oxidation window is destroyed by applying a high voltage between the two terminals. The encryption key can only be programmed into the device via a special port, the on-chip security circuit performs operations for decryption of the incoming bitstream during configuration, the non-volatile programmable logic device has encryption logic (depending on the chip) Built on secure circuits), using 128, 256, 512 or 1024 bit encryption keys.

Users or developers with innovative or applied concepts or ideas can purchase non-volatile programmable logic drive devices, which can develop or write software codes, data or programs to load into the non-volatile programmable logic drive devices. In the non-volatile memory, the software code, data, information of the user loaded or stored in the non-volatile memory IC chip of the non-volatile programmable logic drive device for realizing his/her innovative or application concept or idea , instructions or programs (relating to innovation or application concepts) can be downloaded via TISDs and TPVs (and in some cases BISDs as well) for programmable interaction on standard commercial FPGAIC chips in non-volatile programmable logic drivers Links (switches include pass/no pass switch gates and multiplexers associated with programmable interconnects) and/or programmable logic circuits, cells or elements or blocks (including LUTs and associated programmable logic circuits, unit or element or block associated multiplexer).

Chip packages for non-volatile programmable logic driver devices can include non-volatile memory IC chips and FPGA IC chips, which provide an alternative to existing ASICIC chip design, manufacturing, and the market, logic drivers (non-volatile programmable logic chips). A driver device) chip package with: (i) user software code, data, information, instructions or programs (relating to innovative or application concepts) loaded or stored in a non-volatile memory IC chip; and (ii) An on-chip encryption/decryption function (based on on-chip security circuitry) with an FPGAIC chip can be sold and used as an ASICIC chip.

Another aspect of the present invention provides a programmable, configurable and reconfigurable semiconductor IC chip constructed according to a Coarse-Grained Reconfigurable Architecture (CGRA) for non-volatile programmable logic drivers constructed according to the above disclosure In programmed logic drivers (non-volatile programmable 2D horizontal or 3D stacked logic drivers), CGRA semiconductor IC chips are programmable, configurable and reconfigurable via: (i) programming software or source code, which Comprising operating instructions in an instruction set stored in an on-chip instruction memory unit, wherein the operating instructions in the instruction set are written in assembled language or in machine language or source code, the on-chip instruction memory unit may be an on-chip instruction memory unit. Volatile memory cells (eg, SRAM cells) or on-chip non-volatile memory cells (eg, floating gate non-volatile memory cells, RRAM cells, MRAM cells, FRAM cells); or (ii) as described in this patent application The disclosure of the FPGAIC chip in this case is the same, using either volatile memory cells (eg, SRAM cells) stored on-chip or non-volatile memory cells (eg, floating gate non-volatile memory cells, RRAM cells, MRAM cells) stored on the chip. unit, FRAM unit) configuration information.

A CGRAIC chip includes a massive matrix of functional unit areas, cells or elements (FUBs), each FUBs includes (i) a functional unit (FU), the FU is designed, compiled and implemented with fixed hardwires (metal wire or connecting wire) circuit in which the FU is programmed, configured or reconfigured using programming software or source code, which includes operational instructions in an instruction set stored in an on-chip instruction memory unit, operational instructions in an instruction set Can be written in assembly language (such as MOV, ADD or SUB), which can then be converted to machine language or code in binary numbers (1 or 0) using an assembler, which is represented by binary numbers (1 or 0) The machine language or source code of the machine language or code is stored in on-chip instruction memory cells, which may be on-chip volatile memory cells (eg, SRAM cells) or on-chip non-volatile memory cells. Cells (eg floating gate non-volatile memory cells, RRAM cells, MRAM cells, FRAM cells), FUs are programmed, configured or reconfigured for different functions or applications respectively attached to the chip stored in the instruction memory cell On different instruction sets in volatile or non-volatile memory cells, the FU is programmed, configured or reconfigured using a first specific set of instructions stored in the on-chip volatile or non-volatile memory cells of the instruction memory cells For a first specific function or application, the FU is programmed, configured or reconfigured to execute when a second specific set of instructions is loaded and stored in the on-chip volatile or non-volatile memory cells of the instruction memory cells a second specific function or application. The FU hardware or circuit can be one (or more) hard cores (hardmacros) in the above-mentioned FPGAIC chip, and these hard cores include, for example, DSP slices, GPU slices, microcontroller cores (MCU), multiplexers hard, adder hard, multiplier hard, arithmetic logic unit (ALU) hard, shift circuit hard, compare circuit hard, floating point computation hard, register or flip-flop hard and/or I/ O-interface hard cores, where each hard core is designed, programmed and implemented with fixed wiring for the circuit; (ii) a register or flip-flop for temporary storage of the computational or processing output of the FU Or as a result, the data stored in the registers may be allocated or accessed only to some (but not all) FUBs in the FUB array within a certain clock cycle using control circuits with artificial intelligence; (iii) the register file , used to temporarily store, update, recycle or cyclically calculate or process the output data or results of FU to be used as input data for FU input points, and register files can also be used to store, update and pre-prepare the data required for calculation or processing of FU Or as a result, it is used as the input data at the FU input point, so that the data possessed by the FU can be nearby and timely to execute the calculation and processing instructions, so the speed and performance of the FU can be greatly improved: (iv) The instruction memory segment includes a plurality of volatilized (eg SRAM) or non-volatile memory unit for storing programming software or source code (including operating instructions for FU), the instruction memory segment in the same FUB includes FU, which means that the instruction memory unit is Allocated in each FUB of the FUB matrix for programming, configuring or reconfiguring the FU, wherein the instruction memory unit is used to store the machine language or source code in binary bits (0 or 1) in the FU, the instruction memory The cells can be on-chip volatile (eg SRAM) or on-chip non-volatile memory cells, such as floating gate non-volatile memory cells, RRAM cells, MRAM cells, FRAM cells; (v) a program counter (PC )) is used as an instruction address or an address pointer, wherein the program counter contains the address (location) of the instruction in the instruction memory segment, the program counter is used to control the memory in the instruction memory segment The execution order of the instructions stored in the cell, the program counter increments its stored value by one as each instruction is fetched. After each instruction is fetched, the program counter points to the next instruction in the sequence.

Each FUB in the FUB matrix is interconnected or non-interconnected using a mesh type network, which includes configurable and reconfigurable interconnect circuits. As disclosed in the above-mentioned FPGAIC chip, the FUs can perform common Word-level operations, including addition, subtraction, and multiplication. Compared to FPGAs, CGRAs have shorter reconfiguration times, low latency, and low power consumption because CGRAs are constructed from standard cells. Thus, gate-level reconfigurability is sacrificed, but the result is a substantial increase in hardware efficiency.

CGRAIC chips include configurable and reconfigurable interconnect circuits, volatile (eg, SRAMs) or non-volatile memory cells for storing data therein as configuration or reconfiguration, configurable and reconfigurable Configured interconnect circuitry, interconnects (connected or unconnected) between each FUBs in the FUB matrix can be configured or reconfigured via data stored in volatile or non-volatile memory cells, when The FUs in the FUB matrix of the CGRAIC chip are configured or reconfigured for a specific function or application, and the configurable and reconfigurable interconnect circuits can be stored in volatile or non-volatile memory cells by changing the corresponding configuration or reconfigure the interconnection data while simultaneously configuring or reconfiguring, when the FUs in the FUB matrix of the CGRAIC chip are configured or reconfigured for a first specific function or application, the corresponding interconnection circuit is configured or reconfigured Can be configured or reconfigured using a first specific configuration or reconfiguration interconnect data stored in volatile or non-volatile memory cells on the chip; the CGRAIC chip is configured or reconfigured to perform the first specific function or application, when the FUs in the FUB matrix of the CGRAIC chip are configured or reconfigured for a second specific function or application, the second specific configuration or reconfiguration interconnection data is downloaded and stored on the chip volatile or non-volatile The CGRAIC chip is configured or reconfigured to perform a second specific function or application, for a corresponding configurable or reconfigurable interconnect circuit.

Like the FPGAIC chip, the CGRAIC chip includes a programmable, configurable and reconfigurable interconnect circuit and a first volatile memory cell (for storing the first data therein), wherein the first data is used for configuration Programmable, configurable and reconfigurable interconnect circuit, wherein the programmable, configurable and reconfigurable interconnect circuit includes first and second conductive interconnects and a programmable, configurable and reconfigurable switch circuit (with a second input point coupled to the first conductive interconnection line, a first output point coupled to the second conductive interconnection line and a second input point for inputting data associated with the first data), The programmable, configurable and reconfigurable switching circuit located between the first and second conductive interconnecting lines is programmed, configured or reconfigured according to the input data of the second input point, programmable, configurable and reconfigurable The configuration interconnect circuit is programmed, configured or reconfigured to a first specific function using a first specific data stored in the on-chip volatile or non-volatile unit of the instruction memory unit for a first specific function, when a second specific instruction set is Downloaded and stored in the on-chip volatile or non-volatile unit of the instruction memory unit, the FU is programmed, configured and reconfigured to perform a second specific function.

The same as the FPGAIC chip, the CGRAIC chip further includes a second volatile memory unit for storing the second data therein, wherein the programmable, configurable and reconfigurable interconnection circuit further includes programmable, configurable and reconfigurable The configuration selection circuit is coupled to the programmable, configurable and reconfigurable switching circuit via conductive interconnects, wherein the programmable, configurable and reconfigurable selection circuit includes third and fourth conductive interconnects, a third input The point is coupled to the third conductive interconnection line, a fourth input point is coupled to the fourth conductive interconnection line, a second output point is coupled to the first conductive interconnection line, and a fifth input point is used for input and The data associated with the second data, wherein the programmable, configurable and reconfigurable selection circuit can be programmed, configured or reconfigured according to the data input from the fifth input point to select the third and fourth conductive interconnection lines for coupling second output point.

All disclosures and/or descriptions about FPGAIC chips in this patent application can be applied to CGRAIC chips.

All 2D horizontal and/or 3D stacked chip packages or logic drivers or multi-chip package structures include the FPGAIC chips disclosed in this patent application (all disclosures and/or descriptions of FPGAIC chips in this patent application may be Applications in CGRAIC chips) include the use of non-volatile memory IC chips in the same chip package structure or in a multi-chip package structure to store programming, configuration or reconfiguration data for programming, configuring or reconfiguring FPGA IC chips, including Non-volatile memory IC chips in the same chip package structure or multi-chip package structure with CGRAIC chips for storage and backup: (i) programming software or source code, which includes for each of the FUB matrix on the CGRAIC chip Operational instructions for the FU, stored in the on-chip volatile memory cells (eg SRAMs) in the instruction memory segment of each FUB for the FUB matrix on the CGRAIC chip, and (ii) to program, configure or reconfigure the interconnects Wire data is used to program, configure or reconfigure the programmable, configurable and reconfigurable interconnect wire circuits of the CGRAIC chip, the non-volatile memory IC chip can be a NAND flash memory chip or a NOR flash memory chip, The non-volatile memory IC chip can be used to store complex sets of instructions for multiple functions or applications of the CGRAIC chip, when a second specific instruction set is downloaded and stored in the on-chip volatile memory of the instruction memory unit In the unit, the FU is programmed, configured or reconfigured to perform a second specific function or application. The first and second specific instruction sets stored in the volatile memory unit of the CGRAIC chip can be obtained from the same chip package structure or a multi-chip package. In the structure (including CGRAIC chip) those non-volatile memory cells that store or back up the non-volatile memory IC chip, the user can select the first or second specific instruction set (stored in the non-volatile memory in the non-volatile memory cells of the IC chip and downloaded into the volatile memory cells of the CGRAIC chip) to program, configure or reconfigure the CGRAIC chip for performing a first or second specific function or application.

The disclosure on the other hand provides a standard business logic driver, and a person, user, or software developer, or algorithm/architecture/application developer can buy the standard business logic driver and decipher the software code to edit the logic driver to execute His/her desired algorithm, architecture and/or application, for example, an artificial intelligence, machine learning, deep learning, big data, Internet of Things, virtual reality, electric vehicles, image processing, digital signal processing, for Algorithms, architectures and/or applications of controllers, and/or central processing.

These and other components, steps, features, benefits and advantages of the present invention will become apparent from a review of the following detailed description of the illustrative embodiments, the accompanying drawings, and the scope of the claims.

The configuration of the present invention can be more fully understood when the following description is read in conjunction with the accompanying drawings, which are to be regarded in an illustrative rather than a restrictive nature. The drawings are not necessarily to scale, emphasizing the principles of the invention.

Description of Static Random-Access Memory (SRAM) Units

(1) The first type of SRAM cell (6TSRAM cell)

FIG. 1A is a circuit diagram of a 6TSRAM cell according to an embodiment of the present application. Referring to FIG. 1A, the first type SRAM cell 398 (ie, the 6TSRAM cell) has a memory cell 446 including four data latch transistors 447 and 448, that is, two pairs of P-type metal oxides A metal-oxide-semiconductor (MOS) transistor 447 and an N-type MOS transistor 448, in each pair of the P-type MOS transistor 447 and the N-type MOS transistor 448, have their drains coupled to each other , whose gates are coupled to each other, and their sources are respectively coupled to the power supply terminal (Vcc) and the ground terminal (Vss). The gate of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the left is coupled to the drain of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right , as the output Out1 of the memory unit 446 . The gates of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 located on the right are coupled to the drains of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 located on the left side , as the output Out2 of the memory unit 446 .

Referring to FIG. 1A, the first type SRAM cell 398 further includes two switches or transfer (write) transistors 449, such as P-type MOS transistors or N-type MOS transistors, wherein the gate of the first switch 449 is coupled to word line 451, one end of its channel is coupled to bit line 452, and the other end of its channel is coupled to the pair of P-type MOS transistors 447 and N-type MOS transistors on the left side The drain of 448 and the gate of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right side, and the gate of the second switch 449 is coupled to the word line 451, and the channel of the second switch 449 is coupled to the word line 451. One end is coupled to the bit line 453, and the other end of its channel is coupled to the drains of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 on the right and the pair on the left Gates of the P-type MOS transistor 447 and the N-type MOS transistor 448 . The logic value on bit line 452 is opposite to the logic value on bit line 453 . The switch 449 can be referred to as a programming transistor for writing programming codes or data in the storage nodes of the four data latch transistors 447 and 448, that is, in the four data latch transistors 447 and 448. 448 in the drain and gate. The switch 449 can be controlled by the word line 451 to open the connection, so that the bit line 452 is connected to the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the left side through the channel of the first switch 449. The drain and gate of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right, so the logic value on bit line 452 can be loaded into the P-type of the pair on the right On the wire between the gates of the MOS transistor 447 and the N-type MOS transistor 448 and on the wire between the drains of the pair of the P-type MOS transistor 447 and the N-type MOS transistor 448 on the left side. Furthermore, the bit line 453 can be connected to the drains of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 on the right side and the P of the pair on the left side through the channel of the second switch 449 . gates of type MOS transistor 447 and N type MOS transistor 448, so the logic value on bit line 453 can be loaded into the pair of P type MOS transistor 447 and N type MOS transistor 448 on the left side On the wire between the gates of 1 and the wire between the drains of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right side. Therefore, the logic value on bit line 452 can be recorded or latched on the wire between the gates of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right and between the gates of the pair on the left On the wire between the drains of the P-type MOS transistor 447 and the N-type MOS transistor 448 of the pair; the logic value on the bit line 453 can be recorded or latched in the P-type MOS of the pair on the left side On the wire between the gates of the transistor 447 and the N-type MOS transistor 448 and on the wire between the drains of the pair of the P-type MOS transistor 447 and the N-type MOS transistor 448 on the right side.

(2) The second type of SRAM cell (5TSRAM cell)

FIG. 1B is a circuit diagram of a 5TSRAM cell according to an embodiment of the present application. Referring to FIG. 1B, the second type SRAM cell 398 (ie, the 5TSRAM cell) has the memory cell 446 as shown in FIG. 1A. The second-type SRAM cell 398 also includes a switch or transfer (write) transistor 449, such as a P-type MOS transistor or an N-type MOS transistor, the gate of which is coupled to the word line 451, and the channel of which is coupled to the word line 451. One end is coupled to the bit line 452, and the other end of its channel is coupled to the drains of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 on the left and the pair on the right The gates of the P-type MOS transistor 447 and the N-type MOS transistor 448. The switch 449 can be referred to as a programming transistor for writing programming codes or data in the storage nodes of the four data latch transistors 447 and 448, that is, in the four data latch transistors 447 and 448. 448 in the drain and gate. The switch 449 can be controlled by the word line 451 to open the connection, so that the bit line 452 is connected through the channel of the switch 449 to the drain of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the left side and The gates of the pair of P-type MOS transistors 447 and N-type MOS transistors 448 on the right side, so the logic value on bit line 452 can be loaded into the pair of P-type MOS transistors on the right side 447 and the wire between the gates of the N-type MOS transistor 448 and on the wire between the drains of the pair of the P-type MOS transistor 447 and the N-type MOS transistor 448 on the left. Therefore, the logic value on bit line 452 can be recorded or latched on the wire between the gates of the pair of P-type MOS transistor 447 and N-type MOS transistor 448 on the right and between the gates of the pair on the left On the line between the drains of the P-type MOS transistor 447 and the N-type MOS transistor 448 of the pair; in contrast, the logic value on the bit line 452 can be recorded or latched on the P of the pair on the left On the wire between the gates of the P-type MOS transistor 447 and the N-type MOS transistor 448 and on the wire between the drains of the P-type MOS transistor 447 and the N-type MOS transistor 448 on the right side.

Description of the pass/fail switch

(1) Type 1 pass/fail switch

FIG. 2A is a circuit diagram of a first type pass/no pass switch according to an embodiment of the present application. Referring to FIG. 2A, the first-type pass/fail switch 258 includes an N-type MOS transistor 222 and a P-type MOS transistor 223 arranged in parallel with each other. One end of the channel of each of the N-type MOS transistor 222 and the P-type MOS transistor 223 of the first type pass/fail switch 258 is coupled to the node N21, and the other end is coupled to the node N22. Therefore, the first type pass/fail switch 258 can turn on or off the connection between the node N21 and the node N22. The gate of the P-type MOS transistor 223 of the first-type pass/stop switch 258 is coupled to the node SC-1, and the gate of the N-type MOS transistor 222 of the first-type pass/stop switch 258 is coupled to the node SC-1 SC-2.

(2) Type 2 pass/fail switch

FIG. 2B is a circuit diagram of a second-type pass/no pass switch according to an embodiment of the present application. Please refer to FIG. 2B, the second type pass/stop switch 258 includes an N-type MOS transistor 222 and a P-type MOS transistor 223, which is the same as the N-type of the first type pass/stop switch 258 shown in FIG. 2A MOS transistor 222 and P-type MOS transistor 223 . The second-type pass/fail switch 258 includes an inverter 533, the input of which is coupled to the gate of the N-type MOS transistor 222 and the node SC-3, and the output of which is coupled to the gate of the P-type MOS transistor 223, Inverter 533 is adapted to invert its input to form its output.

(3) Type 3 pass/fail switch

FIG. 2C is a circuit diagram of a third type of pass/no pass switch according to an embodiment of the present application. Referring to FIG. 2C, the third-type pass/fail switch 258 may be a multi-stage tri-state buffer 292 or a switch buffer, and each stage has a pair of P-type MOS transistors 293 and N-type MOS transistors In the crystal 294, the drains of the two are coupled to each other, and the sources of the two are connected to the power supply terminal Vcc and the ground terminal Vss, respectively. In this embodiment, the multi-stage tri-state buffer 292 is a two-stage tri-state buffer 292 , that is, a two-stage inverter, which are the first stage and the second stage respectively, and have a pair of P-type MOSs respectively. Transistor 293 and N-type MOS transistor 294 . The node N21 can be coupled to the gates of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the first stage, and the drains of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the first stage. The first stage is coupled to the gate stage of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the second stage, and the drain stage of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the second stage is coupled connected to node N22.

Referring to FIG. 2C, the multi-level tri-state buffer 292 further includes a switching mechanism to enable or disable the multi-level tri-state buffer 292, wherein the switching mechanism includes: (1) a P-type MOS transistor 295 whose source is The pole is coupled to the power supply terminal (Vcc), and its drain is coupled to the source of the P-type MOS transistor 293 of the first stage and the second stage; (2) the N-type MOS transistor 296, its source is coupled to the ground terminal (Vss), and its drain is coupled to the sources of the N-type MOS transistors 294 of the first and second stages; and (3) an inverter 297, the input of which is coupled to N The gate of the P-type MOS transistor 296 and the node SC-4, its output is coupled to the gate of the P-type MOS transistor 295, and the inverter 297 is adapted to invert its input to form its output.

For example, referring to FIG. 2C, when the logic value "1" is coupled to the node SC-4, the multi-level tri-state buffer 292 is turned on, and the signal can be transmitted from the node N21 to the node N22. When the logic value "0" is coupled to the node SC-4, the multi-level tri-state buffer 292 is turned off, and no signal is transmitted between the node N21 and the node N22.

(4) Type 4 pass/fail switch

FIG. 2D is a circuit diagram of a fourth type of pass/no pass switch according to an embodiment of the present application. Referring to FIG. 2D, the fourth type pass/fail switch 258 may be a multi-level tri-state buffer or a switching buffer, which is similar to the multi-level tri-state buffer 292 shown in FIG. 2C. For elements indicated by the same reference numerals shown in FIG. 2C and FIG. 2D, the element shown in FIG. 2D may refer to the description of the element in FIG. 2C. The difference between the circuits shown in Fig. 2C and Fig. 2D is as follows: Please refer to Fig. 2D, the drain of the P-type MOS transistor 295 is coupled to the second-stage P-type MOS transistor The source of 293 is not coupled to the source of the first-stage P-type MOS transistor 293; the source of the first-stage P-type MOS transistor 293 is coupled to the power supply terminal (Vcc) and the P-type The source of the MOS transistor 295. The drain of the N-type MOS transistor 296 is coupled to the source of the N-type MOS transistor 294 of the second stage, but is not coupled to the source of the N-type MOS transistor 294 of the first stage; the first stage The source of the N-type MOS transistor 294 is coupled to the ground terminal (Vss) and the source of the N-type MOS transistor 296 .

(5) Type 5 pass/fail switch

FIG. 2E is a circuit diagram of a fifth type of pass/no pass switch according to an embodiment of the present application. For elements indicated by the same reference numerals shown in FIGS. 2C and 2E, the description of the element shown in FIG. 2E may be referred to in FIG. 2C. Referring to FIG. 2E, the fifth-type pass/fail switch 258 may include a pair of multi-level tri-state buffers 292 as shown in FIG. 2C or switch buffers. The gates of the P-type and N-type MOS transistors 293 and 294 in the first stage of the multi-stage tri-state buffer 292 on the left are coupled to the gates of the second stage in the multi-stage tri-state buffer 292 on the right. The drains of the P-type and N-type MOS transistors 293 and 294 are coupled to the node N21. The gates of the P-type and N-type MOS transistors 293 and 294 in the first stage of the multi-stage tri-state buffer 292 on the right are coupled to the gates of the second stage in the multi-stage tri-state buffer 292 on the left. The drains of the P-type and N-type MOS transistors 293 and 294 are coupled to the node N22. For the multi-stage tri-state buffer 292 on the left, the input of the inverter 297 is coupled to the gate of the N-type MOS transistor 296 and the node SC-4, and the output of the inverter 297 is coupled to the P-type The gate stage of MOS transistor 295, whose inverter 297 is adapted to invert its input to form its output. For the multi-stage tri-state buffer 292 on the right, the input of the inverter 297 is coupled to the gate of the N-type MOS transistor 296 and the node SC-6, and the output of the inverter 297 is coupled to the P-type The gate stage of MOS transistor 295, whose inverter 297 is adapted to invert its input to form its output.

For example, referring to Figure 2E, when a logic value "1" is coupled to node SC-5, the multi-level tri-state buffer 292 on the left is turned on, and when a logic value "0" is coupled to node SC-5 In SC-6, the multi-level tri-state buffer 292 on the right is turned off, and the signal can be transmitted from the node N21 to the node N22. When a logic value "0" is coupled to node SC-5, the multi-level tri-state buffer 292 on the left is turned off, and when a logic value "1" is coupled to node SC-6, the bit on the right is turned on If the multi-level tri-state buffer 292 is used, the signal can be transmitted from the node N22 to the node N21. When a logic value "0" is coupled to node SC-5, the multi-level tri-state buffer 292 on the left is turned off, and when a logic value "0" is coupled to node SC-6, the bit on the right is turned off If the multi-level tri-state buffer 292 is used, there is no signal transmission between the node N21 and the node N22.

(6) Sixth type pass/fail switch

FIG. 2F is a circuit diagram of a sixth type of pass/no pass switch according to an embodiment of the present application. The sixth type pass/fail switch 258 may include a pair of multi-level tri-state buffers or switching buffers, similar to the pair of multi-level tri-state buffers 292 as depicted in Figure 2E. For the elements indicated by the same reference numerals shown in FIGS. 2E and 2F, the element shown in FIG. 2F may refer to the description of the element in FIG. 2E. The differences between the circuits shown in FIG. 2E and FIG. 2F are as follows: Please refer to FIG. 2F, for each multi-level tri-state buffer 292, the drain of the P-type MOS transistor 295 is is coupled to the source of its second-stage P-type MOS transistor 293, but not coupled to its first-stage P-type MOS transistor 293; its first-stage P-type MOS transistor 293 The source of is coupled to the power supply terminal (Vcc) and the source of the P-type MOS transistor 295 . For each multi-stage tri-state buffer 292, the drain of its N-type MOS transistor 296 is coupled to the source of its second stage of N-type MOS transistor 294, but not to its first stage The source of the N-type MOS transistor 294; the source of the first-stage N-type MOS transistor 294 is coupled to the ground terminal (Vss) and the source of the N-type MOS transistor 296.

Description of crosspoint switch consisting of pass/fail switches

(1) Type 1 crosspoint switch

FIG. 3A is a circuit diagram of a first-type crosspoint switch composed of six pass/no switches according to an embodiment of the present application. Referring to FIG. 3A, six pass/no switches 258 can form a first-type crosspoint switch 379, wherein each pass/no switch 258 can be of the first to the first type as shown in FIGS. 2A to 2F. Any of the six types of pass/fail switches. The first-type cross-point switch 379 may include four contacts N23 to N26 , and each of the four contacts N23 to N26 may be coupled to the other of the four contacts N23 to N26 through one of the six pass/no switches 258 . One. Any of the first to sixth types of pass/no switches can be applied to the pass/no switch 258 shown in FIG. 3A, and one of the nodes N21 and N22 is coupled to the four contacts N23 to One of the nodes N26 and the other of the nodes N21 and N22 are coupled to the other of the four nodes N23 to N26. For example, the contact N23 of the first-type cross-point switch 379 is adapted to be coupled to the contact N24 through the six pass/no pass switches 258 of the first one, and the six pass/no pass switches of the first one The switch 258 is located between the contact N23 and the contact N24, and/or the contact N23 of the first-type cross-point switch 379 is adapted to be coupled to the contact through the second one of the six pass/no switches 258 thereof. Point N25, the six pass/fail switches 258 of the second one are located between contact N23 and contact N25, and/or contact N23 of the first type crosspoint switch 379 is adapted to pass through its six The third of the pass/no switches 258 is coupled to the contact N26, and the six pass/no switches 258 of the third are located between the contact N23 and the contact N26.

(2) Type 2 crosspoint switch

FIG. 3B is a circuit diagram of a second-type crosspoint switch composed of four pass/fail switches according to an embodiment of the present application. Referring to FIG. 3B, four pass/no switches 258 can form a second-type crosspoint switch 379, wherein each pass/no switch 258 can be of the first to second types as shown in FIGS. 2A to 2F. Any of the six types of pass/fail switches. The second-type crosspoint switch 379 may include four contacts N23 to N26, each of which may be coupled to one of the four contacts N23 to N26 through two of the six pass/no switches 258 another. The central node of the second-type cross-point switch 379 is adapted to be coupled to its four contacts N23 to N26 through its four pass/no switches 258 , and any of the first to sixth type pass/no switches are It can be applied to the pass/fail switch 258 shown in FIG. 3B, one of the nodes N21 and N22 is coupled to one of the four contacts N23 to N26, and the other of the nodes N21 and N22 is coupled to to the central node of the second type crosspoint switch 379 . For example, the contact N23 of the second-type cross-point switch 379 is adapted to be coupled to the contact N24 through the pass/no-pass switches 258 on the left and upper sides thereof, and to the contact point N24 through the pass/no-pass switches 258 on the left and right sides thereof. Point N25 is coupled to contact N26, and/or via pass/fail switches 258 on the left and underside thereof.

Description of multiplexer (MUXER)

(1) The first type multiplexer

FIG. 4A is a circuit diagram of a first-type multiplexer according to an embodiment of the present application. Referring to FIG. 4A, the first-type multiplexer 211 has a first group of inputs arranged in parallel and a second group of inputs arranged in parallel, and can select one of the first group of inputs according to the combination of the second group of inputs as its output. For example, the first-type multiplexer 211 may have 16 inputs D0-D15 arranged in parallel as the first group of inputs, and 4 inputs A0-A3 arranged in parallel as the second group of inputs. The first-type multiplexer 211 can select one of the 16 inputs D0-D15 of the first group as its output Dout according to the combination of the 4 inputs A0-A3 of the second group.

Referring to FIG. 4A , the first-type multiplexer 211 may include multi-stage tri-state buffers coupled in stages, such as four-stage tri-state buffers 215 , 216 , 217 and 218 . The first-type multiplexer 211 may have eight pairs of 16 parallel-arranged tri-state buffers 215 disposed in the first stage, the first input of each of which is coupled to one of the 16 inputs D0-D15 of the first group. One of them, the second input of each of which is related to the input A3 of the second group. Each of the eight pairs of 16 tri-state buffers 215 in the first stage can be turned on or off according to its second input to control whether its first input is to be passed to its output. The first-type multiplexer 211 may include an inverter 219, the input of which is coupled to the input A3 of the second group, and the inverter 219 is adapted to invert its input to form its output. In the first stage, one of each pair of tri-state buffers 215 can be switched on according to its second input coupled to one of the input and output of the inverter 219, so that its first input is passed to its output; in the first stage, the other of each pair of tri-state buffers 215 can be switched to the off state according to the input and output of the other one coupled to the inverter 219, making its first input Not sent to its output. The outputs of each pair of tri-state buffers 215 in the first stage are coupled to each other. For example, the upper one of the uppermost pair of tri-state buffers 215 in the first stage has its first input coupled to the first group's input D0 and its second input coupled to the inverter The output of 219; the lower one of the uppermost pair of tri-state buffers 215 in the first stage has its first input coupled to the first group's input D1 and its second input coupled to the inverter 219 input. The upper one of the uppermost pair of tri-state buffers 215 in the first stage can be switched on according to its second input, causing its first input to pass to its output; the uppermost pair in the first stage The lower one of the tri-state buffers 215 can be switched off according to its second input so that its first input is not passed to its output. Thus, each of the eight pairs of tri-state buffers 215 in the first stage is controlled to have two of its first inputs based on its two second inputs coupled to the input and output of the inverter 219, respectively. One of them is sent to its output, which is coupled to the first input of one of the second stage tri-state buffers 216 .

Referring to FIG. 4A, the first-type multiplexer 211 may have four pairs of 8 tri-state buffers 216 arranged in parallel in the second stage, the first input of each of which is coupled to the first input in the first stage The tri-state buffer 215 has a pair of outputs, and the second input of each is related to the input A2 of the second group. Each of the four pairs of eight tri-state buffers 216 in the second stage can be turned on or off according to its second input to control whether its first input is to be passed to its output. The first-type multiplexer 211 may include an inverter 220, the input of which is coupled to the input A2 of the second group, and the inverter 220 is adapted to invert its input to form its output. In the second stage, one of each pair of tri-state buffers 216 can be switched on according to its second input coupled to one of the inputs and outputs of the inverter 220, passing its first input to its second input. Output; in the second stage, the other of each pair of tri-state buffers 216 can be switched to the off state according to the input and output of the other of the pair coupled to the inverter 220, making its first input Not sent to its output. The outputs of each pair of tri-state buffers 216 in the second stage are coupled to each other. For example, the upper one of the uppermost pair of tri-state buffers 216 in the second stage has its first input coupled to the output of the uppermost pair of tri-state buffers 215 in the first stage, and Its second input is coupled to the output of inverter 220; the lower one of the uppermost pair of tri-state buffers 216 in the second stage has its first input coupled to the next uppermost one in the first stage The output of the pair of tri-state buffers 215 and its second input are coupled to the input of the inverter 220 . The upper one of the uppermost pair of tri-state buffers 216 in the second stage can be switched on according to its second input, causing its first input to pass to its output; the uppermost pair in the second stage The next one of the tri-state buffers 216 can be switched off according to its second input so that its first input is not passed to its output. Thus, each of the four pairs of tri-state buffers 216 in the second stage is controlled to have two of its first inputs according to its two second inputs coupled to the input and output of the inverter 220, respectively. One of them is sent to its output, which is coupled to the first input of one of the third stage tri-state buffers 217 .

Referring to FIG. 4A , the first-type multiplexer 211 may have two pairs of four tri-state buffers 217 arranged in parallel in the third stage, and the first input of each of them is coupled to the second stage. The tri-state buffer 216 has a pair of outputs, and the second input of each is related to the input A1 of the second group. Each of the two pairs of four tri-state buffers 21 in the third stage can be turned on or off according to its second input to control whether its first input is to be passed to its output. The first-type multiplexer 211 may include an inverter 207, the input of which is coupled to the input A1 of the second group, and the inverter 207 is adapted to invert its input to form its output. In the third stage, one of each pair of tri-state buffers 217 can be switched on according to its second input coupled to one of the input and output of the inverter 207, so that its first input is passed to its Output; in the third stage, the other of each pair of tri-state buffers 217 can be switched to the off state according to the second input of the other of the input and output coupled to the inverter 207, making its first input Not sent to its output. The outputs of each pair of tri-state buffers 217 in the third stage are coupled to each other. For example, the upper one of the upper pair of tri-state buffers 217 in the third stage has its first input coupled to the output of the uppermost pair of tri-state buffers 216 in the second stage, and its The second input is coupled to the output of inverter 207; the lower one of the upper pair of tri-state buffers 217 in the third stage has its first input coupled to the next upper pair in the second stage The output of tri-state buffer 216 and its second input are coupled to the input of inverter 207 . The upper one of the upper pair of tri-state buffers 217 in the third stage can be switched on according to its second input, causing its first input to pass to its output; in the third stage the upper pair of tri-stated The lower one of the buffers 217 can be switched off according to its second input so that its first input does not pass to its output. Therefore, in the third stage, each pair of the two pairs of tri-state buffers 217 is controlled so that the two first inputs of the two pairs of the three-state buffers 217 are respectively coupled to the input and output of the inverter 207 according to their two second inputs. One of them is sent to its output, which is coupled to the first input of the fourth stage tri-state buffer 218 .

Referring to FIG. 4A, the first-type multiplexer 211 may have a pair of two tri-state buffers 218 arranged in parallel in the fourth stage, and the first input of each of which is coupled to the third stage The tri-state buffer 217 has a pair of outputs, and the second input of each is related to the input A0 of the second group. In the fourth stage each of a pair of 2 tri-state buffers 218 can be turned on or off according to its second input to control whether its first input is to be passed to its output. The first-type multiplexer 211 may include an inverter 208, the input of which is coupled to the input A0 of the second group, and the inverter 208 is adapted to invert its input to form its output. In the fourth stage, one of the pair of tri-state buffers 218 can be switched on according to its second input coupled to one of the input and output of the inverter 208, passing its first input to its output ; In the fourth stage, the other of the pair of tri-state buffers 218 can be switched to the off state according to the second input of the other of the input and output of the pair coupled to the inverter 208, so that its first input does not sent to its output. The outputs of the pair of tri-state buffers 218 in the fourth stage are coupled to each other. For example, the upper one of the pair of tri-state buffers 218 in the fourth stage has its first input coupled to the output of the upper pair of tri-state buffers 217 in the third stage, and its second input is coupled to the output of inverter 208; in the fourth stage the lower one of the pair of tri-state buffers 218 has its first input coupled to the other of the lower pair of tri-state buffers 217 in the third stage output, and its second input is coupled to the input of the inverter 208 . In the fourth stage, the upper one of the tri-state buffers 218 of the pair can be switched on according to its second input, causing its first input to pass to its output; in the fourth stage the pair of tri-state buffers The lower one of 218 can be switched off according to its second input so that its first input does not pass to its output. Therefore, in the fourth stage, the pair of tri-state buffers 218 is controlled to have one of its two first inputs sent to the Its output is used as the output Dout of the first type multiplexer 211 .

FIG. 4B is a circuit diagram of the tri-state buffer of the first-type multiplexer according to the embodiment of the present application. Please refer to FIGS. 4A and 4B, each of the tri-state buffers 215, 216, 217 and 218 may include (1) a P-type MOS transistor 231, suitable for forming a channel, one end of the channel is connected to At the first input of each of the tri-state buffers 215, 216, 217 and 218, the other end of the channel is at the output of each of the tri-state buffers 215, 216, 217 and 218 (2) an N-type MOS transistor 232, suitable for forming a channel, one end of the channel is located at the first input of each of the three-state buffers 215, 216, 217 and 218, the channel The other end is located at the output of each of the tri-state buffers 215 , 216 , 217 and 218 ; and (3) an inverter 233 whose input is coupled to the gate of the N-type MOS transistor 232 And at the second input of each of the tri-state buffers 215, 216, 217 and 218, the inverter 233 is adapted to invert its input to form its output, the output of which is coupled to to the gate of the P-type MOS transistor 231 . For each of the tri-state buffers 215, 216, 217 and 218, when the logic value of the input of the inverter 233 is "1", the P-type and N-type MOS transistors 231 and 232 are switched to In the open state, its first input can be transmitted to its output through the channels of its P-type and N-type MOS transistors 231 and 232; when the logic value of the input of its inverter 233 is "0", its P Both the P-type and N-type MOS transistors 231 and 232 are switched to the off state. At this time, the P-type and N-type MOS transistors 231 and 232 do not form a channel, so that the first input is not transmitted to its output. The respective two inputs of the respective two inverters 233 of the two tri-state buffers 215 of each pair in the first stage are respectively coupled to the respective two inputs of the inverters 219 associated with the input A3 of the second group. output and input. In the second stage, the respective two inputs of the respective two inverters 233 of each pair of the two tri-state buffers 216 are respectively coupled to the inverter 220 associated with the input A2 of the second group. output and input. In the third stage, the respective two inputs of the respective two inverters 233 of the two tri-state buffers 217 of each pair are respectively coupled to the inverters 207 associated with the input A1 of the second group. output and input. In the fourth stage, the respective two inputs of the respective two inverters 233 of the two tri-state buffers 218 of the pair are respectively coupled to the respective two of the inverters 208 associated with the input A0 of the second group output and input.

Accordingly, the first-type multiplexer 211 can select one of the inputs D0-D15 of the first group as its output Dout according to the combination of the inputs A0-A3 of the second group.

(2) The second type of multiplexer

FIG. 4C is a circuit diagram of a second-type multiplexer according to an embodiment of the present application. Please refer to FIG. 4C, the second-type multiplexer 211 is similar to the first-type multiplexer 211 as described in FIG. 4A and FIG. 4B, but also adds a third-type pass/fail as described in FIG. 2C The input of switch 292 at node N21 is coupled to the output of the pair of two tri-state buffers 218 in the last stage (eg, the fourth stage). For the elements shown in Figures 2C, 4A, 4B and 4C indicated by the same reference numerals, the elements shown in Figure 4C may refer to the elements in Figures 2C, 4A or the description in Figure 4B. Accordingly, please refer to FIG. 4C , the third-type pass/fail switch 258 can amplify its input at node N21 to form its output at node N22 as the output Dout of the second-type multiplexer 211 .

Accordingly, the second-type multiplexer 211 can select one of the inputs D0-D15 of the first group as its output Dout according to the combination of the inputs A0-A3 of the second group.

(3) The third type of multiplexer

FIG. 4D is a circuit diagram of a third-type multiplexer according to an embodiment of the present application. Please refer to FIG. 4D, the third-type multiplexer 211 is similar to the first-type multiplexer 211 as described in FIG. 4A and FIG. 4B, but also adds the fourth-type pass/fail as described in FIG. 2D The input of switch 258 at node N21 is coupled to the output of the pair of two tri-state buffers 218 in the last stage (eg, the fourth stage). For the element indicated by the same reference number shown in Fig. 2C, Fig. 2D, Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D, the element shown in Fig. 4D may refer to the element Description in Figure 2C, Figure 2D, Figure 4A, Figure 4B, or Figure 4C. Accordingly, referring to FIG. 4D, the fourth type pass/fail switch 258 can amplify its input at node N21 to form its output at node N22 as the output Dout of the third type multiplexer 211 .

Accordingly, the third-type multiplexer 211 can select one of the inputs D0-D15 of the first group as its output Dout according to the combination of the inputs A0-A3 of the second group.

In addition, the number of parallel-arranged inputs of the first group of the first-type, second-type or third-type multiplexer 211 is 2 to the nth power, and the number of parallel-arranged inputs of the second group is n, the number n can be any integer greater than or equal to 2, for example, between 2 and 64. FIG. 4E is a circuit diagram of a multiplexer according to an embodiment of the present application. In this embodiment, please refer to FIG. 4E, the first type, second type or third type multiplexer 211 as described in FIG. 4A, FIG. 4C or FIG. 4D can be modified to have eight Two sets of inputs A0-A7 and 256 (that is, 2 to the 8th power) of the first set of inputs D0-D255 (that is, the result values corresponding to all combinations of the second set of inputs A0-A7) or programming code). The first-type, second-type or third-type multiplexers 211 may include eight-stage cascade-coupled tri-state buffers or switching buffers, each of which has a structure as shown in FIG. 4B . The number of tri-state buffers or switch buffers arranged in parallel in the first stage may be 256, the first input of each of which may be coupled to one of the 256 inputs D0-D255 of the first group of the multiplexer 211 One of them, and can each be turned on or off according to the second input of each of them in relation to the second set of inputs A7 of the multiplexer 211, to control whether its first input is to be passed to its output. Each of the tri-state buffers or switch buffers arranged in parallel in the second to seventh stages, the first input of which can be coupled to the output of the tri-state buffer or the switch buffer of each preceding stage , and each of the multiplexer 211 can be turned on or off according to the second input of each of the inputs A6-A1 of the second group of the multiplexer 211, respectively, to control whether to transmit its first input to its output. In each of the tri-state buffers or switch buffers arranged in parallel in the eighth stage, the first input can be coupled to the output of the tri-state buffer or the switch buffer of the seventh stage, and according to the multiplexing The second input of the second set of inputs A0 of the device 211 can each be turned on or off to control whether its first input is to be passed to its output. In addition, a pass/no switch 292 as described in FIG. 4C or FIG. 4D can be added therein, that is, its input is coupled to the output of the pair of tri-state buffers in the eighth stage, and its input is amplified to Its output is formed as the output Dout of the multiplexer 211 .

For example, FIG. 4F is a circuit diagram of a multiplexer depicted in accordance with an embodiment of the present application. Referring to FIG. 4F , the second-type multiplexer 211 includes a first group of parallel-arranged inputs D0 , D1 and D3 and a second group of parallel-arranged inputs A0 and A1 . The second-type multiplexer 211 may include two-stage tri-state buffers 217 and 218 coupled in stages, and the second-type multiplexer 211 may have three parallel-arranged tri-state buffers 217 disposed in the first stage, which The first input of each is coupled to one of the three inputs D0-D2 of the first group, and the second input of each is related to the input A1 of the second group. Each of the three tri-state buffers 217 in the first stage can be turned on or off according to its second input to control whether its first input is to be passed to its output. The second type of multiplexer 211 may include an inverter 207, the input of which is coupled to the input A1 of the second group, and the inverter 207 is adapted to invert its input to form its output. In the first stage, one of the upper pair of tri-state buffers 217 can be switched on according to its second input coupled to one of the inputs and outputs of the inverter 207 so that its first input is sent to Its output; in the first stage, the other one of the tri-state buffers 217 of the upper pair can be switched to the off state according to the second input of the other one of the inputs and outputs coupled to the inverter 207, making its first An input is not routed to its output. The outputs of the pair of tri-state buffers 217 above the first stage are coupled to each other. Therefore, the upper pair of tri-state buffers 217 in the first stage is controlled to transmit one of its two first inputs according to its two second inputs coupled to the input and output of the inverter 217 respectively to its output, which is coupled to the first input of one of the second-stage tri-state buffers 218 . The lower tri-state buffer 217 in the first stage controls whether its first input is to be passed to its output according to its second input coupled to the output of the inverter 207, and its output is coupled to The first input of the other of the second stage tri-state buffers 218 .

Referring to FIG. 4F, the second-type multiplexer 211 may have a pair of two tri-state buffers 218 arranged in parallel in the second stage, and the first input of the upper one is coupled to the first stage in the first stage The output of the upper pair of tri-state buffers 217, the second input of the upper one is related to the input A0 of the second group, and the first input of the lower one is coupled to the lower tri-state buffer in the first stage The output of the controller 217, the second input of the lower one is related to the input A0 of the second group. In the second stage each of a pair of 2 tri-state buffers 218 can be turned on or off according to its second input to control whether its first input is to be passed to its output. The second type of multiplexer 211 may include an inverter 208, the input of which is coupled to the input A0 of the second group, and the inverter 208 is adapted to invert its input to form its output. In the second stage, one of the pair of tri-state buffers 218 can be switched on according to its second input coupled to one of the input and output of the inverter 208, passing its first input to its output ; in the second stage the other of the pair of tri-state buffers 218 can be switched to the off state according to the second input of the other of the input and output of the pair coupled to the inverter 208, so that its first input does not sent to its output. The outputs of the pair of tri-state buffers 218 in the second stage are coupled to each other. Thus, in the second stage the pair of tri-state buffers 218 is controlled to have one of its two first inputs sent to the its output. The second type multiplexer 211 may also include a third type pass/fail switch 258 as depicted in Figure 2C, whose input at node N21 is coupled to the two tri-states of the pair in the second stage The output of the buffer 218, the third type pass/fail switch 258 can amplify its input at node N21 to form its output at node N22 as the output Dout of the second type multiplexer 211.

In addition, please refer to FIGS. 4A to 4F, each of the tri-state buffers 215, 216, 217 and 218 can be replaced by a transistor, such as an N-type MOS transistor or a P-type MOS transistor, as shown in FIG. 4G as shown in Figure 4J. 4G to 4J are circuit diagrams of a multiplexer according to an embodiment of the present application. The first-type multiplexer 211 shown in FIG. 4G is similar to the first-type multiplexer 211 shown in FIG. 217 and 218 are replaced by a transistor, such as an N-type MOS transistor or a P-type MOS transistor. The second-type multiplexer 211 shown in FIG. 4H is similar to the second-type multiplexer 211 shown in FIG. 217 and 218 are replaced by a transistor, such as an N-type MOS transistor or a P-type MOS transistor. The first-type multiplexer 211 shown in FIG. 4I is similar to the first-type multiplexer 211 shown in FIG. 217 and 218 are replaced by a transistor, such as an N-type MOS transistor or a P-type MOS transistor. The second-type multiplexer 211 shown in FIG. 4J is similar to the second-type multiplexer 211 shown in FIG. 217 and 218 are replaced by a transistor, such as an N-type MOS transistor or a P-type MOS transistor.

Referring to FIGS. 4G to 4J, each transistor 215 may form a channel, the input terminal of which is coupled to the third replacement of the former tri-state buffer 215 as shown in FIGS. 4A to 4F. Where an input is coupled, the output of the channel is coupled to where the output of the former tri-state buffer 215 is coupled as shown in FIGS. 4A to 4F, and its gate is coupled To where the second input of the former tri-state buffer 215 is coupled as shown in FIGS. 4A-4F. Each transistor 216 may form a channel whose input is coupled to where the first input of the replacement tri-state buffer 216 is coupled as shown in FIGS. 4A-4F, the channel Its output is coupled to where the output of the former tri-state buffer 216 is coupled as shown in FIGS. 4A to 4F, and its gate is coupled to the place shown in FIGS. 4A to 4F. Shown instead of where the second input of the tri-state buffer 216 is coupled. Each transistor 217 may form a channel whose input is coupled to where the first input of the replacement tri-state buffer 217 is coupled as shown in FIGS. 4A-4F, the channel The output terminal is coupled to the place where the output of the replacement tri-state buffer 217 is coupled as shown in FIGS. 4A to 4F, and its gate is coupled to the place as shown in FIGS. 4A to 4F Shown instead of where the second input of the tri-state buffer 217 is coupled. Each transistor 218 may form a channel whose input is coupled to where the first input of the replacement tri-state buffer 218 is coupled as shown in FIGS. 4A-4F, the channel Its output is coupled to where the output of the former tri-state buffer 218 is coupled as shown in Figures 4A to 4F, and its gate is coupled to the place shown in Figures 4A to 4F. Shown instead of where the second input of the tri-state buffer 218 is coupled.

Explanation of Crosspoint Switches Consisting of Multiplexers

The first and second type crosspoint switches 379 as depicted in FIGS. 3A and 3B are composed of a plurality of pass/no switches 258 as depicted in FIGS. 2A to 2F. However, the cross-point switch 379 can also be composed of any type of the first to third type multiplexers 211, as described below:

(1) Type 3 crosspoint switch

FIG. 3C is a circuit diagram of a third-type cross-point switch composed of a plurality of multiplexers according to an embodiment of the present application. Referring to FIG. 3C, the third type crosspoint switch 379 may include four first, second or third type multiplexers 211 as shown in FIGS. 4A to 4J, each of which includes a first Three inputs of one group and two inputs of the second group, and are adapted to select one of the three inputs of its first group to transmit to its output according to the combination of the two inputs of its second group. For example, the second-type multiplexer 211 applied to the third-type crosspoint switch 379 may refer to the second-type multiplexer 211 shown in FIG. 4F and FIG. 4J . Each of the three inputs D0-D2 of the first group of one of the four multiplexers 211 may be coupled to one of the three inputs D0-D2 of the first group of the other two of the four multiplexers 211 One and the other of the four multiplexers 211 output Dout. Therefore, the three inputs D0-D2 of the first set of each of the four multiplexers 211 can be respectively coupled to three strips extending in three different directions to the outputs of the other three of the four multiplexers 211, respectively metal lines, and each of the four multiplexers 211 can select one of its first set of inputs D0-D2 to send to its output Dout according to the combination of its second set of inputs A0 and A1. Each of the four multiplexers 211 also includes a pass/fail switch or switch buffer 258, which can be switched on or off according to its input SC-4, allowing A0 and A1 to be switched from its second set according to its second set of inputs A0 and A1. A selected one of the three inputs D0-D2 of a group is routed or not routed to its output Dout. For example, the three inputs of the first group of the upper multiplexer 211 can be respectively coupled to the outputs Dout (located at the node N23) of the multiplexer 211 extending to the left, lower and right sides in three different directions, respectively. , N26 and N25), and the above multiplexer 211 can select one of the inputs D0-D2 of the first group to transmit to its output according to the combination _{of the inputs A0 1} and A1 _{1 of the second group.} Dout (bit at node N24). Through the multiplexer 211. The above / barrier switch or switch in accordance with an input buffer 258 may be SC ₁ -4 switched on or off state, so that according to its inputs A0 ₁ and a second group of its first group A1 ₁ A selected one of its three inputs D0-D2 is routed or not routed to its output Dout (bit at node N24).

(2) Type 4 crosspoint switch

FIG. 3D is a circuit diagram of a fourth-type cross-point switch composed of a multiplexer according to an embodiment of the present application. Referring to FIG. 3D, the fourth-type cross-point switch 379 may be composed of any of the first-type to third-type multiplexers 211 as described in FIGS. 4A-4J. For example, when the fourth type crosspoint switch 379 is a multiplexer of any one of the first to third types as described in FIGS. 4A, 4C, 4D, and 4G to 4I When constituted by 211, the fourth-type cross-point switch 379 can select one of the inputs D0-D15 of the first group and transmit it to the output Dout according to the combination of the inputs A0-A3 of the second group.

Description of Large Input/Output (I/O) Circuits

FIG. 5A is a circuit diagram of a large I/O circuit according to an embodiment of the present application. Referring to FIG. 5A , a semiconductor die may include a plurality of I/O pads 272 , which may be coupled to its bulk electrostatic discharge (ESD) protection circuit 273 , its bulk driver 274 and its bulk receiver 275 . The large electrostatic discharge (ESD) protection circuit, the large driver 274 and the large receiver 275 may form a large I/O circuit 341 . The large electrostatic discharge (ESD) protection circuit 273 may include two diodes 282 and 283, wherein the cathode of the diode 282 is coupled to the power supply terminal (Vcc), the anode thereof is coupled to the node 281, and the diode 283 is The cathode is coupled to node 281 , and its anode is coupled to ground (Vss), which is coupled to I/O pad 272 .

Please refer to FIG. 5A, the first input of the large driver 274 is coupled to the signal (L_Enable) for enabling the large driver 274, and the second input of the large driver 274 is coupled to the data (L_Data_out), so that the data (L_Data_out) can be passed through the large driver 274 is amplified or driven to form its output (at node 281 ), which is transmitted via I/O pads 272 to circuits located outside the semiconductor die. The large driver 274 may include a P-type MOS transistor 285 and an N-type MOS transistor 286, the drains of which are coupled to each other as their outputs (at node 281), and the sources of which are coupled to Power supply terminal (Vcc) and ground terminal (Vss). The large driver 274 may include a NAND gate 287 and a NOR gate 288, wherein the output of the NAND gate 287 is coupled to the gate of the P-type MOS transistor 285, and the NOR gate 285 The output of the NOR gate 288 is coupled to the gate of the N-type MOS transistor 286 . The first input of the non-and (NAND) gate 287 of the large driver 274 is coupled to the output of the inverter 289 of the large driver 274, and the second input thereof is coupled to the data (L_Data_out), non-and (NAND) gate 287 can negate its first input and its second input to generate its output, which is coupled to the gate of the P-type MOS transistor 285 . The first input of the NOR gate 288 of the large driver 274 is coupled to the data (L_Data_out), and the second input thereof is coupled to the signal (L_Enable). The input and its second input are NOT ORed to generate its output, which is coupled to the gate of the N-type MOS transistor 286 . The input of the inverter 289 is coupled to the signal (L_Enable), and its input can be inverted to form its output, the output of which is coupled to the first input of the NAND gate 287 .

Please refer to Fig. 5A, when the signal (L_Enable) is a logic value "1", the output of the NAND gate 287 is always a logic value "1" to turn off the P-type MOS transistor 285 instead of The output of the OR (NOR) gate 288 is always logic "0" to turn off the N-type MOS transistor 286. At this time, the signal (L_Enable) disables the large driver 274, so that the data (L_Data_out) is not transmitted to the output of the large driver 274 (bit at node 281).

Referring to FIG. 5A, when the signal (L_Enable) is a logic value of "0", the large driver 274 is enabled. Meanwhile, when the data (L_Data_out) is the logic value "0", the outputs of the NAND gate 287 and the NOR gate 288 are the logic value "1" to turn off the P-type MOS transistor 285 and The N-type MOS transistor 286 is turned on, causing the output of the bulk driver 274 (bit at node 281 ) to be at a logic "0" state and sent to the I/O pad 272 . If the data (L_Data_out) is the logic value "1", the outputs of the NAND gate 287 and the NOR gate 288 are the logic value "0" to turn on the P-type MOS transistor 285 and turn off The N-type MOS transistor 286 causes the output of the bulk driver 274 (bit at node 281 ) to be in a logic "1" state, which is transmitted to the I/O pad 272 . Therefore, the signal (L_Enable) can enable the large driver 274 to amplify or drive the data (L_Data_out) to form its output (at node 281 ) and transmit it to the I/O pad 272 .

Please refer to FIG. 5A , the first input of the large receiver 275 is coupled to the I/O pad 272 , which can be amplified or driven by the large receiver 275 to form its output (L_Data_in), and the second input of the large receiver 275 The input is coupled to a signal (L_Inhibit) for inhibiting the bulk receiver 275 from generating its output (L_Data_in) relative to its first input. The large receiver 275 includes a NAND gate 290, the first input of which is coupled to the I/O pad 272, and the second input of which is coupled to the signal (L_Inhibit), the NAND gate 290 Its first input and its second input can be negated to produce its output, which is coupled to the inverter 291 of the bulk receiver 275 . The input of the inverter 291 is coupled to the output of the NAND gate 290 and can invert its input to form its output as the output of the large receiver 275 (L_Data_in).

Please refer to Fig. 5A, when the signal (L_Inhibit) is a logic value "0", the output of the NAND gate 290 is always a logic value "1", and the output of the large receiver 275 (L_Data_in) is a logic value "1". Always logical "1". At this time, the large receiver 275 can be inhibited from generating its output (L_Data_in) related to its first input, which is coupled to the I/O pad 272 .

Referring to Figure 5A, when the signal (L_Inhibit) is a logic "1", the large receiver 275 is activated. At the same time, when the data transmitted to the I/O pad 272 by a circuit located outside the semiconductor chip is a logic value "1", the output of the NAND gate 290 is a logic value "0", so that The output (L_Data_in) of the large receiver 275 is a logic value "1"; when the data transmitted to the I/O pad 272 by a circuit located outside the semiconductor chip is a logic value "0", the non-and ( The output of the NAND gate 290 is a logic value "1", so that the output of the large receiver 275 (L_Data_in) is a logic value "0". Thus, a signal (L_Inhibit) can activate the large receiver 275 to amplify or drive the data transmitted to the I/O pad 272 from a circuit located outside the semiconductor die to form its output (L_Data_in).

Referring to FIG. 5A, the input capacitance of the I/O pad 272 is generated, for example, by a large electrostatic discharge (ESD) protection circuit 273 and a large receiver 275, and its range is, for example, between 2pF and 100pF, Between 2pF and 50pF, between 2pF and 30pF, greater than 2pF, greater than 5pF, greater than 10pF, greater than 15pF, or greater than 20pF. The output capacitance or drive capability or load of the large driver 274 is, for example, between 2pF and 100pF, between 2pF and 50pF, between 2pF and 30pF, or greater than 2pF, greater than 5pF, greater than 10pF, greater than 15pF or greater than 20pF. The size of the large electrostatic discharge (ESD) protection circuit 273 is, for example, between 0.5pF and 20pF, between 0.5pF and 15pF, between 0.5pF and 10pF, between 0.5pF and 5pF, Between 0.5pF and 20pF, greater than 0.5pF, greater than 1 pF, greater than 2pF, greater than 3pF, greater than 5pF, or greater than 10pF.

Description of Small Input/Output (I/O) Circuits

FIG. 5B is a circuit diagram of a small I/O circuit according to an embodiment of the present application. Referring to FIG. 5B , the semiconductor die may include a plurality of I/O pads 372 , which may be coupled to its miniature electrostatic discharge (ESD) protection circuit 373 , its miniature driver 374 and its miniature receiver 375 . A small electrostatic discharge (ESD) protection circuit, a small driver 374 and a small receiver 375 can form a small I/O circuit 203 . The miniature electrostatic discharge (ESD) protection circuit 373 may include two diodes 382 and 383, wherein the cathode of the diode 382 is coupled to the power supply terminal (Vcc), the anode thereof is coupled to the node 381, and the diode 383 is The cathode is coupled to node 381 , and its anode is coupled to ground (Vss), which is coupled to I/O pad 372 .

Please refer to FIG. 5B, the first input of the small driver 374 is coupled to the signal (S_Enable) to enable the small driver 374, and the second input of the small driver 374 is coupled to the data (S_Data_out), so that the data (S_Data_out) can be passed through the small driver 374 is amplified or driven to form its output (at node 381 ), which is transmitted via I/O pads 372 to circuits located outside the semiconductor die. The miniature driver 374 may include a P-type MOS transistor 385 and an N-type MOS transistor 386, the drains of which are coupled to each other as their outputs (located at node 381), and the sources of the two are respectively coupled to Power supply terminal (Vcc) and ground terminal (Vss). The miniature driver 374 may include a NAND gate 387 and a NOR gate 388, wherein the output of the NAND gate 387 is coupled to the gate of the P-type MOS transistor 385, and the NOR gate 385 The output of the NOR gate 388 is coupled to the gate of the N-type MOS transistor 386 . The first input of the non-and (NAND) gate 387 of the small driver 374 is coupled to the output of the inverter 389 of the small driver 374, and the second input thereof is coupled to the data (S_Data_out), the non-and (NAND) gate 387 can negate its first input and its second input to generate its output, which is coupled to the gate of the P-type MOS transistor 385 . The first input of the NOR gate 388 of the small driver 374 is coupled to the data (S_Data_out), and the second input thereof is coupled to the signal (S_Enable). The input and its second input are NOT ORed to generate its output, which is coupled to the gate of the N-type MOS transistor 386 . The input of the inverter 389 is coupled to the signal (S_Enable), and its input can be inverted to form its output, the output of which is coupled to the first input of the NAND gate 387 .

Please refer to Fig. 5B, when the signal (S_Enable) is a logic value "1", the output of the NAND gate 387 is always a logic value "1" to turn off the P-type MOS transistor 385 instead of The output of the OR (NOR) gate 388 is always logic "0" to turn off the N-type MOS transistor 386. At this time, the signal (S_Enable) disables the small driver 374, so that the data (S_Data_out) is not transmitted to the output of the small driver 374 (bit at node 381).

Referring to FIG. 5B, when the signal (S_Enable) is a logic value of "0", the small driver 374 is enabled. Meanwhile, when the data (S_Data_out) is the logic value "0", the outputs of the NAND gate 387 and the NOR gate 388 are the logic value "1" to turn off the P-type MOS transistor 385 and The N-type MOS transistor 386 is turned on, causing the output of the miniature driver 374 (bit at node 381 ) to be at a logic "0" state and sent to the I/O pad 372 . If the data (S_Data_out) is the logic value "1", the outputs of the NAND gate 387 and the NOR gate 388 are the logic value "0" to turn on the P-type MOS transistor 385 and turn it off The N-type MOS transistor 386 causes the output of the miniature driver 374 (bit at node 381 ) to be in the logic "1" state, which is transmitted to the I/O pad 372 . Therefore, the signal (S_Enable) can enable the small driver 374 to amplify or drive the data (S_Data_out) to form its output (at node 381 ) and transmit it to the I/O pad 372 .

Please refer to FIG. 5B , the first input of the small receiver 375 is coupled to the I/O pad 372 , which can be amplified or driven by the small receiver 375 to form its output (S_Data_in), and the second input of the small receiver 375 The input is coupled to a signal (S_Inhibit) for inhibiting the small receiver 375 from generating its output (S_Data_in) relative to its first input. The small receiver 375 includes a NAND gate 390, the first input of which is coupled to the I/O pad 372, and the second input of which is coupled to the signal (S_Inhibit), the NAND gate 290 Its first input and its second input can be negated to produce its output, which is coupled to the inverter 391 of the small receiver 375 . The input of the inverter 391 is coupled to the output of the NAND gate 390, and its input can be inverted to form its output as the output of the small receiver 375 (S_Data_in).

Please refer to Fig. 5B, when the signal (S_Inhibit) is a logic value "0", the output of the NAND gate 390 is always a logic value "1", and the output of the small receiver 375 (S_Data_in) is a logic value "1". Always logical "1". At this time, the small receiver 375 can be inhibited from generating its output (S_Data_in) related to its first input, which is coupled to the I/O pad 372 .

Referring to Fig. 5B, when the signal (S_Inhibit) is logic "1", the small receiver 375 is activated. At the same time, when the data transmitted to the I/O pad 372 by a circuit located outside the semiconductor chip is a logic value "1", the output of the NAND gate 390 is a logic value "0", so that The output (S_Data_in) of the small receiver 375 is a logic value of "1"; when the data transmitted to the I/O pad 372 by a circuit located outside the semiconductor chip is a logic value of "0", not and ( The output of the NAND gate 390 is a logic value "1", so that the output of the small receiver 375 (S_Data_in) is a logic value "0". Thus, the signal (S_Inhibit) can activate the small receiver 375 to amplify or drive the data sent to the I/O pad 372 by circuitry located outside the semiconductor die to form its output (S_Data_in).

Referring to FIG. 5B, the input capacitance of the I/O pad 372 is, for example, generated by a small electrostatic discharge (ESD) protection circuit 373 and a small receiver 375, and the range is, for example, between 0.1 pF and 10 pF , between 0.1pF and 5pF, between 0.1pF and 3pF, between 0.1pF and 2pF, less than 10pF, less than 5pF, less than 3pF, less than 1pF, or less than 1pF. The output capacitance or driving capability or load of the small driver 374 is, for example, between 0.1pF and 10pF, between 0.1pF and 5pF, between 0.1pF and 3pF, between 0.1pF and 2pF, Less than 10 pF, less than 5 pF, less than 3 pF, less than 2 pF, or less than 1 pF. The size of the small electrostatic discharge (ESD) protection circuit 373 is, for example, between 0.05pF and 10pF, between 0.05pF and 5pF, between 0.05pF and 2pF, between 0.05pF and 1pF, less than 5pF, less than 3pF, less than 2pF, less than 1pF, or less than 0.5pF.

Description of Programmable Logic Blocks

FIG. 6A is a block diagram of a programmable logic block according to an embodiment of the present application. Referring to FIG. 6A, the programmable logic block (LB) 201 can be in various forms, including a look-up table (LUT) 210 and a multiplexer 211 (ie, a configurable or reconfigurable logic circuit or a selection circuit), which can The multiplexer 211 of the programming logic block (LB) 201 includes a first set of inputs, such as D0-D15 as shown in Figure 4A, Figure 4C, Figure 4D, or Figure 4G to Figure 4I, or are D0-D255 as shown in FIG. 4E, each of which is coupled to one of the result values or programming codes stored in the look-up table (LUT) 210; the multiplexer of the programmable logic block (LB) 201 211 also includes a second set of inputs, such as four inputs A0-A3 as shown in Figure 4A, Figure 4C, Figure 4D or Figure 4G to Figure 4I or as shown in Figure 4E The 8 inputs A0-A7 are used to determine one of the inputs of the first group to send to its output, for example as shown in Figure 4A, Figure 4C to Figure 4E, or Figure 4G to Figure 4I The Dout is used as the output of the programmable logic block (LB) 201 . The input of the second group of the multiplexer 211 is, for example, four inputs A0-A3 as shown in Fig. 4A, Fig. 4C, Fig. 4D or Fig. 4G to Fig. 4I or as shown in Fig. 4E The eight inputs A0-A7 shown are used as inputs to the programmable logic block (LB) 201 . For example, the multiplexer 211 of the programmable logic block (LB) 201 may have: (1) a first set of input points for a first input data set for logic operations, the first input data set and the first input data set Two sets of inputs (i.e. four digital inputs A0-A3 as shown in Fig. 4A, Fig. 4C, Fig. 4D or Fig. 4G-4I, or eight digital inputs in Fig. 4E A0-A7) are associated, (2) a second set of input points for a second input data set, the second input data set is associated with Figure 4A, Figure 4C, Figure 4D or Figure 4G to Figure 4 The first set of inputs (ie D0-D15) shown in Figure 4I or the first set of inputs (ie D0-D255) in Figure 4E are associated, and each second set of input points is coupled and stored in the search One of the result values or programming codes in the table (LUT) 210, the multiplexer 211 of the programmable logic block (LB) 201 is configured from the second input data set (associated with the result value of the look-up table (LUT)) According to the first input data set, a result value is selected as an output data for an input data of a logic operation on an output point of the multiplexer 211 .

Referring to FIG. 6A, the look-up table (LUT) 210 of the programmable logic block (LB) 201 may include a plurality of memory cells 490, each of which stores a result value or a programming code, and each memory cell 490 is a An on-chip volatile memory cell, such as the memory cell 398 depicted in Figure 1A or 1B, or a non-volatile memory cell, such as a floating gate non-volatile memory cell, random access by magnetoresistive Memory (Magnetoresistive Random Access Memory, MRAM) IC chip or resistive random access memory (resistive random access memory, RRAM) IC chip, phase change random access memory (Phase Change Random Access Memory) IC chip or ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM) IC chips. The input of the first group of the multiplexer 211 of the programmable logic block (LB) 201 is, for example, D0-D15 as shown in Fig. 4A, Fig. 4C, Fig. 4D or Fig. 4G to Fig. 4I Or D0-D255 as shown in FIG. 4E, each of which is coupled to the output of one of the memory cells 490 for the look-up table (LUT) 210 (ie, the output Out1 or Out2 of the memory cell 398) , so the result value or programming code stored in each memory cell 490 can be transmitted to one of the inputs of the first group of the multiplexer 211 of the programmable logic block (LB) 201 .

Furthermore, when the multiplexer 211 of the programmable logic block (LB) 201 is of the second type or the third type, as shown in FIG. 4C , FIG. 4D , FIG. 4H or FIG. 4I , programmable The logic block (LB) 201 also includes other memory cells 490 for storing programming codes, the output of which is coupled to the input SC-4 of the multi-level tri-state buffer 292 of the multiplexer 211 thereof. Each of these other memory cells 490 is an on-chip volatile memory cell, such as the memory cell 398 depicted in FIG. 1A or 1B, or an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell. The output of the other memory cells 490 (ie, the output Out1 or Out2 of the memory cell 398 ) is coupled to the programmable logic The input SC-4 of the multi-level tri-state buffer 292 of the multiplexer 211 of the block (LB) 201, and other memory cells 490 store programming codes for turning on or off the programmable logic block (LB) 201 The multiplexer 211. Alternatively, the gates of the P-type and N-type MOS transistors 295 and 296 of the multi-level tri-state buffer 292 of the multiplexer 211 of the programmable logic block (LB) 201 are respectively coupled to other memory cells 490 . output (ie, the outputs Out1 and Out2 of the memory cell 398), and the other memory cells 490 store programming codes for turning on or off the multiplexer 211 of the programmable logic block (LB) 201, and as shown in Section 4C The inverter 297 shown in Fig. 4D, Fig. 4H or Fig. 4I can be omitted.

The programmable logic block (LB) 201 can be programmed to perform logical operations or Boolean operations, such as AND (AND), NOT AND (NAND), OR (OR), NOT OR (NOR) operations. A look-up table (LUT) 210 can be programmed so that the programmable logic block (LB) 201 can perform logic operations, such as the same logic operations performed by the logic operators shown in FIG. 6B. Referring to FIG. 6B, the logic operator includes, for example, an AND gate 212 and a NAND gate 213 arranged in parallel, wherein the AND gate 212 can input X0 and X1 to the two (that is, The AND (AND) operation is performed for the two inputs of the logic operator) to generate an output, and the NOT AND (NAND) gate 213 can perform the AND (AND) operation on its two inputs X2 and X3 (that is, the two inputs of the logic operator). (NAND) operation to generate an output. The logic operator further includes, for example, a NAND gate 214, the two inputs of which are respectively coupled to the output of the AND gate 212 and the output of the NAND gate 213. The NAND gate 214 can be A NAND operation is performed on the two inputs to generate an output Y as the output of the logic operator. The programmable logic block (LB) 201 as shown in FIG. 6A can achieve the logic operations performed by the logic operators as shown in FIG. 6B. For this embodiment, the programmable logic block (LB) 201 may include the above-mentioned 4 inputs, such as A0-A3, the first input A0 is equal to the input X0 of the logic operator, and its first input A0 is equal to the input X0 of the logic operator. The second input A1 corresponds to the input X1 of the logic operator, the third input A2 corresponds to the input X2 of the logic operator, and the fourth input A3 corresponds to the input X3 of the logic operator. The programmable logic block (LB) 201 may include the output Dout as described above, which is equal to the output Y of the logic operator.

FIG. 6C shows a look-up table (LUT) 210 that can be used to achieve logical operations performed by the logical operators shown in FIG. 6B. Referring to FIG. 6C, the look-up table (LUT) 210 can record or store all 16 result values or programming codes generated by the logic operator as shown in FIG. 6B according to 16 combinations of its inputs X0-X3 respectively. . The look-up table (LUT) 210 can be programmed with these 16 result values or programming codes, which are respectively stored in a total of 16 memory cells 490 as shown in FIG. 1A or FIG. 1B (each memory cell 490 may be a chip upper volatile memory cell), and its output Out1 or Out2 is respectively coupled to a total of 16 inputs D0-D15 of the first group of the multiplexer 211 of the programmable logic block (LB) 201, as shown in FIG. As shown in Figure 4C, Figure 4D, or Figures 4G to 4I, or each memory cell 490 may be an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell, a magnetoresistive Random Access Memory (Magnetoresistive Random Access Memory, MRAM) IC chip or Resistive Random Access Memory (RRAM) IC chip, Phase Change Random Access Memory (Phase Change Random Access Memory) IC chip or Ferroelectric Random Access Memory (Ferroelectric Random Access Memory) ,FRAM) IC chip, the multiplexer 211 can determine one of the inputs D0-D15 of the first group to transmit to its output Dout according to the combination of the inputs A0-A3 of the second group, as a programmable logic block (LB ) 201, as shown in Figure 6A.

Alternatively, the programmable logic block (LB) 201 may be replaced by a plurality of programmable logic gates, which are programmed to perform logic operations or Boolean operations as shown in FIG. 6B.

Alternatively, multiple programmable logic blocks (LBs) 201 may be programmed to integrate to form a computational operator, such as to perform addition, subtraction, multiplication or division operations. Computational operators are, for example, adder circuits, multiplexers, shift registers, floating point circuits and multiply and/or divide circuits. For example, the computation operator can multiply two binary numbers [A1, A0] and [A3, A2] to produce an output of four binary numbers [C3, C2, C1, C0], as shown in Figure 6D Show. To achieve this operation, four programmable logic blocks (LB) 201 as shown in FIG. 6A can be programmed to integrate to form the calculation operator, each of which can be based on the combination of its inputs [A1, A0, A3, A2]. combined to produce its output, which is the binary number of one of the four binary numbers [C3, C2, C1, C0]. When multiplying the binary numbers [A1, A0] by the binary numbers [A3, A2], the four programmable logic blocks (LB) 201 can be generated according to the same combination of their inputs [A1, A0, A3, A2] The output is generated respectively, which is one of the four binary numbers [C3, C2, C1, C0]. The four programmable logic blocks (LB) 201 can be programmed with a look-up table (LUT) 210 respectively, that is, For Table-0, Table-1, Table-2 and Table-3.

For example, referring to FIGS. 6A and 6D, a number of memory cells 490 can be formed for each look-up table (LUT) 210 (Table-0, Table-1, Table-2 or Table-3), Each of the memory cells 490 may be an on-chip volatile memory cell, such as the memory cell 398 depicted in FIG. 1A or 1B, or a non-volatile memory cell, such as a floating gate non-volatile memory cell. Body unit, composed of magnetoresistive random access memory (MRAM) IC chip or resistive random access memory (RRAM) IC chip, phase change random access memory (Phase Change Random Access Memory) IC chip or ferroelectric random access memory The access memory (Ferroelectric Random Access Memory, FRAM) IC chip can store one of the result values or programming codes corresponding to one of the four binary numbers C0-C3. Each of the inputs D0-D15 of the first group of the multiplexer 211 of the first of the four programmable logic blocks (LB) 201 is coupled to one of the memories of the look-up table 210 (Table-0) The output Out1 or Out2 of the unit 490, and the input A0-A3 of the second group is determined to send one of the inputs D0-D15 of the first group to its output Dout as the first programmable logic block (LB ) 201 output C0; the four programmable logic blocks (LB) 201 in which the second one of the first group of inputs D0-D15 of the multiplexer 211 are each coupled for look-up table 210 (Table- 1) The output Out1 or Out2 of one of the memory cells 490, and the input A0-A3 of the second group is determined to send one of the inputs D0-D15 of the first group to its output Dout, as the second available The output C1 of the programming logic block (LB) 201; the inputs D0-D15 of the first group of the multiplexer 211 of the third of the four programmable logic blocks (LB) 201 are each coupled for The output Out1 or Out2 of one of the memory cells 490 of the lookup table 210 (Table-2), and the input A0-A3 of the second group is determined to send one of the inputs D0-D15 of the first group to its output Dout , as the output C2 of the third programmable logic block (LB) 201; among the four programmable logic blocks (LB) 201, each of the inputs D0-D15 of the first group of the multiplexer 211 of the fourth programmable logic block (LB) 201 One is coupled to the output Out1 or Out2 of one of the memory cells 490 used in the lookup table 210 (Table-3), and the input A0-A3 of the second group is determined to be one of the inputs D0-D15 of the first group One is sent to its output Dout as the output C3 of the fourth programmable logic block (LB) 201 .

Therefore, please refer to FIG. 6D, the four programmable logic blocks (LB) 201 can constitute the calculation operator, and can respectively generate binary other Output C0-C3 to form four binary digits [C0,C1,C2,C3]. In this embodiment, the same input of the four programmable logic blocks (LB) 201 is the input of the calculation operator, and the outputs C0-C3 of the four programmable logic blocks (LB) 201 are The output of this computation operator. The computational operator can generate an output of four binary numbers [C0, C1, C2, C3] according to the combination of its four-bit inputs [A1, A0, A3, A2].

Please refer to FIG. 6D, for example, for the example of multiplying 3 by 3, the combination [A1, A0, A3, A2] of the inputs of the four programmable logic blocks (LB) 201 are all [1, 1, 1, 1], according to the combination of its inputs, the binary output [C3, C2, C1, C0] can be determined as [1, 0, 0, 1]. The first programmable logic block (LB) 201 can generate its output C0 according to the combination of inputs ([A1,A0,A3,A2]=[1,1,1,1]), which is the logic value of " 1” binary number; the second programmable logic block (LB) 201 can generate its output C1 according to the combination of inputs ([A1,A0,A3,A2]=[1,1,1,1]), is a binary number with a logic value of "0"; the third programmable logic block (LB) 201 can be based on the combination of the input ([A1,A0,A3,A2]=[1,1,1,1]) , to generate its output C2, which is a binary number with a logic value of "0"; the fourth programmable logic block (LB) 201 can ,1,1]), which produces its output C3, which is a binary number with a logic value of "1".

Alternatively, the four programmable logic blocks (LB) 201 can be replaced by a plurality of programmable logic gates, and after programming, a circuit as shown in FIG. 6E can be formed to perform calculation operations, which is the same as the above-mentioned four programmable logic regions Computational operations performed by block (LB) 201 . The calculation operator can be programmed to form a circuit as shown in Figure 6E, which can multiply two binary numbers [A1, A0] and [A3, A2] to obtain four binary numbers [C3, C2, C1, C0] , and its operation result is shown in Fig. 6D. Referring to FIG. 6E, the calculation operator can be programmed with an AND gate 234, which can AND its two inputs (ie, the two inputs A0 and A3 of the calculation operator) to generate an output The calculation operator is also programmed with an AND gate 235, which can perform AND (AND) operation on its two inputs (that is, the two inputs A0 and A2 of the calculation operator) to generate an output as the calculation operation The output C0 of the sub; the calculation operator is also programmed with an AND gate 236, which can perform AND (AND) operation on its two inputs (that is, the two inputs A1 and A2 of the calculation operator) to generate an output; The calculation operator is also programmed with an AND gate 237, which can AND its two inputs (that is, the two inputs A1 and A3 of the calculation operator) to generate an output; the calculation operator also An exclusive-OR (ExOR) gate 238 is programmed to perform an exclusive-OR operation on the two inputs coupled to the outputs of the AND (AND) gates 234 and 236, respectively, to generate an output as the calculation operation the output C1 of the sub; the calculation operator is also programmed with an AND gate 239 that can AND its two inputs coupled to the outputs of the AND gates 234 and 236, respectively, to produce an output; The computational operator is also programmed with an exclusive-OR (ExOR) gate 242, which can perform an exclusive-OR (Exclusive-OR) operation on the two inputs coupled to the outputs of the AND (AND) gates 239 and 237, respectively, to generate an output , as the output C2 of the calculation operator; the calculation operator is also programmed with an AND gate 253 to perform AND operation on its two inputs coupled to the outputs of the AND gates 239 and 237, respectively to generate an output as the output C3 of the calculation operator.

To sum up, the programmable logic block (LB) 201 may be provided with n memory cells 490 for the look-up table (LUT) 210 to the second power, storing all combinations of n inputs thereof (n of 2 in total) The result value or programming code of the nth power of 2 corresponding to the combination). For example, the number n can be any integer greater than or equal to 2, such as between 2 and 64. For example, referring to FIG. 6C and FIG. 6D, the number of inputs of the programmable logic block (LB) 201 can be equal to 4, so the number of result values or programming codes corresponding to all combinations of its inputs is 2 4 to the power, that is, 16.

As described above, the programmable logic block (LB) 201 shown in FIG. 6A can perform logical operations on its inputs to generate an output, wherein the logical operations include Boolean operations, such as AND operations, NOT AND (NAND) operation, OR (OR) operation, NOT OR (NOR) operation. The programmable logic block (LB) 201 as shown in FIG. 6A can also perform computational operations on its inputs to generate an output, wherein the computational operations include addition, subtraction, multiplication or division.

Description of Programmable Interconnect Cables

FIG. 7A is a block diagram of a programmable interconnection line programmed by a pass/fail switch shown in accordance with an embodiment of the present application. Referring to FIG. 7A, the pass/no switch 258 (ie, configurable or reconfigurable interconnect circuit) of the first to sixth types shown in FIGS. 2A to 2F can be programmed to control the two Whether the programming interconnection lines 361 should be coupled to each other, wherein one programmable interconnection line 361 is coupled to the node N21 of the pass/non-pass switch 258, and the other programmable interconnection line 361 is coupled to the pass/fail switch 258 Node N22 of switch 258 is blocked. Therefore, the pass/no switch 258 can be switched to an on state, allowing one of the programmable interconnect lines 361 to be coupled to the other one of the programmable interconnect lines 361 via the pass/no switch 258; alternatively, a pass/no switch 258 can also be switched to an off state, so that one of the programmable interconnect lines 361 is not coupled to the other of the programmable interconnect lines 361 through the pass/no switch 258 .

Please refer to FIG. 7A, the memory unit 362 can be coupled to the pass/fail switch 258 to control turning on or off of the pass/fail switch 258, wherein the memory unit 362 is an on-chip volatile memory cell, as shown in FIG. 1A or 1B The memory cell 398 depicted in the figure is also a non-volatile memory cell, such as a floating gate non-volatile memory cell, a magnetoresistive random access memory (MRAM) IC chip or a resistive random access memory cell. Memory (resistiverandomaccessmemories, RRAM) IC chip, phase change random access memory (PhaseChangeRandomAccessMemory)IC chip or ferroelectric randomaccessmemory (FerroelectricRandomAccessMemory,FRAM) IC chip. When the programmable interconnect 361 is programmed through the first type pass/stop switch 258 as shown in FIG. 2A, each node SC-1 and SC-2 of the first type pass/break switch 258 is respectively coupled to the outputs of the memory unit 362 (ie, the outputs Out1 and Out2 of the memory unit 398 ) to receive its outputs related to the programming code stored in the memory unit 362 to control the opening or closing of the first type pass/fail switch 258 , making the two programmable interconnecting lines 361 respectively coupled to the two nodes N21 and N22 of the first type pass/fail switch 258 to be in a mutually coupled state or in an open state. When the programmable interconnection line 361 is programmed through the second type pass/fail switch 258 as shown in FIG. 2B, the node SC-3 of the second type pass/fail switch 258 is coupled to the memory cell 362 The output (that is, the output Out1 or Out2 of the memory unit 398) is used to receive its output related to the programming code stored in the memory unit 362 to control the opening or closing of the second-type pass/no-pass switch 258, so that the The two programmable interconnecting lines 361 of the two nodes N21 and N22 of the type 2 pass/fail switch 258 are in a mutually coupled state or in an open state. When the programmable interconnect 361 is programmed through the third or fourth type pass/fail switch 258 as depicted in FIG. 2C or 2D, the third or fourth type pass/fail switch 258 The node SC-4 is coupled to the output of the memory unit 362 (ie, the output Out1 or Out2 of the memory unit 398 ) to receive its output related to the programming code stored in the memory unit 362 to control turning on or off the third Type 3 or Type 4 pass/stop switch 258, so that the two programmable interconnecting lines 361 respectively coupled to two nodes N21 and N22 of Type 3 or Type 4 pass/stop switch 258 are in a coupled state or in an open state; Alternatively, the gates of the P-type and N-type MOS transistors 295 and 296 are respectively coupled to the two outputs of the memory unit 362 (ie, the outputs Out1 and Out2 of the memory unit 398 ) to receive and store in the memory unit 362 The other two outputs related to the programming code in it are used to control the opening or closing of the third-type or fourth-type pass/fail switch 258, so that the two nodes N21 and N22 respectively coupled to the third-type or fourth-type pass/fail switch 258 The two programmable interconnecting lines 361 are in a mutually coupled state or in an open state, and the inverter 297 can be omitted at this time. When the programmable interconnect 361 is programmed through the fifth or sixth type pass/fail switch 258 as depicted in FIG. 2E or FIG. 2F, the connection between the fifth or sixth type pass/fail switch 258 Each node SC-5 and SC-6 is coupled to the output of memory cell 362 (ie, the output Out1 or Out2 of memory cell 398 ), respectively, to receive its output related to the programming code stored in memory cell 362 to control the opening or closing of the fifth type or sixth type pass/fail switch 258, so that the two programmable interconnection lines 361 respectively coupled to the two nodes N21 and N22 of the fifth type or sixth type pass/fail switch 258 are connected to each other. The coupled state or the open-circuit state; or, the gates of the P-type and N-type MOS transistors 295 and 296 on the left side thereof are respectively coupled to the two outputs of a memory cell 362 (that is, the output of the memory cell 398 ). Out1 and Out2) to receive its two outputs related to the programming code stored in the memory cell 362, and the gates of its P-type and N-type MOS transistors 295 and 296 on the right side thereof are respectively coupled to The second output of the other memory unit 362 (that is, the outputs Out1 and Out2 of the memory unit 398 ) is used to receive the other two outputs related to the programming code stored in the other memory unit 362 to control the opening or closing of the fifth The pass/no switch 258 of the type 5 or the type 6 makes the two programmable interconnecting lines 361 respectively coupled to the two nodes N21 and N22 of the pass/no switch 258 of the type 5 or type 6 to be in a mutually coupled state or in an open state, At this time, the inverter 297 can be omitted. Before programming the memory unit 362 or at the time of programming the memory unit 362, the programmable interconnection cable 361 will not be used for signal transmission, and through the programming memory unit 362, the pass/fail switch 258 can be switched to the on state to couple The two programmable interconnecting wires 361 are connected for signal transmission; alternatively, the pass/fail switch 258 can be switched to an off state by programming the memory unit 362 to cut off the coupling of the two programmable interconnecting wires 361 . Likewise, the first-type and second-type crosspoint switches 379 shown in FIGS. 3A and 3B are composed of a plurality of pass/no-pass switches 258 of any of the above-mentioned types, each of which is a pass/no-pass switch. 258 nodes (SC-1 and SC-2), SC-3, SC-4 or (SC-5 and SC-6) are coupled to the output of memory cell 362 to receive and store in memory cell 362 The output of the programming code is related to control to turn on or off each pass/no switch 258, so that the two programmable interconnecting lines 361 respectively coupled to the two nodes N21 and N22 of each pass/no switch 258 are in a mutually coupled state or open circuit.

FIG. 7B is a circuit diagram of a programmable interconnection line programmed by a crosspoint switch according to an embodiment of the present application. Referring to FIG. 7B, the four programmable interconnection lines 361 are respectively coupled to the four nodes N23-N26 of the third-type cross-point switch 379 shown in FIG. 3C. Therefore, one of the four programmable interconnect lines 361 can be coupled to the other one of the four programmable interconnect lines 361 through the switching of the third type crosspoint switch 379 (ie, the configurable or reconfigurable interconnect line circuit), the other two interconnect lines, or are the other three; therefore, three inputs of each multiplexer 211 are coupled to three of the four programmable interconnect lines 361, and its output is coupled to the other of the four programmable interconnect lines 361, each A multiplexer 211 (ie, a configurable or reconfigurable interconnect circuit) can have one of the three inputs of its first set routed to its output according to its second set of two inputs A0 and A1. When the cross-point switch 379 is composed of four first-type multiplexers 211 , the two inputs A0 and A1 of the second group of each first-type multiplexer 211 are respectively coupled to the three memory cells 362 The output of two memory cells in (ie, the output Out1 or Out2 of memory cell 398); and each pass/fail switch 258 (ie, configurable or reconfigurable interconnect circuit) may have node SC-4 It is coupled to the output of another memory unit 361 (ie, the output Out1 or Out2 of the memory unit 398 ). Alternatively, when the crosspoint switch 379 is composed of four second or third type multiplexers 211 (as shown in FIG. 4F or 4J), each of the second or third type multiplexers 211 is more Each of the two inputs A0 and A1 of the second group of the processor 211 and the node SC-4 is coupled to the output of two memory cells 262 of the three memory cells 262 (ie, the output Out1 or Out2 of the memory cell 398 ). , and each node SC-4 that passes/does not pass through switch 258 (ie, a configurable or reconfigurable crosslink circuit is coupled to the output of another memory cell 362); or, when crosspoint switch 379 is connected by When four second-type or third-type multiplexers 211 are formed, each of the two inputs A0 and A1 of the second group of each second-type or third-type multiplexer 211 is coupled to the memory unit 262 The output of the memory cell 398 (that is, the output Out1 or Out2 of the memory cell 398 ), and the gates of the P-type and N-type MOS transistors 295 and 296 are respectively coupled to the two outputs of the memory cell 362 (that is, the memory cell 398 ) output Out1 and Out2), to receive the other two outputs related to the programming code stored in the memory unit 362 to control opening or closing of its third or fourth type pass/fail switch 258, allowing its third or fourth type The input and output Dout of the four-type pass/fail switch 258 are in a mutually coupled state or in an open-circuit state, and the inverter 297 can be omitted at this time. Therefore, three inputs of each multiplexer 211 are coupled to three of the four programmable interconnection lines 361, and its output is coupled to the other of the four programmable interconnection lines 361. Each multiplexer 211 According to the two inputs A0 and A1 of the second group, one of the three inputs of the first group can be transmitted to its output, or according to the logic value of the node SC-4 or the P-type and N-type MOS transistors 295 The logic value of the gate of and 296 causes one of the three inputs of its first group to be sent to its output.

For example, please refer to FIG. 3C and FIG. 7B , the following description is based on an example in which the cross-point switch 379 is constituted by four second-type or third-type multiplexers 211 . _{The inputs A0 1} and A1 ₁ and nodes SC ₁ -4 of the second group of the above multiplexer 211 are coupled to the outputs of the three memory cells 362 - 1 (ie, the outputs Out1 or Out2 of the three memory cells 398 ) _{), the inputs A0 2} and A1 ₂ and the nodes SC ₂ -4 of the second group of the multiplexer 211 on the left are coupled to the outputs of the three memory units 362 - 2 (that is, the output Out1 of the three memory units 398 ) _{or Out2), the inputs A0 3} and A1 ₃ and nodes SC _3-4 of the second group of the multiplexer 211 below are coupled to the outputs of the three memory cells 362-3 (that is, the three memory cells 398 or output Out1 and Out2), the right of the input multiplexer 211 of the second group of nodes A0 ₄ A1 ₄ SC ₄ -4-based and is coupled to the memory unit 362-4 of three (i.e., three memory units 398 output Out1 or Out2). Before programming memory cells 362-1, 362-2, 362-3 and 362-4 or while programming memory cells 362-1, 362-2, 362-3 and 362-4, four programmable interconnect lines 361 is not used for signal transmission, but by programming memory cells 362-1, 362-2, 362-3 and 362-4, each of the four second or third type multiplexers 211 can be One of the inputs of the first set is selected to be sent to its output, so that one of the four programmable interconnect lines 361 can be coupled to the other, the other two, or the other three of the four programmable interconnect lines 361 for use in signal transmission.

FIG. 7C is a circuit diagram of a programmable interconnection line programmed by a crosspoint switch according to an embodiment of the present application. Referring to FIG. 7C, as shown in FIG. 3D, each of the first group of inputs (eg, 16 inputs D0-D15) of the fourth-type crosspoint switch 379 is coupled to a plurality of programmable interconnection lines One of the 361 (for example, 16), and its output Dout is coupled to another programmable interconnection line 361, so that the fourth-type crosspoint switch 379 can be connected from the plurality of programmable interconnections coupled to its input One of the lines 361 is selected to be coupled to the other programmable interconnect line 361 . Each of the inputs A0 - A3 of the second group of the fourth type cross point switch 379 is coupled to the output of the memory unit 362 (ie, the output Out1 or Out2 of the memory unit 398 ) to receive and store in the memory unit 362 its output related to the programming code to control the fourth type crosspoint switch 379 to select one of its first set of inputs (eg, its inputs D0-D15 coupled to the 16 programmable interconnect lines 361) to its output (eg, its output Dout coupled to the other programmable interconnect line 361). Before programming the memory cell 362 or when programming the memory cell 362 , the plurality of programmable interconnection lines 361 and the other programmable interconnection line 361 are not used for signal transmission. The fourth-type crosspoint switch 379 can select one of its first set of inputs to send to its output, so that one of the plurality of programmable interconnect lines 361 can be coupled to the other programmable interconnect line 361 for signal transmission.

Description of fixed interactive connection lines

Before or while programming memory cells 490 for look-up tables (LUTs) 210 as depicted in FIG. 6A and memory cells 362 for programmable interconnect lines 361 as depicted in FIGS. 7A-7C, through Fixed interconnection lines 364 that are not field programmable can be used for signal transmission or power/ground supply to (1) a look-up table (LUT) 210 for a programmable logic block (LB) 201 as depicted in FIG. 6A memory cell 490 for programming memory cell 490; and/or (2) memory cell 362 for programmable interconnect 361 as described in FIGS. 7A-7C for programming memory cell 362. After programming memory cells 490 for look-up table (LUT) 210 and memory cells 362 for programmable interconnect lines 361, fixed interconnect lines 364 can also be used for signal transmission or power/ground supply during operation.

Description of Standard Commercial Field Programmable Gate Array (FPGA) Integrated Circuit (IC) Chips

FIG. 8A is a top view block diagram of a standard commercial field programmable gate array (FPGA) integrated circuit (IC) chip according to an embodiment of the present application. Please refer to FIG. 8A, the standard commercial FPGAIC chip 200 is designed and manufactured by using a more advanced semiconductor technology generation, such as a process advanced in or less than or equal to 30nm, 20nm or 10nm. Due to the use of mature semiconductor technology generation, so While pursuing the minimization of manufacturing cost, the wafer size and manufacturing yield can be optimized. The area of standard commercial FPGAIC chip 200 is between 400mm ² to 9mm ² , 225mm ² to 9mm ² , 144mm ² to 16mm ^{2 , 100mm 2} to 16mm ² , between 100mm 2 to 16mm 2 Between 75mm ² and 16mm ² or between 50mm ² and 16mm ² . The transistors or semiconductor elements used in the standard commercialized FPGAIC chip 200 of the advanced semiconductor technology generation can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layer (FINFET SOI), fully depleted type Field effect transistor (FDSOIMOSFET) with silicon-on-insulator layer, semi-depletion-type metal-oxide-semiconductor field-effect transistor (PDSOIMOSFET) on insulating layer, or traditional metal oxide semiconductor field effect transistor.

Please refer to FIG. 8A, since the standard commercial FPGAIC chip 200 is a standard commercial IC chip, the standard commercial FPGAIC chip 200 only needs to be reduced by at least a few types, so the standard commercial FPGAIC manufactured by advanced semiconductor technology generation The number of expensive masks or mask sets required for wafer 200 can be reduced to between 3 and 20 sets, between 3 and 10 sets, or 3 sets for a generation of semiconductor technology. Between groups of 5, the one-time engineering cost (NRE) will also be greatly reduced. Since there are few types of standard commercial FPGAIC chips 200, the fabrication process can be optimized to achieve very high throughputs of fabricated wafers. Furthermore, the inventory management of the chips can be simplified to achieve the goals of high performance and high efficiency, so the lead time of the chips can be shortened, which is very cost-effective.

Referring to FIG. 8A, various types of standard commercial FPGAIC chips 200 include: (1) a plurality of programmable logic blocks (LB) 201, as described in FIGS. 6A to 6E, in an array manner Arranged in the middle area thereof; (2) a plurality of intra-chip interconnection lines 502, each of which extends in the upper space between two adjacent programmable logic blocks (LB) 201; and (3) a plurality of small The I/O circuit 203, as depicted in FIG. 5B, wherein each output S_Data_in is coupled to one or more intra-chip interconnect lines 502, and each of which is coupled to each input S_Data_out, S_Enable or S_Inhibit Connect to another one or more inter-chip interconnection lines 502 .

Referring to FIG. 8A, each intra-chip interconnection line 502 may be a programmable interconnection line 361 or a fixed interconnection line 364 as described in FIGS. 7A-7C. A standard commercial FPGA IC chip 200 has small I/O circuits 203 as depicted in FIG. 5B, each output S_Data_in of which is coupled to one or more programmable interconnect lines 361 and/or one or more of the The fixed interconnection lines 364, each of whose inputs S_Data_out, S_Enable or S_Inhibit are coupled to the other one or more programmable interconnection lines 361 and/or the other one or more fixed interconnection lines 364.

Referring to Figure 8A, each programmable logic block (LB) 201 is as described in Figures 6A-6E, with each of its inputs A0-A3 coupled to one or more programmable logic blocks The interconnection line 361 and/or one or more fixed interconnection lines 364 are used to perform a logic operation or calculation operation on its input to generate an output Dout, which is coupled to the other one or more programmable interconnection lines 361 and/or other one or more fixed interconnection lines 364, wherein the logical operations include Boolean operations, such as AND (AND), NOT AND (NAND), OR (OR), NOT OR (NOR) An operation, such as an addition operation, a subtraction operation, a multiplication operation or a division operation, is performed.

Referring to FIG. 8A, a standard commercial FPGA IC die 200 may include a plurality of I/O pads 372, each of which is disposed vertically above one of the small I/O circuits 203, as depicted in FIG. 5B, and connected to the node 381 of the one of the small I/O circuits 203 . In the first clock, the output Dout of one of the programmable logic blocks (LB) 201 as shown in FIG. 6A can be transmitted to one of the small I/ The input S_Data_out of the small driver 374 of the O circuit 203, the small driver 374 of the one of the small I/O circuits 203 can amplify its input S_Data_out to the I/O pad vertically above the one of the small I/O circuits 203 372 for transfer to circuitry outside of standard commercial FPGAIC die 200. In the second clock, signals from circuits external to the standard commercial FPGAIC chip 200 can be transmitted via the I/O pads 372 to the miniature receiver 375 of one of the miniature I/O circuits 203, which is The small receiver 375 of the I/O circuit 203 can amplify the signal to its output S_Data_in, which can be transmitted to the input A0 of the other programmable logic block (LB) 201 via one or more of the programmable interconnect lines 361. -A3 one of them.

Referring to FIG. 8A, the standard commercial FPGAIC chip 200 further includes (1) a plurality of power pads 205, which can apply the power supply voltage Vcc through one or more fixed interconnecting wires 364 to the power supply voltage Vcc as described in FIG. 6A Memory cell 490 in look-up table (LUT) 201 of programmable logic block (LB) 201 and/or memory cell 362 for crosspoint switch 379 as depicted in FIGS. 7A-7C, where the power supply voltage Vcc can be between 0.2 volts and 2.5 volts, between 0.2 volts and 2 volts, between 0.2 volts and 1.5 volts, between 0.1 volts and 1 volts, between 0.2 volts and 1 volts or less than or equal to 2.5 volts, 2 volts, 1.8 volts, 1.5 volts or 1 volt; and (2) a plurality of ground pads 206, which can transmit the ground reference voltage Vss through one or more fixed interconnecting lines 364 to memory cells 490 for look-up table (LUT) 201 of programmable logic block (LB) 201 as depicted in Figure 6A and/or for crosspoint switch 379 as depicted in Figures 7A-7C The memory unit 362.

I. Setting of memory cells, multiplexers and pass/fail switches of standard commercial FPGAIC chips

Figures 8B to 8E illustrate memory cells (for look-up tables) and multiplexers for programmable logic blocks (LBs) and for programmable interconnects according to embodiments of the present application Schematic diagrams of various arrangements/layouts of memory cells of lines and pass/no switches. The pass/fail switch 258 may constitute the first and second type crosspoint switches 379 as shown in FIGS. 3A and 3B. The various arrangements/layouts are described below:

(1) The first arrangement/layout of memory cells, multiplexers and pass/fail switches of standard commercial FPGAIC chips

Referring to FIG. 8B , for each programmable logic block (LB) 201 of the standard commercial FPGAIC chip 200 , the memory cells 490 used for its look-up table 210 may be disposed on the semiconductor substrate 2 of the standard commercial FPGAIC chip 200 Its multiplexer 211 coupled with its memory cells 490 for its look-up table 210 can be disposed on a second region of the semiconductor substrate 2 of a standard commercial FPGAIC chip 200, wherein the first region is adjacent to the second region. Each programmable logic block (LB) 201 may include one or more multiplexers 211 and one or more sets of memory cells 490, each set of memory cells 490 for one of the look-up tables 210 and coupled to One of the inputs D0-D15 of the first group of the multiplexer 211, each of the memory cells 490 of each group can store one of the result value of the one of the look-up table 210 or the programming code, and its output can be coupled to To one of the inputs D0-D15 of the first group of the one of the multiplexers 211.

Referring to FIG. 8B, a group of memory cells 362 for programmable interconnection lines 361 as described in FIG. 7A may be arranged in one or more lines between two adjacent programmable logic blocks (LB) 201 , a set of pass/no-pass switches 258 for programmable interconnection lines 361 as described in FIG. 7A can be arranged between two adjacent programmable logic blocks (LB) 201 into one or more lines, a set of The pass/no switch 258 cooperates with a set of memory cells 362 to form a crosspoint switch 379 as described in FIG. 3A or 3B, each of which can be coupled to the pass/no switch 258 of each set. One or more of the memory units 362.

(2) The second arrangement/layout of memory cells, multiplexers and pass/fail switches of standard commercial FPGAIC chips

Referring to FIG. 8C, for a standard commercial FPGAIC chip 200, the memory cells 490 for all of its look-up tables 210 and the memory cells 362 for all of its programmable interconnect lines 361 can be collectively disposed on its semiconductor substrate 2 Within the memory array block 395 in the middle area. For the same programmable logic block (LB) 201, the memory cells 490 for its one or more look-up tables 210 and its one or more multiplexers 211 are arranged in separate areas, one of which is houses memory cells 490 for one or more of its look-up tables 210, while another area therein houses one or more of its multiplexers 211 for pass/no-pass switches for its programmable interconnect lines 361 258 is arranged in one or more lines between the multiplexers 211 of two adjacent programmable logic blocks (LB) 201 .

(3) The third arrangement/layout of memory cells, multiplexers and pass/no pass switches of standard commercial FPGA IC chips

Referring to FIG. 8D, for a standard commercial FPGAIC chip 200, the memory cells 490 for all of its look-up tables 210 and the memory cells 362 for all of its programmable interconnect lines 361 can be collectively disposed on its semiconductor substrate 2 Within the memory array blocks 395a and 395b in separate intermediate regions. For the same programmable logic block (LB) 201, the memory cells 490 for its one or more look-up tables 210 and its one or more multiplexers 211 are arranged in separate areas, one of which is houses memory cells 490 for one or more of its look-up tables 210, while another area therein houses one or more of its multiplexers 211 for pass/no-pass switches for its programmable interconnect lines 361 258 is arranged in one or more lines between the multiplexers 211 of two adjacent programmable logic blocks (LB) 201 . For a standard commercial FPGAIC chip 200, some of its multiplexers 211 and some of its pass/fail switches 258 are provided between memory array blocks 395a and 395b.

(4) The fourth arrangement/layout of memory cells, multiplexers and pass/no pass switches of standard commercial FPGA IC chips

Referring to FIG. 8E, for a standard commercial FPGAIC chip 200, the memory cells 362 for its programmable interconnection lines 361 can be collectively arranged in the memory array block 395 in the middle region on the semiconductor substrate 2 thereof, and Can be coupled to (1) its first plurality of pass/no switches 258 located on its semiconductor substrate 2, each of the first plurality of pass/no switches 258 being located in the same row of its programmable Logic block (LB) 201 between two adjacent ones or between its programmable logic block (LB) 201 and its memory array block 395 in the same column; coupled to (2) its semiconductor The pass/no switches 258 of the plurality of second groups on the substrate 2, each of the pass/no switches 258 of the plurality of second groups is located adjacent to its programmable logic block (LB) 201 in the same row between two or between its programmable logic block (LB) 201 and its memory array block 395 in the same row; and coupled to (3) its plurality of thirds on its semiconductor substrate 2 The pass/no switch 258 of the group, and each of the pass/no switches 258 of the plurality of third groups are located in the same row of the pass/no switches 258 of the first group, wherein two adjacent ones are located between and in the same column. The pass/fail switches 258 of the second group are between two adjacent ones. For a standard commercial FPGA IC chip 200, each programmable logic block (LB) 201 may include one or more multiplexers 211 and one or more sets of memory cells 490, each set of memory cells 490 is used for One of the look-up tables 210 is coupled to the inputs D0-D15 of the first group of one of the multiplexers 211, and each of the memory cells 490 of each group can store the result value or the programming code of the one of the look-up tables 210 One of them, and its output can be coupled to one of the inputs D0-D15 of the first group of the one of the multiplexers 211, as described in FIG. 8B.

(5) The fifth arrangement/layout of memory cells, multiplexers and pass/no pass switches of standard commercial FPGA IC chips

Referring to FIG. 8F, for a standard commercial FPGAIC chip 200, the memory cells 362 for its programmable interconnection lines 361 can be collectively arranged in a plurality of memory array blocks 395 on its semiconductor substrate 2, and can be coupled to (1) its plurality of first groups of pass/fail switches 258 located on its semiconductor substrate 2, each of the plurality of first group of pass/no pass switches 258 being located in the same row of its programmable logic The block (LB) 201 is between two adjacent ones or between its programmable logic block (LB) 201 and its memory array block 395 in the same column; coupled to (2) its semiconductor substrate The pass/no switches 258 of the plurality of second groups on the 2nd group, each of the pass/no switches 258 of the plurality of second groups is located in its programmable logic block (LB) 201 in the same row, two adjacent ones of which are located in the same row. between its programmable logic block (LB) 201 and its memory array block 395 in the same row; and coupled to (3) its plurality of third groups on its semiconductor substrate 2 Each of the pass/no switches 258 of the third group is located in the same row of the pass/no switches 258 of the first group, which are located between two adjacent ones and in the same column. The pass/no pass switch 258 of the two groups is between two adjacent ones. For a standard commercial FPGA IC chip 200, each programmable logic block (LB) 201 may include one or more multiplexers 211 and one or more sets of memory cells 490, each set of memory cells 490 is used for One of the look-up tables 210 is coupled to the inputs D0-D15 of the first group of one of the multiplexers 211, and each of the memory cells 490 of each group can store the result value or the programming code of the one of the look-up tables 210 One of them, and its output can be coupled to one of the inputs D0-D15 of the first group of the one of the multiplexers 211, as described in FIG. 8B. In addition, one or more programmable logic blocks (LBs) 201 may be provided between the memory array blocks 395 .

(6) Memory cells for the first to fifth arrangements/layouts

Referring to FIGS. 8B-8F, for a standard commercial FPGAIC chip 200, each of the memory cells 490 for its look-up table 210 may be an on-chip volatile memory cell, as shown in FIG. 1A or FIG. The memory unit 398 depicted in Fig. 1B, and the generated output Out1 or Out2 can be coupled to one of the inputs D0-D15 of the first group of the multiplexer 211, as described in Figs. 6A to 6E , or an on-chip non-volatile memory cell, such as a floating-gate non-volatile memory cell, a magnetoresistive random access memory (MRAM) IC chip or a resistive random access memory ( Resistive random access memory (RRAM) IC chip, Phase Change Random Access Memory (Phase Change Random Access Memory) IC chip or Ferroelectric Random Access Memory (FRAM) IC chip, wherein the multiplexer 211 can be as shown in FIG. 4A to FIG. 4J The described first to third type multiplexers 211; each of the memory cells 362 for its programmable interconnection lines 361 may also refer to the memory cells 398 as described in FIG. 1A or 1B, so The resulting outputs Out1 and/or Out2 may be coupled to their pass/fail switches 258, as described in Figure 7A, which may be of the first type as described in Figures 2A-2F To the sixth type pass/fail switch 258 .

II. SETTING OF BYPASS INTERCONNECTION LINES FOR STANDARD COMMERCIAL FPGAIC DIGITS

FIG. 8G is a schematic diagram of a programmable interconnection line as a bypass interconnection line according to an embodiment of the present application. Referring to FIG. 8G, a standard commercial FPGA IC chip 200 may include a first set of programmable interconnect lines 361 as bypass interconnect lines 279, each of which may connect one of the cross-point switches 379 to another remote cross-point The switch 379 bypasses one or more other cross-point switches 379. The cross-point switches 379 may be any of the first to fourth types shown in FIGS. 3A to 3D. A standard commercial FPGA IC chip 200 may include a second set of programmable interconnects 361 that do not bypass any cross-point switches 379, and each bypass interconnect 279 is parallel to a plurality of pass-through cross-point switches 379 A second set of programmable interconnect lines 361 are coupled to each other.

For example, the nodes N23 and N25 of the cross-point switch 379 as described in FIGS. 3A to 3C can be respectively coupled to the programmable interconnection lines 361 of the second group, and the nodes N24 and N26 thereof can be respectively coupled to the detours cross-connect line 279, so crosspoint switch 379 can be selected from two detour cross-connect lines 279 coupled to its nodes N24 and N26 and two second set of programmable cross-connect lines 361 coupled to its nodes N23 and N25 One of them is coupled to the other one or more of them. Thus, the cross-point switch 379 can be toggled to select the detour cross-connect line 279 coupled to its node N24 to the second set of programmable cross-connect lines 361 coupled to its node N23; alternatively, the cross-point switch 379 Can be toggled to select a second set of programmable interconnect lines 361 coupled to its node N23 to a second set of programmable interconnect lines 361 coupled to its node N25; alternatively, the cross point switch 379 can be toggled To select the detour interconnect 279 coupled to its node N24 is coupled to the detour interconnect 279 coupled to its node N26.

Or, for example, each of the nodes N23-N26 of the cross-point switch 379 as described in FIGS. 3A-3C may be coupled to the second set of programmable interconnect lines 361, so the cross-point switch 379 can be connected from One of the four programmable interconnect lines 361 of the second group coupled to its nodes N23-N26 is selected to be coupled to the other one or more of them.

Referring to FIG. 8G, a plurality of cross-point switches 379 may be disposed around a region 278 in which are disposed a plurality of memory cells 362, each of which may be an on-chip volatile memory cell, as shown in FIG. The memory cell 398 disclosed in Fig. 1A or Fig. 1B, and the output Out1 and/or Out2 of each of which may be coupled to one of the plurality of cross-point switches 379, as described in Figs. 7A-7C , or on-chip non-volatile memory cells, such as floating gate non-volatile memory cells, MRMIC chips, phase change random access memory IC chips, RRMIC chips or FRMIC chips. Also disposed in this area 278 are a plurality of memory cells 490 for the look-up table 210 of the programmable logic block (LB) 201, each of which may be an on-chip volatile memory cell, as shown in Figure 1A or Figure 1B The exposed memory cells 398, and the output Out1 and/or Out2 of each of them may be coupled to the first set of inputs D0- One of D15, as described in Figures 6A to 6E, or an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell, MRMIC chip, phase change random access memory IC chip, RRMIC chip or FRMIC chip. The memory cells 362 for the crosspoint switches 379 are wrapped around the programmable logic block (LB) 201 in a pattern of one or more rings. A plurality of the second set of programmable interconnect lines 361 around the region 278 may couple a plurality of crosspoint switches 379 around the region 278 to one of the multiplexers 211 of the programmable logic block (LB) 201 The inputs A0-A3 of the second group, and the other one of the programmable interconnect lines 361 of the second group around the area 278 can be coupled to the output Dout of the multiplexer 211 of the programmable logic block (LB) 201 to Another crosspoint switch 379 around the area 278.

Therefore, please refer to FIG. 8G, wherein the output Dout of the multiplexer 211 of one programmable logic block (LB) 201 may (1) alternately pass through one or more programmable interconnect lines 361 of the second group and One or more cross-point switches 379 are sent to one of the detour cross-connect lines 279, (2) then alternately pass through one or more cross-point switches 379 and one or more bypass cross-connect lines 279 from one of the detour cross-connect lines 279. Bypass cross-connect line 279 to another programmable cross-connect line 361 of the second group, and (3) finally pass through one or more cross-point switches 379 and one or more programmable cross-connect lines 379 in turn The interconnection line 361 is transmitted from the programmable interconnection line 361 of the second group of the other one to one of the inputs A0-A3 of the second group of the multiplexer 211 of the other programmable logic block (LB) 201 .

III. SETTINGS OF CROSSPOINT SWITCHES FOR STANDARD COMMERCIAL FPGAIC DIE

FIG. 8H is a schematic diagram of a cross-point switch arrangement of a standard commercial FPGA IC chip depicted in accordance with an embodiment of the present application. Referring to FIG. 8H, a standard commercial FPGA IC chip 200 may include: (1) programmable logic blocks (LB) 201 arranged in a matrix; (2) a plurality of connection blocks (CB) 455, each of which is located in Between two adjacent programmable logic blocks (LB) 201 in the same row or the same row; and (3) a plurality of switch blocks (SB) 456, each of which is arranged in the same row or the same row phase Between two adjacent connecting blocks (CBs) 455. Each connection block (CB) 455 may be provided with a plurality of fourth type cross point switches 379 as shown in FIGS. 3D and 7C, and each switch block (SB) 456 may be provided with A plurality of third-type cross-point switches 379 are shown in FIG. 7B.

Referring to FIG. 8H, for each connection block (CB) 455, each of the inputs D0-D15 of each fourth-type crosspoint switch 379 is coupled to one of the programmable interconnection lines 361, and its The output Dout is coupled to the other of the programmable interconnect lines 361 . The programmable interconnection line 361 can be coupled to one of the inputs D0-D15 of the fourth-type crosspoint switch 379 of the connection block (CB) 455 as shown in FIG. 3D and FIG. 7C to (1) as shown in FIG. 6A The output Dout of the programmable logic block (LB) 201 shown in the figure, or to (2) the switch block (SB) 456 is a third-type crosspoint switch as shown in Figures 3C and 7B One of the nodes N23-N26 of 379. Alternatively, the programmable interconnection line 361 can be coupled to the output Dout of the fourth type cross point switch 379 of the connection block (CB) 455 as shown in FIG. 3D and FIG. 7C to (1) as shown in FIG. 6A One of the inputs A0-A3 of the programmable logic block (LB) 201 shown, or to (2) the switch block (SB) 456, a third-type crossover as shown in Figures 3C and 7B One of the nodes N23-N26 of the switch 379 is turned on.

For example, referring to Fig. 8H, one or more of the inputs D0-D15 of the crosspoint switch 379 of the connection block (CB) 455 as depicted in Figs. 3D and 7C may be interconnected through programmable interconnects One or more of the lines 361 are coupled to the output Dout of the programmable logic block (LB) 201 as shown in FIG. 6A on the first side thereof, and are connected to the block (CB) 455 as shown in FIG. 3D and One or more of the inputs D0-D15 of the cross-point switch 379 shown in FIG. 7C can be coupled on the second side of the cross-point switch 379 through the programmable interconnection line 361 on the second side thereof relative to the first side thereof. The output Dout of the programmable logic block (LB) 201 as shown in Figure 6A is connected to the input D0- of the crosspoint switch 379 of the connection block (CB) 455 as shown in Figures 3D and 7C One or more of D15 can be coupled to the switch block (SB) 456 on the third side thereof through the programmable interconnection line 361 one or more of the intersections as shown in FIGS. 3C and 7B One of the nodes N23-N26 of the point switch 379 is connected to the input D0-D15 of the cross-point switch 379 of the block (CB) 455 as shown in FIG. 3D and FIG. 7C, and the other or more of them can be programmed through One or more of the interconnection lines 361 are coupled to the switch block (SB) 456 located on its fourth side relative to its third side to the cross-point switch 379 as shown in FIGS. 3C and 7B. One of nodes N23-N26. The output Dout of the crosspoint switch 379 of the connection block (CB) 455 as shown in FIG. 3D and FIG. 7C can be coupled to the third side or the fourth side thereof through one of the programmable interconnection lines 361 One of the nodes N23-N26 of the cross-point switch 379 of the switch block (SB) 456 as shown in FIGS. 3C and 7B, or one of the programmable interconnect lines 361 is coupled on its first side Or one of the inputs A0-A3 of the programmable logic block (LB) 201 on the second side as shown in FIG. 6A.

Referring to FIG. 8H, for each switch block (SB) 456, the four nodes N23-N26 of the third-type crosspoint switch 379 shown in FIGS. 3C and 7B can be respectively coupled to one by one. Programmable interconnect lines 361 in four different directions. For example, the node N23 of the third-type cross-point switch 379 shown in FIGS. 3C and 7B of each switch block (SB) 456 can be connected via one of the four programmable interconnect lines 361 One of the inputs D0-D15 or the output Dout of the fourth-type crosspoint switch 379 as shown in FIG. 3D and FIG. 7C coupled to the connection block (CB) 455 on its left side, each switch is The node N24 of the third-type crosspoint switch 379 of the block (SB) 456 as shown in FIG. 3C and FIG. 7B can be coupled to the connection on the upper side thereof via the other one of the four programmable interconnection lines 361 One of the inputs D0-D15 of the fourth type cross-point switch 379 as shown in FIG. 3D and FIG. 7C of the block (CB) 455 or its output Dout, each switch block (SB) 456 has As shown in FIGS. 3C and 7B, the node N25 of the third-type cross-point switch 379 can be coupled to the connection block (CB) 455 on the right side of the four programmable interconnection lines 361 through the other one. As shown in FIG. 3D and FIG. 7C, one of the inputs D0-D15 of the fourth-type crosspoint switch 379 or its output Dout, and each switch block (SB) 456 is as shown in FIGS. 3C and 7C. The node N25 of the third-type cross-point switch 379 shown in FIG. 7B can be coupled to the connecting block (CB) 455 on the lower side of the four programmable interconnection lines 361 through the other one as shown in FIG. 3D and One of the inputs D0-D15 of the fourth-type cross-point switch 379 shown in FIG. 7C or its output Dout.

Therefore, referring to FIG. 8H, a signal can be transmitted from one of the programmable logic blocks (LB) 201 to the other of the programmable logic blocks (LB) 201 through a plurality of switch blocks (SB) 456, A connection block (CB) 455 is provided between each adjacent two of the switch blocks (SB) 456 for the signal transmission, and a programmable logic block (LB) located in one of the plurality of switch blocks (SB) 456 There is a connection block (CB) 455 between 201 and one of the plurality of switch blocks (SB) 456 for the transmission of the signal, and the programmable logic block (LB) 201 located in the other one is connected to A connection block (CB) 455 is provided between one of the plurality of switch blocks (SB) 456 for the signal transmission. For example, the signal may be transmitted from the output Dout of the one of the programmable logic blocks (LB) 201 as shown in FIG. 6A to the first connection area via one of the programmable interconnect lines 361 One of the inputs D0-D15 of the fourth type cross-point switch 379 of block (CB) 455 as shown in Fig. 3D and Fig. 7C, and then the first connecting block (CB) 455 as shown in Fig. 3D The fourth-type cross-point switch 379 shown in FIG. 7C can switch one of the inputs D0-D15 to be coupled to its output Dout for the transmission of the signal, so that the signal can be transmitted from its output through the other The programmable interconnect 361 is routed to node N23 of the third type crosspoint switch 379 as shown in Figures 3C and 7B of one of the switch blocks (SB) 456, followed by the one of the switch blocks The third type crosspoint switch 379 of (SB) 456 as shown in Figures 3C and 7B can switch its node N23 to be coupled to its node N25 for the transmission of the signal, so that the signal can pass from its node N25 through One of the programmable interconnection lines 361 of the other one is transmitted to one of the inputs D0-D15 of the fourth-type cross-point switch 379 as shown in FIG. 3D and FIG. 7C of the second connection block (CB) 455 , then the fourth-type cross-point switch 379 of the second connection block (CB) 455 as shown in FIG. 3D and FIG. 7C can switch one of the inputs D0-D15 to be coupled to its output Dout For the transmission of the signal so that the signal can be transmitted from its output through the programmable interconnection line 361 of the other one to the input of the other programmable logic block (LB) 201 as shown in FIG. 6A One of A0-A3.

IV. Repair of standard commercial FPGAIC chips

FIG. 8I is a schematic diagram of a commercialized FPGAIC chip according to the repair standard shown in the embodiment of the present application. Referring to Figure 8I, a standard commercial FPGAIC die 200 has programmable logic blocks (LBs) 201, of which a spare one 201-s can replace a broken one. A standard commercial FPGAIC chip 200 includes: (1) a plurality of repair input switch arrays 276, wherein each of the plurality of outputs of each is coupled in series to a programmable logic block ( One of the inputs A0-A3 of LB) 201; and (2) a plurality of repair output switch arrays 277, wherein one or more inputs of each of them are respectively coupled in series one-to-one to the one shown in FIG. 6A Output Dout of one or more programmable logic blocks (LB) 201 . In addition, the standard commercial FPGA IC chip 200 also includes: (1) a plurality of spare repair input switch arrays 276-s, wherein each of the plurality of outputs of each is coupled in parallel to each of the other spare repair input switch arrays 276-s one of the outputs of the input switch array 276-s, coupled in series to one of the inputs A0-A3 of the programmable logic block (LB) 201 as shown in FIG. 6A; and (2) a plurality of spares The repair output switch array 277-s, wherein one or more inputs of each are coupled in parallel to one or more inputs of each of the other spare repair output switch arrays 277-s, respectively one or more. An output Dout coupled in series to one or more of the programmable logic blocks (LB) 201 as shown in FIG. 6A. Each spare repair input switch array 276-s has a plurality of inputs, each of which is coupled in parallel with one of the inputs of one of the repair input switch arrays 276. Each spare repair output switch array 277-s has one or more outputs, which are respectively coupled to one or more outputs of one of the repair output switch arrays 277 in parallel one by one.

Therefore, referring to FIG. 8I, when one of the programmable logic blocks (LB) 201 is damaged, one of the inputs and outputs of the programmable logic blocks (LB) 201 respectively coupled to the one of the programmable logic blocks (LB) 201 can be turned off The repair input switch array 276 and the repair output switch array 277 of one of them are turned on, and the standby repair input switch array 276 having the inputs of the repair input switch array 276 whose inputs are respectively coupled in parallel one-to-one -s, turn on the spare repair output switch array 277-s having outputs coupled to the outputs of the one of the repair output switch arrays 277 in parallel, and turn off the other spare repair input switch arrays 276-s And a spare repair output switch array 277-s. In this way, the spare programmable logic block (LB) 201-s can replace one of the defective programmable logic blocks (LB) 201 .

FIG. 8J is a schematic diagram of a commercialized FPGAIC chip according to the repair standard shown in the embodiment of the present application. Please refer to FIG. 8J, the programmable logic blocks (LB) 201 are arranged in the form of an array. When one of the programmable logic blocks (LB) 201 whose bits are on one of the rows is broken, all the programmable logic blocks (LB) 201 whose bits are on one of the rows are turned off, and the LBs 201 whose bits are on one of the rows are turned on. All spare programmable logic blocks (LBs) 201-s. Next, the row numbers of the programmable logic block (LB) 201 and the spare programmable logic block (LB) 201-s will be renumbered, and the row numbers of the renumbered programmable logic blocks in each row and column after repairing are renumbered. The operation performed by (LB) 201 is the same as that performed by the programmable logic block (LB) 201 of each row with the same row number and each column with the same column number without renumbering before repairing. For example, when one of the programmable logic blocks (LB) 201 in row N-1 is broken, all programmable logic blocks (LB) 201 in row N-1 are turned off, The turn-on bits are in all spare programmable logic blocks (LBs) 201-s in the rightmost row. Next, the row numbers of the programmable logic block (LB) 201 and the spare programmable logic block (LB) 201-s will be renumbered, and set for all the spare programmable logic block (LB) 201-s before repairing The rightmost row will be renumbered as row 1 after the repair of the programmable logic block (LB) 201, and the first row for the programmable logic block (LB) 201-s set before repair is in the repaired programmable logic block (LB) 201-s. (LB) 201 will be renumbered to line 2, and so on. The n-2th row set for the programmable logic block (LB) 201-s before repair will be renumbered to the n-1th row after the programmable logic block (LB) 201 is repaired, where n is between 3 an integer to N. The operation performed by the programmable logic block (LB) 201 of each column of the m-th row with the renumbered row number after the repair is the same as the operation performed by the m-th row of the un-renumbered row number and each column with the same column number before the repair. The operations performed by the programmable logic block (LB) 201 , where m is an integer between 1 and N. For example, the operation performed by the programmable logic block (LB) 201 in each column of the 1st row with renumbered row numbers after repair is the same as that of the 1st row without renumbered row numbers and the same column number as before the repair. The operation performed by the programmable logic block (LB) 201 of each column.

Description of Integrated Circuit (IC) Chips for Dedicated Programmable-Interconnection (DPI)

FIG. 9 is a top view of an integrated circuit (IC) chip dedicated to programmable interconnection (DPI) according to an embodiment of the present application. Referring to FIG. 9, an integrated circuit (IC) chip 410 dedicated to programmable interconnect (DPI) is designed and fabricated using more advanced semiconductor technology generations, such as 30nm, 20nm or 10nm advanced or less than or equal to The process, because of the use of mature semiconductor technology generations, can optimize the chip size and manufacturing yield while pursuing the minimization of manufacturing costs. The area of the integrated circuit (IC) chip 410 dedicated to programmable interconnect (DPI) is between 400mm ² to 9mm ² , 225mm ² to 9mm ² , 144mm ² to 16mm ² , between 100mm ² and 16mm ² , between 75mm ² and 16mm ² or between 50mm ² and 16mm ² . The transistor or semiconductor device used in the integrated circuit (IC) chip 410 dedicated to programmable interconnect (DPI) of the generation of advanced semiconductor technology can be a fin field effect transistor (FINFET), a fin with long silicon on an insulating layer Type field effect transistor (FINFETSOI), full depletion type field effect transistor with silicon-on-insulator metal oxide semiconductor (FDSOIMOSFET), semi-depletion type field effect transistor with silicon-on-insulator metal oxide semiconductor field effect transistor (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor.

Referring to FIG. 9A, since the integrated circuit (IC) chip 410 dedicated to programmable interconnect (DPI) is a standard commercial IC chip, the integrated circuit (IC) dedicated to programmable interconnect (DPI) Chips 410 need only be reduced in at least a few types, so that the number of expensive masks or mask sets required for integrated circuit (IC) chips 410 dedicated to Programmable Interconnection (DPI) to be manufactured using advanced semiconductor technology generations is reduced in number can be reduced, the mask set for a semiconductor technology generation can be reduced to between 3 sets to 20 sets, 3 sets to 10 sets, or 3 sets to 5 sets, the one-time engineering cost (NRE) will also be greatly reduced. Since there are few types of integrated circuit (IC) chips 410 dedicated to programmable interconnect (DPI), the fabrication process can be optimized to achieve very high throughput of fabricated chips. Furthermore, the inventory management of the chips can be simplified to achieve the goals of high performance and high efficiency, so the lead time of the chips can be shortened, which is very cost-effective.

Referring to FIG. 9, various types of integrated circuit (IC) chips 410 dedicated to programmable interconnect (DPI) include: (1) a plurality of memory array blocks 423, which are arranged in an array in the middle area thereof (2) a plurality of sets of cross-point switches 379, as described in Figures 3A to 3D, wherein each set surrounds one of the memory array blocks 423 in a pattern of one or more rings; and (3) A plurality of small I/O circuits 203, as described in FIG. 5B, each of the outputs S_Data_in is coupled to one of them via the programmable interconnection lines 361 as shown in FIG. 3A to FIG. 3C, One of the nodes N23-N26 of the cross-point switch 379 shown in FIGS. 7A and 7B may be coupled to one of the inputs D0-D16 of the cross-point switch 379 shown in FIGS. 3D and 7C. One, the output S_Data_out of each is coupled to the other one of the nodes of the cross-point switch 379 as shown in FIGS. 3A-3C, 7A, and 7B via programmable interconnect lines 361 One of N23-N26 is either coupled to the output Dout of the other cross-point switch 379 as shown in FIG. 3D and FIG. 7C. In each memory array block 423, there are a plurality of memory cells 362, each of which may be an on-chip volatile memory cell, such as the memory cell 398 shown in FIG. 1A or FIG. 1B, which The output Out1 and/or Out2 of each is coupled to one of the pass/fail switches 258 of the cross-point switch 379 located near the memory array block 423 of each, as shown in FIGS. 3A , 3B and 7A What is described, or on-chip non-volatile memory cells, such as floating gate non-volatile memory cells, MRMIC chips, phase-change random access memory IC chips, RRMIC chips, or FRMIC chips; or, its The output Out1 or Out2 of each is coupled to the second set of inputs A0 and A1 of the multiplexer 211 of the cross-point switch 379 located near the memory array block 423 of the each and the input SC- of the multiplexer 211 4. One of them, as described in Figures 3C and 7B; alternatively, the output Out1 or Out2 of each is coupled to the multiplexing of the cross-point switch 379 located near the memory array block 423 of each One of the inputs A0-A3 of the second group of the device 211, as described in FIG. 3D and FIG. 7C.

Referring to FIG. 9, the DPIIC chip 410 includes a plurality of intra-chip interconnection lines (not shown), each of which may extend in the upper space between two adjacent memory array blocks 423, and may be as shown in FIG. 7A Programmable interconnection lines 361 or fixed interconnection lines 364 depicted in FIGS. 7C through 7C. Each output S_Data_in of the small I/O circuits 203 of the DPIIC chip 410 as depicted in FIG. 5B is coupled to one or more programmable interconnect lines 361 and/or one or more fixed interconnect lines 364 , each of whose inputs S_Data_out, S_Enable or S_Inhibit are coupled to one or more other programmable interconnect lines 361 and/or one or more other fixed interconnect lines 364 .

Referring to FIG. 9, the DPIIC chip 410 may include a plurality of I/O pads 372, as described in FIG. 5B, each of which is disposed vertically above one of the small I/O circuits 203 and connects to the Node 381 of one of the small I/O circuits 203 . In the first clock, the signal from one of the nodes N23-N26 of the cross-point switch 379 as shown in FIGS. 3A to 3C, 7A and 7B, or as shown in FIGS. 3D and 7B The output Dout of the cross-point switch 379 shown in FIG. 7C can be transmitted to the input S_Data_out of the small driver 374 of one of the small I/O circuits 203 through one or more of the programmable interconnect lines 361, one of the The small driver 374 of the small I/O circuits 203 can amplify its input S_Data_out to the I/O pads 372 located vertically above the one of the small I/O circuits 203 for transmission to circuits outside the DPIIC chip 410 . In the second clock, signals from circuits external to the DPIIC chip 410 can be transmitted via the I/O pads 372 to the small receiver 375 of the one of the small I/O circuits 203, the one of the small I/O The small receiver 375 of the circuit 203 can amplify the signal to its output S_Data_in, which can be transmitted to others such as Figures 3A to 3C, Figure 7A and Figure 7B via one or more of the programmable interconnect lines 361. One of the nodes N23-N26 of the cross-point switch 379 shown in the figure, or may be transmitted to one of the inputs D0-D15 of the other cross-point switch 379 as shown in FIGS. 3D and 7C. Referring to FIG. 9 , the DPIIC chip 410 further includes (1) a plurality of power supply pads 205 , which can apply the power supply voltage Vcc to the power supply voltage Vcc as described in FIGS. 7A to 7C through one or more fixed interconnecting lines 364 The memory cell 362 for the crosspoint switch 379, wherein the power supply voltage Vcc can be between 0.2 volts to 2.5 volts, between 0.2 volts and 2 volts, between 0.2 volts and 1.5 volts, between between 0.1 volts and 1 volts, between 0.2 volts and 1 volts, or less than or equal to 2.5 volts, 2 volts, 1.8 volts, 1.5 volts, or 1 volt; and (2) a plurality of ground pads 206, accessible via One or more fixed interconnect lines 364 transmit the ground reference voltage Vss to the memory cell 362 for the crosspoint switch 379 as described in FIGS. 7A-7C.

Description of chips dedicated to input/output (I/O)

FIG. 10 is a block diagram of an input/output (I/O) dedicated chip depicted in accordance with an embodiment of the present application. Referring to FIG. 10, a chip 265 dedicated to input/output (I/O) includes a plurality of large I/O circuits 341 (only one of which is shown) and a plurality of small I/O circuits 203 (only one of which is shown) ). The large I/O circuit 341 can refer to the content described in FIG. 5A, and the small I/O circuit 203 can refer to the content described in FIG. 5B.

5A, 5B and 10, the input L_Data_out of the large driver 274 of each large I/O circuit 341 is coupled to the output S_Data_in of the small receiver 375 of one of the small I/O circuits 203. The output L_Data_in of the large receiver 275 of each large I/O circuit 341 is coupled to the input S_Data_out of the small driver 374 of one of the small I/O circuits 203 . When the signal (L_Enable) is used to enable the large driver 274 and the signal (S_Inhibit) is used to enable the small receiver 375, the signal (L_Inhibit) is used to inhibit the large receiver 275 and the signal (S_Enable) is used to disable the small driver 374 at the same time. Time data can be transmitted from the I/O pad 372 of the small I/O circuit 203 to the I/O pad 272 of the large I/O circuit 341 through the small receiver 375 and the large driver 274 in sequence. When the signal (L_Inhibit) is used to enable the large receiver 275 and the signal (S_Enable) is used to enable the small driver 374, the signal (L_Enable) is used to disable the large driver 274 and the signal (S_Inhibit) is used to inhibit the small driver 375 at the same time. Data can be transferred from the I/O pads 272 of the large I/O circuit 341 to the I/O pads 372 of the small I/O circuit 203 through the large receiver 275 and the small driver 374 in sequence.

Description of logical drives

Various standard commercial logic drivers (also called logic operation package structures, logic operation package drivers, logic operation devices, logic operation modules, logic operation disks or logic operation disk drivers, etc.) are introduced as follows:

I. Type 1 logical drive

FIG. 11A is a schematic top view of a first type standard commercial logic driver according to an embodiment of the present application. Referring to FIG. 11A, a standard commercial logic driver 300 may be packaged with a plurality of standard commercial FPGA IC chips 200 as described in FIGS. 8A-8J, one or more non-volatile memory (NVM) ICs A circuit (IC) chip 250 and a dedicated control chip 260 are arranged in an array, wherein the dedicated control chip 260 is composed of a standard commercial FPGA IC chip 200 and a non-volatile memory (NVM) integrated circuit (IC) chip 250. Surrounded by and may be located between non-volatile memory (NVM) integrated circuit (IC) chips 250 and/or between standard commercial FPGA IC chips 200 . A non-volatile memory (NVM) integrated circuit (IC) chip 250 located in the right middle of the logic driver 300 may be disposed between two standard commercial FPGA IC chips 200 located on the upper and lower right sides of the logic driver 300 . Several of the standard commercial FPGA IC chips 200 may be arranged in a line above the logic driver 300 .

Referring to FIG. 11A , the logic driver 300 may include a plurality of inter-die interconnection lines 371 , each of which may be above between adjacent two of the standard commercial FPGAIC die 200 , the NVMIC die 250 and the dedicated control die 260 . extend in space. The logic driver 300 may include a plurality of DPIIC chips 410 aligned at the intersections of a vertically extending bundle of inter-wafer interconnect lines 371 and a horizontally extending bundle of inter-wafer interconnect lines 371, surrounding corners of each DPIIC chip 410 There are four standard commercial FPGAIC chips 200 , NVMIC chips 250 and special control chips 260 in the system. For example, the shortest distance between the first DPIIC die 410 located at the upper left corner of the dedicated control die 260 and the first standard commercial FPGAIC die 200 located at the upper left corner of the first DPIIC die 410 is is the distance between the lower right corner of the first standard commercial FPGAIC die 200 and the upper left corner of the first DPIIC die 410 ; The shortest distance between a standard commercial FPGAIC chip 200 is the distance between the lower left corner of the second standard commercial FPGAIC chip 200 and the upper right corner of the first DPIIC chip 410; The shortest distance between the NVMIC chips 250 at the lower left corner of the first DPIIC chip 410 is the distance between the upper right corner of the NVMIC chip 250 and the lower left corner of the first DPIIC chip 410; The shortest distance between the dedicated control chips 260 at the lower right corner of the first DPIIC chip 410 is the distance between the upper left corner of the dedicated control chip 260 and the lower right corner of the first DPIIC chip 410 .

Referring to FIG. 11A, each inter-chip interconnection line 371 may be a programmable interconnection line 361 or a fixed interconnection line 364 as described in FIGS. 7A to 7C, and refer to the aforementioned “Programmable Interconnection Line 364” "Description of Connecting Lines" and "Description of Fixed Interchangeable Connecting Lines". Signals can be transmitted (1) via the small I/O circuits 203 of the standard commercial FPGAIC chip 200 , the programmable interconnect wires 361 of the inter-chip interconnect wires 371 and the intra-chip interconnect wires 502 of the standard commercial FPGA IC chip 200 or (2) through the small I/O circuit 203 of the DPIIC chip 410, the programmable interconnection line 361 of the inter-chip interconnection line 371 and the in-chip interconnection of the DPIIC chip 410 Programmable interconnection of lines is made between lines 361 . The transmission of the signal can be (1) through the small I/O circuit 203 of the standard commercial FPGAIC chip 200, between the fixed inter-chip interconnect 364 of the inter-chip interconnect 371 and the intra-chip interconnect 502 of the standard commercial FPGA IC chip 200. Or (2) through the small I/O circuit 203 of the DPIIC chip 410, the fixed interconnection line 364 of the inter-chip interconnection line 371 and the intra-chip interconnection line of the DPIIC chip 410 are fixed Interconnection between lines 364 takes place.

Referring to FIG. 11A, each standard commercial FPGAIC chip 200 can be coupled to all DPIIC chips 410 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371. A standard commercial FPGA IC chip 200 can be coupled to a dedicated control chip 260 through one or more inter-chip interconnect lines 371, programmable interconnect lines 361 or fixed interconnect lines 364, each of the standard commercial FPGA IC chips 200 Can be coupled to all NVMIC chips 250 through one or more programmable interconnects 361 or fixed interconnects 364 of inter-die interconnects 371, and each DPIIC die 410 can be interconnected through one or more inter-die interconnects The programmable interconnection lines 361 or fixed interconnection lines 364 of the lines 371 are coupled to all the NVMIC chips 250, and each NVMIC chip 250 can be connected through the programmable interconnection lines 361 of one or more inter-die interconnection lines 371 or The fixed interconnection line 364 is coupled to the dedicated control chip 260 .

Therefore, referring to FIG. 11A, the first programmable logic block 201 of the first standard commercialized FPGAIC chip 200 may be as described in FIG. 6A, and its output Dout may pass through one of the DPIIC chips The crosspoint switch 379 of 410 transmits to one of the inputs A0-A3 of the second programmable logic block 201 of the second standard commercial FPGAIC chip 200. Accordingly, the process of transmitting the output Dout of the first programmable logic block 201 to one of the inputs A0-A3 of the second programmable logic block 201 is sequentially through (1) the first standard The programmable interconnection lines 361 of the intra-chip interconnection lines 502 of the commercialized FPGAIC chip 200, (2) the programmable interconnection lines 361 of the inter-chip interconnection lines 371 of the first group, (3) the DPIIC chip of one of them The programmable interconnection lines 361 of the first group of intra-chip interconnection lines of 410, (4) the cross-point switch 379 of the one of the DPIIC chips 410, (5) of the second group of the one of the DPIIC chips 410 Programmable interconnection lines 361 of intra-chip interconnection lines, (6) programmable interconnection lines 361 of inter-chip interconnection lines 371 of the second set, and (2) chips of the second standard commercial FPGAIC chip 200 Programmable interconnect 361 within interconnect 502 .

Alternatively, referring to FIG. 11A, the first programmable logic block 201 of one of the standard commercial FPGAIC chips 200 may be as described in FIG. 6A, the output Dout of which may be via one of the DPIIC chips 410 The cross-point switch 379 is transmitted to one of the inputs A0-A3 of the second programmable logic block 201 of the one of the standard commercial FPGA IC chips 200. Accordingly, the process of transmitting the output Dout of the first programmable logic block 201 to one of the inputs A0-A3 of the second programmable logic block 201 sequentially passes through (1) the one of the criteria The programmable interconnection lines 361 of the first group of intra-chip interconnection lines 502 of the commercialized FPGAIC chip 200, (2) the programmable interconnection lines 361 of the inter-chip interconnection lines 371 of the first group, (3) the among (4) the cross-point switch 379 of the one of the DPIIC chips 410, (5) the one of the DPIIC chips 410 Programmable interconnect lines 361 of the second group of intra-chip interconnect lines, (6) programmable interconnect lines 361 of the second group of inter-die interconnect lines 371, and (7) a standard commercial FPGAIC of one of them Programmable interconnect lines 361 of the second set of intra-chip interconnect lines 502 of the chip 200 .

Referring to FIG. 11A, the logical driver 300 may include a plurality of dedicated I/O chips 265 located in the surrounding area of the logical driver 300, which surrounds the middle area of the logical driver 300, wherein the middle area of the logical driver 300 accommodates the Standard commercial FPGAIC die 200 , NVMIC die 321 , dedicated control die 260 and DPIIC die 410 . Each standard commercial FPGAIC die 200 may be coupled to all of the dedicated I/O die 265 via one or more inter-die interconnects 371, programmable interconnects 361 or fixed interconnects 364, each DPIIC Die 410 can be coupled to all of the dedicated I/O die 265 via one or more programmable interconnect lines 361 or fixed interconnect lines 364 of inter-die interconnect lines 371, and each NVMIC die 321 can be coupled to all of the dedicated I/O die 265 via one or more The programmable interconnect lines 361 or the fixed interconnect lines 364 of the inter-die interconnect lines 371 are coupled to all the dedicated I/O chips 265, and the dedicated control chips 260 can be connected via one or more inter-die interconnect lines 371. Program interconnect lines 361 or fixed interconnect lines 364 are coupled to all dedicated I/O chips 265 .

Referring to FIG. 11A , each standard commercial FPGAIC chip 200 can refer to the content disclosed in FIGS. 8A to 8J , and each DPIIC chip 410 can refer to the content disclosed in FIG. 9 .

Referring to FIG. 11A, each dedicated I/O chip 265 and dedicated control chip 260 can be designed and manufactured using older or more mature semiconductor technology generations, such as older than or greater than or equal to 40nm, 50nm, 90nm, 130nm , 250nm, 350nm or 500nm process. In the same logic driver 300, the semiconductor technology generation employed by each of the dedicated I/O die 265 and the dedicated control die 260 may be a higher generation of semiconductors than that employed by each of the standard commercial FPGAIC die 200 and each of the DPIIC die 410. Technology generations later or older than 1, 2, 3, 4, 5, or more than 5 generations.

Referring to FIG. 11A, the transistors or semiconductor elements used in each of the dedicated I/O chip 265 and the dedicated control chip 260 may be fully depleted type field effect transistors (FDSOI MOSFETs) with long silicon on insulating layers. ), a semi-depleted type of metal-oxide-semiconductor field effect transistor (PDSOIMOSFET) or a traditional metal-oxide-semiconductor field effect transistor. In the same logic driver 300, the transistors or semiconductor elements used for each of the dedicated I/O die 265 and the dedicated control die 260 may be different from the standard commercial FPGAIC die 200 used for each and the DPIIC die of each 410 transistors or semiconductor components. For example, in the same logic driver 300, the transistors or semiconductor elements used for each of the dedicated I/O chip 265 and the dedicated control chip 260 may be conventional metal-oxide-semiconductor field effect transistors, while those used for The transistors or semiconductor elements of each standard commercial FPGAIC die 200 and each DPIIC die 410 may be fin field effect transistors (FINFETs); or, in the same logic driver 300, for each dedicated I/ The transistors or semiconductor elements of the O chip 265 and the dedicated control chip 260 may be fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (FDSOI MOSFETs), and standard commercial FPGA IC chips for each The transistors or semiconductor elements of DPIIC chip 410 of 200 and each may be fin field effect transistors (FINFETs).

Referring to FIG. 11A, each NVMIC chip 250 may be a NAND flash memory chip or a NOR flash memory chip in a bare die form or a multi-chip package form. When the power of the logical driver 300 is turned off, the data stored in the NVMIC chip 250 in the logical driver 300 can still be preserved. Alternatively, the NVMIC chip 250 may be a non-volatile random access memory (NVRAM) integrated circuit (IC) chip, such as a ferroelectric random access memory (FRAM), magnetoresistive Random Access Memory (MRAM) or Phase Change Memory (PRAM). The memory density or capacity of each NVMIC chip 250 may be greater than 64Mbit, 512Mbit, 1Gbit, 4Gbit, 16Gbit, 64Gbit, 128Gbit, 256Gbit or 512Gbit . Each NVMIC chip 250 is fabricated using advanced non-and (NAND) flash memory or NOR flash memory technology generations, such as advanced at or less than or equal to 45nm, 28nm, 20nm, 16nm, or 10nm. The non-and (NAND) flash memory or NOR flash memory technology can be single-level memory cell (SLC) technology or multi-level memory cell (MLC) technology, applied in 2D non-and (NAND) memory architecture or On the 3D non-sum (NAND) memory structure, the multi-layer memory cell (MLC) technology is, for example, the double-layer memory cell (DLC) technology or the triple-layer memory cell (TLC) technology, while the 3D non-sum (NAND) memory technology The body structure can be a stack structure of 4, 8, 16 or 32 layers composed of NAND memory cells. Therefore, the non-volatile memory density or capacity of the logical drive 300 may be greater than or equal to 8Mbytes, 64Mbytes, 128Mbytes, 512Mbytes, 1Gbytes, 4Gbytes, 16Gbytes tuple, 64G bytes, 256G bytes, or 512G bytes, where each byte includes 8 bits.

Referring to FIG. 11A, in the same logic driver 300, the power supply voltage Vcc for each of the dedicated I/O chip 265 and the dedicated control chip 260 may be greater than or equal to 1.5V, 2V, 2.5V, 3V, 3.5V V, 4V or 5V, while the power supply voltage Vcc for each standard commercial FPGAIC chip 200 and each DPIIC chip 410 may be between 0.2V and 2.5V, between 0.2V and 2V , between 0.2V and 1.5V, between 0.1V and 1V, between 0.2V and 1V, or less than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V. In the same logic driver 300, the power supply voltage Vcc for each dedicated I/O die 265 and dedicated control die 260 may be different from the standard commercial FPGAIC die 200 for each and the DPIIC die 410 for each The power supply voltage Vcc. For example, in the same logic driver 300, the power supply voltage Vcc for each of the dedicated I/O chip 265 and the dedicated control chip 260 may be 4V, while the standard commercial FPGAIC chip 200 for each and each of the dedicated control chips 260 may be 4V. The power supply voltage Vcc of one DPIIC chip 410 may be 1.5V; or, in the same logic driver 300, the power supply voltage Vcc for each dedicated I/O chip 265 and dedicated control chip 260 may be 2.5V, And the power supply voltage Vcc for each standard commercial FPGAIC chip 200 and each DPIIC chip 410 may be 0.75V.

Referring to FIG. 11A, in the same logical driver 300, the physical thickness of the gate oxide of the field effect transistors (FETs) used for the semiconductor elements of each dedicated I/O chip 265 and dedicated control chip 260 is greater than or equal to 5nm, 6nm, 7.5nm, 10nm, 12.5nm or 15nm, and the physics of the gate oxides of the field effect transistors (FETs) for each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410 Thickness is less than or equal to 4.5 nm, 4 nm, 3 nm or 2 nm. In the same logical driver 300, the physical thickness of the gate oxides of the field effect transistors (FETs) used for the semiconductor elements of each dedicated I/O die 265 and dedicated control die 260 is different from that used for each The physical thickness of the gate oxides of the field effect transistors (FETs) of standard commercial FPGAIC chips 200 and DPIIC chips 410 of each. For example, in the same logical driver 300, the physical thickness of the gate oxides of the field effect transistors (FETs) for the semiconductor elements of each dedicated I/O chip 265 and dedicated control chip 260 may be 10 nm, While the physical thickness of the gate oxide of the field effect transistor (FET) for each standard commercial FPGAIC die 200 and each DPIIC die 410 may be 3 nm; or, in the same logic driver 300, use The physical thickness of the gate oxides of the field effect transistors (FETs) of the semiconductor elements of each dedicated I/O chip 265 and dedicated control chip 260 may be 7.5 nm, and the standard commercial FPGAIC chip 200 for each And the physical thickness of the gate oxide of the field effect transistor (FET) of each DPIIC chip 410 may be 2 nm.

Referring to FIG. 11A, in the logic driver 300, the dedicated I/O chips 265 may be in the form of multi-chip packages, and each dedicated I/O chip 265 includes a circuit as disclosed in FIG. 10, that is, there are a plurality of Large I/O circuits 341 and I/O pads 272, as disclosed in Figures 5A and 10, are used by logic driver 300 for one or more (2, 3, 4, or more than 4 one) Universal Serial Bus (USB) port, one or more IEEE1394 ports, one or more Ethernet ports, one or more HDMI ports, one or more VGA ports, one or more Multiple audio source connections or serial ports (such as RS-232 or communication (COM) ports), wireless transceiver I/O ports and/or Bluetooth transceiver I/O ports, etc. Each dedicated I/O chip 265 may include a plurality of large I/O circuits 341 and I/O pads 272, as disclosed in FIGS. 5A and 10, for use by the logic driver 300 for serial advanced technology Attachment (SATA) port or external link (PCIe) port to connect a memory drive.

Referring to FIG. 11A, the standard commercial FPGAIC chip 200 may have standard specifications or characteristics as follows: (1) The number of programmable logic blocks (LB) 201 of each standard commercial FPGAIC chip 200 may be greater than or equal to 16K, 64K, 256K, 512K, 1M, 4M, 16M, 64M, 256M, 1G or 4G; (2) each of the programmable logic blocks (LB) 201 of the standard commercial FPGAIC chip 200 of each The number of inputs may be greater than or equal to 4, 8, 16, 32, 64, 128 or 256; (3) the power supply voltage (Vcc) applied to the power pads 205 of each standard commercial FPGA IC chip 200 may be between 0.2V and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V, between 0.2V and 1V, or less than or Equal to 2.5V, 2V, 1.8V, 1.5V or 1V; (4) I/O pads 372 of all standard commercial FPGAIC chips 200 have the same layout and number, and the same relative to all standard commercial FPGAIC chips 200 The I/O pads 372 in place have the same function.

II. The second type of logical driver

FIG. 11B is a schematic top view of a second-type standard commercial logic driver according to an embodiment of the present application. Referring to FIG. 11B, the functions of the dedicated control chip 260 and the dedicated I/O chip 265 can be combined into a single chip 266, that is, the dedicated control and I/O chip, for performing the above-mentioned functions of the dedicated control chip 260 and The function of the dedicated I/O chip 265, so the dedicated control and I/O chip 266 has the circuit structure as shown in FIG. The dedicated control chip 260 as shown in FIG. 11A can be replaced by a dedicated control and I/O chip 266 at the location where the dedicated control chip 260 is placed, as shown in FIG. 11B. For the elements indicated by the same reference numerals shown in FIGS. 11A and 11B, the element shown in FIG. 11B may refer to the description of the element in FIG. 11A.

For wiring connections, see FIG. 11B , each of the standard commercial FPGAIC chips 200 can be coupled to one or more inter-chip interconnect lines 371 , programmable interconnect lines 361 or fixed interconnect lines 364 . Dedicated control and I/O chips 266, each DPIIC chip 410 can be coupled to the dedicated control and I/O chips through one or more programmable interconnects 361 of inter-chip interconnects 371 or fixed interconnects 364 266, dedicated control and I/O chips 266 can be coupled to all dedicated I/O chips 265 through one or more programmable interconnects 361 or fixed interconnects 364 of one or more inter-chip interconnects 371, and dedicated control and I/O chips 266 may be coupled to all NVMIC chips 250 through programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 .

Referring to FIG. 11B, each dedicated I/O chip 265 and dedicated control and I/O chip 266 can be designed and manufactured using older or more mature semiconductor technology generations, such as older than or greater than or equal to 40nm, 50nm , 90nm, 130nm, 250nm, 350nm or 500nm process. Within the same logic driver 300, each dedicated I/O die 265 and dedicated control and I/O die 266 may be of a generation of semiconductor technology that is more advanced than the standard commercial FPGAIC die 200 of each and the DPIIC die 410 of each The semiconductor technology generation used is 1, 2, 3, 4, 5, or more than 5 generations later or older.

Referring to FIG. 11B, the transistors or semiconductor elements used in each of the dedicated I/O chips 265 and the dedicated control and I/O chips 266 may be fully depleted type of metal oxide semiconductors with silicon on insulating layers. Transistor (FDSOIMOSFET), semi-depleted type metal oxide semiconductor field effect transistor (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor. In the same logic driver 300, the transistors or semiconductor components used for each of the dedicated I/O die 265 and the dedicated control and I/O die 266 may be different from the standard commercial FPGAIC die 200 used for each and each A transistor or semiconductor element of the DPIIC chip 410. For example, in the same logic driver 300, the transistors or semiconductor devices used for each dedicated I/O die 265 and dedicated control and I/O die 266 may be conventional metal-oxide-semiconductor field effect transistors , while the transistors or semiconductor elements used for each standard commercial FPGAIC die 200 and each DPIIC die 410 may be fin field effect transistors (FINFETs); or, in the same logic driver 300, for each The transistors or semiconductor elements of a dedicated I/O chip 265 and dedicated control and I/O chip 266 may be fully depleted type silicon-on-insulator metal-oxide-semiconductor field effect transistors (FDSOIMOSFETs) for use in The transistors or semiconductor elements of each of the standard commercial FPGAIC chips 200 and of each of the DPIIC chips 410 may be fin field effect transistors (FINFETs).

Referring to FIG. 11B, in the same logic driver 300, the power supply voltage Vcc for each dedicated I/O chip 265 and the dedicated control and I/O chip 266 may be greater than or equal to 1.5V, 2V, 2.5V , 3V, 3.5V, 4V or 5V, and the power supply voltage Vcc for each standard commercial FPGAIC chip 200 and each DPIIC chip 410 may be between 0.2V to 2.5V, between 0.2V to 2V, 0.2V to 1.5V, 0.1V to 1V, 0.2V to 1V, or less than or equal to 2.5V, 2V, 1.8V, 1.5V or 1V. In the same logic driver 300, the power supply voltage Vcc for each dedicated I/O die 265 and dedicated control and I/O die 266 may be different from the standard commercial FPGAIC die 200 for each and each The power supply voltage Vcc of the DPIIC chip 410 . For example, in the same logic driver 300, the power supply voltage Vcc for each of the dedicated I/O chip 265 and the dedicated control and I/O chip 266 may be 4V, while the standard commercial FPGAIC for each The power supply voltage Vcc of the chip 200 and each of the DPIIC chips 410 may be 1.5V; or, in the same logic driver 300, the power supply for each of the dedicated I/O chips 265 and the dedicated control and I/O chips 266 The supply voltage Vcc may be 2.5V, while the power supply voltage Vcc for each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410 may be 0.75V.

Referring to FIG. 11B, in the same logic driver 300, the gate oxides of the field effect transistors (FETs) used for the semiconductor elements of each dedicated I/O chip 265 and dedicated control and I/O chips 266 The physical thickness is greater than or equal to 5 nm, 6 nm, 7.5 nm, 10 nm, 12.5 nm, or 15 nm for the gates of the field effect transistors (FETs) of each of the standard commercial FPGAIC chips 200 and of each of the DPIIC chips 410 The physical thickness of the oxide is less than or equal to 4.5 nm, 4 nm, 3 nm or 2 nm. In the same logical driver 300, the physical thickness of the gate oxides of the field effect transistors (FETs) used for the semiconductor elements of each dedicated I/O die 265 and dedicated control and I/O die 266 is different from that used in the The physical thickness of the gate oxide of the field effect transistor (FET) on each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410. For example, in the same logical driver 300, the physical thickness of the gate oxide of the field effect transistors (FETs) used for the semiconductor elements of each dedicated I/O die 265 and dedicated control and I/O die 266 Can be 10 nm, while the physical thickness of the gate oxide of the field effect transistor (FET) for each standard commercial FPGAIC die 200 and each DPIIC die 410 can be 3 nm; alternatively, in the same logic driver In 300, the physical thickness of the gate oxide of the field effect transistor (FET) used for each dedicated I/O chip 265 and the semiconductor elements of the dedicated control and I/O chip 266 may be 7.5 nm, while the The physical thickness of the gate oxide of the field effect transistor (FET) of a standard commercial FPGAIC chip 200 and each of the DPIIC chips 410 may be 2 nm.

III. The third type of logical drive

FIG. 11C is a schematic top view of a third-type standard commercial logic driver according to an embodiment of the present application. The structure shown in FIG. 11C is similar to the structure shown in FIG. 11A, except that the innovative Application Specific Integrated Circuit (ASIC) or Customer Own Tool (COT) chip 402 (hereafter abbreviated as IAC chip) ) may also be provided in the logical drive 300. For the elements indicated by the same reference numerals shown in Figs. 11A and 11C, the elements shown in Fig. 11C may refer to the description of the elements in Fig. 11A.

Referring to FIG. 11C, the IAC chip 402 may include intellectual property (IP) circuits, dedicated circuits, logic circuits, mixed-signal circuits, radio frequency circuits, transmitter circuits, receiver circuits, and/or transceiver circuits, and the like. Each of the dedicated I/O chip 265, the dedicated control chip 260, and the IAC chip 402 can be designed and fabricated using older or more mature semiconductor technology generations, such as older than or greater than or equal to 40nm, 50nm, 90nm, 130nm, 250nm , 350nm or 500nm process. Alternatively, advanced semiconductor technology generations can also be used to fabricate the IAC wafer 402 , such as using a semiconductor technology generation that is advanced or less than or equal to 40 nm, 20 nm, or 10 nm to fabricate the IAC wafer 402 . Within the same logic driver 300, each dedicated I/O die 265, dedicated control die 260, and IAC die 402 may be of a generation of semiconductor technology that is more advanced than the standard commercial FPGAIC die 200 of each and the DPIIC die 410 of each The semiconductor technology generation used is 1, 2, 3, 4, 5, or more than 5 generations later or older. The transistors or semiconductor elements used in the IAC chip 402 can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layer (FINFET SOI), and metal oxide with long silicon on insulating layer of fully depletion type Semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor. In the same logic driver 300, the transistors or semiconductor elements used for each of the dedicated I/O die 265, the dedicated control die 260, and the IAC die 402 may be different from the standard commercial FPGAIC die 200 used for each and each A transistor or semiconductor element of the DPIIC chip 410. For example, in the same logic driver 300, the transistors or semiconductor devices used for each of the dedicated I/O chip 265, the dedicated control chip 260, and the IAC chip 402 may be conventional metal-oxide-semiconductor field effect transistors , while the transistors or semiconductor elements used for each standard commercial FPGAIC die 200 and each DPIIC die 410 may be fin field effect transistors (FINFETs); or, in the same logic driver 300, for each The transistors or semiconductor elements of a dedicated I/O chip 265, a dedicated control chip 260, and an IAC chip 402 may be fully depleted silicon-on-insulator field effect transistors (FDSOIMOSFETs) for use in The transistors or semiconductor elements of each of the standard commercial FPGAIC chips 200 and of each of the DPIIC chips 410 may be fin field effect transistors (FINFETs).

In this embodiment, since the IAC chip 402 can be designed and manufactured by using an older or more mature semiconductor technology generation, such as a process older than or greater than or equal to 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm or 500 nm, Therefore, its one-time engineering cost (NRE) will be less than that of traditional application-specific integrated circuits (ASICs) or customer-owned integrated circuits (ASICs) designed or manufactured using advanced semiconductor technology generations (such as those that are advanced or less than or equal to 30nm, 20nm, or 10nm). Tool (COT) wafer. For example, a one-off required for application-specific integrated circuit (ASIC) or customer-owned-tool (COT) wafers designed or manufactured using advanced semiconductor technology generations (such as those advanced or less than or equal to 30nm, 20nm, or 10nm) The engineering cost (NRE) may exceed $5 million, $10 million, $20 million, or even $50 million or $100 million. In the 16nm technology generation, the cost of a mask set for an Application Specific Integrated Circuit (ASIC) or Customer Own Tool (COT) chip can exceed $2 million, $5 million or $10 million, however, If the third-type logic driver 300 of the present embodiment is used, an IAC chip 402 manufactured by using an older semiconductor generation can be provided, and the same or similar innovations or applications can be achieved, so the one-time engineering expense (NRE) Can be reduced by at least $10 million, $7 million, $5 million, $3 million, or $1 million. A one-off implementation of the IAC chip 402 required for the same or similar innovations or applications in the third type logic driver 300 as compared to today's or traditional application specific integrated circuit (ASIC) or customer owned tool (COT) chip implementations The engineering expense (NRE) can be less than 2 times, 5 times, 10 times, 20 times or 30 times less.

For wiring connections, see FIG. 11C , each of the standard commercial FPGA IC chips 200 can be coupled to one or more inter-chip interconnect lines 371 , programmable interconnect lines 361 or fixed interconnect lines 364 . IAC chips 402, each DPIIC chip 410 can be coupled to the IAC chip 402 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of the inter-chip interconnect lines 371, and the IAC chip 402 can be coupled to the IAC chip 402 through one or more The programmable interconnect lines 361 or fixed interconnect lines 364 of the inter-die interconnect lines 371 are coupled to all dedicated I/O chips 265, and the IAC chip 402 can be programmed through one or more inter-die interconnect lines 371. The interconnect 361 or the fixed interconnect 364 is coupled to the dedicated control chip 260, and the IAC chip 402 can be coupled to the IAC chip 402 through the programmable interconnect 361 or the fixed interconnect 364 of the one or more inter-die interconnect 371 All NVMIC wafers 250.

IV. The fourth type of logical driver

FIG. 11D is a schematic top view of a fourth type standard commercialized logic driver according to an embodiment of the present application. Referring to FIG. 11D, the functions of the dedicated control chip 260 and the IAC chip 402 can be combined into a single chip 267, that is, the dedicated control and IAC chip (hereinafter abbreviated as DCIAC chip), for executing the above-mentioned functions of the dedicated control chip 260 Function and function of the IAC chip 402 . The structure shown in FIG. 11D is similar to the structure shown in FIG. 11A , except that the DCIAC chip 267 can also be provided in the logic driver 300 . The dedicated control chip 260 as shown in FIG. 11A can be replaced by a DCIAC chip 267 at the location where the dedicated control chip 260 is placed, as shown in FIG. 11D. For the elements indicated by the same reference numerals shown in Figs. 11A and 11D, the elements shown in Fig. 11D may refer to the description of the elements in Fig. 11A. The DCIAC chip 267 may include control circuits, intellectual property (IP) circuits, dedicated circuits, logic circuits, mixed-signal circuits, radio frequency circuits, transmitter circuits, receiver circuits, and/or transceiver circuits, and the like.

Referring to FIG. 11D, each dedicated I/O chip 265 and DCIAC chip 267 can be designed and fabricated using older or more mature semiconductor technology generations, such as older or greater than or equal to 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm process. Alternatively, advanced semiconductor technology generations can also be used to fabricate DCIAC wafers 267 , such as DCIAC wafers 267 using semiconductor technology generations that are advanced at or below 40 nm, 20 nm, or 10 nm. In the same logic driver 300, the semiconductor technology generation employed by each of the dedicated I/O die 265 and the DCIAC die 267 may be greater than the semiconductor technology employed by each of the standard commercial FPGAIC die 200 and each of the DPIIC die 410 Generations are 1, 2, 3, 4, 5, or more than 5 generations later or older. The transistors or semiconductor elements used in the DCIAC chip 267 can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layer (FINFET SOI), and metal oxide with long silicon on insulating layer of fully depletion type Semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor. In the same logic driver 300, the transistors or semiconductor components used for each of the dedicated I/O die 265 and the DCIAC die 267 may be different from the standard commercial FPGAIC die 200 used for each and the DPIIC die 410 of each transistors or semiconductor components. For example, in the same logic driver 300, the transistors or semiconductor elements used for each of the dedicated I/O chips 265 and the DCIAC chips 267 may be conventional metal-oxide-semiconductor field effect transistors, while the transistors or semiconductor elements used for each of the dedicated I/O chips 265 and DCIAC chips 267 may be conventional metal oxide semiconductor field effect transistors. The transistors or semiconductor elements of a standard commercial FPGAIC die 200 and each of the DPIIC die 410 may be fin field effect transistors (FINFETs); or, in the same logic driver 300, for each dedicated I/O The transistors or semiconductor elements of chip 265 and DCIAC chip 267 may be fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (FDSOIMOSFETs), while standard commercial FPGAIC chips 200 and The transistors or semiconductor elements of each DPIIC chip 410 may be fin field effect transistors (FINFETs).

In this embodiment, since the DCIAC chip 267 can be designed and manufactured by using an older or more mature semiconductor technology generation, such as a process older than or greater than or equal to 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm or 500 nm, Therefore, its one-time engineering cost (NRE) will be less than that of traditional application-specific integrated circuits (ASICs) or customer-owned integrated circuits (ASICs) designed or manufactured using advanced semiconductor technology generations (such as those that are advanced or less than or equal to 30nm, 20nm, or 10nm). Tool (COT) wafer. For example, a one-off required for application-specific integrated circuit (ASIC) or customer-owned-tool (COT) wafers designed or manufactured using advanced semiconductor technology generations (eg, those that are advanced or less than or equal to 30 nm, 20 nm, or 10 nm) The engineering cost (NRE) may exceed $5 million, $10 million, $20 million, or even $50 million or $100 million. In the 16nm technology generation, the cost of a mask set for an Application Specific Integrated Circuit (ASIC) or Customer Own Tool (COT) chip will exceed $2 million, $5 million or $10 million, however, If the fourth type logic driver 300 of the present embodiment is used, a DCIAC chip 267 manufactured by using an older semiconductor generation can be provided, and the same or similar innovations or applications can be achieved, so the one-time engineering expense (NRE) Can be reduced by at least $10 million, $7 million, $5 million, $3 million, or $1 million. A one-off of the DCIAC chip 267 required to achieve the same or similar innovations or applications in the fourth type logic driver 300 as compared to today's or traditional Application Specific Integrated Circuit (ASIC) or Customer Own Tool (COT) chip implementations The engineering expense (NRE) can be less than 2 times, 5 times, 10 times, 20 times or 30 times less.

For wiring connections, see FIG. 11D, each of the standard commercial FPGA IC chips 200 can be coupled to one or more inter-chip interconnect lines 371 via programmable interconnect lines 361 or fixed interconnect lines 364. The DCIAC chip 267, each DPIIC chip 410 can be coupled to the DCIAC chip 267 through one or more programmable interconnection lines 361 or fixed interconnection lines 364 of the inter-chip interconnection lines 371, and the DCIAC chip 267 can be coupled to the DCIAC chip 267 through one or more The programmable interconnection lines 361 or fixed interconnection lines 364 of the inter-die interconnection lines 371 are coupled to all the dedicated I/O chips 265, and the DCIAC chips 267 can pass through one or more of the inter-die interconnection lines 371. The programming interconnects 361 or the fixed interconnects 364 are coupled to all of the NVMIC chips 250 .

V. Type 5 Logical Driver

FIG. 11E is a schematic top view of a fifth-type standard commercial logic driver according to an embodiment of the present application. Referring to FIG. 11E, the functions of the dedicated control chip 260, the dedicated I/O chip 265 and the IAC chip 402 as shown in FIG. 11C can be combined into a single chip 268, that is, dedicated control, dedicated IO and IAC The chip (hereinafter abbreviated as DCDI/OIAC chip) is used to perform the functions of the dedicated control chip 260 , the functions of the dedicated I/O chip 265 and the functions of the IAC chip 402 . The structure shown in FIG. 11E is similar to the structure shown in FIG. 11A , except that the DCDI/OIAC chip 268 can also be provided in the logical driver 300 . The dedicated control chip 260 as shown in FIG. 11A can be replaced by a DCDI/OIAC chip 268 at the location where the dedicated control chip 260 is placed, as shown in FIG. 11E. For the elements indicated by the same reference numerals shown in FIGS. 11A and 11E, the elements shown in FIG. 11E may refer to the description of the elements in FIG. 11A. The DCDI/OIAC chip 268 has a circuit structure as shown in FIG. 10, and the DCDI/OIAC chip 268 may include control circuits, intellectual property (IP) circuits, dedicated circuits, logic circuits, mixed-signal circuits, radio frequency circuits, transmission A receiver circuit, a receiver circuit, and/or a transceiver circuit, etc.

Referring to FIG. 11E, each dedicated I/O chip 265 and DCDI/OIAC chip 268 may be designed and fabricated using older or more mature semiconductor technology generations, such as older than or greater than or equal to 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm process. Alternatively, advanced semiconductor technology generations can also be used to fabricate DCDI/OIAC wafers 268 , such as DCDI/OIAC wafers 268 using semiconductor technology generations that are advanced or less than or equal to 40 nm, 20 nm, or 10 nm. Within the same logic driver 300, each dedicated I/O die 265 and DCDI/OIAC die 268 may employ a generation of semiconductor technology that is greater than that employed by each of the standard commercial FPGAIC die 200 and each of the DPIIC die 410 Semiconductor technology generations later or older than 1, 2, 3, 4, 5, or more than 5 generations. The transistors or semiconductor elements used in the DCDI/OIAC chip 268 may be fin field effect transistors (FINFET), fin field effect transistors with silicon-on-insulator (FINFET SOI), and fully depletion-type metal with silicon-on-insulator. Oxide semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor. In the same logic driver 300, the transistors or semiconductor components used for each of the dedicated I/O die 265 and the DCDI/OIAC die 268 may be different from the standard commercial FPGAIC die 200 used for each and the DPIIC of each The transistor or semiconductor element of the chip 410 . For example, in the same logic driver 300, the transistors or semiconductor devices used for each of the dedicated I/O die 265 and the DCDI/OIAC die 268 may be conventional metal-oxide-semiconductor field effect transistors, while using The transistors or semiconductor elements in each standard commercial FPGAIC die 200 and each DPIIC die 410 may be fin field effect transistors (FINFETs); alternatively, in the same logic driver 300, for each dedicated I The transistors or semiconductor elements of the /O chip 265 and the DCDI/OIAC chip 268 may be fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (FDSOIMOSFETs) for standard commercialization of each The transistors or semiconductor elements of the FPGAIC chip 200 and each of the DPIIC chips 410 may be fin field effect transistors (FINFETs).

In this embodiment, since the DCDI/OIAC chip 268 can be designed and manufactured using older or more mature semiconductor technology generations, for example, those older than or greater than or equal to 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm or 500 nm process, so its one-time engineering expense (NRE) will be less than that of application-specific integrated circuits (ASICs) or customer Own Tool (COT) wafers. For example, a one-off required for application-specific integrated circuit (ASIC) or customer-owned-tool (COT) wafers designed or manufactured using advanced semiconductor technology generations (such as those advanced or less than or equal to 30nm, 20nm, or 10nm) The engineering cost (NRE) may exceed $5 million, $10 million, $20 million, or even $50 million or $100 million. In the 16nm technology generation, the cost of a mask set for an Application Specific Integrated Circuit (ASIC) or Customer Own Tool (COT) chip can exceed $2 million, $5 million or $10 million, however, If the fifth type logic driver 300 of the present embodiment is used, a DCDI/OIAC chip 268 manufactured by using an older semiconductor generation can be provided, and the same or similar innovations or applications can be achieved, so the one-time engineering cost ( NRE) can be reduced by less than $10 million, $7 million, $5 million, $3 million, or $1 million. Compared to current or traditional application specific integrated circuit (ASIC) or customer owned tool (COT) chip implementations, the DCDI/OIAC chip 268 required to achieve the same or similar innovations or applications in the fifth logic driver 300 The one-time engineering expense (NRE) can be less than 2 times, 5 times, 10 times, 20 times or 30 times less.

For wiring connection, please refer to FIG. 11E, each of the standard commercial FPGA IC chips 200 can be coupled to one or more inter-chip interconnect lines 371 via programmable interconnect lines 361 or fixed interconnect lines 364. DCDI/OIAC chip 268, each DPIIC chip 410 can be coupled to DCDI/OIAC chip 268, DCDI/OIAC chip through one or more programmable interconnect lines 361 of inter-die interconnect lines 371 or fixed interconnect lines 364 268 can be coupled to all dedicated I/O chips 265 through one or more programmable interconnects 361 of inter-die interconnects 371 or fixed interconnects 364, and DCDI/OIAC chips 268 can be coupled to all dedicated I/O chips 265 through one or more Programmable interconnect lines 361 or fixed interconnect lines 364 of inter-die interconnect lines 371 are coupled to all NVMIC chips 250 .

VI. The sixth type of logical drive

FIG. 11F and FIG. 11G are schematic top views of the sixth type standard commercial logic driver according to the embodiment of the present application. Referring to FIGS. 11F and 11G, the logic driver 300 shown in FIGS. 11A to 11E may further include a processing and/or computing (PC) integrated circuit (IC) chip 269 (hereinafter referred to as PCIC chip), such as a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a digital signal processing (DSP) chip, a tensor processor (TPU) chip or an application processor (APU) chip. An application processing unit (APU) chip can (1) be combined with a central processing unit (CPU) and a digital signal processing (DSP) unit for mutual operation; (2) combined with a central processing unit (CPU) and a graphics processing unit (GPU) to interoperate; (3) combine graphics processing unit (GPU) and digital signal processing (DSP) units for mutual operation; or (4) combine central processing unit (CPU), graphics processing unit (GPU) and digital Signal processing (DSP) units to operate with each other. The structure shown in FIG. 11F is similar to the structure shown in FIG. 11A, FIG. 11B, FIG. 11D and FIG. 11E, except that the PCIC chip 269 can also be provided in the logical driver 300, close to Dedicated control chip 260 in the structure shown in FIG. 11A, near the control and I/O chip 266 in the structure shown in FIG. 11B, close to the DCIAC chip in the structure shown in FIG. 11D 267 or near the DCDI/OIAC wafer 268 in the structure shown in Figure 11E. The structure shown in FIG. 11G is similar to the structure shown in FIG. 11C , the difference is that the PCIC chip 269 can also be disposed in the logical driver 300 and disposed close to the dedicated control chip 260 . 11A, 11B, 11D, 11E and 11F for the elements indicated by the same reference numerals, the elements shown in the 11F can refer to the elements in the 11A , Figures 11B, 11D, and 11E. For the elements shown in FIGS. 11A , 11C and 11G denoted by the same reference numerals, the elements shown in FIG. 11G may refer to the descriptions of the elements in FIGS. 11A and 11C .

Referring to FIGS. 11F and 11G, there is a central area between the inter-wafer interconnecting lines 371 extending vertically between adjacent two bundles and between the inter-wafering interconnecting lines 371 extending horizontally between adjacent two bundles, A PCIC chip 269 and a dedicated control chip 260, a dedicated control and I/O chip 266, a DCIAC chip 267 or a DCDI/OIAC chip 268 are arranged in the central area. For wiring connection, please refer to FIG. 11F and FIG. 11G , each of the standard commercial FPGAIC chips 200 can pass through one or more programmable interconnection lines 361 of inter-chip interconnection lines 371 or fixed interconnection lines 364 is coupled to the PCIC chip 269, and each DPIIC chip 410 can be coupled to the PCIC chip 269 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of the inter-chip interconnect lines 371. The PCIC chip 269 can The PCIC chip 269 can be coupled to the dedicated I/O chip 265 through the programmable interconnection line 361 or the fixed interconnection line 364 of the one or more inter-chip interconnection lines 371 . The programmable interconnect line 361 or the fixed interconnect line 364 is coupled to the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268, and the PCIC chip 269 can pass through one or more chips Programmable interconnect lines 361 or fixed interconnect lines 364 between interconnect lines 371 are coupled to all NVMIC chips 250 . In addition, the PCIC chip 269 may be coupled to the IAC chip 402 as depicted in FIG. 11G through programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 . Advanced semiconductor technology generations may be used to manufacture PCIC wafers 269 , for example, PCIC wafers 269 are fabricated using semiconductor technology generations that are advanced at or below 40 nm, 20 nm, or 10 nm. The generation of semiconductor technology employed by the PCIC chip 269 may be the same as that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410, or may be greater than that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410. A DPIIC chip 410 employs a semiconductor technology generation later or older than 1 generation. The transistors or semiconductor elements used in the PCIC chip 269 can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layers (FINFET SOI), and metal oxides with long silicon on insulating layers of fully depletion type. Semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor.

VII. Type VII Logical Drive

FIG. 11H and FIG. 11I are schematic top views of the seventh type standard commercial logic driver according to the embodiment of the present application. Referring to FIGS. 11H and 11I, the logical driver 300 shown in FIGS. 11A to 11E may further include two PCIC chips 269, for example, from a central processing unit (CPU) chip, an image processor ( Choose two from a combination of GPU) chips, digital signal processing (DSP) chips, and tensor processor (TPU) chips. For example, (1) one of the PCIC chips 269 may be a central processing unit (CPU) chip, and the other PCIC chip 269 may be a graphics processing unit (GPU) chip; (2) one of the PCIC chips 269 It can be a central processing unit (CPU) chip, and the other PCIC chip 269 can be a digital signal processing (DSP) chip; (3) one of the PCIC chips 269 can be a central processing unit (CPU) chip, and the other one The PCIC chip 269 may be a tensor processing unit (TPU) chip; (4) one of the PCIC chips 269 may be a graphics processing unit (GPU) chip, and the other PCIC chip 269 may be a digital signal processing (DSP) chip (5) one of the PCIC chips 269 may be a graphics processing unit (GPU) chip, and the other PCIC chip 269 may be a tensor processor (TPU) chip; (6) one of the PCIC chips 269 may be A digital signal processing (DSP) chip, and the other PCIC chip 269 may be a tensor processor (TPU) chip. The structure shown in FIG. 11H is similar to the structure shown in FIG. 11A , FIG. 11B , FIG. 11D , and FIG. 11E , except that the two PCIC chips 269 can also be provided in the logical driver 300 . , near the dedicated control chip 260 in the structure shown in FIG. 11A, near the control and I/O chip 266 in the structure shown in FIG. 11B, near the The DCIAC die 267 is at or near the DCDI/OIAC die 268 in the structure as shown in FIG. 11E. The structure shown in FIG. 11I is similar to the structure shown in FIG. 11C , the difference is that the two PCIC chips 269 can also be provided in the logical driver 300 and located close to the dedicated control chip 260 . 11A, 11B, 11D, 11E and 11H for the elements indicated by the same reference numerals, the elements shown in the 11H can refer to the elements in the 11A , Figures 11B, 11D, and 11E. For elements indicated by the same reference numerals shown in FIGS. 11A , 11C and 11I, the elements shown in FIG. 11I may refer to the descriptions of the elements in FIGS. 11A and 11C.

Referring to FIG. 11H and FIG. 11I, there is a central area between the inter-wafer interconnecting lines 371 extending vertically between adjacent two bundles and between the inter-wafering interconnecting lines 371 extending horizontally between adjacent two bundles, Two PCIC chips 269 and one of the dedicated control chips 260 , the dedicated control and I/O chips 266 , the DCIAC chips 267 or the DCDI/OIAC chips 268 are located in the central area. For wiring connections, please refer to Sections 11H and 11I, each of the standard commercial FPGA IC chips 200 can be coupled through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371 Connected to all PCIC chips 269, each DPIIC chip 410 can be coupled to all PCIC chips 269 through one or more programmable interconnects 361 or fixed interconnects 364 of one or more inter-chip interconnects 371, each The PCIC chips 269 can be coupled to all the dedicated I/O chips 265 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. The programmable interconnect line 361 or the fixed interconnect line 364 of the or plurality of inter-die interconnect lines 371 is coupled to the dedicated control die 260, the dedicated control and I/O die 266, the DCIAC die 267 or the DCDI/OIAC die 268, and Each PCIC chip 269 can be coupled to all NVMIC chips 250 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371, and each PCIC chip 269 can be coupled to all NVMIC chips 250 through one or more The programmable interconnection lines 361 or the fixed interconnection lines 364 of the plurality of inter-chip interconnection lines 371 are coupled to other PCIC chips 269 . In addition, each PCIC chip 269 may be coupled to the IAC chip 402 as depicted in FIG. 11G through programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 . Advanced semiconductor technology generations may be used to manufacture PCIC wafers 269 , for example, PCIC wafers 269 are fabricated using semiconductor technology generations that are advanced at or below 40 nm, 20 nm, or 10 nm. The generation of semiconductor technology employed by the PCIC chip 269 may be the same as that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410, or may be greater than that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410. A DPIIC chip 410 employs a semiconductor technology generation later or older than 1 generation. The transistors or semiconductor elements used in the PCIC chip 269 can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layers (FINFET SOI), and metal oxides with long silicon on insulating layers of fully depletion type. Semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor.

VIII. Type VIII Logical Drive

FIG. 11J and FIG. 11K are schematic top views of the eighth type standard commercial logic driver according to the embodiment of the present application. Referring to FIGS. 11J and 11K, the logical driver 300 shown in FIGS. 11A to 11E may further include three PCIC chips 269, for example, a central processing unit (CPU) chip, an image processor ( Select three from a combination of GPU) chips, digital signal processing (DSP) chips and tensor processor (TPU) chips. For example, (1) one of the PCIC chips 269 may be a central processing unit (CPU) chip, the other PCIC chip 269 may be a graphics processing unit (GPU) chip, and the last PCIC chip 269 may be a digital Signal processing (DSP) chips; (2) one of the PCIC chips 269 may be a central processing unit (CPU) chip, the other PCIC chip 269 may be a graphics processing unit (GPU) chip, and the last PCIC chip 269 It can be a tensor processing unit (TPU) chip; (3) one of the PCIC chips 269 can be a central processing unit (CPU) chip, the other PCIC chip 269 can be a digital signal processing (DSP) chip, and the last one The PCIC chip 269 may be a tensor processing unit (TPU) chip; (4) one of the PCIC chips 269 may be a graphics processing unit (GPU) chip, and the other PCIC chip 269 may be a digital signal processing (DSP) chip, And the last PCIC die 269 may be a tensor processor (TPU) die. The structure shown in FIG. 11J is similar to the structure shown in FIG. 11A , FIG. 11B , FIG. 11D , and FIG. 11E , except that the three PCIC chips 269 can also be provided in the logical driver 300 . , near the dedicated control chip 260 in the structure shown in FIG. 11A, near the control and I/O chip 266 in the structure shown in FIG. 11B, near the The DCIAC die 267 is at or near the DCDI/OIAC die 268 in the structure as shown in FIG. 11E. The structure shown in FIG. 11K is similar to the structure shown in FIG. 11C , except that the three PCIC chips 269 can also be provided in the logical driver 300 and located close to the dedicated control chip 260 . 11A, 11B, 11D, 11E, and 11J for the elements indicated by the same reference numerals, the elements shown in Fig. 11J may refer to the elements in Fig. 11A , Figures 11B, 11D, and 11E. For the elements shown in Figures 11A, 11C and 11K indicated by the same reference numerals, the elements shown in Figure 11K may refer to the descriptions of the elements in Figures 11A and 11C.

Referring to FIG. 11H and FIG. 11I, there is a central area between the inter-wafer interconnecting lines 371 extending vertically between adjacent two bundles and between the inter-wafering interconnecting lines 371 extending horizontally between adjacent two bundles, There are three PCIC chips 269 and one of the dedicated control chips 260, dedicated control and I/O chips 266, DCIAC chips 267 or DCDI/OIAC chips 268 in the central area. For wiring connections, see Sections 11J and 11K, each of the standard commercial FPGA IC chips 200 can be coupled through one or more programmable interconnects 361 or fixed interconnects 364 of inter-chip interconnects 371 Connected to all PCIC chips 269, each DPIIC chip 410 can be coupled to all PCIC chips 269 through one or more programmable interconnects 361 or fixed interconnects 364 of one or more inter-chip interconnects 371, each The PCIC chips 269 can be coupled to all the dedicated I/O chips 265 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. The programmable interconnection line 361 or the fixed interconnection line 364 of the plurality of inter-chip interconnection lines 371 is coupled to the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268, each One PCIC chip 269 can be coupled to all NVMIC chips 250 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371, and each PCIC chip 269 can be coupled to all NVMIC chips 250 through one or more inter-chip interconnect lines 371. The programmable interconnection lines 361 or the fixed interconnection lines 364 of the inter-die interconnection lines 371 are coupled to the other two PCIC chips 269 . In addition, each PCIC chip 269 may be coupled to the IAC chip 402 as depicted in FIG. 11G through programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 . Advanced semiconductor technology generations may be used to manufacture PCIC wafers 269 , for example, PCIC wafers 269 are fabricated using semiconductor technology generations that are advanced at or below 40 nm, 20 nm, or 10 nm. The generation of semiconductor technology employed by the PCIC chip 269 may be the same as that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410, or may be greater than that employed by each of the standard commercial FPGAIC chips 200 and each of the DPIIC chips 410. A DPIIC chip 410 employs a semiconductor technology generation later or older than 1 generation. The transistors or semiconductor elements used in the PCIC chip 269 can be fin field effect transistors (FINFET), fin field effect transistors with long silicon on insulating layers (FINFET SOI), and metal oxides with long silicon on insulating layers of fully depletion type. Semiconductor field effect transistor (FDSOIMOSFET), semi-depletion type metal oxide semiconductor field effect transistor with long silicon on insulating layer (PDSOIMOSFET) or traditional metal oxide semiconductor field effect transistor.

IX. Type IX Logical Drive

FIG. 11L is a schematic top view of the ninth type standard commercial logic driver according to the embodiment of the present application. For the elements indicated by the same reference numerals shown in FIGS. 11A to 11L, the elements shown in FIG. 11L may refer to the descriptions of the elements in FIGS. 11A to 11K. Referring to FIG. 11L, the ninth type standard commercial logic driver 300 may be packaged with one or more PCIC chips 269, one or more standard commercial FPGA IC chips 200 as described in FIGS. 8A to 8J, a One or more NVMIC chips 250, one or more volatile (VM) integrated circuit (IC) chips 324, one or more high speed high bandwidth memory (HBM) integrated circuit (IC) chips 251 and dedicated Control die 260, arranged in an array, wherein PCIC die 269, standard commercial FPGAIC die 200, NVMIC die 250, VMIC die 324 and HBMIC die 251 may be arranged around a dedicated control die 260 located in the middle area. The combination of PCIC chips 269 may include (1) multiple GPU chips, such as 2, 3, 4, or more than 4 GPU chips; (2) one or more CPU chips and/or one or more (3) one or more CPU chips and/or one or more DSP chips; (4) one or more CPU chips, one or more GPU chips and/or one or more (5) one or more CPU chips and/or one or more TPU chips; or (6) one or more CPU chips, one or more DSP chips and/or one or more Multiple TPU chips. The HBMIC chip 251 may be a high-speed and high-bandwidth dynamic random access memory (DRAM) chip, a high-speed and high-bandwidth static random access memory (SRAM) chip, a magnetoresistive random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip. Take a memory (RRAM) chip. The PCIC chip 269 and the standard commercial FPGAIC chip 200 can cooperate with the HBMIC chip 251 to perform high-speed, high-bandwidth parallel processing and/or parallel computing.

Referring to FIG. 11L, a standard commercial logic driver 300 may include inter-die interconnects 371 that may be used on standard commercial FPGAIC die 200, NVMIC die 250, VMIC die 324, dedicated control die 260, PCIC die 269, and HBMIC die 251, among which between two adjacent ones. A standard commercial logic driver 300 may include a plurality of DPIIC dies 410 aligned at the intersection of a vertically extending bundle of inter-die interconnect lines 371 and a horizontally extending bundle of inter-die interconnect lines 371 . Each DPIIC die 410 is disposed around and at the corners of four of the standard commercial FPGAIC die 200, NVMIC die 250, VMIC die 324, dedicated control die 260, PCIC die 269, and HBMIC die 251. Each inter-chip interconnection line 371 may be a programmable interconnection line 361 or a fixed interconnection line 364 as described in FIGS. 7A to 7C , and see the aforementioned “Description of Programmable Interconnection Lines” and "Description of Fixed Interconnect Lines". Signals can be transmitted (1) via the small I/O circuits 203 of the standard commercial FPGAIC chip 200 , the programmable interconnect wires 361 of the inter-chip interconnect wires 371 and the intra-chip interconnect wires 502 of the standard commercial FPGA IC chip 200 or (2) through the small I/O circuit 203 of the DPIIC chip 410, the programmable interconnection line 361 of the inter-chip interconnection line 371 and the in-chip interconnection of the DPIIC chip 410 Programmable interconnection of lines is performed between lines 361 . The transmission of the signal can be (1) through the small I/O circuit 203 of the standard commercial FPGAIC chip 200, between the fixed inter-chip interconnect 364 of the inter-chip interconnect 371 and the intra-chip interconnect 502 of the standard commercial FPGA IC chip 200. Or (2) through the small I/O circuit 203 of the DPIIC chip 410, the fixed interconnection line 364 of the inter-chip interconnection line 371 and the intra-chip interconnection line of the DPIIC chip 410 are fixed Interconnection between lines 364 takes place.

Referring to FIG. 11L, each standard commercial FPGAIC chip 200 can be coupled to all DPIIC chips 410 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371. A standard commercial FPGA IC chip 200 may be coupled to a dedicated control chip 260 through one or more inter-chip interconnect lines 371, programmable interconnect lines 361 or fixed interconnect lines 364, each of the standard commercial FPGA IC chips 200 Can be coupled to all NVMIC chips 250 through one or more programmable interconnects 361 of inter-chip interconnects 371 or fixed interconnects 364, and each standard commercial FPGAIC chip 200 can be coupled to all NVMIC chips 200 through one or more chips The programmable interconnection lines 361 or fixed interconnection lines 364 of the inter-chip interconnection lines 371 are coupled to all PCIC chips 269, and each standard commercial FPGAIC chip 200 can be connected through one or more inter-chip interconnection lines 371. The programming interconnection lines 361 or the fixed interconnection lines 364 are coupled to all the HBMIC chips 251, and each DPIIC chip 410 can be connected to the programmable interconnection lines 361 or fixed interconnection lines of one or more inter-chip interconnection lines 371 through one or more inter-chip interconnection lines 371. 364 is coupled to the dedicated control chip 260, and each DPIIC chip 410 can be coupled to all the NVMIC chips 250 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. One DPIIC chip 410 can be coupled to all PCIC chips 269 via one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371, and each DPIIC chip 410 can be coupled to all PCIC chips 269 through one or more inter-chip interconnect lines 371. The programmable interconnection lines 361 or fixed interconnection lines 364 of the inter-die interconnection lines 371 are coupled to all the HBMIC chips 251 , and one of the PCIC chips 269 can be programmed through one or more inter-die interconnection lines 371 . The interconnection line 361 or the fixed interconnection line 364 is coupled to one of the HBMIC chips 251, and the data bit width transmitted between the one of the PCIC chips 269 and the one of the HBMIC chips 251 may be greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, each NVMIC chip 250 can pass through one or more inter-chip interconnect lines 371 programmable interconnect lines 361 or fixed interconnect lines 364 is coupled to the dedicated control chip 260, and each HBMIC chip 251 can be coupled to the dedicated control chip 260 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. Each PCIC The chip 269 may be coupled to the dedicated control chip 260 through programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 . Each PCIC chip 269 may be coupled to all other PCIC chips 269 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 .

Referring to FIG. 11L, the logical driver 300 may include a plurality of dedicated I/O chips 265 located in the surrounding area of the logical driver 300, which surrounds the middle area of the logical driver 300, wherein the middle area of the logical driver 300 accommodates the Standard commercial FPGAIC die 200 , NVMIC die 321 , VMIC die 324 , dedicated control die 260 , PCIC die 269 , HBMIC die 251 , and DPIIC die 410 . Each standard commercial FPGAIC die 200 may be coupled to all of the dedicated I/O die 265 via one or more inter-die interconnects 371, programmable interconnects 361 or fixed interconnects 364, each DPIIC Die 410 can be coupled to all of the dedicated I/O die 265 via one or more programmable interconnect lines 361 or fixed interconnect lines 364 of inter-die interconnect lines 371, and each NVMIC die 321 can be coupled to all of the dedicated I/O die 265 via one or more The programmable interconnect lines 361 or the fixed interconnect lines 364 of the inter-die interconnect lines 371 are coupled to all the dedicated I/O chips 265, and the dedicated control chips 260 can be connected via one or more inter-die interconnect lines 371. Programmable interconnect lines 361 or fixed interconnect lines 364 are coupled to all dedicated I/O chips 265, and each PCIC chip 269 can be connected via programmable interconnect lines 361 or fixed interconnect lines 371 via one or more inter-die interconnect lines 371. Interconnects 364 are coupled to all dedicated I/O chips 265, and each HBMIC die 251 may be coupled to the programmable interconnects 361 or fixed interconnects 364 of one or more inter-die interconnects 371 All dedicated I/O chips 265.

Referring to FIG. 11L, each standard commercial FPGAIC chip 200 can refer to the content disclosed in FIGS. 8A to 8J, and each DPIIC chip 410 can refer to the content disclosed in FIG. 9. FIG. In addition, standard commercial FPGAIC chip 200, DPIIC chip 410, dedicated I/O chip 265, NVMIC chip 250, dedicated control chip 260 can also refer to the contents disclosed in FIG. 11A.

For example, referring to FIG. 11L, all PCIC chips 269 in logical drive 300 may be multiple GPU chips, such as 2, 3, 4, or more than 4 GPU chips, and all HBMIC chips 251 can be all high-speed high-bandwidth dynamic random access memory (DRAM) chips, all high-speed high-bandwidth static random access memory (SRAM) chips, all magnetoresistive random access memory (MRAM) chips, or all is a resistive random access memory (RRAM) chip, and the width of data bits transferred between one of the PCIC chips 269 such as GPU chips and one of the HBMIC chips 251 can be greater than or equal to 64, 128 , 256, 512, 1024, 2048, 4096, 8K or 16K.

For example, referring to FIG. 11L, all PCIC chips 269 in the logical drive 300 may be multiple TPU chips, such as 2, 3, 4 or more than 4 TPU chips, and each HBMIC The chip 251 may be a high-speed and high-bandwidth dynamic random access memory (DRAM) chip, a high-speed and high-bandwidth static random access memory (SRAM) chip, a magnetoresistive random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip. Memory (RRAM) chips, and the data bit widths transferred between one of the PCIC chips 269 such as TPU chips and one of the HBMIC chips 251 may be greater than or equal to 64, 128, 256, 512, 1024 , 2048, 4096, 8K or 16K.

X. Type 10 Logical Drive

FIG. 11M is a schematic top view of the tenth type standard commercial logic drive according to the embodiment of the present application. For the elements indicated by the same reference numerals shown in FIGS. 11A to 11M, the elements shown in FIG. 11M may refer to the descriptions of the elements in FIGS. 11A to 11L. Referring to FIG. 11M, the tenth type standard commercial logic driver 300 is packaged with the above-mentioned PCIC chips 269, such as a plurality of GPU chips 269a and one CPU chip 269b. Furthermore, the standard commercial logic driver 300 is also packaged with a plurality of HBMIC chips 251, each of which is adjacent to one of the GPU chips 269a for high-speed and high-bandwidth data transfer with the one of the GPU chips 269a. . In a standard commercial logic drive 300, each HBMIC chip 251 may be a high-speed high-bandwidth dynamic random access memory (DRAM) chip, a high-speed high-bandwidth static random access memory (SRAM) chip, a magnetoresistive random access memory Take a memory (MRAM) chip or a resistive random access memory (RRAM) chip. The standard commercial logic driver 300 also encapsulates a plurality of standard commercial FPGAIC chips 200 and one or more NVMIC chips 250. The NVMIC chips 250 store programmable logic blocks for programming the FPGAIC chips 200 in a non-volatile manner 201 and the result value or programming code of the crosspoint switch 379 and storing the programming code for programming the crosspoint switch 379 of the DPIIC chip 410, as disclosed in FIGS. 6A-9. The CPU chip 269b, the dedicated control chip 260, the standard commercial FPGAIC chip 200, the GPU chip 269a, the NVMIC chip 250 and the HBMIC chip 251 are arranged in the form of a matrix in the logic driver 300, wherein the CPU chip 269b and the dedicated control chip 260 are designed In its middle region, it is surrounded by a peripheral region housing the standard commercial FPGAIC die 200, GPU die 269a, NVMIC die 250, and HBMIC die 251.

Referring to FIG. 11M, the tenth type standard commercial logic driver 300 includes inter-die interconnection lines 371, which can be connected between standard commercial FPGAIC chips 200, NVMIC chips 250, dedicated control chips 260, GPU chips 269a, CPU chips 269b and HBMIC chips Between two adjacent wafers 251 . A standard commercial logic driver 300 may include a plurality of DPIIC dies 410 aligned at the intersection of a vertically extending bundle of inter-die interconnect lines 371 and a horizontally extending bundle of inter-die interconnect lines 371 . Each DPIIC die 410 is disposed around and at the corners of four of the standard commercial FPGAIC die 200, NVMIC die 250, dedicated control die 260, GPU die 269a, CPU die 269b, and HBMIC die 251. Each inter-chip interconnection line 371 may be a programmable interconnection line 361 or a fixed interconnection line 364 as described in FIGS. 7A to 7C , and see the aforementioned “Description of Programmable Interconnection Lines” and "Description of Fixed Interconnect Lines". Signals can be transmitted (1) via the small I/O circuits 203 of the standard commercial FPGAIC chip 200 , the programmable interconnect wires 361 of the inter-chip interconnect wires 371 and the intra-chip interconnect wires 502 of the standard commercial FPGA IC chip 200 or (2) through the small I/O circuit 203 of the DPIIC chip 410, the programmable interconnection line 361 of the inter-chip interconnection line 371 and the in-chip interconnection of the DPIIC chip 410 Programmable interconnection of lines is made between lines 361 . The transmission of the signal can be (1) through the small I/O circuit 203 of the standard commercial FPGAIC chip 200, between the fixed inter-chip interconnect 364 of the inter-chip interconnect 371 and the intra-chip interconnect 502 of the standard commercial FPGA IC chip 200. Or (2) through the small I/O circuit 203 of the DPIIC chip 410, the fixed interconnection line 364 of the inter-chip interconnection line 371 and the intra-chip interconnection line of the DPIIC chip 410 are fixed Interconnection between lines 364 takes place.

Referring to FIG. 11M, each standard commercial FPGAIC chip 200 can be coupled to all DPIIC chips 410 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371. A standard commercial FPGA IC chip 200 may be coupled to a dedicated control chip 260 through one or more inter-chip interconnect lines 371, programmable interconnect lines 361 or fixed interconnect lines 364, each of the standard commercial FPGA IC chips 200 Can be coupled to all NVMIC chips 250 through one or more programmable interconnects 361 of inter-chip interconnects 371 or fixed interconnects 364, and each standard commercial FPGAIC chip 200 can be coupled to all NVMIC chips 200 through one or more chips The programmable interconnect lines 361 or fixed interconnect lines 364 of the inter-chip interconnect lines 371 are coupled to all of the GPU chips 269a, and each of the standard commercial FPGA IC chips 200 can be connected via one or more inter-die interconnect lines 371. Programmable interconnection lines 361 or fixed interconnection lines 364 are coupled to CPU chip 269b, and each standard commercial FPGAIC chip 200 can be interconnected through programmable interconnection lines 361 or fixed interconnection lines 371 through one or more inter-chip interconnection lines 371 The line 364 is coupled to all the HBMIC chips 251, and each DPIIC chip 410 can be coupled to the dedicated control chip 260 through the programmable interconnect line 361 or the fixed interconnect line 364 of one or more inter-die interconnect lines 371, Each DPIIC chip 410 can be coupled to all NVMIC chips 250 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 , and each DPIIC chip 410 can be coupled to all NVMIC chips 250 through one or more inter-die interconnect lines 371 or fixed interconnect lines 364 The programmable interconnection lines 361 or the fixed interconnection lines 364 of the plurality of inter-die interconnection lines 371 are coupled to all the GPU chips 269 a , and each DPIIC chip 410 can be connected by one or more of the inter-die interconnection lines 371 . The programming interconnection line 361 or the fixed interconnection line 364 is coupled to the CPU chip 269b, and each DPIIC chip 410 can be coupled through the programmable interconnection line 361 or the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 Connected to all the HBMIC chips 251, the CPU chip 269b can be coupled to all the GPU chips 269a through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371, and the CPU chip 269b can be connected to all the GPU chips 269a through The programmable interconnection lines 361 or fixed interconnection lines 364 of the one or more inter-die interconnection lines 371 are coupled to all the HBMIC chips 251 , and one of the GPU chips 269 a can pass through the one or more inter-die interconnection lines 371 It can be The programming interconnect 361 or the fixed interconnect 364 is coupled to one of the HBMIC chips 251, and the data bit width transmitted between the one of the GPU chip 269a and the one of the HBMIC chips 251 may be Greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, each NVMIC chip 250 can be interconnected through one or more programmable interconnect lines 361 or fixed interconnect lines 371 The line 364 is coupled to the dedicated control chip 260, and each HBMIC chip 251 can be coupled to the dedicated control chip 260 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. A GPU chip 269a can be coupled to the dedicated control chip 260 through one or more programmable interconnect lines 361 or fixed interconnect lines 364, and the CPU chip 269b can communicate with one or more chips The programmable interconnection lines 361 or the fixed interconnection lines 364 of the connection lines 371 are coupled to the dedicated control chip 260 .

Referring to FIG. 11M, the logical driver 300 may include a plurality of dedicated I/O chips 265 located in the surrounding area of the logical driver 300, which surrounds the middle area of the logical driver 300, wherein the middle area of the logical driver 300 accommodates the Standard commercial FPGAIC die 200, NVMIC die 321, dedicated control die 260, GPU die 269a, CPU die 269b, HBMIC die 251, and DPIIC die 410. Each standard commercial FPGAIC die 200 may be coupled to all of the dedicated I/O die 265 via one or more inter-die interconnects 371, programmable interconnects 361 or fixed interconnects 364, each DPIIC Die 410 can be coupled to all of the dedicated I/O die 265 via one or more programmable interconnect lines 361 or fixed interconnect lines 364 of inter-die interconnect lines 371, and each NVMIC die 321 can be coupled to all of the dedicated I/O die 265 via one or more The programmable interconnect lines 361 or the fixed interconnect lines 364 of the inter-die interconnect lines 371 are coupled to all the dedicated I/O chips 265, and the dedicated control chips 260 can be connected via one or more inter-die interconnect lines 371. Programmable interconnect lines 361 or fixed interconnect lines 364 are coupled to all dedicated I/O chips 265, and each GPU chip 269a can be connected via programmable interconnect lines 361 or fixed through one or more inter-die interconnect lines 371 Interconnect lines 364 are coupled to all dedicated I/O chips 265, and CPU chip 269b may be coupled to all dedicated I/O chips 269 via programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 I/O chips 265, each HBMIC chip 251 can be coupled to all dedicated I/O chips 265 via programmable interconnects 361 or fixed interconnects 364 of one or more inter-die interconnects 371.

Therefore, in the tenth type logical driver 300, the GPU chip 269a can cooperate with the HBMIC chip 251 to perform high-speed, high-bandwidth parallel processing and/or parallel computing. Referring to FIG. 11M , each of the standard commercial FPGAIC chips 200 can refer to the content disclosed in FIGS. 8A to 8J , and each of the DPIIC chips 410 can refer to the content disclosed in FIG. 9 . In addition, standard commercial FPGAIC chip 200, DPIIC chip 410, dedicated I/O chip 265, NVMIC chip 250, dedicated control chip 260 can also refer to the contents disclosed in FIG. 11A.

XI. Logic driver of the eleventh type

FIG. 11N is a schematic top view of an eleventh type standard commercial logic driver according to an embodiment of the present application. For the elements indicated by the same reference numerals shown in FIGS. 11A to 11N, the elements shown in FIG. 11N may refer to the descriptions of the elements in FIGS. 11A to 11M. Referring to FIG. 11N, the eleventh type standard commercial logic driver 300 is packaged with the above-mentioned PCIC chips 269, such as a plurality of TPU chips 269c and one CPU chip 269b. Furthermore, the standard commercial logic driver 300 is also packaged with a plurality of HBMIC chips 251, each of which is adjacent to one of the TPU chips 269c for high-speed and high-bandwidth data transmission with the one of the TPU chips 269c. . In a standard commercial logic drive 300, each HBMIC chip 251 may be a high-speed high-bandwidth dynamic random access memory (DRAM) chip, a high-speed high-bandwidth static random access memory (SRAM) chip, a magnetoresistive random access memory Take a memory (MRAM) chip or a resistive random access memory (RRAM) chip. The standard commercial logic driver 300 also encapsulates a plurality of standard commercial FPGAIC chips 200 and one or more NVMIC chips 250. The NVMIC chips 250 store programmable logic blocks for programming the FPGAIC chips 200 in a non-volatile manner 201 and the result value or programming code of the crosspoint switch 379 and storing the programming code for programming the crosspoint switch 379 of the DPIIC chip 410, as disclosed in FIGS. 6A-9. The CPU chip 269b, the dedicated control chip 260, the standard commercial FPGAIC chip 200, the TPU chip 269c, the NVMIC chip 250 and the HBMIC chip 251 are arranged in a matrix in the logic driver 300, wherein the CPU chip 269b and the dedicated control chip 260 are arranged in a matrix. In its middle area, it is surrounded by a peripheral area housing the standard commercial FPGAIC die 200, TPU die 269c, NVMIC die 250 and HBMIC die 251.

Referring to FIG. 11N, the eleventh type of standard commercialized logic driver 300 includes inter-chip interconnection lines 371, which can be connected between standard commercialized FPGAIC chip 200, NVMIC chip 250, dedicated control chip 260, TPU chip 269c, CPU chip 269b and Between two adjacent HBMIC wafers 251 . A standard commercial logic driver 300 may include a plurality of DPIIC dies 410 aligned at the intersection of a vertically extending bundle of inter-die interconnect lines 371 and a horizontally extending bundle of inter-die interconnect lines 371 . Each DPIIC die 410 is disposed around and at the corners of four of the standard commercial FPGAIC die 200, NVMIC die 250, dedicated control die 260, TPU die 269c, CPU die 269b, and HBMIC die 251. Each inter-chip interconnection line 371 may be a programmable interconnection line 361 or a fixed interconnection line 364 as described in FIGS. 7A to 7C , and see the aforementioned “Description of Programmable Interconnection Lines” and "Description of Fixed Interconnect Lines". Signals can be transmitted (1) via the small I/O circuits 203 of the standard commercial FPGAIC chip 200 , the programmable interconnect wires 361 of the inter-chip interconnect wires 371 and the intra-chip interconnect wires 502 of the standard commercial FPGA IC chip 200 or (2) through the small I/O circuit 203 of the DPIIC chip 410, the programmable interconnection line 361 of the inter-chip interconnection line 371 and the in-chip interconnection of the DPIIC chip 410 Programmable interconnection of lines is performed between lines 361 . The transmission of the signal can be (1) through the small I/O circuit 203 of the standard commercial FPGAIC chip 200, between the fixed inter-chip interconnect 364 of the inter-chip interconnect 371 and the intra-chip interconnect 502 of the standard commercial FPGA IC chip 200. Or (2) through the small I/O circuit 203 of the DPIIC chip 410, the fixed interconnection line 364 of the inter-chip interconnection line 371 and the intra-chip interconnection line of the DPIIC chip 410 are fixed Interconnection between lines 364 takes place.

Referring to FIG. 11N, each standard commercial FPGAIC chip 200 can be coupled to all DPIIC chips 410 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371. A standard commercial FPGA IC chip 200 may be coupled to a dedicated control chip 260 through one or more inter-chip interconnect lines 371, programmable interconnect lines 361 or fixed interconnect lines 364, each of the standard commercial FPGA IC chips 200 Can be coupled to all NVMIC chips 250 through one or more programmable interconnects 361 of inter-chip interconnects 371 or fixed interconnects 364, and each standard commercial FPGAIC chip 200 can be coupled to all NVMIC chips 200 through one or more chips The programmable interconnection lines 361 or the fixed interconnection lines 364 of the inter-chip interconnection lines 371 are coupled to all TPU chips 269c, and each standard commercial FPGAIC chip 200 can be connected by one or more inter-die interconnection lines 371. Programmable interconnection lines 361 or fixed interconnection lines 364 are coupled to CPU chip 269b, and each standard commercial FPGAIC chip 200 can be interconnected through programmable interconnection lines 361 or fixed interconnection lines 371 through one or more inter-chip interconnection lines 371 The line 364 is coupled to all the HBMIC chips 251, and each DPIIC chip 410 can be coupled to the dedicated control chip 260 through the programmable interconnect line 361 or the fixed interconnect line 364 of one or more inter-die interconnect lines 371, Each DPIIC chip 410 can be coupled to all NVMIC chips 250 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 , and each DPIIC chip 410 can be coupled to all NVMIC chips 250 through one or more inter-die interconnect lines 371 or fixed interconnect lines 364 The programmable interconnection lines 361 or the fixed interconnection lines 364 of the plurality of inter-die interconnection lines 371 are coupled to all the TPU chips 269c, and each DPIIC chip 410 can be connected through one or more of the inter-die interconnection lines 371. The programming interconnection line 361 or the fixed interconnection line 364 is coupled to the CPU chip 269b, and each DPIIC chip 410 can be coupled through the programmable interconnection line 361 or the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 Connected to all the HBMIC chips 251, the CPU chip 269b can be coupled to all the TPU chips 269c through one or more programmable interconnection lines 361 or fixed interconnection lines 364 of one or more inter-chip interconnection lines 371, and the CPU chip 269b can be connected to all the TPU chips 269c through The programmable interconnection lines 361 or the fixed interconnection lines 364 of the one or more inter-die interconnection lines 371 are coupled to all the HBMIC chips 251 , and one of the TPU chips 269c can pass through the one or more inter-die interconnection lines 371 It can be The programming interconnect 361 or the fixed interconnect 364 is coupled to one of the HBMIC chips 251, and the data bit width transmitted between the one of the TPU chips 269c and the one of the HBMIC chips 251 may be Greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, each NVMIC chip 250 can be interconnected through one or more programmable interconnect lines 361 or fixed interconnect lines 371 The line 364 is coupled to the dedicated control chip 260, and each HBMIC chip 251 can be coupled to the dedicated control chip 260 through one or more programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-chip interconnect lines 371. A TPU chip 269c can be coupled to the dedicated control chip 260 through one or more programmable interconnect lines 361 or fixed interconnect lines 364, and the CPU chip 269b can communicate with one or more chips. The programmable interconnection lines 361 or the fixed interconnection lines 364 of the connection lines 371 are coupled to the dedicated control chip 260 .

Referring to FIG. 11N, the logical driver 300 may include a plurality of dedicated I/O chips 265 located in the surrounding area of the logical driver 300, which surrounds the middle area of the logical driver 300, wherein the middle area of the logical driver 300 accommodates the Standard commercial FPGAIC die 200, NVMIC die 321, dedicated control die 260, TPU die 269c, CPU die 269b, HBMIC die 251, and DPIIC die 410. Each standard commercial FPGAIC die 200 may be coupled to all of the dedicated I/O die 265 via one or more inter-die interconnects 371, programmable interconnects 361 or fixed interconnects 364, each DPIIC Die 410 can be coupled to all of the dedicated I/O die 265 via one or more programmable interconnect lines 361 or fixed interconnect lines 364 of inter-die interconnect lines 371, and each NVMIC die 321 can be coupled to all of the dedicated I/O die 265 via one or more The programmable interconnect lines 361 or the fixed interconnect lines 364 of the inter-die interconnect lines 371 are coupled to all the dedicated I/O chips 265, and the dedicated control chips 260 can be connected via one or more inter-die interconnect lines 371. Programmable interconnect lines 361 or fixed interconnect lines 364 are coupled to all dedicated I/O chips 265, and each TPU chip 269c can be connected via programmable interconnect lines 361 or fixed through one or more inter-die interconnect lines 371 Interconnect lines 364 are coupled to all dedicated I/O chips 265, and CPU chip 269b may be coupled to all dedicated I/O chips 269 via programmable interconnect lines 361 or fixed interconnect lines 364 of one or more inter-die interconnect lines 371 I/O chips 265, each HBMIC chip 251 can be coupled to all dedicated I/O chips 265 via programmable interconnects 361 or fixed interconnects 364 of one or more inter-die interconnects 371.

Therefore, in the eleventh type logic driver 300, the TPU chip 269c can cooperate with the HBMIC chip 251 to perform high-speed, high-bandwidth parallel processing and/or parallel computing. Referring to FIG. 11N, each standard commercial FPGAIC chip 200 can refer to the content disclosed in FIGS. 8A to 8J, and each DPIIC chip 410 can refer to the content disclosed in FIG. 9. FIG. In addition, standard commercial FPGAIC chip 200, DPIIC chip 410, dedicated I/O chip 265, NVMIC chip 250, dedicated control chip 260 can also refer to the contents disclosed in FIG. 11A.

To sum up, please refer to FIGS. 11F to 11N , when the programmable interconnect lines 361 of the standard commercial FPGAIC chip 200 and the programmable interconnect lines 361 of the DPIIC chip 410 are programmed, the programmable interconnect lines after programming The interconnection lines 361 can cooperate with the fixed interconnection lines 364 of the standard commercial FPGAIC chip 200 and the fixed interconnection lines 364 of the DPIIC chip 410 to provide specific functions for specific applications. In the same logic driver 300, the standard commercial FPGAIC chip 200 can simultaneously cooperate with the operation of the PCIC chip 269 such as a GPU chip, a CPU chip, a TPU chip or a DSP chip to provide powerful functions and operations for the following applications: artificial intelligence (AI) ), Machine Learning, Deep Learning, Big Data, Internet of Things (IOT), Virtual Reality (VR), Augmented Reality (AR), Autonomous Vehicle Electronics, Graphics Processing (GP), Digital Signal Processing (DSP), Microcontroller ( MC) and/or central processing (CP), etc.

Interconnection of logical drives

12A to 12C are schematic diagrams of various connection forms in a logical driver according to an embodiment of the present application. Please refer to FIGS. 12A to 12C, the block 250 represents the combination of the NVMIC chips 250 in the logic driver 300 as shown in FIGS. 11A to 11N, and the two blocks 200 represent the combination of the NVMIC chips 250 as shown in FIGS. 11A to 11N Two different groups of standard commercial FPGAIC chips 200 are shown in logic driver 300, block 410 represents the combination of DPIIC chips 410 in logic driver 300 as shown in FIGS. 11A-11N, block 265 represents the combination of dedicated I/O chips 265 in the logical driver 300 as shown in Figures 11A-11N, and the block 360 represents the combination of the dedicated I/O chips 265 in the logical driver 300 as shown in Figures 11A-11N Control die 260 , dedicated control and I/O die 266 , DCIAC die 267 or DCDI/OIAC die 268 .

Referring to FIGS. 11A to 11N and FIGS. 12A to 12C, the NVMIC chip 250 can load the result value or the first programming code from the external circuit 271 located outside the logic driver 300, so that the inter-chip interconnection The fixed cross-connect line 364 of line 371 and the fixed cross-connect line 364 of the on-chip cross-connect line 502 of the standard commercial FPGAIC chip 200 can transmit the result value or the first programming code from the NVMIC chip 250 to the standard commercial FPGAIC chip 200 The memory cell 490 is used to program the programmable logic block 201 of the standard commercial FPGAIC chip 200, as disclosed in FIG. 6A. The NVMIC chip 250 can load the second programming code from the external circuit 271 located outside the logic driver 300 so that the fixed interconnect 364 of the inter-die interconnect 371 and the intra-chip interconnect of the standard commercial FPGAIC chip 200 The fixed interconnect line 364 of 502 can transmit the second programming code from the NVMIC chip 250 to the memory unit 362 of the standard commercial FPGAIC chip 200 for programming the pass/fail switches 258 and/or crossovers of the standard commercial FPGAIC chip 200 Click the switch 379, as disclosed in Figs. 2A to 2F, Figs. 3A to 3D, and Figs. 7A to 7C. The NVMIC chip 250 can load the third programming code from the external circuit 271 located outside the logic driver 300 , so that the fixed interconnection lines 364 of the inter-die interconnection lines 371 and the in-chip interconnection lines of the DPIIC chip 410 are interconnected The connection line 364 can transmit the third programming code from the NVMIC chip 250 to the memory unit 362 of the DPIIC chip 410 for programming the pass/no pass switch 258 and/or the cross point switch 379 of the DPIIC chip 410, as shown in Figs. The contents disclosed in Figure 2F, Figure 3A to Figure 3D, and Figure 7A to Figure 7C. In one embodiment, the external circuit 271 located outside the logic driver 300 does not allow the above-mentioned result value, the first programming code, the second programming code and the third programming code to be loaded by any NVMIC chip 250 in the logic driver 300. programming code; or in other embodiments, the external circuit 271 located outside the logic driver 300 may be allowed to load the above-mentioned result value, the first programming code, and the second programming code from the NVMIC chip 250 in the logic driver 300 and the third programming code.

I. Type 1 Interconnection Architecture of Logical Drives

Referring to FIGS. 11A to 11N and 12A, the small I/O circuits 203 of each dedicated I/O chip 265 may be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all standard commercial FPGA IC chips 200, the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed to interact via one or more inter-chip interconnect lines 371 The connection lines 361 are coupled to the small I/O circuits 203 of all DPIIC chips 410, and the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed via one or more inter-chip interconnection lines 371. The interconnect line 361 is coupled to the small I/O circuits 203 of all other dedicated I/O chips 265, and the small I/O circuits 203 of each dedicated I/O chip 265 can be interconnected via one or more inter-chips The fixed interconnection lines 364 of line 371 are coupled to the small I/O circuits 203 of all standard commercial FPGAIC chips 200, the small I/O circuits 203 of each dedicated I/O chip 265 can be via one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the miniature I/O circuits 203 of all DPIIC chips 410, and the miniature I/O circuits 203 of each dedicated I/O chip 265 may pass through one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the small I/O circuits 203 of all other dedicated I/O chips 265 .

Referring to FIGS. 11A to 11N and 12A, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all of them via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 The small I/O circuits 203 of the standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to the The small I/O circuits 203 of all other DPIIC chips 410 , the small I/O circuits 203 of each DPIIC chip 410 may be coupled to all the The small I/O circuits 203 of standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all the others via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The small I/O circuit 203 of the DPIIC chip 410.

Referring to FIGS. 11A-11N and 12A, the small I/O circuits 203 of each of the standard commercial FPGAIC chips 200 can be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all other standard commercial FPGA IC chips 200, each of which can interact via fixed interaction of one or more inter-chip interconnect lines 371 Connection lines 364 are coupled to all other small I/O circuits 203 of standard commercial FPGA IC chips 200 .

Please refer to FIG. 11A to FIG. 11N and FIG. 12A , the small I/O circuit 203 of the dedicated control chip 260 represented by the control block 360 , the dedicated control and I/O chip 266 , the DCIAC chip 267 or the DCDI/OIAC chip 268 The small I/O circuits 203 of all standard commercial FPGA IC chips 200 can be coupled to the small I/O circuits 203 of all standard commercial FPGA IC chips 200 via the programmable interconnect wires 361 of one or more inter-chip interconnect wires 371, the dedicated control chip 260 represented by the control block 360, the dedicated The small I/O circuits 203 of the control and I/O chip 266, DCIAC chip 267, or DCDI/OIAC chip 268 may be coupled to all standard commercial The small I/O circuit 203 of the FPGAIC chip 200, the dedicated control chip 260 represented by the control block 360, the dedicated control and I/O chip 266, the small I/O circuit 203 of the DCIAC chip 267, or the DCDI/OIAC chip 268 can pass through a The programmable interconnect lines 361 of the or multiple inter-chip interconnect lines 371 are coupled to the small I/O circuits 203 of all the DPIIC chips 410, the dedicated control chips 260, the dedicated control and I/O chips represented by the control block 360 266. The small I/O circuits 203 of the DCIAC chip 267 or the DCDI/OIAC chip 268 can be coupled to all the small I/O circuits of the DPIIC chip 410 via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 203. The large-scale I/O circuit 341 of the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 can be connected via one or more inter-chip interconnect lines 371 The fixed interconnect line 364 is coupled to the large I/O circuits 341 of all the NVMIC chips 250, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip represented by the control block 360 The large I/O circuits 341 of 268 may be coupled to the large I/O circuits 341 of all dedicated I/O chips 265 via the fixed interconnect lines 364 of one or more inter-die interconnect lines 371 , as represented by the control block 360 The dedicated control chip 260 , dedicated control and I/O chip 266 , DCIAC chip 267 , or large I/O circuit 341 of the DCDI/OIAC chip 268 may be coupled to external circuits 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12A, the large I/O circuits 341 of each dedicated I/O chip 265 may be coupled via fixed interconnection lines 364 of one or more inter-die interconnection lines 371 To the large I/O circuits 341 of all NVMIC chips 250 , the large I/O circuits 341 of each dedicated I/O chip 265 may be coupled via the fixed interconnects 364 of one or more inter-die interconnects 371 To the large I/O circuits 341 of all other special purpose I/O chips 265 , the large I/O circuits 341 of each special purpose I/O chip 265 may be coupled to external circuits 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12A, the large I/O circuits 341 of each NVMIC chip 250 can be coupled to all the others via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The large I/O circuits 341 of the NVMIC chips 250 , each of which may be coupled to an external circuit 271 located outside the logic driver 300 . In the logic driver 300 of the present embodiment, each NVMIC chip 250 does not have an I/O circuit with an input capacitance, an output capacitance, a driving capability or a driving load of less than 2 pF, but has a large I/O circuit as described in FIG. 5A . The O circuit 341 performs the above-mentioned coupling. Each NVMIC chip 250 can transmit data to all standard commercial FPGAIC chips 200 via one or more dedicated I/O chips 265 , and each NVMIC chip 250 can pass through one or more dedicated I/O chips 265 Transferring data to all DPIIC chips 410, each NVMIC chip 250 cannot transfer data to a standard commercial FPGAIC chip 200 without going through the dedicated I/O chip 265, and each NVMIC chip 250 cannot Data is transferred to DPIIC chip 410 without going through dedicated I/O chip 265 .

(1) Interactive connection lines for programming memory cells

Referring to FIGS. 11A to 11N and 12A, in one embodiment, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267, or the DCDI/OIAC chip 268 represented by the control block 360 can be Generates a control command and transmits it to its large I/O circuit 341 to drive the control command to be transmitted to the first large one of the NVMIC chips 250 via the fixed interconnection line 364 of one or more inter-die interconnection lines 371 I/O circuit 341 . For one of the NVMIC chips 250 , the first large I/O circuit 341 can drive the control command to its internal circuit to instruct its internal circuit to transmit programming codes to its second large I/O circuit 341 , the second large-scale I/O circuit 341 can drive the programming code to be transmitted to the large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the programming code through one or more inter-die The fixed interconnect 364 of the interconnect 371 is routed to the small I/O circuit 203 of one of the DPIIC chips 410 . For the one of the DPIIC chips 410, the small I/O circuit 203 thereof can drive the programming code to be transmitted to the other one of the memory array blocks 423 via one or more fixed interconnection lines 364 of its in-chip interconnection lines. Memory cell 362, as described in Figure 9, such that a programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figure 2A To the content described in Figure 2F, Figure 3A to Figure 3D, and Figure 7A to Figure 7C.

Alternatively, referring to FIGS. 11A to 11N and 12A, in another embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC The chip 268 can generate a control command and transmit it to its large I/O circuit 341 to drive the control command to be transmitted to the first one of one of the NVMIC chips 250 via the fixed interconnect 364 of the one or more inter-die interconnects 371 A large I/O circuit 341. For one of the NVMIC chips 250 , the first large I/O circuit 341 can drive the control command to its internal circuit to instruct its internal circuit to transmit programming codes to its second large I/O circuit 341 , the second large-scale I/O circuit 341 can drive the programming code to be transmitted to the large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the programming code through one or more inter-die The fixed interconnect 364 of the interconnect 371 is routed to the small I/O circuit 203 of one of the standard commercial FPGA IC chips 200 . For one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive programming codes to be transmitted to one of its memory cells 362 via one or more fixed interconnect lines 364 of its on-chip interconnect lines 502. , so that the programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figures 2A to 2F, and Figures 3A to 3D and what is described in Figures 7A to 7C.

Alternatively, referring to FIGS. 11A to 11N and 12A, in another embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC The chip 268 can generate a control command and transmit it to its large I/O circuit 341 to drive the control command to be transmitted to the first one of one of the NVMIC chips 250 via the fixed interconnect 364 of the one or more inter-die interconnects 371 A large I/O circuit 341. For one of the NVMIC chips 250, the first large I/O circuit 341 can drive the control command to its internal circuit to command its internal circuit to transmit the result value or programming code to its second large I/O circuit 341. O circuit 341 , whose second large I/O circuit 341 can drive result values or programming codes to one of the dedicated I/O chips 265 via fixed interconnects 364 of one or more inter-die interconnects 371 The large I/O circuit 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the result value or programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the result value or programming code via The fixed interconnects 364 of the one or more inter-die interconnects 371 are routed to the small I/O circuits 203 of one of the standard commercial FPGA IC chips 200 . For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the result value or programming code to transmit the result value or programming code via one or more of its on-chip interconnect lines 502 fixed interconnect lines 364 to one of the other Memory cell 490 so that the result value or programming code can be stored in one of its memory cells 490 for programming its programmable logic block 201, as described in FIG. 6A.

(2) Interactive connection lines for operation

Referring to FIGS. 11A to 11N and 12A, in one embodiment, the large I/O circuit 341 of one of the dedicated I/O chips 265 can drive signals from external circuits 271 other than the logic driver 300 To its small I/O circuit 203, the small I/O circuit 203 of the one of the dedicated I/O chips 265 can drive the signal to be sent to the The first small I/O circuit 203 of one of the DPIIC chips 410. For one of the DPIIC chips 410, the first small I/O circuit 203 can drive the signal to its cross-point switch 379 via the first programmable interconnect line 361 of its on-chip interconnect lines, Its cross-point switch 379 can switch the signal from the programmable interconnect line 361 of the first one of its on-chip interconnect lines to the programmable interconnect line 361 of the second one of its on-chip interconnect lines to transmit the signal to to its second mini-I/O circuit 203, which can drive the signal to it via programmable interconnect lines 361 of one or more inter-die interconnect lines 371 A small I/O circuit 203 of a standard commercial FPGA IC chip 200. For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the signal through the programmable interconnect lines 361 of the first set of its on-chip interconnect lines 502 as shown in Figure 8G and the bypass interconnect 279 to its crosspoint switch 379, which can switch the signal from the programmable interconnect 361 and the bypass interconnect 279 of the first set of its on-chip interconnect 502 to the The programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of in-chip interconnect lines 502 are transmitted to one of the inputs A0-A3 of its programmable logic block (LB) 201, such as The content described in Figure 6A.

Please refer to FIGS. 11A to 11N and 12A. In another embodiment, the programmable logic block (LB) 201 of the first standard commercialized FPGAIC chip 200 can generate the output Dout, as shown in FIG. 6A As described, programmable interconnect lines 361 and bypass interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can transmit the output Dout via The programmable interconnection lines 361 and the bypass interconnection lines 279 of the first group of its in-chip interconnection lines 502 are switched to the programmable interconnection lines 361 and the bypass interconnection lines 279 of the second group of its in-chip interconnection lines 502 to transmit to its small I/O circuit 203, which can drive the output Dout to transmit to one of the programmable interconnect lines 361 of one or more inter-die interconnect lines The small I/O circuit 203 of the first of the DPIIC chips 410 . For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of the second standard commercial FPGA IC chip 200. For the second standard commercial FPGAIC chip 200, its small I/O circuit 203 can drive the output Dout through the programmable interconnect lines of the first set of its on-chip interconnect lines 502 as shown in Figure 8G 361 and the bypass interconnect 279 are sent to its crosspoint switch 379, which can send the output Dout from the programmable interconnect 361 and bypass interconnect 279 of the first set of its on-chip interconnect 502 Switch to the second set of programmable interconnect lines 361 and bypass interconnect lines 279 of its on-chip interconnect lines 502 for transmission to one of the inputs A0-A3 of its programmable logic block (LB) 201 , as described in Figure 6A.

Please refer to FIGS. 11A to 11N and 12A. In another embodiment, the programmable logic block (LB) 201 of the standard commercial FPGAIC chip 200 can generate the output Dout, as described in FIG. 6A , the programmable interconnect lines 361 and the detour interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can communicate the output Dout via its on-chip interconnect The programmable interconnect lines 361 and the bypass interconnect lines 279 of the first group of interconnect lines 502 are switched to the programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of the interconnect lines 502 within its chip for transmission to It is transmitted to its small I/O circuit 203, which can drive the output Dout to be transmitted to one of the DPIIC chips 410 via the programmable interconnect line 361 of one or more inter-die interconnect lines 371. The first small I/O circuit 203. For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of one of the dedicated I/O chips 265. For one of the dedicated I/O chips 265 , its small I/O circuit 203 can drive the output Dout to its large I/O circuit 341 for transmission to an external circuit 271 located outside the logic driver 300 .

(3) Interactive connection lines for control

Referring to FIGS. 11A to 11N and 12A, in one embodiment, for the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 , the large I/O circuit 341 can receive control commands from the external circuit 271 located outside the logic driver 300 , or can transmit control commands to the external circuit 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12A, in another embodiment, the large I/O circuit 341 of the first one of the dedicated I/O chips 265 of one of the dedicated I/O chips 265 can drive a circuit from one of the logic drivers 300 The control command of the external external circuit 271 is transmitted to its second large I/O circuit 341, and the second large I/O circuit 341 can drive the control command through one or more inter-chip interconnection lines 371. The fixed interconnect 364 is routed to the large I/O circuit 341 of the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360.

Referring to FIGS. 11A to 11N and 12A, in another embodiment, the control block 360 represents the dedicated control chip 260 , the dedicated control and I/O chip 266 , the DCIAC chip 267 or the DCDI/OIAC chip 268 The large-scale I/O circuit 341 can drive control commands to be transmitted to the first large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341, the first large I/O circuit 341 of the one of the dedicated I/O chips 265 can drive control commands to its second large I/O circuit 341 for transmission to the logic driver 300 external external circuit 271.

Therefore, please refer to FIG. 11A to FIG. 11N and FIG. 12A, the control command can be transmitted from the external circuit 271 located outside the logic driver 300 to the dedicated control chip 260, dedicated control and I/O represented by the control block 360 Chip 266, DCIAC chip 267, or DCDI/OIAC chip 268, or dedicated control chip 260, dedicated control and I/O chip 266, DCIAC chip 267, or DCDI/OIAC chip 268 represented by control block 360 is sent to the bit-in logic External circuit 271 other than driver 300 .

II. The second type of interconnection architecture of logical drives

Referring to FIGS. 11A to 11N and 12B, the small I/O circuits 203 of each dedicated I/O chip 265 may be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all standard commercial FPGA IC chips 200, the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed to interact via one or more inter-chip interconnect lines 371 The connection lines 361 are coupled to the small I/O circuits 203 of all DPIIC chips 410, and the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed via one or more inter-chip interconnection lines 371. The interconnect line 361 is coupled to the small I/O circuits 203 of all other dedicated I/O chips 265, and the small I/O circuits 203 of each dedicated I/O chip 265 can be interconnected via one or more inter-chips The fixed interconnection line 364 of line 371 is coupled to the mini-I/O circuits 203 of all standard commercial FPGAIC chips 200, the mini-I/O circuits 203 of each dedicated I/O chip 265 can be via one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the small I/O circuits 203 of all the DPIIC chips 410, and the small I/O circuits 203 of each dedicated I/O chip 265 may pass through one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the small I/O circuits 203 of all other dedicated I/O chips 265 .

Referring to FIGS. 11A to 11N and 12B, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all of them via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 The small I/O circuits 203 of the standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to the The small I/O circuits 203 of all other DPIIC chips 410 , the small I/O circuits 203 of each DPIIC chip 410 may be coupled to all the The small I/O circuits 203 of standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all other via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The small I/O circuit 203 of the DPIIC chip 410.

Referring to FIGS. 11A to 11N and 12B, the small I/O circuits 203 of each of the standard commercial FPGAIC chips 200 can be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all other standard commercial FPGA IC chips 200, each of which can interact via fixed interaction of one or more inter-chip interconnect lines 371 Connection lines 364 are coupled to all other small I/O circuits 203 of standard commercial FPGA IC chips 200 .

11A to 11N and 12B, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267, or the large I/O circuit 341 of the DCDI/OIAC chip 268 The large-scale I/O circuits 341 of all the dedicated I/O chips 265 can be coupled to the large-scale I/O circuits 341 of all the dedicated I/O chips 265 through the fixed interconnecting wires 364 of one or more inter-chip interconnecting wires 371 , the dedicated control chips 260 represented by the control block 360 , the dedicated control And the large I/O circuits 341 of the I/O die 266, DCIAC die 267 or DCDI/OIAC die 268 can be coupled to all of the NVMIC die 250 via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371. The large I/O circuit 341, the dedicated control chip 260 represented by the control block 360, the dedicated control and I/O chip 266, the large I/O circuit 341 of the DCIAC chip 267 or the DCDI/OIAC chip 268 can be coupled to the bit-in logic External circuit 271 other than driver 300 .

Referring to FIGS. 11A to 11N and 12B, the large I/O circuits 341 of each NVMIC chip 250 can be coupled to all the The large I/O circuit 341 of the dedicated I/O chip 265, the large I/O circuit 341 of each NVMIC chip 250 can be coupled to all the others via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The large I/O circuits 341 of the NVMIC chip 250, the large I/O circuits 341 of each dedicated I/O chip 265 can be coupled to other The large I/O circuits 341 of all of the dedicated I/O chips 265, the large I/O circuits 341 of each of the NVMIC chips 250 may be coupled to external circuits 271 located outside the logic driver 300, the dedicated I/O circuits of each The large I/O circuits 341 of the /O die 265 may be coupled to external circuits 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12B, in the logic driver 300 of the present embodiment, each NVMIC chip 250 does not have an input capacitance, an output capacitance, a driving capability or an I/O whose driving load is less than 2pF The circuit has a large I/O circuit 341 as described in FIG. 5A for the above-mentioned coupling. Each NVMIC chip 250 can transmit data to all standard commercial FPGAIC chips 200 via one or more dedicated I/O chips 265 , and each NVMIC chip 250 can pass through one or more dedicated I/O chips 265 To transfer data to all DPIIC chips 410, each NVMIC chip 250 cannot transfer data to a standard commercial FPGAIC chip 200 without going through the dedicated I/O chip 265, and each NVMIC chip 250 cannot Data is transferred to DPIIC chip 410 without going through dedicated I/O chip 265 . In the logic driver 300 of this embodiment, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the chip control block 360 do not have input capacitors, output capacitors, drive An I/O circuit with a capacity or drive load of less than 2pF, but with a large I/O circuit 341 as depicted in FIG. 5A, performs the above-mentioned coupling. The dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267, or the DCDI/OIAC chip 268 represented by the control block 360 can transmit control commands or other signals to all of the The standard commercial FPGAIC chip 200, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267, or the DCDI/OIAC chip 268 represented by the control block 360 can pass through one or more of the dedicated I/O chips 265 To transmit control commands or other signals to all DPIIC chips 410, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 cannot be used without the dedicated I/O chip 268. In the case of the /O chip 265, it transmits control commands or other signals to the standard commercial FPGAIC chip 200, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360. It is not possible to transmit control commands or other signals to the DPIIC chip 410 without going through the dedicated I/O chip 265 .

(1) Interactive connection lines for programming memory cells

Referring to FIGS. 11A to 11N and 12B, in one embodiment, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 can be Generates a control command and transmits it to its large I/O circuit 341 to drive the control command to be transmitted to the first large one of the NVMIC chips 250 via the fixed interconnection line 364 of one or more inter-die interconnection lines 371 I/O circuit 341 . For one of the NVMIC chips 250 , the first large I/O circuit 341 can drive the control command to its internal circuit to instruct its internal circuit to transmit programming codes to its second large I/O circuit 341 , the second large-scale I/O circuit 341 can drive the programming code to be transmitted to the large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the programming code through one or more inter-die The fixed interconnect 364 of the interconnect 371 is routed to the small I/O circuit 203 of one of the DPIIC chips 410 . For the one of the DPIIC chips 410, the small I/O circuit 203 thereof can drive the programming code to be transmitted to the other one of the memory array blocks 423 via one or more fixed interconnection lines 364 of its in-chip interconnection lines. Memory cell 362, as described in Figure 9, such that a programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figure 2A To the content described in Figure 2F, Figure 3A to Figure 3D, and Figure 7A to Figure 7C.

Alternatively, referring to FIGS. 11A to 11N and 12B, in one embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 can generate a control command to transmit to its large I/O circuit 341 to drive the control command to be transmitted to the first of one of the NVMIC chips 250 via the fixed interconnect 364 of one or more inter-die interconnects 371 The large I/O circuit 341. For one of the NVMIC chips 250 , the first large I/O circuit 341 can drive the control command to its internal circuit to instruct its internal circuit to transmit programming codes to its second large I/O circuit 341 , the second large-scale I/O circuit 341 can drive the programming code to be transmitted to the large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the programming code through one or more inter-die The fixed interconnect 364 of the interconnect 371 is routed to the small I/O circuit 203 of one of the standard commercial FPGA IC chips 200 . For one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive programming codes to be transmitted to one of its memory cells 362 via one or more fixed interconnect lines 364 of its on-chip interconnect lines 502. , so that the programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figures 2A to 2F, and Figures 3A to 3D and what is described in Figures 7A to 7C.

Alternatively, referring to FIGS. 11A to 11N and 12B, in one embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 can generate a control command to transmit to its large I/O circuit 341 to drive the control command to be transmitted to the first of one of the NVMIC chips 250 via the fixed interconnect 364 of one or more inter-die interconnects 371 The large I/O circuit 341. For one of the NVMIC chips 250, the first large I/O circuit 341 can drive the control command to its internal circuit to command its internal circuit to transmit the result value or programming code to its second large I/O circuit 341. O circuit 341 , whose second large I/O circuit 341 can drive result values or programming codes to one of the dedicated I/O chips 265 via fixed interconnects 364 of one or more inter-die interconnects 371 The large I/O circuit 341. For one of the dedicated I/O chips 265, its large I/O circuit 341 can drive the result value or programming code to its small I/O circuit 203, and its small I/O circuit 203 can drive the result value or programming code via The fixed interconnects 364 of the one or more inter-die interconnects 371 are routed to the small I/O circuits 203 of one of the standard commercial FPGA IC chips 200 . For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the result value or programming code to transmit the result value or programming code via one or more of its on-chip interconnect lines 502 fixed interconnect lines 364 to one of the other Memory cell 490 so that the result value or programming code can be stored in one of its memory cells 490 for programming its programmable logic block 201, as described in FIG. 6A.

(2) Interactive connection lines for operation

Referring to FIGS. 11A to 11N and 12B, in one embodiment, the large I/O circuit 341 of one of the dedicated I/O chips 265 can drive signals from external circuits 271 other than the logic driver 300 To its small I/O circuit 203, the small I/O circuit 203 of the one of the dedicated I/O chips 265 can drive the signal to be sent to the The first small I/O circuit 203 of one of the DPIIC chips 410. For one of the DPIIC chips 410, the first small I/O circuit 203 can drive the signal to its cross-point switch 379 via the first programmable interconnect line 361 of its on-chip interconnect lines, Its cross-point switch 379 can switch the signal from the programmable interconnect line 361 of the first one of its on-chip interconnect lines to the programmable interconnect line 361 of the second one of its on-chip interconnect lines to transmit the signal to to its second mini-I/O circuit 203, which can drive the signal to it via programmable interconnect lines 361 of one or more inter-die interconnect lines 371 A small I/O circuit 203 of a standard commercial FPGA IC chip 200. For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the signal through the programmable interconnect lines 361 of the first set of its on-chip interconnect lines 502 as shown in Figure 8G and the bypass interconnect 279 to its crosspoint switch 379, which can switch the signal from the programmable interconnect 361 and the bypass interconnect 279 of the first set of its on-chip interconnect 502 to the The programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of in-chip interconnect lines 502 are transmitted to one of the inputs A0-A3 of its programmable logic block (LB) 201, such as The content described in Figure 6A.

Please refer to FIGS. 11A to 11N and 12B. In another embodiment, the programmable logic block (LB) 201 of the first standard commercial FPGAIC chip 200 can generate the output Dout, as shown in FIG. 6A As described, programmable interconnect lines 361 and bypass interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can transmit the output Dout via The programmable interconnection lines 361 and the bypass interconnection lines 279 of the first group of its in-chip interconnection lines 502 are switched to the programmable interconnection lines 361 and the bypass interconnection lines 279 of the second group of its in-chip interconnection lines 502 to transmit to its small I/O circuit 203, which can drive the output Dout to transmit to one of the programmable interconnect lines 361 of one or more inter-die interconnect lines The small I/O circuit 203 of the first of the DPIIC chips 410 . For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of the second standard commercial FPGA IC chip 200. For the second standard commercial FPGAIC chip 200, its small I/O circuit 203 can drive the output Dout through the programmable interconnect lines of the first set of its on-chip interconnect lines 502 as shown in Figure 8G 361 and the bypass interconnect 279 are sent to its crosspoint switch 379, which can send the output Dout from the programmable interconnect 361 and bypass interconnect 279 of the first set of its on-chip interconnect 502 Switch to the second set of programmable interconnect lines 361 and bypass interconnect lines 279 of its on-chip interconnect lines 502 for transmission to one of the inputs A0-A3 of its programmable logic block (LB) 201 , as described in Figure 6A.

Referring to FIGS. 11A to 11N and 12B, in another embodiment, the programmable logic block (LB) 201 of the standard commercial FPGAIC chip 200 can generate the output Dout, as described in FIG. 6A , the programmable interconnect lines 361 and the detour interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can communicate the output Dout via its on-chip interconnect The programmable interconnect lines 361 and the bypass interconnect lines 279 of the first group of interconnect lines 502 are switched to the programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of the interconnect lines 502 within its chip for transmission to It is transmitted to its small I/O circuit 203, which can drive the output Dout to be transmitted to one of the DPIIC chips 410 via the programmable interconnect line 361 of one or more inter-die interconnect lines 371. The first small I/O circuit 203. For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of one of the dedicated I/O chips 265. For one of the dedicated I/O chips 265 , its small I/O circuit 203 can drive the output Dout to its large I/O circuit 341 for transmission to an external circuit 271 located outside the logic driver 300 .

(3) Interactive connection lines for control

Referring to FIGS. 11A to 11N and 12B, in one embodiment, for the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 , the large I/O circuit 341 can receive control commands from the external circuit 271 located outside the logic driver 300 , or can transmit control commands to the external circuit 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12B, in another embodiment, the large I/O circuit 341 of the first one of the dedicated I/O chips 265 of one of the dedicated I/O chips 265 can drive the circuit from the logic driver 300 The control command of the external external circuit 271 is transmitted to its second large I/O circuit 341, and the second large I/O circuit 341 can drive the control command through one or more inter-chip interconnection lines 371. The fixed interconnect 364 is routed to the large I/O circuit 341 of the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360.

Please refer to FIGS. 11A to 11N and 12B. In another embodiment, the control block 360 represents the dedicated control chip 260 , the dedicated control and I/O chip 266 , the DCIAC chip 267 or the DCDI/OIAC chip 268 The large-scale I/O circuit 341 can drive control commands to be transmitted to the first large-scale I/O circuit of one of the dedicated I/O chips 265 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 341, the first large I/O circuit 341 of the one of the dedicated I/O chips 265 can drive control commands to its second large I/O circuit 341 for transmission to the logic driver 300 external external circuit 271.

Therefore, referring to FIGS. 11A to 11N and 12B, control commands can be transmitted from the external circuit 271 outside the logic driver 300 to the dedicated control chip 260, dedicated control and I/O represented by the control block 360 Chip 266, DCIAC chip 267, or DCDI/OIAC chip 268, or dedicated control chip 260, dedicated control and I/O chip 266, DCIAC chip 267, or DCDI/OIAC chip 268 represented by control block 360 is sent to the bit-in logic External circuit 271 other than driver 300 .

III. Type 3 Interconnection Architecture of Logical Drives

Referring to FIGS. 11A to 11N and 12C, the small I/O circuits 203 of each dedicated I/O chip 265 may be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all standard commercial FPGA IC chips 200, the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed to interact via one or more inter-chip interconnect lines 371 The connection lines 361 are coupled to the small I/O circuits 203 of all DPIIC chips 410, and the small I/O circuits 203 of each dedicated I/O chip 265 can be programmed via one or more inter-chip interconnection lines 371. The interconnect line 361 is coupled to the small I/O circuits 203 of all other dedicated I/O chips 265, and the small I/O circuits 203 of each dedicated I/O chip 265 can be interconnected via one or more inter-chips The fixed interconnection line 364 of line 371 is coupled to the mini-I/O circuits 203 of all standard commercial FPGAIC chips 200, the mini-I/O circuits 203 of each dedicated I/O chip 265 can be via one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the small I/O circuits 203 of all the DPIIC chips 410, and the small I/O circuits 203 of each dedicated I/O chip 265 may pass through one or more chips The fixed interconnection lines 364 of the interconnection lines 371 are coupled to the small I/O circuits 203 of all other dedicated I/O chips 265 .

Referring to FIGS. 11A to 11N and 12C, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all of them via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 The small I/O circuits 203 of the standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to the The small I/O circuits 203 of all other DPIIC chips 410 , the small I/O circuits 203 of each DPIIC chip 410 may be coupled to all the The small I/O circuits 203 of standard commercial FPGAIC chips 200, the small I/O circuits 203 of each DPIIC chip 410 can be coupled to all other via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The small I/O circuit 203 of the DPIIC chip 410.

Referring to FIGS. 11A to 11N and 12C, the small I/O circuits 203 of each of the standard commercial FPGAIC chips 200 can be coupled via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 Small I/O circuits 203 connected to all other standard commercial FPGA IC chips 200, each of which can interact via fixed interaction of one or more inter-chip interconnect lines 371 Connection lines 364 are coupled to all other small I/O circuits 203 of standard commercial FPGA IC chips 200 .

11A to 11N and 12C, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the small I/O circuit 203 of the DCDI/OIAC chip 268 The small I/O circuits 203 of all standard commercial FPGA IC chips 200 can be coupled to the small I/O circuits 203 of all standard commercial FPGA IC chips 200 via the programmable interconnect wires 361 of one or more inter-chip interconnect wires 371, the dedicated control chip 260 represented by the control block 360, the dedicated The small I/O circuits 203 of the control and I/O chip 266, DCIAC chip 267, or DCDI/OIAC chip 268 may be coupled to all standard commercial The small I/O circuit 203 of the FPGAIC chip 200, the dedicated control chip 260 represented by the control block 360, the dedicated control and I/O chip 266, the small I/O circuit 203 of the DCIAC chip 267, or the DCDI/OIAC chip 268 can pass through a The programmable interconnect lines 361 of the or multiple inter-chip interconnect lines 371 are coupled to the small I/O circuits 203 of all the DPIIC chips 410, the dedicated control chips 260, the dedicated control and I/O chips represented by the control block 360 266. The small I/O circuits 203 of the DCIAC chip 267 or the DCDI/OIAC chip 268 can be coupled to all the small I/O circuits of the DPIIC chip 410 via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 203. The small I/O circuits 203 of the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 can be connected via one or more inter-chip interconnect lines 371 The fixed interconnect line 364 is coupled to the small I/O circuits 203 of all the NVMIC chips 250, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip represented by the control block 360 The mini-I/O circuits 203 of 268 can be coupled to the mini-I/O circuits 203 of all dedicated I/O chips 265 via fixed interconnect lines 364 of one or more inter-die interconnect lines 371, as represented by control block 360 The dedicated control chip 260 , dedicated control and I/O chip 266 , DCIAC chip 267 , or large I/O circuit 341 of the DCDI/OIAC chip 268 may be coupled to external circuits 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12C, the small I/O circuits 203 of each dedicated I/O chip 265 may be coupled via the fixed interconnection lines 364 of one or more inter-chip interconnection lines 371 To the miniature I/O circuits 203 of all NVMIC chips 250 , the miniature I/O circuits 203 of each dedicated I/O chip 265 may be coupled via fixed interconnections 364 of one or more inter-die interconnections 371 To the small I/O circuits 203 of all other dedicated I/O chips 265 , the large I/O circuits 341 of each dedicated I/O chip 265 may be coupled to external circuits 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12C, the small I/O circuits 203 of each NVMIC chip 250 can be coupled to all of them via the programmable interconnect lines 361 of one or more inter-die interconnect lines 371 The small I/O circuits 203 of the standard commercial FPGAIC chips 200, the small I/O circuits 203 of each NVMIC chip 250 can be coupled to all the The small I/O circuits 203 of the standard commercial FPGAIC chips 200, the small I/O circuits 203 of each NVMIC chip 250 can be coupled to the The small I/O circuits 203 of all DPIIC chips 410, and the small I/O circuits 203 of each NVMIC chip 250 can be coupled to all of the DPIICs via the fixed interconnection lines 364 of one or more inter-die interconnection lines 371 The small I/O circuits 203 of the chip 410, the small I/O circuits 203 of each NVMIC chip 250 can be coupled to all other NVMIC chips 250 via the fixed interconnection lines 364 of the one or more inter-die interconnection lines 371 The small I/O circuits 203 , the large I/O circuits 341 of each NVMIC die 250 may be coupled to external circuits 271 located outside the logic driver 300 .

(1) Interactive connection lines for programming memory cells

Referring to FIGS. 11A to 11N and 12C, in one embodiment, the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267, or the DCDI/OIAC chip 268 represented by the control block 360 can be Generates a control command and transmits it to its small I/O circuit 203 to drive the control command to be transmitted to the first one of the NVMIC chips 250 via the fixed interconnection line 364 of one or more inter-die interconnection lines 371 I/O circuit 203 . For one of the NVMIC chips 250, the first small I/O circuit 203 can drive the control command to its internal circuit to instruct its internal circuit to transmit the programming code to its second small I/O circuit 203 , the second small I/O circuit 203 can drive the programming code to be transmitted to the small I/O circuit 203 of one of the DPIIC chips 410 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 . For the one of the DPIIC chips 410, the small I/O circuit 203 thereof can drive the programming code to be transmitted to the other one of the memory array blocks 423 via one or more fixed interconnection lines 364 of its in-chip interconnection lines. Memory cell 362, as described in Figure 9, such that a programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figure 2A To the content described in Figure 2F, Figure 3A to Figure 3D, and Figure 7A to Figure 7C.

Alternatively, referring to FIGS. 11A to 11N and 12C, in another embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC The chip 268 can generate a control command and transmit it to its small I/O circuit 203 to drive the control command to be transmitted to the first one of one of the NVMIC chips 250 via the fixed interconnect line 364 of the one or more inter-die interconnect lines 371 A small I/O circuit 203 is provided. For one of the NVMIC chips 250, the first small I/O circuit 203 can drive the control command to its internal circuit to instruct its internal circuit to transmit the programming code to its second small I/O circuit 203 , the second small I/O circuit 203 can drive the programming code to be transmitted to the small I/O circuit of one of the standard commercial FPGAIC chips 200 via the fixed interconnection line 364 of one or more inter-chip interconnection lines 371 203. For one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive programming codes to be transmitted to one of its memory cells 362 via one or more fixed interconnect lines 364 of its on-chip interconnect lines 502. , so that the programming code can be stored in one of its memory cells 362 for programming its pass/fail switch 258 and/or crosspoint switch 379, as shown in Figures 2A to 2F, and Figures 3A to 3D and what is described in Figures 7A to 7C.

Alternatively, referring to FIGS. 11A to 11N and 12C, in another embodiment, the control block 360 represents the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC The chip 268 can generate a control command and transmit it to its small I/O circuit 203 to drive the control command to be transmitted to the first one of one of the NVMIC chips 250 via the fixed interconnect line 364 of the one or more inter-die interconnect lines 371 A small I/O circuit 203 is provided. For one of the NVMIC chips 250, the first small I/O circuit 203 can drive the control command to its internal circuit to command its internal circuit to transmit the result value or programming code to its second small I/O circuit 203. O circuit 203 , whose second small I/O circuit 203 can drive result values or programming codes to one of the standard commercial FPGA IC chips 200 via fixed interconnect lines 364 of one or more inter-die interconnect lines 371 The small I/O circuit 203. For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the result value or programming code to transmit the result value or programming code via one or more of its on-chip interconnect lines 502 fixed interconnect lines 364 to one of the other Memory cell 490 so that the result value or programming code can be stored in one of its memory cells 490 for programming its programmable logic block 201, as described in FIG. 6A.

(2) Interactive connection lines for operation

Referring to FIGS. 11A to 11N and 12C, in one embodiment, the large I/O circuit 341 of one of the dedicated I/O chips 265 can drive signals from external circuits 271 other than the logic driver 300 To its small I/O circuit 203, the small I/O circuit 203 of the one of the dedicated I/O chips 265 can drive the signal to be sent to the The first small I/O circuit 203 of one of the DPIIC chips 410. For one of the DPIIC chips 410, the first small I/O circuit 203 can drive the signal to its cross-point switch 379 via the first programmable interconnect line 361 of its on-chip interconnect lines, Its cross-point switch 379 can switch the signal from the programmable interconnect line 361 of the first one of its on-chip interconnect lines to the programmable interconnect line 361 of the second one of its on-chip interconnect lines to transmit the signal to to its second mini-I/O circuit 203, which can drive the signal to it via programmable interconnect lines 361 of one or more inter-die interconnect lines 371 A small I/O circuit 203 of a standard commercial FPGA IC chip 200. For the one of the standard commercial FPGA IC chips 200, its small I/O circuits 203 can drive the signal through the programmable interconnect lines 361 of the first set of its on-chip interconnect lines 502 as shown in Figure 8G and the bypass interconnect 279 to its crosspoint switch 379, which can switch the signal from the programmable interconnect 361 and the bypass interconnect 279 of the first set of its on-chip interconnect 502 to the The programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of in-chip interconnect lines 502 are transmitted to one of the inputs A0-A3 of its programmable logic block (LB) 201, such as The content described in Figure 6A.

Referring to FIGS. 11A to 11N and 12C, in another embodiment, the programmable logic block (LB) 201 of the first standard commercial FPGAIC chip 200 can generate the output Dout, as shown in FIG. 6A As described, programmable interconnect lines 361 and bypass interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can transmit the output Dout via The programmable interconnection lines 361 and the bypass interconnection lines 279 of the first group of its in-chip interconnection lines 502 are switched to the programmable interconnection lines 361 and the bypass interconnection lines 279 of the second group of its in-chip interconnection lines 502 to transmit to its small I/O circuit 203, which can drive the output Dout to transmit to one of the programmable interconnect lines 361 of one or more inter-die interconnect lines The small I/O circuit 203 of the first of the DPIIC chips 410 . For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of the second standard commercial FPGA IC chip 200. For the second standard commercial FPGAIC chip 200, its small I/O circuit 203 can drive the output Dout through the programmable interconnect lines of the first set of its on-chip interconnect lines 502 as shown in Figure 8G 361 and the bypass interconnect 279 are sent to its crosspoint switch 379, which can send the output Dout from the programmable interconnect 361 and bypass interconnect 279 of the first set of its on-chip interconnect 502 Switch to the second set of programmable interconnect lines 361 and bypass interconnect lines 279 of its on-chip interconnect lines 502 for transmission to one of the inputs A0-A3 of its programmable logic block (LB) 201 , as described in Figure 6A.

Please refer to FIGS. 11A to 11N and 12C. In another embodiment, the programmable logic block (LB) 201 of the standard commercial FPGAIC chip 200 can generate the output Dout, as described in FIG. 6A , the programmable interconnect lines 361 and the detour interconnect lines 279 of the first set of interconnect lines 502 via its on-chip can be communicated to its cross-point switch 379, which can communicate the output Dout via its on-chip interconnect The programmable interconnect lines 361 and the bypass interconnect lines 279 of the first group of interconnect lines 502 are switched to the programmable interconnect lines 361 and the bypass interconnect lines 279 of the second group of the interconnect lines 502 within its chip for transmission to It is transmitted to its small I/O circuit 203, which can drive the output Dout to be transmitted to one of the DPIIC chips 410 via the programmable interconnect line 361 of one or more inter-die interconnect lines 371. The first small I/O circuit 203. For the one of the DPIIC chips 410, its first small I/O circuit 203 can drive the output Dout to its cross-point switch 379 via the first set of programmable interconnect lines 361 of its on-chip interconnect lines , its cross-point switch 379 can switch the output Dout from the programmable interconnect lines 361 of its first group of intra-chip interconnect lines to the programmable interconnect lines 361 of its second group of intra-chip interconnect lines for transmission , to be transmitted to its second mini-I/O circuit 203, which can drive the output Dout via one or more programmable interconnect lines 371 between wafers 361 to the small I/O circuit 203 of one of the dedicated I/O chips 265. For one of the dedicated I/O chips 265 , its small I/O circuit 203 can drive the output Dout to its large I/O circuit 341 for transmission to an external circuit 271 located outside the logic driver 300 .

(3) Interactive connection lines for control

Referring to FIGS. 11A to 11N and 12C, in one embodiment, for the dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 represented by the control block 360 , the large I/O circuit 341 can receive control commands from the external circuit 271 located outside the logic driver 300 , or can transmit control commands to the external circuit 271 located outside the logic driver 300 .

Referring to FIGS. 11A to 11N and 12C, in another embodiment, the large I/O circuits 341 of one of the dedicated I/O chips 265 can drive external circuits from outside the logic driver 300 The control command of 271 is sent to its small I/O circuit 203, and its small I/O circuit 341 can drive the control command to be sent to the control block 360 through one or more fixed interconnecting lines 364 of the inter-chip interconnecting lines 371. The dedicated control chip 260, the dedicated control and I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 are the small I/O circuits 203.

Referring to FIGS. 11A to 11N and 12C, in another embodiment, the control block 360 represents the dedicated control chip 260 , the dedicated control and I/O chip 266 , the DCIAC chip 267 or the DCDI/OIAC chip 268 The small I/O circuit 203 can drive control commands to be transmitted to the small I/O circuit 203 of one of the dedicated I/O chips 265 through the fixed interconnection line 364 of one or more inter-chip interconnection lines 371, wherein the A small I/O circuit 203 of a dedicated I/O chip 265 can drive control commands to its large I/O circuit 341 for transmission to an external circuit 271 located outside the logic driver 300.

Therefore, referring to FIGS. 11A to 11N and 12C, control commands can be transmitted from the external circuit 271 outside the logic driver 300 to the dedicated control chip 260, dedicated control and I/O represented by the control block 360 Chip 266, DCIAC chip 267, or DCDI/OIAC chip 268, or dedicated control chip 260, dedicated control and I/O chip 266, DCIAC chip 267, or DCDI/OIAC chip 268 represented by control block 360 is sent to the bit-in logic External circuit 271 other than driver 300 .

Algorithm for downloading data to memory cells

FIG. 13A is a block diagram of an algorithm for downloading data to a memory unit according to an embodiment of the present invention. As shown in FIG. 13A, it is used for downloading data to a commercial standard FPGAIC chip 200 as shown in FIGS. 8A to 8J. The plurality of memory cells 490 and 362 of the memory cells and the plurality of memory cells 362 downloaded to the memory matrix block 423 in the DPIIC chip 410 as shown in FIG. 9, a buffer/drive unit or buffer 340 may provide For driving data, such as resulting values or programming codes, output in series to the buffer/driver unit or buffer 340, and amplify the data in parallel to the plurality of memory cells 490 and memory cells 362 and ( or) to the plurality of memory cells 362 of the DPIIC chip 410, in addition, the control unit 337 can be used to control the plurality of memory cells 446 of the buffer/drive unit 340 (ie, a plurality of SRAM cells as in the first type of FIG. 1A ) is coupled in series to an input of the buffer/drive unit 340 and the control memory unit 446 is coupled in parallel to a plurality of corresponding outputs, the buffer/drive unit 340 can be respectively coupled to the commercial The plurality of memory cells 490 and 362 of the standard FPGAIC chip 200 and/or are respectively coupled to the plurality of memory cells 362 of the memory matrix block 423 in the DPIIC chip 410 in FIG. 9 .

FIG. 13B is a schematic diagram of a structure for data downloading according to an embodiment of the present invention. As shown in FIG. 13B, in the SATA standard, the joint connection point 586 includes: (1) the memory unit 446 (that is, as shown in FIG. 1A , the first (2) One end of the channel of each switch 449 in the plurality of switches 449 (that is, a complex SRAM cell of the first type as shown in FIG. 1A ) is coupled in parallel to the other or each of the other switches 449, and the other end of the channel of the switch 449 is coupled in series to a memory cell 446, and (3) one end of the channel of each of the plurality of switches 336 is coupled in series to a memory cell 446 and other terminals are coupled in series to a plurality of memory cells 490 and 362 of a commercial standard FPGAIC chip 200 as in FIGS. 8A-8J or a memory matrix block as in a DPIIC chip 410 in FIG. 9 423 of a plurality of memory cells 362.

As shown in FIG. 13B, the control unit 337 is coupled to the complex gate terminals of the switch 449 through the complex digital element line 451 (ie, a complex SRAM cell of the first type as shown in FIG. 1A ), whereby the control unit 337 For turning on the first switch 449 and turning off other switches 449 in each first clock period of each clock cycle, the control unit 337 is used for turning on a second clock in each clock period All switches 336 in the pulse period and all switches 336 in each first clock period in each clock period are closed, and the control unit 337 is used to close all switches 449 in the second clock period in each clock period .

For example, as shown in FIG. 13B, during a first first clock period within a first clock period, the control unit 337 may open the bottommost one switch 449 and close the other switches 449, thereby from The first data (eg, a first first generated value or programming code) input from the buffer/drive unit 340 is latched or stored in the bottommost memory unit 446 through the channel of the bottommost switch 449, and then , during the second first clock period in the first clock period, a switch 449 at the second bottom end can be turned on and other switches 449 can be turned off, so that the second data input from the buffer/drive unit 340 (for example, The second generation value or programming code) passes through a channel of a switch 449 on the second bottom, and is latched or stored in a memory cell 446 on the second bottom. During the first clock cycle, the control unit 337 can Turn on switch 449 sequentially, and turn on other parts of switch 449 in turn during the first clock period, so that the first set of data buffer/drive unit 340 inputs can be passed through the switches sequentially one by one from the first generated value or programming code The channels of 449 are latched or stored in memory unit 446. In the first clock period, after the input data from the buffer/driving unit 340 is sequentially and one by one latched or stored in all the memory cells 446, the control unit 337 can turn on all the memory cells 446 in the second clock period switch 336 and close all switches 449, so that the data latched or stored in the memory cell 446 can pass through the channel of the switch 336 and connect to the commercial standard FPGAIC chip 200 as shown in FIGS. 8A to 8J, respectively. The plurality of memory cells 490 and/or the memory cells 362, and/or the plurality of memory cells 362 to the memory matrix block 423 of the DPIIC chip 410 in FIG.

Next, as shown in FIG. 13B, in a second clock cycle, the control unit 337 and the buffer/drive unit 340 may perform the same steps as shown in the first clock cycle above. In the second clock period, the control unit 337 can sequentially and one by one turn on the switches 449 and close the other switches 449 in the first clock period, thereby the data from the buffer/driving unit 340 (eg, A second set of generated values or programming codes) can be latched or stored in the memory unit 446 through the switches 449 in sequence and one by one. In the second clock cycle, the data input from the buffer/drive unit 340 are sequentially After being latched or stored in all the memory cells 446 one by one, the control unit 337 can open all the switches 336 and close all the switches 449 during the second clock period, thereby latching or storing in the memory cells 446 The data can be passed in parallel through the plurality of channels of 349 to the plurality of memory cells 490 and/or memory cells 362 and/or the commercial standard FPGAIC chip 200 as shown in Figs. The plural memory cells 362 of the memory matrix block 423 of the DPIIC chip 410 in FIG. 9 are shown.

As shown in FIG. 13B, the above steps can be repeated multiple times so that the data (eg, generated values or programming codes) input from the buffer/drive unit 340 is downloaded to a commercial standard FPGAIC chip as shown in FIGS. 8A to 8J. 200 of memory cell 490 and/or memory cell 362 and or memory cell 362 of memory matrix block 423 of DPIIC chip 410 in FIG. , and increase (enlarge) the data bit-width to the plurality of memory cells 490 and/or memory cells 362 and 200 of the commercial standard FPGAIC chip 200 as shown in FIGS. (or) the plural memory cells 362 of the memory matrix block 423 of the DPIIC chip 410 in FIG. 9 .

Alternatively, under a peripheral-component-interconnect (PCI) standard, as shown in Figures 13A and 13B, a plurality of buffer/driver units 340 may be provided in parallel to buffer data (eg, generated values or programming codes) ), and transmits (transmits) data from its own input and drive or amplification in parallel to the plurality of memory cells 490 and/or memory cells 362 of a commercial standard FPGAIC chip 200 as shown in Figures 8A-8J And or as in the plurality of memory cells 362 of the memory matrix block 423 of the DPIIC chip 410 in FIG. 9, each buffer/drive unit 340 can perform the same function as described above.

I. The first arrangement (layout) for the control unit, buffer/drive unit and multiple memory units

As shown in FIGS. 13A to 13B , in the case where the bit width between the commercial standard FPGAIC chip 200 and its external circuits is 32 bits as shown in FIGS. 8A to 8J , the number of buffer/driver units 340 is 32 can be paralleled in a commercial standard FPGAIC chip 200 from its 32 corresponding inputs into buffer data (such as generated values or programming codes) and coupled to external circuits (ie, with parallel 32 bits of width (bitwidth) and drive or zoom data to a plurality of memory cells 490 and/or memory cells 362 of a commercial standard FPGAIC chip 200 as shown in Figures 8A-8J, in each clock cycle, The control unit 337 provided in the commercial standard FPGAIC chip 200 can turn on the switch 449 of each 32 buffer/driver units 340 and turn off each 32 buffer/driver units 340 in the first clock period in sequence and one by one other switches 449, so data from each of the 32 buffer/drive units 340 (eg, generated values or programming codes) can pass through the lock sequentially and one by one through the channels of the switches 449 of each of the 32 buffer/drive units 340 Stored or stored in the memory unit 446 of each of the 32 buffer/drive units 340, in each clock cycle, the data from its 32 corresponding parallel inputs are sequentially and one by one latched or stored in all 32 After the memory unit 446 of the buffer/driver unit 340, the control unit 337 can turn on the switches 336 of all 32 buffer/driver units 340 and turn off the switches 449 of all 32 buffer/driver units 340 during the second clock period, thus Data latched or stored in the memory cells 446 of all 32 buffer/drive units 340 can be passed in parallel and individually through the channels of the switches 336 of the 32 buffer/drive units 340 to Figures 8A to 8J A plurality of memory cells 490 and/or memory cells 362 of a commercial standard FPGA IC chip 200 .

For the first type of commercial standard FPGAIC chip 200, each of the plurality of memory cells 490 for look-up tables (LUTs) 210 may be on-chip volatile memory cells, as shown in FIG. 1A or 1B The memory cell 398 in the figure is an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell, MRMIC chip, RRMIC chip, phase change random access memory IC chip, or FRMIC chip, and uses The plurality of memory cells 362 in the plurality of crosspoint switches 379 may be on-chip volatile memory cells, such as memory cells 398 in Figure 1A or 1B, or on-chip non-volatile memory cells, such as floating gates Very Non-Volatile Memory Cell, MRAMIC Chip, Phase Change Random Access Memory IC Chip, RRAMIC Chip or FRMIC Chip.

For each single-level package logic driver 300 as shown in FIGS. 11A-11N, each commercial standard FPGAIC chip 200 may have a control unit 337, a buffer/drive unit 340, and a plurality of memory cells for use as described above 490 and the first arrangement (layout) of the memory cells 362.

II. Second arrangement (layout) for control units, buffer/drive units and multiple memory units

As shown in FIG. 13A to FIG. 13B, as shown in FIG. 13A to FIG. 13B, in the case where the bit width between the DPIIC chip 410 and its external circuit is 32 bits in FIG. 9, the buffer/drive unit The number of 340 is 32 which can be set in parallel in the DPIIC chip 410 from its 32 corresponding inputs to buffer data (such as programming code), and coupled to external circuits (ie, having a parallel 32-bit bit width ( bitwidth)) and drive or amplify the data to a plurality of memory cells 490 and/or memory cells 362 of the DPIIC chip 410 as shown in Figures 8A to 8J, disposed on the DPIIC chip 410 in each clock cycle The control unit 337 in can turn on the switches 449 of each of the 32 buffer/drive units 340 in sequence and one by one and close the other switches 449 of each of the 32 buffer/drive units 340 in the first clock period, thus from Data (eg, generated values or programming codes) of each 32 buffer/drive units 340 can be latched or stored in each In the memory unit 446 of the buffer/driver unit 340, in each clock cycle, the data from its 32 corresponding parallel inputs are sequentially and one by one latched or stored in the memory of all 32 buffer/driver units 340 After unit 446, control unit 337 may open switches 336 of all 32 buffer/drive units 340 and close switches 449 of all 32 buffer/drive units 340 during the second clock period, thus latching or storing in all 32 The data of the memory cells 446 of the buffer/drive unit 340 can be passed in parallel and individually through the channels of the switches 336 of the 32 buffer/drive units 340 to the pluralities of the memory matrix blocks 423 of the DPIIC chip 410 in FIG. 9 memory unit 362 .

For the first type of DPIIC chip 410, each of the plurality of memory cells 362 for the plurality of crosspoint switches 379 may be an on-chip volatile memory cell for use as in Figure 1A or Figure 1B The memory cell 398 is an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell, an MRMIC chip, an RRMIC chip, a phase change random access memory IC chip, or a FRMIC chip.

For each single-level package logic driver 300 as shown in FIGS. 11A-11N, each DPIIC chip 410 may have a first for the control unit 337, the buffer/drive unit 340, and the plurality of memory units 362 as described above. Two arrangement (layout) ways.

III. Third Arrangement (Layout) for Control Units, Buffer/Drive Units and Multiple Memory Units

As shown in FIGS. 13A to 13B , the control unit 337 , the buffer/drive unit 340 , the plurality of memory units 490 and the memory unit 362 of the single-level package logic driver 300 as shown in FIGS. 11A to 11N The three arrangements (layouts) and the first of the control units 337 , buffer/drive units 340 , and the plurality of memory units 490 and 362 of each of the plurality of commercial standard FPGAIC chips 200 for the single-level package logic driver 300 The first arrangement (layout) is similar, but the difference between the two is that the control unit 337 in the third arrangement is arranged on the dedicated control chip 260, the dedicated control chip and the dedicated I/O chip as shown in FIGS. 11A to 11N. 266, the DCIAC die 267 or the DCDI/OIAC die 268, instead of being provided in any of the plurality of commercial standard FPGAIC die 200 of the single-level package logic driver 300, the control unit 337 is provided on the dedicated control die 260, the dedicated control die and the dedicated control die 266. In I/O die 266 , DCIAC die 267 or DCDI/OIAC die 268 may be (1) a switch via a word line 451 through a control command to buffer/drive unit 340 in a plurality of commercial standard FPGAIC die 200 449, wherein word line 451 is provided by a fixed interconnect line 364 or on-chip interconnect line 371; or (2) via a word line 454 through a control command to a plurality of commercial standard FPGAIC chips 200 All switches 336 of the buffer/drive unit 340, where the word line 454 is provided by another fixed interconnect 364 or an intra-chip interconnect 371.

IV. Fourth Arrangement (Layout) Method for Control Unit, Buffer/Drive Unit and Multiple Memory Units

As shown in FIGS. 13A-13B, a fourth arrangement (layout) of the control unit 337, the buffer/drive unit 340, and the plurality of memory units 362 for the single-level package logic driver 300 as shown in FIGS. 11A-11N ) is similar to the second arrangement (layout) of the control units 337, buffer/drive units 340, and memory units 362 of each of the DPIIC chips 410 for the single-level package logic driver 300, but the difference between the two The difference is that the control unit 337 in the fourth arrangement is provided in the dedicated control chip 260, the dedicated control chip and the dedicated I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 as shown in Figures 11A to 11N, Rather than being located in any of the plurality of DPIIC dies 410 of the single level package logic driver 300, the control unit 337 is located in the dedicated control die 260, the dedicated control die and the dedicated I/O die 266, the DCIAC die 267 or the DCDI/OIAC die 268 Can be (1) a control command to a switch 449 of the buffer/drive unit 340 in a plurality of DPIIC chips 410 via a word line 451, which is interconnected by a fixed interconnect 364 or intra-chip provided by connection line 371; or (2) by a control command to all switches 336 of buffer/drive units 340 in a plurality of DPIIC chips 410 via a word line 454, wherein word line 454 is interconnected by another fixed Wire 364 or intra-wafer interconnect wire 371 is provided.

V. Fifth arrangement (layout) of control units, buffer/drive units and multiple memory units for logical drivers

As shown in FIGS. 13A to 13B, for the control unit 337 and the buffer/drive unit 340 of the single-level package logic driver 300 as shown in FIGS. 11B, 11E, 11F, 11H, and 11J and the fifth arrangement (layout) of the plurality of memory cells 490 and 362 and the control unit 337, buffer/driver unit 340 and the control units 337, buffer/driver units 340 and The first arrangement (layout) of the plurality of memory cells 490 and the memory cells 362 is similar, but the difference between the two is that both the control unit 337 and the buffer/drive unit 340 in the fifth arrangement are arranged in such as 11B, 11E, 11F, 11H, and 11J in the dedicated control die and dedicated I/O die 266 or the DCDI/OIAC die 268, rather than on the single-level package logic driver 300 In any of the plurality of commercial standard FPGAIC chips 200, the control unit 337 provided in the dedicated control chip 260, the dedicated control chip and the dedicated I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 can (1) pass a word Word line 451 passes a control command to a switch 449 of buffer/drive unit 340 in a plurality of DPIIC chips 410, wherein word line 451 is provided by a fixed interconnect 364 or an intra-chip interconnect 371; or ( 2) Pass a control command to all switches 336 of buffer/drive units 340 in a plurality of DPIIC chips 410 via a word line 454 connected by another fixed interconnect 364 or an intra-chip interconnect 371 provided.

VI. Sixth Arrangement (Layout) of Control Unit, Buffer/Drive Unit and Multiple Memory Units for Logical Drivers

As shown in FIGS. 13A to 13B, for the control unit 337 and the buffer/drive unit 340 of the single-level package logic driver 300 as shown in FIGS. 11B, 11E, 11F, 11H, and 11J and the sixth arrangement (layout) of the plurality of memory cells 362 and the second for the control unit 337 , the buffer/drive unit 340 and the plurality of memory cells 362 of each of the plurality of DPIIC chips 410 of the single-level package logic driver 300 The arrangement (layout) of the first arrangement is similar, but the difference between the two is that both the control unit 337 and the buffer/drive unit 340 in the fifth arrangement are arranged in the configuration shown in Fig. 11B, Fig. 11E, Fig. 11F, The dedicated control die and dedicated I/O die 266 or the DCDI/OIAC die 268 in FIGS. 11H and 11J are provided on the dedicated control die instead of any of the plurality of DPIIC die 410 of the single-package logic driver 300 260. The control unit 337 in the dedicated control chip and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268 may (1) pass a control command via a word line 451 to buffering in a plurality of DPIIC chips 410 / a switch 449 of the drive unit 340, wherein the word line 451 is provided by a fixed interconnect 364 or an on-chip interconnect 371; or (2) via a word line 454 through a control command to a plurality of All switches 336 of the buffer/drive unit 340 in the DPIIC die 410, where the word line 454 is provided by another fixed interconnect 364 or an intra-die interconnect 371.

VII. Seventh arrangement (layout) of control unit, buffer/drive unit and plural memory units for logical drives

As shown in FIGS. 13A to 13B , the control unit 337 , the buffer/drive unit 340 , the plurality of memory units 490 and the memory unit 362 of the single-level package logic driver 300 as shown in FIGS. 11A to 11N Seven arrangements (layouts) and the first of the control unit 337 , the buffer/drive unit 340 , and the plurality of memory cells 490 and 362 of each of the plurality of commercial standard FPGAIC chips 200 for the single-level package logic driver 300 The first arrangement (layout) is similar, but the difference between the two is that the control unit 337 in the seventh arrangement is arranged on the dedicated control chip 260, the dedicated control chip and the dedicated I/O chip as shown in FIGS. 11A to 11N. 266, DCIAC die 267 or DCDI/OIAC die 268, instead of being provided in any of the plurality of commercial standard FPGAIC die 200 of single level package logic driver 300, in addition, buffer/driver unit 340 is provided in a seventh arrangement Control unit 337 is provided on a dedicated control die within a plurality of dedicated I/O die 265 as shown in Figures 11A-11N, rather than on any of the commercial standard FPGAIC die 200 of single level package logic driver 300 260. Dedicated control chip and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268 may be (1) buffered in a plurality of dedicated I/O chips 265 via a word line 451 through a control command / a switch 449 of the drive unit 340, wherein the word line 451 is provided by a fixed interconnect 364 or an on-chip interconnect 371; or (2) via a word line 454 through a control command to a plurality of All switches 336 of buffer/drive unit 340 in dedicated I/O die 265 where word line 454 is provided by another fixed interconnect 364 or intra-die interconnect 371. Data may be serially transferred to buffer/drive unit 340 in a plurality of dedicated I/O chips 265, latched or stored in memory unit 446 of buffer/drive unit 340, in buffer/drive unit 446 of a plurality of dedicated I/O chips 265 Drive unit 340 can pass data from its own memory cell 446 in parallel to a plurality of memory cells 490 and memory cells 362 of a plurality of commercial standard FPGAIC chips 200 in sequence, and sequentially through a plurality of dedicated I/O chips 265 of a set of parallel complex small I/O circuits 203, a set of parallel fixed cross-connect lines 364 of intra-chip interconnect lines 371, and a set of parallel complex small I/O circuits 203 of a complex commercial standard FPGAIC chip 200.

VIII. Eighth arrangement (layout) of control unit, buffer/drive unit and plural memory units for logical drives

As shown in FIGS. 13A to 13B, an eighth arrangement (layout) of the control unit 337, the buffer/drive unit 340, and the plurality of memory units 362 for the single-level package logic driver 300 as shown in FIGS. 11A to 11N ) is similar to the first arrangement (layout) of the control unit 337, the buffer/drive unit 340, and the plurality of memory units 362 for each of the DPIIC chips 410 of the single-level package logic driver 300, but the difference between the two The difference is that the control unit 337 in the eighth arrangement is provided in the dedicated control chip 260, the dedicated control chip and the dedicated I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268 as shown in Figures 11A to 11N, Instead of being located in any of the plural DPIIC die 410 of the single-level package logic driver 300, in addition, the buffer/driver unit 340 is located in a plural dedicated I/O as shown in FIGS. 11A-11N in the eighth arrangement. Within die 265, rather than being located in any of the plurality of DPIIC die 410 of single-level package logic driver 300, control unit 337 is located on dedicated control die 260, dedicated control die and dedicated I/O die 266, DCIAC die 267 or DCDI/ The OIAC chip 268 may (1) pass a control command to a switch 449 of the buffer/drive unit 340 in a plurality of dedicated I/O chips 265 via a word line 451, wherein the word line 451 is communicated by a fixed or (2) via a word line 454 through a control command to all switches 336 of the buffer/drive unit 340 in a plurality of dedicated I/O chips 265, where the word Metaline 454 is provided by another fixed interconnect 364 or on-chip interconnect 371, and data can be transmitted in series to buffer/drive units 340 in a plurality of dedicated I/O chips 265, latched or stored in buffer/drive units 340. Within the memory unit 446 of the drive unit 340, the buffer/drive unit 340 of a plurality of dedicated I/O chips 265 can pass data from its own memory unit 446 in parallel in sequence to a set of plural memories of a plurality of DPIIC chips 410 The body unit 490 and the memory unit 362 are fixed in sequence through a set of parallel complex small I/O circuits 203 of a complex dedicated I/O chip 265 and a set of parallel intra-chip interconnection lines 371 of the intra-chip interconnection lines 371 Interconnect lines 364 and a set of parallel complex miniature I/O circuits 203 of a complex DPIIC chip 410 .

First interconnect structure for wafer (FISC) and method of making the same

Each standard commercial FPGAIC die 200, DPIIC die 410, dedicated I/O die 265, dedicated control die 260, dedicated control die and dedicated I/O die 266, IAC die 402, DCIAC die 267, DCDI/OIAC die 268, DRAM Chip 321, computing and/or computing IC chip 269 may be formed through the following steps:

FIG. 14A is a cross-sectional view of a semiconductor wafer according to an embodiment of the present invention. As shown in FIG. 14A, a semiconductor substrate or a semiconductor blank wafer 2 may be a silicon substrate or a silicon wafer, a gallium arsenide (GaAs) substrate, an arsenic Gallium oxide wafers, silicon germanium (SiGe) substrates, silicon germanium wafers, silicon-on-insulator (SOI) substrates, the substrate wafer size is, for example, 8 inches, 12 inches or 18 inches in diameter.

As shown in FIG. 14A, a plurality of semiconductor elements 4 are formed on the semiconductor element region of the semiconductor substrate 2. The semiconductor elements 4 may include a memory unit, a logic operation circuit, a passive element (for example, a resistor, a capacitor, a An inductor or a filter or an active element, wherein the active element is, for example, a p-channel metal oxide semiconductor (MOS) element, an n-channel MOS element, a CMOS (complementary metal oxide semiconductor) element, a BJT (bipolar junction transistor) device, BiCMOS (Bipolar CMOS) device, Field Effect Transistor (FINFET) device as shown in Figures 31A and 31B or a gate full ring transistor as shown in Figures 32A and 32B ( Gate-All-AroundField-Effect-Transistor (GAAFET)), FINFET on Silicon-On-Insulator (FINFETSOI), Fully Depleted Silicon-On-Insulator (FDSOI) MOSFET, Partially Depleted Silicon-On-Insulator (FDSOI) MOSFET Partially Depleted Silicon-On-Insulator (PDSOI) MOSFETs or conventional MOSFETs, while semiconductor elements 4 are used for standard commercial FPGAIC chips 200, DPIIC chips 410, dedicated I/O chips 265, dedicated control chips 260, Dedicated control chip and dedicated I/O chip 266 , IAC chip 402 , DCIAC chip 267 , DCDI/OIAC chip 268 , DRAM chip 321 , complex transistors in arithmetic and/or computing IC chip 269 .

Regarding the single-level package logic driver 300, as shown in FIGS. 11A to 11N, for each standard commercial FPGAIC chip 200, the semiconductor elements 4 can constitute the multiplexer 211 of the complex logic block (LB) 201 for complex logic The complex memory cells 490 of the lookup table 210 in the block (LB) 201, the complex memory cells 362 for the complex pass/fail switches 258, the complex crosspoint switches 379, and the complex small I/O circuits 203 are as described above in Section 1. As shown in Figures 8A to 8J; for each DPIIC chip 410, the semiconductor elements 4 may constitute a plurality of pass/fail switches 258, a plurality of cross-point switches 379, and a plurality of memory cells 362 of a plurality of small I/O circuits 203, such as As shown in FIG. 9 above, for each dedicated I/O chip 265, dedicated control chip and dedicated I/O chip 266 or DCDI/OIAC chip 268, the semiconductor elements 4 can form a plurality of small I/O circuits 341 and a plurality of small I/O circuits 341. The /O circuit 203 is shown in Fig. 10 above; the semiconductor element 4 can form a control unit 337 as shown in Fig. 13A and Fig. 13B, which are arranged on each standard commercial FPGAIC chip 200, each DPIIC chip 410, and a dedicated control unit. In the chip 260, the dedicated control chip and the dedicated I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268; the semiconductor element 4 can form a buffer/drive unit 340 as shown in the above-mentioned Fig. 13A and Fig. 13B, and arranged in the Each of the plurality of commercial standard FPGAIC chips 200 , each of the plurality of DPIIC chips 410 , each of the plurality of dedicated I/O chips 265 , dedicated control chips and dedicated I/O chips 266 or DCDI/OIAC chips 268 .

As shown in FIG. 14A, the first interconnect structure 20 formed on the semiconductor substrate 2 is connected to the semiconductor element 4, and the first interconnect structure 20 on or in the chip (FISC) is formed on the semiconductor substrate 2 through a wafer process. FISC 20 may include 4 to 15 layers or 6 to 12 layers of patterned multiple interconnection wire metal layers 6 (only 3 layers are shown in this figure), wherein the patterned multiple interconnected interconnection wire metal layer 6 has a plurality of metal pads, Lines and connections 8 and metal plugs 10 , metal pads, lines and connections 8 and metal plugs 10 of FISC 20 may be used for multiple programming of multiple intra-chip interconnect lines 502 in each commercial standard FPGAIC chip 200 and fixed interconnection lines 361 and 364, as shown in FIG. 8A, the first interconnection line structure 20 of the FISC 20 may include a plurality of insulating dielectric layers 12 and a plurality of interconnection line metal layers 6 in every two adjacent layers. Between the insulating dielectric layers 12 , each interconnecting metal layer 6 of the FISC 20 may include a plurality of metal pads, lines and connecting lines 8 on its top, and a metal plug 10 on its bottom, and the plurality of insulating dielectric layers 12 of the FISC 20 One of them may be between two adjacent plurality of metal pads, lines and connection lines 8 in the plurality of interconnecting wire metal layers 6 with metal plugs 10 on top of the FISC 20 in a plurality of insulating dielectric layers 12, each In the metal layer 6 of the plurality of interconnecting lines of the FISC 20, the plurality of metal pads, lines and connecting lines 8 have a thickness t1 of less than 3 μm (for example, between 3 nm and 500 nm, between 10 nm and 1000 nm, or between 10 nm and 10 nm). between 3000nm, or a thickness greater than or equal to 5nm, 10nm, 30nm, 50nm, 100nm, 200nm, 300nm, 500nm or 1000nm), or have a width such as between 3nm and 500nm, between 10nm and 1000nm, Or narrower than 5nm, 10nm, 20nm, 30nm, 70nm, 100nm, 300nm, 500nm or 100nm, for example, the metal plug 10 and the plurality of metal pads, lines and connecting lines 8 in the FISC 20 are mainly made of copper metal, through the following One of the damascene processes, such as a single damascene process or a dual damascene process, may include a copper layer for each of the plurality of metal pads, lines and connection lines 8 in the plurality of interconnection wire metal layers 6 of the FISC 20. The copper layer Having a thickness less than 3 μm (eg, between 0.2 μm and 2 μm), each of the plurality of insulating dielectric layers 12 in the FISC 20 may have a thickness between, for example, between 3 nm and 500 nm, between 10 nm and 1000 nm, Or thickness greater than 5 nm, 10 nm, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 500 nm or 1000 nm.

I. FISC single damascene process

In the following, a single damascene process of the FISC 20 is shown in Fig. 14B to Fig. 14H. As shown in Fig. 14B, a first insulating dielectric layer 12 and a plurality of metal plugs 10 or a plurality of metal pads, lines and connecting lines are provided. 8 (only one is shown in the figure) in the first insulating dielectric layer 12, and the upper surfaces of the plurality of metal plugs 10 or the plurality of metal pads, lines and connecting lines 8 are exposed, and the uppermost surface of the first insulating dielectric layer 12 is exposed. The top layer can be, for example, a low-k dielectric layer, such as a silicon oxycarbide (SiOC) layer.

As shown in FIG. 14C, a second insulating dielectric layer 12 (the upper layer) is deposited on or over the first insulating dielectric layer 12 (the lower layer) using a chemical vapor deposition (CVD) method, And on the exposed surfaces of the plurality of metal plugs 10 and the plurality of metal pads, lines and connecting lines 8 in the first insulating dielectric layer 12, the second insulating dielectric layer 12 (the upper layer) may be deposited via (a) a A bottom distinguishing etch stop layer 12a, such as a silicon-on-carbon nitride (SiON) layer, is formed on the topmost layer of the first insulating dielectric layer 12 (the lower layer) and on the first insulating dielectric layer 12 (the lower layer) on the exposed surfaces of the plurality of metal plugs 10 and the plurality of metal pads, lines, and connecting lines 8 in, and (b) then depositing a low-k dielectric layer 12b on the bottom distinguishing etch stop layer 12a, such as a SiOC Layer, the low-k dielectric layer 12b may have a low-k material, and its low-k is smaller than that of silicon dioxide (SiO ₂ ). The SiCN layer, the SiOC layer, the SiOC layer, and the SiO ₂ layer are CVD The materials used for the first and second plural insulating dielectric layers 12 of the FISC 20 include inorganic materials or compounds including silicon, nitrogen, carbon and/or oxygen.

Next, as shown in FIG. 14D, a photoresist layer 15 is coated on the second insulating dielectric layer 12 (the upper layer), and then the photoresist layer 15 is exposed and developed to form a plurality of trenches or a plurality of openings 15a ( Only one is shown in the figure) in the photoresist layer 15, and then as shown in FIG. 14E, an etching process is performed to form a plurality of trenches or a plurality of openings 12d (only one is shown in the figure) in the second insulating dielectric In layer 12 (the layer above) and under the trenches or openings 15a in photoresist layer 15, then, as shown in Figure 14F, photoresist layer 15 may be removed.

Next, as shown in FIG. 14G, an adhesive layer 18 may be deposited on the upper surface of the second insulating dielectric layer 12 (the layer above), the sidewalls of the trenches or the openings 12D in the second insulating dielectric layer 12 Above and within the first insulating dielectric layer 12 (the layer below) the plurality of metal plugs 10 or the upper surface of the plurality of metal pads, lines and connecting lines 8, for example by sputtering or CVD-a Ti layer or TiN layer 18 (which The thickness is, for example, between 1 nm and 50 nm), and then, the seed layer 22 for electroplating can be, for example, sputtered or CVD-a seed layer 22 for electroplating (the thickness of which is between 3 nm and 200 nm, for example) on the adhesion layer 18. Next, a copper metal layer 24 (the thickness of which is between 10 nm and 3000 nm, between 10 nm and 1000 nm, or between 10 nm and 500 nm) can be electroplated on the seed layer 22 for electroplating.

Next, as shown in FIG. 14H, a CMP process is used to remove the adhesion layer 18, the plating seed layer 22, and the second insulating dielectric layer 12 (the upper layer) and located in the trenches or openings 12D outside the copper metal layer 24 until the upper surface of the second insulating dielectric layer 12 (the layer above) is exposed, remaining or remaining in the second insulating dielectric layer 12 (the layer above) the plurality of trenches or the plurality of trenches The metal in the opening 12D is used as a metal plug 10 or a plurality of metal pads, lines and connecting lines 8 for each interconnecting wire metal layer 6 in the FISC 20 .

In a single damascene process, the copper electroplating process steps and the CMP process steps are used for the plurality of metal pads, lines and connection lines 8 in the lower layers of the plurality of interconnection line metal layers 6, and then sequentially performed once in the insulating dielectric The metal plugs 10 of the lower plurality of interconnect metal layers 6 in layer 12 are on the lower plurality of interconnect metal layers 6. In other words, in a single damascene copper process, the copper electroplating process steps and the CMP process steps is performed twice to form the metal pads, lines and connection lines 8 of the lower layer of the interconnect metal layer 6 and the metal of the higher interconnect metal layer 6 within the insulating dielectric layer 12 The plug 10 is on the lower multiple interconnect metal layer 6 .

II. The dual damascene process of FISC

Alternatively, a dual damascene process can be used to fabricate the metal plugs 10 and the plurality of metal pads, lines and connecting lines 8 of the FISC 20, as shown in FIGS. 14I-14Q, and as shown in FIG. 14I, to provide a first insulating dielectric The electrical layer 12 and a plurality of metal pads, wires and connecting wires 8 (only one is shown in the figure), wherein the plurality of metal pads, wires and connecting wires 8 are located in the first insulating dielectric layer 12 and the upper surface is exposed, The topmost layer of the first insulating dielectric layer 12 can be, for example, a SiCN layer or a SiN layer, and then the dielectric stack including a second and a third plurality of insulating dielectric layers 12 is deposited on the topmost layer of the first insulating dielectric layer 12 and on the topmost layer. The exposed upper surface of the plurality of metal pads, lines and connecting lines 8 in the first insulating dielectric layer 12. The dielectric stack from bottom to top includes: (a) a bottom low-k dielectric layer 12e on the first insulating dielectric layer 12e. On the dielectric layer 12 (the lower layer), for example, a SiOC layer (used as an inter-metal dielectric layer to form the metal plug 10); (b) an intermediate etch stop layer 12f at the bottom of the low-k dielectric On the electrical layer 12e, for example, a SiCN layer or a SiN layer; (c) a top low-dielectric SiOC layer 12g (used as an insulation between the plurality of metal pads, wires and connecting wires 8 of the same interconnect wire metal layer 6); (d) a top-level differential etching stop layer 12h is formed on the top low-dielectric SiOC layer 12g, and the top-level differential etching stop layer 12h is, for example, a SiCN layer or a SiN layer, and all of The SiCN layer, SiN layer or SiOC layer can be deposited by CVD. The bottom low-k dielectric layer 12e and the middle distinguishing etch stop layer 12f can form the second insulating dielectric layer 12 (the middle layer); the top low-k SiOC layer 12g and the top distinguishing etch stop layer 12h can form a third insulating dielectric layer 12 Insulating dielectric layer 12 (the top layer).

Next, as shown in FIG. 14J, a first photoresist layer 15 is coated on the top portion of the third insulating dielectric layer 12 (the top layer) on the etch stop layer 12h, and then the first photoresist layer 15 is exposed and Development to form a plurality of trenches or a plurality of openings 15A (only one is shown in the figure) in the first photoresist layer 15 to expose the top portion of the third insulating dielectric layer 12 (the top layer) to distinguish the etch stop layer 12h, Next, as shown in FIG. 14K, an etching process is performed to form trenches or top openings 12i (only one is shown) in the third insulating dielectric layer 12 (the top layer) and in the first photoresist layer 15 Under the inner plurality of trenches or the plurality of openings 15A, and the etch stop layer 12f stops in the middle of the second insulating dielectric layer 12 (the middle layer), the trenches or top openings 12i are used for the subsequent formation of the interconnecting wire metal layer 6 The dual damascene copper process of the plurality of metal pads, lines and connecting lines 8, and then the first photoresist layer 15 can be removed following FIG. 14L.

Next, as shown in FIG. 14M, the second photoresist layer 17 is coated on the top layer of the third insulating dielectric layer 12 (the top layer) to distinguish between the etching stop layer 12h and the second insulating dielectric layer 12 (the middle layer). The etch stop layer 12f is separated in the middle, and then the second photoresist layer 17 is exposed and developed to form trenches or openings 117a (only one is shown in the figure) in the second photoresist layer 17 to expose the second insulating dielectric layer 12 ( Then, as shown in FIG. 14N, an etching process is performed to form holes or bottom openings 12j (only one is shown in the figure) in the second insulating dielectric layer 12 (the middle layer). layer) and below the trenches or openings 117a in the second photoresist layer 17, and a plurality of metal pads, lines and connecting lines 8 (only one is shown in the figure) stopped in the first insulating dielectric layer 12, The hole or bottom opening 12j can be used for the subsequent dual damascene copper process to form the metal plug 10 in the second insulating dielectric layer 12, that is, the intermetal dielectric layer, and then, as shown in FIG. 14O, the second photoresist layer 17 can be removed, and the second and third plurality of insulating dielectric layers 12 (intermediate and upper layers) can form a dielectric stack, located on the dielectric stack (ie, the third insulating dielectric layer 12 (the top layer). )) trenches or top openings 12i in the top may overlap with openings and holes 12j in the bottom of the dielectric stack (ie, the second insulating dielectric layer 12 (the middle layer)), and the trenches or tops The opening 12i has a larger size than the plurality of openings and holes 12j. In other words, from the above view, the plurality of openings located at the bottom of the dielectric stack (ie, the second insulating dielectric layer 12 (the middle layer)) and Holes 12j are surrounded or trapped inside by trenches or top openings 12i in the top of the dielectric stack (ie, third insulating dielectric layer 12 (the top layer)).

Next, as shown in FIG. 14P, the adhesion layer 18 is deposited by sputtering, CVD, a Ti layer or a TiN layer (the thickness of which is between 1 nm and 50 nm, for example), on the second and third plural insulating dielectric layers 12 ( The upper surface of the middle and upper layers), the sidewalls of the trenches or top openings 12i in the third insulating dielectric layer 12 (the upper layer), the holes in the second insulating dielectric layer 12 (the middle layer), or The sidewalls of the bottom opening 12J and the upper surfaces of the plurality of metal pads, lines and connecting lines 8 in the first insulating dielectric layer 12 (the bottom layer). Next, the electroplating seed layer 22 may be deposited on the adhesion layer 18 via, for example, sputtering, CVD, and the electroplating seed layer 22 (with a thickness of, for example, between 3 nm and 200 nm) is deposited on the adhesion layer 18, followed by a copper metal layer 24 (with a thickness of, for example, a dielectric between 20 nm and 6000, between 10 and 3000, between 10 and 1000) can be electroplated on the seed layer 22 for electroplating.

Next, as shown in FIG. 14Q, a CMP process is used to remove the adhesion layer 18, the plating seed layer 22, and the holes or bottom openings 12J and trenches or top openings in the second and third separate etch stop layers 12h The copper metal layer 24 outside 12i until the upper surface of the third insulating dielectric layer 12 (the layer above) is exposed, remaining or remaining in the trench or top opening 12i and in the third insulating dielectric layer 12 (the layer above) layer) of metal can be used as a plurality of metal pads, wires and connecting wires 8 of the plurality of interconnecting wire metal layers 6 in the FISC 20, remaining or remaining in the holes or bottom openings 12J and in the second insulating dielectric layer 12 (the middle layer). ) is used as the metal plug 10 of the metal layer 6 of the multiple interconnecting wires in the FISC 20 to couple the metal pads, wires and metals below the metal plug 10 and above the metal plug 10 .

In the dual damascene process, the copper electroplating process step and the CMP process step are performed once to form a plurality of metal pads, lines and connecting lines 8 and metal plugs 10 in the two plurality of insulating dielectric layers 12 .

Therefore, the process of forming the plurality of metal pads, lines and connecting lines 8 and metal plugs 10 is completed by a single damascene copper process, as shown in FIGS. 14B to 14H, or can be completed by a dual damascene copper process, as shown in FIG. 14I As shown in FIG. 14Q, both processes can be repeated several times to form a plurality of interconnecting wire metal layers 6 in the FISC 20. The FISC 20 can include 4 to 15 layers or 6 to 12 layers of a plurality of interconnecting wire metal layers 6. The topmost layer of the metal layers 6 of the interconnecting lines in the FISC may have metal pads 16, such as copper pads, which are formed by the single or dual damascene process, or by the sputtering process. pad.

III. Passivationlayer of the chip

As shown in FIG. 14A, the protective layer 14 is formed on the first interconnect structure 20 of the wafer (FISC) and on the plurality of insulating dielectric layers 12. The protective layer 14 can protect the semiconductor element 4 and the plurality of interconnect metal The layer 6 is not damaged by external ion pollution and moisture pollution in the external environment, such as sodium free particles. In other words, the protective layer 14 can prevent free particles (such as sodium ions), transition metals (such as gold, silver and copper) And prevent the impurity from penetrating to the semiconductor element 4 and the metal layer 6 of the plurality of interconnecting lines, for example, preventing the penetration to the transistor, the polysilicon resistance element and the polysilicon capacitor element.

As shown in FIG. 14A, the protective layer 14 is usually composed of one or more free particle catcher layers. For example, a protective layer 14 composed of a SiN layer, a SiON layer and/or a SiCN layer is formed by deposition through a CVD process. The protective layer 14 It has a thickness t3, for example, greater than 0.3 μm, or between 0.3 μm and 1.5 μm. In the best case, the protective layer 14 has a silicon nitride (SiN) layer with a thickness greater than 0.3 μm, and a single layer or a plurality of layers The total thickness of the composed free particle catcher layer (eg, a combination of SiN layer, SiON layer and/or SiCN layer) may be thicker than or equal to 100 nm, 150 nm, 200 nm, 300 nm, 450 nm or 500 nm.

As shown in FIG. 14A, an opening 14a is formed in the protective layer 14 to expose the topmost surface of the metal layers 6 of the plurality of interconnection lines in the FISC 20. The metal pads 16 can be used for signal transmission or connection to power or ground terminals. The metal pads 16 has a thickness t4 between 0.4 μm and 3 μm or between 0.2 μm and 2 μm. For example, the metal pads 16 can be made of sputtered aluminum layer or sputtered aluminum-copper alloy layer (the thickness of which is between 0.2 μm and 0.2 μm). to 2 μm), alternatively, the metal pads 16 may include an electroplated copper layer 24 formed by a single damascene process as shown in FIG. 14H or a dual damascene process as shown in FIG. 14Q.

As shown in FIG. 14A , the opening 14a has a lateral dimension between 0.5 μm and 20 μm or between 20 μm and 200 μm when viewed from the top. The shape of the opening 14a can be a circle when viewed from the top. The diameter of the circular opening 14a is between 0.5 μm and 200 μm or between 20 μm and 200 μm, or, from the top view, the shape of the opening 14a is a square, and the width of the square opening 14a is Between 0.5 μm and 200 μm or between 20 μm and 200 μm, or, from the top view, the shape of the opening 14a is a polygon, and the width of the polygon is between 0.5 μm and 200 μm or between 20 μm and 20 μm. 200 μm, or, from the top view, the shape of the opening 14a is a rectangle, and the rectangular opening 14a has a short side width between 0.5 μm and 200 μm or between 20 μm and 200 μm. Some of the semiconductor elements 4 under the metal pads 16 are exposed by the openings 14a, alternatively, no active elements are under the metal pads 16 exposed by the openings 14a.

Microbumps of the first type

15A to 15H are cross-sectional views of the process of forming micro-bumps or micro-metal pillars on a wafer according to an embodiment of the present invention. For circuits connected to the outside of the chip, a plurality of micro-bumps can be formed on metal pads 16 , wherein the metal pads 16 are exposed metal surfaces in the plurality of openings 14 a of the protective layer 14 .

As shown in Figure 15A, which is a simplified view of Figure 14A, as shown in Figure 15B, having a thickness between 0.001 μm and 0.7 μm, between 0.01 μm and 0.5 μm, or between 0.03 μm and 0.35 μm An adhesive layer 26 between them is sputtered on the protective layer 14 and on the metal pads 16, such as aluminum metal pads or copper metal pads exposed by the opening 14A. The material of the adhesive layer 26 may include titanium, titanium-tungsten alloy, Titanium nitride, chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials, and the adhesion layer 26 is deposited through an atomic-layer-deposition (ALD) process, chemical vapor deposition (chemical vapor deposition (CVD)) )) process and evaporation process are formed on the protective layer 14 and the metal pads 16 at the bottom of the plurality of openings 14a of the protective layer 14, wherein the thickness of the adhesive layer 26 is between 1 nm and 50 nm.

Next, as shown in FIG. 15C, a seed layer 28 for electroplating having a thickness between 0.001 μm and 1 μm, between 0.03 μm and 3 μm, or between 0.05 μm and 0.5 μm is sputtered on the adhesion layer 26 , or the seed layer 28 for electroplating can be formed by an atomic layer (ATOMIC-LAYER-DEPOSITION (ALD)) deposition process, a chemical vapor deposition (CHEMICAL VAPORDEPOSITION (CVD)) process, an evaporation process, an electroless plating or a physical vapor deposition method, The seed layer 28 for electroplating is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the seed layer 28 for electroplating varies with the material of the metal layer electroplated on the seed layer 28 for electroplating. When a copper layer is electroplated in the electroplating When using the seed layer 28, copper metal is the preferred material for the electroplating seed layer 28. For example, the electroplating seed layer 28 is formed on or above the adhesive layer 26. For example, a copper seed layer can be chemically deposited by sputtering or CVD. on the adhesive layer 26 .

Next, as shown in FIG. 15D, a photoresist layer 30 (for example, a positive photoresist layer) with a thickness between 5 μm and 300 μm or between 20 μm and 50 μm is coated on the seed layer 28 for electroplating. The layer 30 is patterned through exposure, development and other processes to form a plurality of openings 30a to expose the seed layer 28 for electroplating above the metal pads 16. In the exposure process, a 1X stepper, a 1X contact aligner or a laser can be used The scanner performs an exposure process of the photoresist layer 30 .

For example, the photoresist layer 30 can be spin-coated with a positive photosensitive polymer layer on the electroplating seed layer 28, wherein the thickness of the electroplating seed layer 28 is between 5 μm and 100 μm, and then using 1X steps Exposure of the photopolymer layer with a 1X contact aligner, or a laser scanner, where the laser scanner can have a G-LINE with a wavelength range of 434 to 438 nm, an H-line with a wavelength range of 403 to 407 nm. At least two of LINE and I-LINE with wavelengths ranging from 363 to 367 NM, that is, G-LINE and H-LINE, G-LINE and I-LINE, H-LINE and I-LINE or G-LINE , H-LINE and I-LINE are irradiated on the baked polyimide layer, and then the exposed polyimide layer is developed to form a plurality of openings to expose a plurality of pads 16, and then the temperature is between 180° C. to between 400°C or at a temperature greater than or equal to 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C and heated or The curing time is between 20 minutes and 150 minutes, and in a nitrogen environment or an oxygen-free environment, the developed polyimide layer is cured or heated, and the cured polyimide layer has a thickness between 3 μm and 30 μm, Residual polymer material or other contaminants from pads 16 and oxygen (O ₂ ) ions or fluoride ions and oxides below 2000 PPM are then removed.

Next, as shown in FIG. 15D, each opening 30a in the photoresist layer 30 can overlap with the opening 14a in the protective layer 14 and the electroplating seed layer 28 exposed on the bottom of the opening 30a to form a micro-miniature through a subsequent process. Metal pillars or micro-bumps are on each opening 30a, and may extend opening 14a to a region or annular region of protective layer 14 surrounding opening 14a.

Next, as shown in FIG. 15E, a metal layer 32 (eg, copper metal) is electroplated on the seed layer 28 for electroplating in the opening 130a. A copper layer of 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, or 5µm to 15µm is within the opening 30a.

As shown in FIG. 15F, after the copper layer 32 is formed, most of the photoresist layer 30 is removed using an organic solvent containing ammonia, however, some residues from the photoresist layer 30 will remain in the metal layer 32 and the plating seed layer 28, then, this residue may be a metal layer 32 and the ions removed from the seed layer 28 from plating, for example, O ₂ ions or ions containing fluorine and less than 200PPM oxygen ions, then, is not The electroplating seed layer 28 and the adhesive layer 26 under the copper layer 32 are removed by the subsequent dry etching method or wet etching method. As for the wet etching method, when the adhesive layer 26 is a titanium-tungsten alloy layer, a peroxide containing peroxide can be used. Hydrogen solution etching; when the adhesive layer 26 is a titanium layer, it can be etched with a solution containing hydrogen fluoride; when the seed layer 28 for electroplating is a copper layer, it can be _{etched with a solution containing ammonia water (NH 4} OH), as for the dry etching method , when the adhesion layer 26 is a titanium layer or a titanium-tungsten alloy layer, it can be etched using chlorine-containing plasma etching technology or RIE etching technology. Usually, the dry etching method is used to etch the plating seed layer 28 and the adhesion not under the metal layer 32. Layer 26 may be etched using chemical ion etching techniques, sputter etching techniques, argon sputtering techniques, or chemical vapor etching techniques.

Therefore, the adhesive layer 26 , the electroplating seed layer 28 and the electroplating copper layer 32 can form a plurality of micro-bumps or metal pillars 34 on the metal pads 16 at the bottom of the plurality of openings 14 a of the protective layer 14 . Each micro-bump or metal pillar 34 has a height, which is measured protruding from the upper surface of the protective layer 14, and the height is between 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 5µm 30µm, 5µm to 20µm, 5µm to 15µm, or 3µm to 10µm, or a height greater than or equal to 30µm, 20µm, 15µm, 10µm or 3µm, and has A maximum dimension (such as the diameter of a circle, the diagonal of a square or rectangle) is between 3 µm and 60 µm, between 5 µm and 50 µm, between 5 µm and 40 µm, between 5 µm and 30 µm, Between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or with dimensions less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent micro-convex The block or metal post 34 has a space (pitch) dimension between 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm , 5µm to 15µm or 3µm to 10µm, or the size is less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

As shown in FIG. 15G, after the micro-bumps or metal pillars 34 are formed on the semiconductor wafer as described in FIG. 15F, the semiconductor wafer may be separated, separated into a plurality of individual pieces by a laser dicing process or a mechanical dicing process Semiconductor wafers, these semiconductor wafers 100 can be packaged by following the steps of FIGS. 18A to 18U, 19A to 19Z, 20A to 20Z, 21A to 21H, and 22I .

Alternatively, FIG. 15H is a cross-sectional view of the process of forming micro bumps or micro metal pillars on a wafer in accordance with an embodiment of the present invention. Before forming the adhesive layer 26 in FIG. 15B, the polymer layer 36, that is, the insulating dielectric layer Including an organic material, such as a polymer or a compound including carbon, the insulating dielectric layer can be formed on the protective layer 14 through a spin coating process, a lamination process, a stencil brushing, a spraying process or a molding process. and forming a plurality of openings on the metal pads 16 in the polymer layer 36, the thickness of the polymer layer 36 is between 3 μm and 30 μm or between 5 μm and 15 μm, and the material of the polymer layer 36 can include polyamide Imine, benzocyclobutene (BenzoCycloButene (BCB)), parylene (PBO), epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone.

In one case, the polymer layer 36 can be spin-coated to form a negative photosensitive polyimide layer with a thickness between 6 μm and 50 μm on the protective layer 14 and on the pads 16 , and then bake-transfer coated The formed polyimide layer is then used with a 1X stepper, 1X contact aligner or G-Line with a wavelength range of 434 to 438nm, H-Line with a wavelength range of 403 to 407nm and a wavelength range of 403 to 407nm. Exposure of the polyimide layer baked by the laser scanner of at least two kinds of light in the I-Line of 363 to 367 nm, G-LINE and H-LINE, G-LINE and I-LINE, H-LINE and I-LINE or G-LINE, H-LINE and I-LINE are irradiated on the baked polyimide layer, and then the exposed polyimide layer is developed to form a plurality of openings to expose a plurality of pads 16, and then Temperatures between 180°C and 400°C or above or equal to 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300 ° C, and the heating or curing time is between 20 minutes and 150 minutes, and in a nitrogen environment or an oxygen-free environment, the developed polyimide layer is cured or heated, and the cured polyimide layer has a thickness of medium. Between 3 μm and 30 μm, residual polymer material or other contaminants from the pads 16 and oxygen (O ₂ ) ions or fluorine ions and oxides below 2000 PPM are then removed.

Therefore, as shown in FIG. 15H, micro-bumps or metal pillars 34 are formed on the metal pads 16 at the bottom of the plurality of openings 14a of the protective layer 14 and on the polymer layer 36 surrounding the metal pads 16, as shown in FIG. 15H The specification or description of the micro-bumps or metal pillars 34 shown can refer to the specifications or descriptions of the micro-bumps or metal pillars 34 shown in FIG. 15F. Each micro-bump or metal pillar 34 has a height, and the height is Measured protruding from the upper surface of the polymer layer 36, the height is between 3 µm and 60 µm, between 5 µm and 50 µm, between 5 µm and 40 µm, between 5 µm and 30 µm, between 5 µm and 5 µm. to 20µm, 5µm to 15µm, or 3µm to 10µm, or the height is greater than or equal to 30µm, 20µm, 15µm, 10µm or 3µm, and has a maximum dimension in cross-section (e.g. circular diameter, diagonal of a square or rectangle) between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm , between 5µm and 15µm or between 3µm and 10µm, or the size is less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent micro bumps or metal pillars 34 have a Spatial (spacing) dimensions between 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 15µm between 3µm and 10µm, or dimensions less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Embodiment of SISC bit on protective layer

Alternatively, a second interconnect structure on or within a chip (SISC) may be formed on or over the passivation layer 14 and the FISC 20 before the micro bumps or metal pillars 34 are formed. FIGS. 16A to 16D are embodiments of the present invention. In this example, the cross-sectional view of the process of forming the metal layer of the interconnecting wire on a protective layer.

As shown in FIG. 16A, the process of fabricating the SISC over the protective layer 14 may then begin with the step of FIG. 15C by spin coating a photoresist layer 38 (eg, a positive type photoresist layer) having a thickness between 1 μm and 50 μm It is formed on the seed layer 28 for electroplating by cloth or pressing, and the photoresist layer 38 is patterned through exposure, development and other processes to form a plurality of trenches or a plurality of openings 38a to expose the seed layer 28 for electroplating, using a 1X stepper, 1X contact aligner or with at least two of the G-Line with a wavelength range of 434 to 438nm, an H-Line with a wavelength range of 403 to 407nm and an I-Line with a wavelength range of 363 to 367nm The laser scanner exposes the photoresist layer 38, using G-LINE and H-LINE, G-LINE and I-LINE, H-LINE and I-LINE or G-LINE, H-LINE and I-LINE to illuminate the light On the resist layer 38, the exposed photoresist layer 38 is then developed to form a plurality of openings to expose the electroplating seed layer 28, and then the residual polymer material or other contaminants from the electroplating seed layer 28 and less than 2000PPM are removed. Oxygen (O ₂ ) ions or fluorine-containing ions and oxides, for example, the photoresist layer 38 can be patterned to form a plurality of trenches or a plurality of openings 38a to expose the plating seed layer 28 in the photoresist layer 38 . Forming metal pads, metal lines or connecting lines in trenches or holes 38a and on seed layer 28 for electroplating, openings in trenches or holes 38a in photoresist layer 38 and protective layer 14 The area of 14a overlaps.

Next, as shown in FIG. 16B, a metal layer 40 (eg, copper metal material) can be plated on the plating seed layer 28 exposed by the plurality of trenches or the plurality of openings 38a. For example, the metal layer 40 can be plated with a thickness of Electroplating seed layer 28 (copper material) exposed by copper layers between 0.3 μm and 20 μm, between 0.5 μm and 5 μm, between 1 μm and 10 μm, or between 2 μm and 10 μm in the plurality of trenches or the plurality of openings 38a. )superior.

As shown in FIG. 16C, after the metal layer 40 is formed, most of the photoresist layer 38 may be removed, and then the plating seed layer 28 and the adhesion layer 26 not under the metal layer 40 are etched away, wherein The process of removing and etching can refer to the process description disclosed in FIG. 15F above. Therefore, the adhesive layer 26 , the plating seed layer 28 and the electroplating metal layer 40 are patterned to form an interconnecting wire metal layer 27 on the protective layer. 14 above.

Next, as shown in FIG. 16D, a polymer layer 42 (eg, an insulating or inter-metal dielectric layer) is formed on the protective layer 14 and the metal layer 40, and the plurality of openings 42a of the polymer layer 42 are located on the interconnecting wire metal Above the plurality of connection points of layer 27, the material and process of this polymer layer 42 are the same as those used to form polymer layer 36 in Fig. 15H.

The process of forming the interconnect metal layer 27 is shown in FIG. 15A, FIG. 15B, and FIG. 16A to FIG. 16C, and the process of forming the polymer layer 42 as shown in FIG. 16D can be alternately performed for several times. As shown in SISC29 in FIG. 17, FIG. 17 is a schematic cross-sectional view of the second interconnection structure of the chip (SISC), wherein the second interconnection structure is composed of a plurality of interconnection metal layers 27 and a plurality of polymer layers 42 and The polymer layer 51, ie, an insulator or an intermetal dielectric layer, may alternatively be selectively arranged and arranged according to embodiments of the present invention. As shown in FIG. 17 , the SISC 29 may include an upper interconnect metal layer 27 having metal plugs 27 a in the openings 42 a of the polymer layer 42 and metal on the polymer layer 42 Pads, metal lines or connection lines 27b, the upper interconnection line metal layer 27 can be connected to the lower interconnection line metal layer 27 through the metal plugs 27a of the upper interconnection line metal layer 27 in the plurality of openings 42a in the polymer layer 42 The SISC 29 may include a bottommost interconnecting wire metal layer 27, and the bottommost interconnecting wire metal layer 27 has a plurality of metal plugs 27a in the plurality of openings 14a of the protective layer 14 and a plurality of metal pads, metal pads, and metal pads on the protective layer 14 Lines or connecting lines 27b, the bottommost interconnecting line metal layers 27 can be connected to the plurality of interconnecting line metal layers 6 of the FISC 20 through the bottommost metal plugs 27a of the interconnecting line metal layers 27 in the plurality of openings 14a of the protective layer 14.

Alternatively, as shown in FIGS. 16K , 16L and 17 , the polymer layer 51 may be formed on the protective layer 14 before the bottommost interconnection wire metal layer 27 is formed. The manufacturing process is the same as the material and forming process of the polymer layer 36. Please refer to the description disclosed in FIG. 15H. In this case, the SISC 29 may include a plurality of metal plugs 27a in the plurality of openings 51a of the polymer layer 51 and a plurality of metal plugs 27a in the polymer layer 51. The bottommost interconnecting line metal layer 27 formed by the metal pads, metal lines or connecting lines 27b on the material layer 51, the bottommost interconnecting line metal layer 27 can pass through the bottommost interconnection in the plurality of openings 14a of the protective layer 14. The metal plugs 27a of the connecting wire metal layer 27, and the metal plugs 27a of the interconnecting wire metal layer 27 at the bottommost end of the plurality of openings 51a in the polymer layer 51 are connected to the plurality of interconnecting wire metal layers 6 of the FISC 20.

Therefore, the SISC 29 may optionally form 2 to 6 layers or 3 to 5 layers of interconnecting wire metal layers 27 on the protective layer 14. For each interconnecting wire metal layer 27 of the SISC 29, its metal pads, wires or connections The thickness of the line 27b is, for example, between 0.3 µm and 20 µm, between 0.5 µm and 10 µm, between 1 µm and 5 µm, between 1 µm and 10 µm, or between 2 µm and 10 µm, or Thickness greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, or width e.g. between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm between 1µm and 10µm, between 2µm and 10µm, or whose width is greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, 42 µm per polymer layer and the thickness of the polymer layer 51 is between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, or between 1µm and 10µm, or its thickness is greater than or equal to 0.3µm , 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, the metal pads, metal lines or connecting lines 27b of the interconnection line metal layer 27 of the SISC 29 can be used for the programmable interconnection line 202 .

16E to 16I are cross-sectional views of the process of forming micro metal pillars or micro bumps on the interconnect metal layer above the protective layer in accordance with an embodiment of the present invention. As shown in FIG. 16E, the adhesive layer 44 can be sputtered on the polymer layer 42 and the surface of the metal layer 40 exposed by the plurality of openings 42a. The specifications of the adhesive layer 44 and the method of forming the adhesive layer 44 can refer to the adhesive layer 26 shown in FIG. 15B. and its manufacturing method. An electroplating seed layer 46 may be sputtered on the adhesion layer 44. The specification of the electroplating seed layer 46 and the method of forming the electroplating seed layer 46 may refer to the electroplating seed layer 28 and its manufacturing method shown in FIG. 15C.

Next, as shown in FIG. 16F , the photoresist layer 48 is formed on the seed layer 46 for electroplating, and the photoresist layer 48 is patterned to form openings 48 a through processes such as exposure and development, and the seed layer 46 for electroplating is exposed in the photoresist layer 48 . , the specification of the photoresist layer 48 and its formation method can refer to the photoresist layer 48 and its fabrication method shown in FIG. 15D .

Next, as shown in FIG. 16G, the copper metal layer 50 is electroplated on the plating seed layer 46 exposed by the plurality of openings 48a. The specifications of the copper metal layer 50 and the method of forming the copper metal layer 50 can be referred to the copper metal layers 32 and 32 shown in FIG. 15E. its manufacturing method.

Next, as shown in FIG. 16H, most of the photoresist layer 48 is removed, then the plating seed layer 46 and the adhesion layer 44 not under the copper metal layer 50 are etched away, the photoresist layer 48 is removed, and The method of etching the plating seed layer 46 and the adhesion layer 44 may refer to the method of removing the photoresist layer 30 and etching the plating seed layer 28 and the adhesion layer 26 shown in FIG. 15F .

Therefore, as shown in FIG. 16H , the adhesion layer 44 , the electroplating seed layer 46 and the electroplating copper metal layer 50 may constitute a plurality of micro-bumps or metal pillars 34 at the top of the SISC 29 and the bottom of the plurality of openings 42 a of the polymer layer 42 at the top of the SISC 29 On the top interconnect metal layer 27, the specifications of the micro-bumps or metal pillars 34 and the formation method thereof can refer to the micro-bumps or metal pillars 34 and the manufacturing method thereof shown in FIG. 15F. Each micro-bump or metal pillar 34 a height protruding from the upper surface of the topmost polymer layer 42 of the SISC29, for example between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm , between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, and having a maximum dimension in cross-section (such as the diameter of a circle, the diagonal of a square or rectangle) 3µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 5µm to 20µm, 5µm to 15µm, or 3µm to 10µm, or dimensions less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

As shown in FIG. 16I, microbumps or metal pillars 34 are formed over the semiconductor wafer shown in FIG. 16H, and the semiconductor wafer is diced and separated into a plurality of individual semiconductor chips 100, integrated by a laser dicing or mechanical dicing process, as shown in FIG. 16H. A bulk circuit chip, the semiconductor chip 100 can be packaged using the following steps, as shown in FIGS. 18A to 18U, 19A to 19Z, 20A to 20Z, 21A to 21H, and 22I steps.

As shown in FIG. 16J, the above-mentioned interconnecting wire metal layer 27 may include a power interconnecting wire metal connecting wire or a grounding interconnecting wire metal connecting wire connected to a plurality of metal pads 16 and micro bumps or metal pillars 34 formed thereon, As shown in FIG. 16L, the above-mentioned interconnecting metal layer 27 may include an interconnecting metal connecting line connected to the plurality of metal pads 16 and no micro-metal pillars or bumps are formed thereon.

As shown in FIGS. 16I to 16L and 17, the interconnect metal layer 27 of the FISC 29 can be used for multiple programmable and fixed multiple intra-chip interconnect lines 502 of each commercial standard FPGA IC chip 200 Interconnect lines 361 and 364, as shown in Figure 8A.

Example of FOIT

A Fan-Out Interconnect Technology (FOIT) can be used to fabricate or fabricate the single-level package logic driver 300 in a multi-die package. The FOIT is disclosed as follows:

FIGS. 18A to 18T are schematic diagrams of a process of forming a logic driver according to FOIT according to an embodiment of the present invention. As shown in FIG. 18A, an adhesive material 88 is formed through a dripping process to form a plurality of adhesive regions on the carrier substrate 90. The carrier substrate 90 is intended to That is, a carrier, holder, molder, or substrate. The carrier substrate 90 may be a wafer type (with a diameter of 8 inches, 12 inches, or 18 inches), or a square or rectangular panel type (with a width or The length is greater than or equal to 20cm, 30cm, 50cm, 75cm, 100cm, 150cm, 200cm or 300cm), and various types of semiconductor wafers 100 are disclosed in FIGS. 15G, 15H, 16I to 16L, and 17. The adhesive material 88 may be disposed, mounted, secured, or bonded to the carrier substrate 90, and each semiconductor die 100 is packaged within a single-level package logic driver 300, wherein the single-level package logic driver 300 may be formed with the aforementioned heights (from each A micro-bump or metal pillar 34 with a protruding height from the upper surface of the semiconductor chip 100 , the height of which is between 3 μm and 60 μm, between 5 μm and 50 μm, between 5 μm and 40 μm, between 5 μm and 5 μm. Between 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm or 3µm, 100 sets per semiconductor chip, accommodated, fixed or adhered on the carrier substrate 90, and the semiconductor element 4 is formed on one side or surface of the semiconductor wafer 100, that is, the side or surface with the transistor is upward, and the backside of each semiconductor wafer 100 is not formed with any active element, and a rear surface facing downward, fixing, adhesive, or the adhesive material 88 provided on the carrier substrate 90, adhesive material 88 is then at a temperature between 100 ^o C to 200 ^o C between the hardened or baked.

The single level package logic driver 300 is shown in FIGS. 11A to 11N, and each semiconductor die 100 may be a commercial standard FPGAIC die 200, a DPIIC die 410, an NVMIC die 250, a dedicated I/O die 265, an arithmetic and ( or) computing IC chip 269 (eg CPU chip, GPU chip, TPU chip, DSP chip or APU chip), DRAM chip 321, dedicated control chip 260, dedicated control and I/O chip 266, IAC chip 402, DCIAC chip 267 or DCDI/OIAC wafer 268. For example, the six semiconductor chips 100 shown in FIG. 18A are, from left to right, an NVMIC chip 250 , a commercial standard FPGAIC chip 200 , a CPU chip 269 , a dedicated control chip 260 , and a commercial standard FPGAIC chip 200 and GPU chip 269. For example, the six semiconductor chips 100 shown in FIG. 18A are, from left to right, an NVMIC chip 250 , a commercial standard FPGAIC chip 200 , a DPIIC chip 410 , a CPU chip 269 , a DPIIC chip 410 , and a GPU chip 269 . For example, the six semiconductor chips 100 shown in FIG. 18A are, from left to right, a dedicated I/O chip 265, an NVMIC chip 250, a commercial standard FPGAIC chip 200, a DPIIC chip 410, and a commercial standard FPGAIC chip Die 200 and dedicated I/O die 265.

As shown in FIG. 18A , the material of the adhesive material 88 can be a polymer material, such as polyimide or epoxy resin, and the thickness of the adhesive material 88 is between 1 μm and 50 μm. For example, the adhesive material 88 can be It is polyimide with a thickness between 1 μm and 50 μm, or the adhesive material 88 can be epoxy resin with a thickness between 1 μm and 50 μm, so the semiconductor chip 100 can be adhered to the carrier substrate using polyimide. Alternatively, the semiconductor wafer 100 may be adhered to the carrier substrate 90 using epoxy resin.

As shown in FIG. 18A, the material of the carrier substrate 90 can be silicon material, metal material, glass material, plastic material, ceramic material, polymer material, epoxy-base polymer material or epoxy base compound material, for example, a carrier The substrate 90 can be a reinforced glass fiber epoxy resin substrate with a thickness between 200 μm and 2000 μm; or the carrier substrate 90 can be a glass substrate with a thickness between 200 μm and 2000 μm; or, the carrier substrate 90 may be a silicon substrate with a thickness between 200 μm and 2000 μm; or the carrier substrate 90 may be a ceramic substrate with a thickness between 200 μm and 2000 μm; or, the carrier substrate 90 may be an organic substrate with a thickness between 200 μm and 2000 μm. is between 200 μm and 2000 μm; alternatively, the carrier substrate 90 may be a metal substrate (for example, including copper metal), and its thickness is between 200 μm and 2000 μm; the carrier substrate 90 may not have metal connection lines, but may have bearing (carrying) the function of the semiconductor wafer 100 .

As shown in FIG. 18B , a polymer layer 92 having a thickness t7 between 250 μm and 1000 μm is formed on the carrier substrate 90 and the semiconductor wafer 100 by spin coating, screen printing, dripping or casting and surrounding the semiconductor wafer 100 . the microbumps or metal pillars 34 of the semiconductor wafer 100 and fill in the gaps between the plurality of semiconductor wafers 100 by compression molding (using top and bottom molds) or casting (using a dripper), A resin material or compound is used for the polymer layer 92, which can be a polymer material such as polyimide, benzocyclobutene (BenzoCycloButene (BCB)), parylene, epoxy resin base material or compound, light Sensitive epoxy resin SU-8, elastomer or silicone, the polymer layer 92 can be, for example, photosensitive polyimide/PBOPIMEL™ provided by Japan Asahi Kasei Corporation, epoxy resin provided by Japan NagaseChemteX Corporation A base potting compound, resin or sealant, polymer layer 92 is applied (via coating, printing, dripping or potting) over semiconductor wafer 100 and on carrier substrate 90 to a horizontal plane such as (i) the (ii) covering the upper surface of the plurality of semiconductor wafers 100; (iii) filling the gaps between the micro bumps or metal pillars 34 on the plurality of semiconductor wafers 100; (iv) covering the plurality of semiconductor wafers 100 On the upper surface of the micro-bumps or metal pillars 34 on the semiconductor wafer 100, the polymer material, resin or potting compound can be cured or cross-linked by heating to a specific temperature, such as is greater than or equal to 50°C, 70°C, 90°C, 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C.

As shown in FIG. 18C, the polymer layer 92 is ground from the front side, eg, through a mechanical grinding process to expose the front surface of each microbump or metal post 34 and to planarize the front side of the polymer layer 92, or, alternatively, the polymer layer 92 may be polished through a CMP process. When the polymer layer 92 is polished, the front side portion of each microbump or metal post 34 may be allowed to be removed, and after the structural polishing process, its adhesive layer 44 has a thickness of t8 dielectric. between 250 μm and 8000 μm.

Next, a top interconnect structure (Top Interconnection Scheme, onor of the logic drive (TISD)) in (or on) the logic driver can be formed on or over the front side of the polymer layer 92 and on the microbumps or metal pillars 34 through a wafer or panel process. On the front side, as shown in Figures 18D to 18N.

As shown in FIG. 18D, a polymer layer 93 (ie, insulating dielectric layer) is formed on the polymer layer 92 and micro metal pillars or micro bumps by spin coating, screen printing, dripping or molding. A plurality of openings 93a are formed on or on metal pillars 34, and in polymer layer 93, which may include, for example, polyimide, benzocyclic Butene (BenzoCycloButene (BCB)), parylene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the material of the insulating dielectric layer of the polymer layer 93 Including an organic material, such as a polymer, a polymer or a polymer material compound including carbon, the material of the polymer layer 93 can be a photosensitive material, which can be used for the photoresist layer to form a plurality of patterned openings 93a, so that in the subsequent procedures To form metal plugs, the polymer layer 93 can be coated and exposed through a mask, then developed and etched to form openings 93a in the polymer layer 93, the openings 93a in the polymer layer 93 and microbumps or metal The upper surfaces of the pillars 34 overlap. In some applications or designs, the size or lateral maximum dimension of the plurality of openings 93a in the polymer layer 93 may be smaller than the upper surface of the microbumps or metal pillars 34 below the openings 93a. In other applications Or in the design, the size or the lateral maximum size of the plurality of openings 93a of the polymer layer 93 is larger than the upper surface of the micro-bumps or metal pillars 34 under the openings 93a, and then the polymer layer 93 (ie, the insulating dielectric layer) is a Hardening (curing) at a specific temperature, such as, for example, higher than or equal to 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C or 300°C, and the hardened polymer layer The thickness of 93 is between 3µm and 30µm or between 5µm and 15µm. Some dielectric particles or glass fibers may be added to the polymer layer 93. The material of the polymer layer 93 and its formation method can be referred to in Figure 15H. The material and method of forming the polymer layer 36 are shown.

Next, a relief process is performed on the polymer layer 93 and on the exposed top surface of the microbumps or metal pillars 34 .

Next, as shown in FIG. 18E, an adhesion/seed layer 94 is formed on the polymer layer 93 and the exposed upper surface of the microbumps or metal pillars 34. Alternatively, the adhesion/seed layer 94 may be formed around the microbumps On the polymer layer 92 on the exposed upper surface of the block or metal post 34, first, the thickness of the adhesive layer is between 0.001 μm and 0.7 μm, between 0.01 μm and 0.5 μm, or between 0.03 μm and 0.35 μm. In between, and an adhesion layer can be sputtered on the polymer layer 93 and on the microbumps or metal pillars 34, alternatively, an adhesion layer can be formed on the polymer surrounding the exposed upper surface of the microbumps or metal pillars 34 On the layer 92, the material of the adhesion layer includes titanium, titanium-tungsten alloy, titanium nitride, chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials. The adhesion layer can be processed by ALD process, CVD process or vapor deposition Process formation, for example, the adhesion layer can be deposited by CVD to form a Ti layer or a TiN layer (with a thickness between 1 nm and 50 nm, for example) on the exposed upper surface of the polymer layer 93 and the micro bumps or metal pillars 34 .

Next, a seed layer for electroplating with a thickness between 0.001 μm and 1 μm, between 0.03 μm and 2 μm, or between 0.05 μm and 0.5 μm can be sputtered on the upper surface of the entire adhesion layer, or , The seed layer for electroplating can be formed by atomic layer (ATOMIC-LAYER-DEPOSITION (ALD)) deposition process, chemical vapor deposition (CHEMICAL VAPORDEPOSITION (CVD)) process, evaporation process, electroless plating or physical vapor deposition. The seed layer for electroplating is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the seed layer for electroplating varies with the material of the metal layer electroplated on the seed layer for electroplating. When a copper layer is electroplated on the seed layer for electroplating Copper metal is the preferred material for the seed layer for electroplating, for example, the seed layer for electroplating is formed on or above the adhesive layer, for example, a copper seed layer (with a thickness of, for example, 3 nm to 300 nm or between 3 nm and 200 nm) on the adhesion layer, the adhesion layer and the seed layer for electroplating may constitute the adhesion/seed layer 94 as shown in FIG. 18E.

Next, as shown in FIG. 18F, a photoresist layer 96 (eg, a positive-type photoresist layer) having a thickness between 5 μm and 50 μm is spin-coated or press-bonded to form a seed layer for electroplating on the adhesion/seed layer 94 On the photoresist layer 96, a plurality of trenches or a plurality of openings 96a are formed in the photoresist layer 96 through processes such as exposure and development, and the seed layer for electroplating of the adhesion/seed layer 94 is exposed, using a 1X stepper with a wavelength range of intermediate 1X contact aligner or laser scanner for at least two of the G-Line from 434 to 438 nm, H-Line from 403 to 407 nm and I-Line from 363 to 367 nm Can be used to expose the photoresist layer 96 by illuminating the photoresist layer 96, namely G-Line and H-Line, G-Line and I-Line, H-Line and I-Line or G-Line, H-Line and I-Line is irradiated on photoresist layer 96, then exposed polymer photoresist layer 96 is developed, then oxygen ions (O ₂ plasma) or fluoride ions at 2000 PPM and oxygen are used to remove residual adhesion/seed layer 94 The polymer material or other contaminants of the electroplating seed layer, so that the photoresist layer 96 can be patterned to form a plurality of openings 96a, in the photoresist layer 96 and exposing the electroplating seed layer of the adhesion/seed layer 94, through the subsequent Steps (processes) to be performed to form metal pads, metal lines or connecting lines in trenches or openings 96a and in a seed layer for electroplating of solder balls 325 in one of the trenches in photoresist layer 96 Or the plurality of openings 96a may overlap the area of the plurality of openings 93a in the polymer layer 93 .

Next, referring to FIG. 18G, a metal layer 98 (eg, a copper layer) is electroplated on the seed layer for electroplating of the adhesion/seed layer 94 exposed by the trenches or openings 96A. For example, the metal layer 98 may be electroplated A copper layer having a thickness between 0.3 μm and 20 μm, between 0.5 μm and 5 μm, between 1 μm and 10 μm, and between 2 μm and 10 μm is exposed in the trenches or openings 96A On the seed layer for electroplating formed of copper metal material.

As shown in FIG. 18H, after the metal layer 98 is formed, most of the photoresist layer 38 can be removed, and then the adhesion/seed layer 94 not under the metal layer 98 is etched away, wherein the removal and etching process Referring to the process of removing photoresist layer 30 and etching plating seed layer 28 and adhesion layer 26 as disclosed in FIG. 15F, respectively, adhesion/seed layer 94 and electroplated metal layer 98 may be patterned to form The interconnect metal layer 99 is on the polymer layer 92, and the interconnect metal layer 99 can be formed by a plurality of metal plugs 99a in the plurality of openings 93a of the polymer layer 93 and metal pads, wires or connections on the polymer layer 93 formed by line 99b.

Next, as shown in FIG. 18I , a polymer layer 104 (ie, an insulating or intermetal dielectric layer) is formed on the polymer layer 93 , the metal layer 98 , and the interconnected metal wires in the plurality of openings 104 a of the polymer layer 104 On the connection point of the layer 99, the thickness of the polymer layer 104 is between 3 μm and 30 μm or between 5 μm and 15 μm, some dielectric particles or glass fibers can be added to the polymer layer 104, the material of the polymer layer 104 and its For the formation method, reference may be made to the material of the polymer layer 93 or the polymer layer 36 and the formation method thereof shown in Fig. 18D or Fig. 15H.

FIGS. 18F to 18H disclose the process of forming the interconnect metal layer 99, and the process of forming the polymer layer 104 can be alternately performed multiple times to form the TISD shown in FIGS. 18D to 18N, such as the process of FIG. 18N. As shown in the figure, the TISD 101 includes an upper interconnection wire metal layer 99, and the upper interconnection interconnection wire metal layer 99 has metal plugs 99a in the plurality of openings 104a in the polymer layer 104 and a plurality of metal pads on the polymer layer 104, Metal lines or connection lines 99b, the upper interconnection line metal layer 99 can be connected to the lower interconnection line metal layer 99 through metal plugs 99a in the upper interconnection line metal layer 99 within the plurality of openings 104a of the polymer layer 104, TISD 101 can be Including the bottommost interconnect metal layer 99, wherein the interconnect metal layer 99 has metal plugs 99a in the plurality of openings 93a of the polymer layer 93 and a plurality of metal pads, metal lines or connecting lines 99b on the polymer layer 93 , the bottommost interconnect metal layer 99 can be connected to the SISC 29 of the semiconductor chip 100 through its metal plugs 99 a , a plurality of micro metal pillars or bumps 34 .

Therefore, as shown in Fig. 18N, TISD101 may include 2 to 6 layers or 3 to 5 layers of interconnecting wire metal layers 99, and the metal pads, metal wires or connecting wires 99B of the interconnecting wire metal layers 99 in TISD101 may be Extending above the semiconductor die 100 and horizontally across the edge of the semiconductor die 100 , in other words, the metal pads, wires or connecting lines 99b may extend to the space between two adjacent semiconductor dies 100 of the single level package logic driver 300 . Above the gap, the metal pads, metal lines or connecting lines 99B of the interconnect metal layer 99 in the TISD 101 are connected or coupled to the micro bumps or metal pillars 34 of the two or more semiconductor chips 100 in the single level package logic driver 300 .

As shown in FIG. 18N, the interconnect metal layer 99 of the TISD 101 is connected or electrically connected to the interconnect metal layers 27 of the SISC 29 and the plurality of interconnect metal layers 6 of the FISC 20 through the micro bumps or metal pillars 34 of the semiconductor wafer 100. and/or the semiconductor element 4 (ie, the transistor) of the semiconductor wafer 100 in the single-layer package logic driver 300, the polymer layer 92 fills the gap between the semiconductor wafers 100 to enclose the semiconductor wafer 100, and the semiconductor wafer 100 and The upper surface of the semiconductor wafer 100 is also covered by the polymer layer 92, wherein the thickness of the TISD 101, the metal pads of the metal layer 99 of the interconnecting wires, the metal wires or the connecting wires 99B are, for example, between 0.3 μm and 30 μm, between 0.3 μm and 30 μm. 0.5µm to 20µm, 1µm to 10µm or 0.5µm to 5µm, or thickness e.g. greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm , and its width is, for example, between 0.3 µm and 30 µm, between 0.5 µm and 20 µm, between 1 µm and 10 µm, or between 0.5 µm and 5 µm, or wider than or equal to 0.3 µm , 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, for TISD, the thickness of the polymer layer 104 (that is, the intermetal dielectric layer) is between 0.3µm and 30µm, the dielectric between 0.5µm and 20µm, between 1µm and 10µm, or between 0.5µm and 5µm, or with a thickness such as greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, the interconnect metal layer 99 of the TISD101 can be used for the in-chip interconnect 371 as shown in Figures 11A-11N.

As shown in FIG. 18N, the programmable interconnect lines 361 of the in-chip interconnect lines 371 in the single-level package logic driver 300 as shown in FIGS. 11A to 11N are provided through the interconnect line metal layer 99 of the TISD 101, and can be accessed via Plural memory cells 362 and Plural DPIIC die 410 (shown in Each (or each group) of the plurality of memory cells 362 is used to turn on or off to control whether the connection between the two programmable interconnect lines 361 in the TISD 101 coupled to the two ends of the plurality of pass/no pass switches 258 is established, Thus, a set of programmable interconnect lines 361 of TISD 101 in single-level package logic driver 300 as shown in FIGS. 11A-11N can pass through a plurality of cross-point switches 379 disposed in one or more DPIIC die 410 . / Not interconnected through switch 258 to (1) connect a plurality of commercial standard FPGAIC chips 200 to another plurality of commercial standard FPGAIC chips 200; (2) connect a plurality of commercial standard FPGAIC chips 200 to a plurality of dedicated I/Os Chip 265; (3) connecting a plurality of commercial standard FPGAIC chips 200 to a plurality of DRAM chips 321; (4) connecting a plurality of commercial standard FPGA IC chips 200 to a plurality of processing IC chips and a plurality of computing IC chips 269; (5) Connect a plurality of commercial standard FPGAIC chips 200 to a dedicated control chip 260, a dedicated control chip and a dedicated I/O chip 266, a DCIAC chip 267 or a DCDI/OIAC chip 268; (6) connect a plurality of dedicated I/O chips 265 to another A plurality of dedicated I/O chips 265; (7) connecting a plurality of dedicated I/O chips 265 to a plurality of DRAM chips 321; (8) connecting a plurality of dedicated I/O chips 265 to a plurality of processing IC chips and a plurality of computing ICs Chip 269; (9) connecting a plurality of dedicated I/O chips 265 to a dedicated control chip 260, dedicated control chip and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268; (10) connecting a plurality of DRAMs The chip 321 is connected to another plurality of DRAM chips 321; (11) a plurality of DRAM chips 321 are connected to a plurality of processing IC chips and a plurality of computing IC chips 269; (12) a plurality of DRAM chips 321 are connected to the dedicated control chip 260, the dedicated control chip and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268; (13) connect one complex processing IC chip and complex computing IC chip 269 to another complex processing IC chip and complex computing IC chip 269 or (14) Connect a complex number processing IC chip and complex number calculation IC Die 269 to Dedicated Control Die 260, Dedicated Control Die and Dedicated I/O Die 266, DCIAC Die 267 or DCDI/OIAC Die 268.

Usually, the thickness of the metal pads, metal lines or connecting lines 99B of TISD101 as shown in Fig. 18T and Fig. 18U is greater than or equal to the thickness of the metal pads, metal lines of SISC29 as shown in Figs. 16I to 16L and Fig. 17 Or connecting line 27B, but larger than the plurality of metal pads, lines and connecting line 8 as in Figure 14A.

Metal bumps above TISD

Next, as shown in FIG. 18O to FIG. 18R, a plurality of metal pillars or bumps can be formed on the topmost interconnection line metal layer 99 of the TISD 101. FIG. 18O to FIG. 18R illustrate the formation of a plurality of metal pillars or bumps in the TISD according to the embodiment of the present invention. A schematic cross-sectional view of the process of metal pillars or bumps on the interconnect metal layer.

As shown in FIG. 180, an adhesion/seed layer 116 is formed on the topmost polymer layer 104 of the TISD 101, and on the topmost interconnecting wire metal layer 99 of the TISD 101, first, with a thickness between 0.001 μm and 0.7 μm, An adhesive layer between 0.01 μm and 0.5 μm or between 0.03 μm and 0.35 μm can be sputtered on the topmost polymer layer 104 of TISD101 and on the topmost interconnecting wire metal layer 99 of TISD101. The material can include titanium, titanium-tungsten alloy, titanium nitride, chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials. The adhesion layer can be formed by ALD process, CVD process or evaporation process, for example, adhesion The layers can be deposited by CVD to form a Ti layer or a TiN layer (with a thickness between 1 nm and 50 nm, for example) on the topmost polymer layer 104 of the TISD 101 and on the topmost interconnect metal layer 99 of the TISD 101 .

Next, a seed layer for electroplating with a thickness between 0.001 μm and 1 μm, between 0.03 μm and 2 μm, or between 0.05 μm and 0.5 μm can be sputtered on the upper surface of the entire adhesion layer, or, electroplating The seed layer can be formed through the seed layer 283 for electroplating. The seed layer for electroplating is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the seed layer for electroplating varies with the material of the metal layer electroplated on the seed layer for electroplating. , when a copper layer is electroplated on the electroplating seed layer (for the first type of metal bumps formed by the following steps), copper metal is the preferred material for the electroplating seed layer, when the copper barrier layer is When electroplating the seed layer for electroplating (for the second type of metal bumps formed by the following steps), copper metal is the preferred material for the seed layer for electroplating. When the gold layer is electroplated on the seed layer for electroplating (for the The second type of metal bump is formed by the following steps), and copper metal is the preferred material for the electroplating seed layer. When the gold layer is electroplated on the electroplating seed layer (for the third type of metal bumps) formed by the following steps), gold metal (Au) is the preferred material for the electroplating seed layer, for example, the electroplating seed layer can be deposited on or over the adhesion layer (for the first or second type of metal bump The block is formed by the following steps), for example by sputtering or CVD depositing a copper seed layer (thickness for example between 3nm to 400nm or between 10nm and 200nm) on the adhesion layer, the seed layer for electroplating can be deposited on On or over the adhesion layer (formed by the following steps for the third type of metal bumps), for example by sputtering or CVD deposition of a gold seed layer (for example, between 1 nm and 300 nm thick or between 1 nm and 50 nm in thickness) between) on the adhesion layer, the adhesion layer and the seed layer for electroplating may constitute the adhesion/seed layer 116 in FIG. 18O.

Next, as shown in FIG. 18P, a photoresist layer 118 (eg, a positive photoresist layer) having a thickness between 5 μm and 500 μm is spin-coated or laminated on the electroplating seed layer of the adhesion/seed layer 116 , The photoresist layer 118 is exposed, developed and other processes to form a plurality of interconnecting lines a in the photoresist layer 118 and expose the seed layer for electroplating of the adhesion/seed layer 116, using a 1X stepper, with a wavelength range of 434 to 438nm. G-Line, H-Line with wavelengths ranging from 403 to 407nm and I-Line with wavelengths ranging from 363 to 367nm. 1X contact aligner or laser scanner for at least two of them can be used to illuminate the light On the photoresist layer 118, that is, G-Line and H-Line, G-Line and I-Line, H-Line and I-Line or G-Line, H-Line and I-Line are illuminated on the photoresist layer 118, The exposed photoresist layer 118 is then developed and then oxygen ions (O ₂ plasma) or fluoride ions at 2000 PPM and oxygen are used to remove polymer materials or other contaminants remaining in the plating seed layer of the adhesion/seed layer 116 , so that the photoresist layer 118 can be patterned to form a plurality of openings 118a within the photoresist layer 96 and exposing the metal pads, metal lines, or adhesion/seed layers over the topmost interconnect metal layer 99 116 Seed layer for electroplating.

As shown in FIG. 18P, the openings 118a in the photoresist layer 118 may overlap with the areas of the openings 104a in the uppermost polymer layer 104, and metal pads or bumps are formed through subsequent processes, and the adhesion/seed layer 116 The exposed plating seed layer is located at the bottom of opening 118a and may extend opening 104 to a region or annular region of the topmost polymer layer 104 of TISD 101 surrounding opening 104a.

As shown in FIG. 18Q, a metal layer 120 (eg, a copper layer) is plated on the plating seed layer of the adhesion/seed layer 116 exposed to the plurality of openings 118a. For example, in the first version, the metal layer 120 can be plated with a thickness of Electroplating seed layer exposed in the plurality of openings 118a with copper layers between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm (copper material).

As shown in FIG. 18, after the metal layer 120 is formed, most of the photoresist layer 118 can be removed, and then the adhesion/seed layer 116 that is not under the metal layer 120 can be etched away, wherein the process of removal and etching can be Referring to the process of removing photoresist layer 30 and etching plating seed layer 28 and adhesion layer 26, respectively, as disclosed in FIG. 15F, adhesion/seed layer 116 and electroplated metal layer 120 may thus be patterned to form a plurality of The metal pillars or bumps 122 are on the metal pads, metal lines or connection lines 99b of the topmost interconnection wire metal layer 99 at the bottom of the plurality of openings 104a in the topmost polymer layer 104, and the metal pillars or bumps 122 can be used to connect or The semiconductor die 100 of the single-level package logic driver 300 (eg, the dedicated I/O die 265 in FIGS. 11A-11N ) is coupled to the external circuits or components of the single-level package logic driver 300 .

The height of the metal pillar or bump 122 of the first type (the height protruding from the upper surface of the topmost polymer layer 104 ) is between 5 μm and 120 μm, between 10 μm and 100 μm, between 10 μm and 60 μm between 10µm and 40µm or between 10µm and 30µm, or having a height greater than or equal to 50µm, 30µm, 20µm, 15µm or 5µm, and having a maximum dimension in cross-section (e.g. the diameter of a circle, diagonal of a square or rectangle) between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or dimension Is greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm. The minimum distance between two adjacent first-type metal pillars or bumps 122 is, for example, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, and between 10µm and 40µm. Either between 10µm and 30µm, or with dimensions greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Alternatively, for the second type of metal pillars or bumps 122, the metal layer 120 as shown in FIG. 18Q may be electroplated through a copper barrier layer (eg, a nickel layer) exposed in the plurality of openings 118a by electroplating seed layers (eg, formed by copper), the thickness of the copper barrier layer is between 1µm to 50µm, 1µm to 40µm, 1µm to 30µm, 1µm to 20µm, 1µm to 10µm, 1µm to 5µm, 1µm to 3µm, and then electroplating a solder layer on the copper barrier layer in the plurality of openings 118a, the thickness of the solder layer is, for example, between 1µm and 150µm. 1µm to 120µm, 5µm to 120µm, 5µm to 100µm, 5µm to 75µm, 5µm to 50µm, 5µm to 40µm, Between 5µm to 30µm, 5µm to 20µm, 5µm to 10µm, 1µm to 5µm, 1µm to 3µm, the material of this solder layer can be lead-free solder , which includes tin-containing alloys, copper metal, silver metal, bismuth metal, indium metal, zinc metal, antimony metal, or other metals, such as lead-free solder can include tin-silver-copper (SAC) solder, tin-silver solder or Tin-silver-copper-zinc solder, in addition, after removing most of the photoresist layer 118 and the adhesion/seed layer 116 not under the metal layer 120 in Figure 18R, a reflow process is performed to reflow the solder layer to become the second Type plural round solder balls or bumps.

The second-type metal pillars or bumps 122 protrude from the upper surface of the topmost polymer layer 104 to a height between 5 μm and 150 μm, between 5 μm and 120 μm, between 10 μm and 100 μm, between 10 μm and 10 μm. between 60µm, between 10µm and 40µm or between 10µm and 30µm, or greater than, higher or equal to 75µm, 50µm, 30µm, 20µm, 15µm or 10µm, and having a maximum dimension in cross-section (e.g. Diameter of circle, diagonal of square or rectangle) between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm between, 10µm to 40µm or 10µm to 30µm, or the size is greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the two adjacent metal pillars or bumps 122 have a minimum space (pitch) dimension between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm between 30µm, or dimensions greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Alternatively, for the third type of metal pillars or bumps 122, the seed layer for electroplating as shown in FIG. 18O may be sputtered or CVD deposited with a gold seed layer (eg, between 1 nm and 300 nm in thickness or between 1 nm and 100 nm in thickness) Formed on the adhesion layer, the adhesion layer and the plating seed layer constitute the adhesion/seed layer 116 shown in FIG. 18O, and the metal layer 120 shown in FIG. A gold layer between 3µm and 10µm is formed on the electroplating seed layer exposed by the plurality of openings 118a, wherein the electroplating seed layer is formed of gold, and then, most of the photoresist layer 118 is removed, and then not in the electroplating seed layer. The adhesion/seed layer 116 below the metal layer 120 is etched away to form the third type of metal pillars or bumps 122 .

The third-type metal pillars or bumps 122 protrude from the upper surface of the topmost polymer layer 104 to a height between 3 μm and 40 μm, between 3 μm and 30 μm, between 3 μm and 20 μm, between 3 μm and 3 μm. Between 15µm or between 3µm and 10µm, or less than, greater than or equal to 40µm, 30µm, 20µm, 15µm or 10µm, and having a maximum dimension in cross-section (such as the diameter of a circle, the diameter of a square or a rectangle angle) between 3µm and 40µm, between 3µm and 30µm, between 3µm and 20µm, between 3µm and 15µm, or between 3µm and 10µm, or with dimensions less than or equal to 40µm , 30µm, 20µm, 15µm or 10µm, two adjacent metal pillars or bumps 122 have a minimum space (spacing) dimension between 3µm to 40µm, between 3µm to 30µm, and between 3µm to 20µm , between 3µm and 15µm or between 3µm and 10µm, or with dimensions less than or equal to 40µm, 30µm, 20µm, 15µm or 10µm.

Alternatively, for the fourth type of metal pillars or bumps 122, the metal layer 120 shown in FIG. 18Q may be electroplated on a seed layer for electroplating (eg, made of copper material) exposed by a copper layer on the plurality of openings 118a, The thickness of this copper layer is, for example, 1µm to 100µm, 1µm to 50µm, 1µm to 30µm, 1µm to 20µm, 1µm to 10µm, 1µm to 5µm or 1µm to 3µm, and then electroplating a solder layer on the copper layer in the plurality of openings 118a, the thickness of the solder layer is, for example, between 1µm and 150µm, between 1µm and 120µm, 5µm to 120µm, 5µm to 100µm, 5µm to 75µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, between 5µm to 20µm, 5µm to 10µm, 1µm to 5µm, 1µm to 3µm, the material of this solder layer can be lead-free solder, which includes tin-containing alloy, copper metal, Silver metal, bismuth metal, indium metal, zinc metal, antimony metal, or other metals, such as lead-free solder may include tin-silver-copper (SAC) solder, tin-silver solder, or tin-silver-copper-zinc solder, in addition to , after removing most of the photoresist layer 118 and the adhesion/seed layer 116 not under the metal layer 120 in FIG. 18R, a reflow process is performed to reflow the solder layer into a plurality of round solder balls or bumps to form a Fourth type metal pillars or bumps 122 .

The fourth type of metal pillars or bumps 122 protrudes from the upper surface of the topmost polymer layer 104 to a height between 5 μm and 150 μm, between 5 μm and 120 μm, between 10 μm and 100 μm, and between 10 μm and 100 μm. Between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than, higher or equal to 75µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, and having a Maximum dimension (e.g. diameter of circle, diagonal of square or rectangle) between 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, medium Between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or with dimensions greater than or equal to 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent metals The pillars or bumps 122 have a minimum space (pitch) dimension between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm Between or between 10µm and 30µm, or greater than, higher or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Chip packaging process

Next, as shown in FIG. 18S, the carrier substrate 90 may be removed by a grinding or CMP process as shown in FIG. 18R, or the carrier substrate 90 may be removed by a grinding or CMP process as shown in FIG. 18C After grinding the polymer layer 92 and before forming the polymer layer 93 in Figure 18D. Alternatively, a wafer or panel thinning process, such as a CMP process or a polishing process, may polish the back surface 110a of the semiconductor wafer 100 and the back surface 92a of the polymer layer 92 to thin the structure, as shown in FIG. 18S, The thickness of the polymer layer 92 is between 50 μm and 500 μm, alternatively, the carrier substrate 90 may not be removed.

After the carrier substrate 90 is removed in FIG. 18S, the package structure shown in FIG. 18S can be separated into a plurality of individual chip packages by laser cutting or mechanical cutting, that is, the single-layer package logic driver shown in FIG. 18T 300 , without removing the carrier substrate 90 , the carrier substrate 90 can be cut and separated into a plurality of individual chip-packaged carrier units, ie, the single-layer packaged logic driver 300 shown in FIG. 18U .

Assembly of Chip Packages

As shown in FIG. 18T and FIG. 18U, the first, second or third type of metal pillars or bumps 122 can be used for the single-level package logic driver 300 to be assembled on an assembly substrate, a flex board or a motherboard, and a flip chip The technology of chip packaging or COF assembly technology in LCD driver packaging, wherein the assembly substrate, flexible board or motherboard is such as a printed circuit board (PCB), a silicon substrate structure with interconnecting wires, a A metal substrate, a glass substrate with an interconnected wire structure, a ceramic substrate with an interconnected wire structure, or a flexible board with an interconnected wire structure.

Fig. 18V is the bottom schematic diagram of Fig. 18T, and Fig. 18V is the layout of the metal bumps of the logic driver according to the embodiment of the present invention. The blocks 122 may be arranged in a matrix arrangement with the first, second or third pattern of the first set of metal pillars or bumps 122 arranged in a matrix in the middle region of the bottom surface of the chip package (ie, the single level package logic driver 300), While the second group of metal pillars or bumps 122 of the first, second or third type are arranged in a matrix in the peripheral area surrounding the middle area on the bottom surface of the chip package (ie the single-level package logic driver 300 ), the first, second The first set of metal pillars or bumps 122 of the second or third type has a maximum lateral dimension d1 (ie, the diameter of a circle, or the diagonal of a square or rectangle) larger than that of the first, second or third type The largest lateral dimension d2 (ie, the diameter of a circle, or the diagonal of a square or rectangle) of the second group of metal pillars or bumps 122, exceeds 90% or 80% of the first, second or third type The first group of metal pillars or bumps 122 can be used for power supply connections or ground connections, and more than 50% or 60% of the first, second or third types of the second group of metal pillars or bumps 122 can be used for signal transmission , the second group of metal pillars or bumps 122 of the first, second or third type may be arranged in one or more turns, for example, one turn along the boundary of the bottom surface of the chip package (ie, the single-level package logic driver 300 ) , 2 turns, 3 turns, 4 turns, 5 turns or 6 turns, the minimum spacing of the second group of metal posts or bumps 122 of the first, second or third type is smaller than that of the first, second or third type Minimum pitch for a set of metal pillars or bumps 122 .

In order to bond the first type of metal posts or bumps 122 to the packaged substrate, flex board or motherboard, the packaged substrate, flex board or motherboard may be provided on the top surface with metal posts or bumps 122 of the first type engaged A plurality of metal joints or bumps of a solder layer, and a solder reflow process or a thermocompression bonding process is used to bond the first type of metal posts or bumps 122 to the solder layer on top of the assembly substrate, flex board or motherboard, so that the The chip package (ie, the single-level package logic driver 300 ) is bonded to an assembly substrate, a flex board, or a motherboard.

For the second type of metal pillars or bumps 122 , the chip package (ie, the single-level package logic driver 300 ) can be bonded to the assembly substrate, flex board or motherboard through a soldering or reflow process (with or without flux). board.

The third-type metal pillars or bumps 122 can be bonded to a flexible circuit board or substrate by thermocompression bonding through COF technology. In COF assembly, the third-type metal pillars or bumps 122 can be provided with a very high number of I /Os In a small area (area), the third-type metal studs or bumps 122 have a pitch of less than 20µm, while the square single-layer package logic driver 300 with a width of 10mm has one of the third-type metal studs or bumps 122 The number of I/Os for signal input or output is arranged along the bottom surface and arranged on 4 boundaries, for example, arranged in 2 circles in its peripheral area, for example, the number is greater than or equal to 5000 (with a two-bump spacing of 15µm), 4000 pcs (with 2-bump pitch of 20µm) or 2500 (with 2-bump pitch of 15µm), when using a single-layer film with single-sided metal lines or connecting lines for flexible circuit boards or film bonding to third The reason for designing 2 circles or 2 rows along the edge of the metal post or bump 122 is to facilitate the fan-out (Finout) from the single-level package logic driver 300, on the upper surface of the metal pad on the flexible circuit board or film It has a gold layer, which can be bonded to the third-type metal post or bump 122 by gold-to-gold thermocompression bonding, or has a metal pad on the upper surface of the flexible circuit board or film. The solder layer can be bonded to the third-type metal pillars or bumps 122 through gold-to-solder thermocompression bonding.

For example, FIG. 18W is a schematic cross-sectional view of a plurality of metal pillars or bumps of a logic driver according to an embodiment of the present invention being bonded to a flexible circuit board or film. As shown in FIG. 18W, the first, second or third type of metal pillars or The bumps 122 are bonded to the flexible circuit board or film 126, which includes a polymer layer 148, a copper bond wire 146 on the polymer layer 148, a polymer protective layer 150 on the copper bond wire 146 and On the polymer layer 148, and a gold or solder layer 152 electrolessly plated on the copper bonding wires 146 exposed by the openings in the polymer protective layer 150, the flexible circuit board or film 126 is further connected to an external circuit, such as another semiconductor chip , PCB board, glass substrate, another flexible circuit board or film, ceramic substrate, glass fiber reinforced epoxy substrate, polymer or organic substrate, wherein the printed circuit board comprises a fiberglass and a plurality of circuit layers above or below the core layer , the first, second or third type of metal pillars or bumps 122 are bonded to the tin layer or solder layer 152, for the third type of metal pillars or bumps 122, the metal layer 152 may be thermocompression bonded using a gold-solder material A tin or solder layer in combination with the method, whereby a tin-gold alloy 154 can be formed between the copper bond wire 14 and the third type of metal post or bump 122, or, for the third type of metal post or bump 122. The solder layer 152 may be a metal layer bonded to it using a gold-gold thermocompression bonding method, after which a polymer material 156 (eg, polyimide) may be filled into the logic driver (ie, the single-layer package logic driver 300). ) and the gap between the flexible circuit board or the film 126 to close the first, second or third type of metal posts or bumps 122 .

As described above, the semiconductor wafers 100 are arranged in a single layer to form the single-layer packaged logic driver 300. A plurality of single-layered packaged logic drivers 300 may form an integrated logic driver, and the integrated logic driver may be formed of two or more single-layered packages. The logic driver 300 is manufactured, for example, is composed of 2, 3, 4, 5, 6, 7, 8, or more than 8 single-layer packaging logic drivers 300, for example: (1) in a planar manner Flip-chip packaging on a PCB board; or (2) Package-on-Package (POP) technology in which one of the single-level package logic drivers 300 is mounted on top of another single-level package logic driver 300, in order to achieve stacked assembly In the single-level package logic driver 300, a package through-hole or via-polymer (TPV) may be formed in the middle and at the bottom of the single-level package logic driver 300, as shown below:

First Embodiment of a Chip Package with Multiple Through-Package Vias TPVS

Each single-level package logic driver 300 in stacked form (ie, within a POP package) can be fabricated according to the same process steps and specifications as described in the preceding paragraphs, as in the present invention shown in FIGS. 18A-18T. A schematic cross-sectional view of the process of an embodiment, a plurality of TPVS 158 may also be disposed in the polymer layer 92, between every two adjacent semiconductor chips 100 of the single-layer packaging logic driver 300, and/or the single-layer packaging in the peripheral area The logic driver 300 surrounds the semiconductor chip 100 in the middle area. FIGS. 19A to 19O are cross-sectional schematic diagrams of a process for forming a chip package with TPVS according to FOIT according to an embodiment of the present invention. The TPVS 158 may be formed in one of the single-level package logic drivers 300 for connecting or coupling a plurality of circuits or components located on the front side of the one-level package logic driver 300 to the one of the single-level package logic drivers 300 300 complex circuits or components on the back.

FIGS. 19A to 19O are schematic diagrams of forming a chip package with TPVS according to the first embodiment of the present invention. Before the semiconductor chip 100 is mounted on the carrier substrate 90 shown in FIG. 18A (as shown in FIG. 18A ), as shown in FIG. 19D The TPVS 158 shown can be formed over the carrier substrate 90 as shown in FIG. 18A, and the insulating base layer 91 including a silicon oxide layer, a silicon nitride layer, a polymer layer, or a combination thereof can be formed as shown in FIG. 19A on a carrier substrate 90 as shown in Figure 18A.

Next, as shown in FIG. 19B, TPVS158 (that is, the insulating dielectric layer) is formed on the base insulating layer 91 by spin coating, screen printing, dripping or molding, and a plurality of openings in the polymer layer 97 Above the base insulating layer 91 exposed by 97a, the polymer layer 97 may include, for example, polyimide, BenzoCycloButene (BCB), parylene, epoxy base material or compound, photosensitive epoxy Resin SU-8, elastomer or silicone, the polymer layer 97 can include an organic material, such as a polymer or carbon-containing compound material, the polymer layer 97 can be a photosensitive material and can be used as a photoresist layer for patterning the plurality of openings 97a therein, and forming the terminal portions of the plurality of TPVs through a subsequent process, the polymer layer 97 can be coated, exposed through a photomask, and then developed to form the plurality of openings 97a therein, and then polymerized. a plurality of openings in the layer 97 exposed surface area 97a on a plurality of insulating base layer 91, and then the polymer layer 97 (i.e. an insulating dielectric layer) cured (hardened) at a temperature of, for example, a temperature of greater than or equal to 100 ^o C, 125 ^o C, 150 ^o C, 175 ^o C, 200 ^o C, 225 ^o C, 250 ^o C, 275 ^o C or 300 ^o C, the thickness of the polymer layer 97 after curing is, for example, between 2 µm and 50 µm , 3µm to 50µm, 3µm to 30µm, 3µm to 20µm, or 3µm to 15µm, or thickness greater than or equal to 2µm, 3µm, 5µm, 10µm, 20µm or 30µm, some dielectric particles or glass fibers can be added to the polymer layer 97. The material of the polymer layer 97 and its formation method can refer to the material of the polymer layer 36 and its formation method, as shown in FIG. 15H.

Next, a plurality of metal pillars or bumps are formed on the base insulating layer 91, as shown in FIGS. 19C to 19F. FIGS. 19C to 19F are schematic cross-sectional views of the process of forming a plurality of TPVs on the carrier substrate according to the embodiment of the present invention. As shown in FIG. 19C, an adhesion/seed layer 140 is formed on the polymer layer 97 and on the insulating base layer 91 at the bottom of the plurality of openings 97a in the polymer layer 97, and then can be sputtered to a thickness of between 0.001 μm and 0.7 μm. , an adhesive layer between 0.01 μm and 0.5 μm or between 0.03 μm and 0.35 μm On the polymer layer 97 and on the base insulating layer 91 at the bottom of the plurality of openings 97a of the polymer layer 97, the material of the adhesive layer It can include titanium, titanium-tungsten alloy, titanium nitride, chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials. The adhesion layer can be formed by ALD process, CVD process or evaporation process, for example, the adhesion layer A layer of Ti or TiN may be deposited via sputtering or CVD on the polymer layer 97 (eg, between 1 nm and 200 nm thick or between 5 nm and 50 nm thick).

Next, a seed layer for electroplating with a thickness between 0.001 μm and 1 μm, between 0.03 μm and 2 μm, or between 0.05 μm and 0.5 μm is sputtered on the entire upper surface of the adhesive layer, or, a seed layer for electroplating The layer can be formed by atomic layer (ATOMIC-LAYER-DEPOSITION (ALD)) deposition process, chemical vapor deposition (CHEMICAL VAPORDEPOSITION (CVD)) process, evaporation process, electroless plating or physical vapor deposition. The seed layer for electroplating is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the seed layer for electroplating varies with the material of the metal layer electroplated on the seed layer for electroplating. When a copper layer is electroplated on the seed layer for electroplating Copper metal is the preferred material for the seed layer for electroplating, for example, the seed layer for electroplating is formed on or above the adhesive layer, for example, a copper seed layer (with a thickness of, for example, 3 nm to 300 nm or between 3 nm and 200 nm) on the adhesion layer, the adhesion layer and the seed layer for electroplating can form the adhesion/seed layer 140 as shown in FIG. 19A.

Next, as shown in FIG. 19D, a photoresist layer 142 (for example, a positive photoresist layer) having a thickness between 5 μm and 500 μm is spin-coated or laminated on the electroplating seed layer of the adhesive/seed layer 140 , The photoresist layer 142 is exposed, developed and other processes to form a plurality of openings 142a in the photoresist layer 142 and expose the seed layer for electroplating of the adhesion/seed layer 140, using a 1X stepper with a G- Line, H-Line with wavelengths ranging from 403 to 407nm and I-Line with wavelengths ranging from 363 to 367nm. At least two types of 1X contact aligners or laser scanners can be used to illuminate the photoresist layer 142, that is, G-Line and H-Line, G-Line and I-Line, H-Line and I-Line or G-Line, H-Line and I-Line are illuminated on the photoresist layer 142, and then developed The exposed photoresist layer 142 is then used oxygen ions (O ₂ plasma) or fluoride ions at 2000 PPM and oxygen to remove the polymer material or other contaminants remaining in the plating seed layer of the adhesion/seed layer 140 such that The photoresist layer 142 may be patterned to form a plurality of openings 142a that expose the plating seed layer of the adhesion/seed layer 140, each opening 142a in the photoresist layer 142 overlapping an opening 97a in the polymer layer 97, and in the polymer layer 97. The opening 97a in the polymer layer 97 extends to a region or annular region surrounding the opening 97a of the polymer layer 97, wherein the annular region of the polymer layer 97 has a width between 1 µm and 15 µm, between 1 µm and 10 µm, or between 1 µm and 10 µm. between 1µm and 5µm.

As shown in FIG. 19D, these positions of the plurality of openings 142a are located in the plurality of gaps between the semiconductor chips 100, will be mounted on the polymer layer 97 in the subsequent process, and may be arranged in a plurality of individual chip packages in the subsequent process The peripheral regions 300 , wherein each peripheral region surrounds the semiconductor wafer 100 , forms a central region where the individual chip packages 300 are placed.

As shown in Figure 19E, thicknesses are between 5µm and 300µm, between 5µm and 200µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between Electroplating is formed on the seed layer for electroplating of the adhesion/seed layer 140 exposed to the opening 142a between 10µm and 40µm or between 10µm and 30µm.

As shown in FIG. 19F, after the copper layer 144 is formed, most of the photoresist layer 142 can be removed, and then the adhesion/seed layer 140 not under the copper layer 144 can be etched away, wherein the removal and etching process can be With reference to the process of removing photoresist layer 30 and etching electroplating seed layer 28 and adhesion layer 26, respectively, as disclosed in FIG. 15F, adhesion/seed layer 140 and electroplated copper layer 144 may thus be patterned to form a plurality of The TPVs 158 are on the base insulating layer 91 and on the polymer layer 97 around the plurality of openings 97a in the polymer layer 97, and each TPVs 158 protrudes from the upper surface of the polymer layer 97 by a height between 5µm and 300µm, between 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm , or the height is greater than or equal to 50µm, 30µm, 20µm, 15µm or 5µm, and the cross-section has a maximum dimension (such as the diameter of a circle, the diagonal of a square or rectangle) between 5µm and 300µm, the medium 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm Between 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent TPVs158 have a space (spacing) between 5µm and 300µm, 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or dimensions greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Next, the subsequent steps of the FOIT in Figures 19G to 19J can refer to the FOIT steps disclosed in Figures 18A to 18R, which are shown in Figures 18A to 18R and Figures 19G to 19J The same component numbers in 19G to 19J represent the same components, so the process and description of the components with the same component numbers in FIGS. 19G to 19J can refer to the descriptions disclosed in FIGS. 18A to 18R .

As shown in FIG. 19G, the adhesive material 88 is formed on the plurality of regions of the polymer layer 97, followed by the semiconductor wafer 100 as shown in FIGS. 15G, 15H, 16I to 16L, and 17. The backside adhesive material 88 is bonded to the polymer layer 97 .

As shown in FIG. 19H, a polymer layer 92 having a thickness t7 of between 250 μm and 1000 μm is disposed on or over the polymer layer 97 and on or over the semiconductor wafer 100 to a level: (i) filling the semiconductor wafer 100 (ii) covering the upper surface of the semiconductor wafer 100; (iii) filling the gaps between the micro-bumps or metal pillars 34 of the semiconductor wafer 100; (iv) covering the micro-bumps or metal posts 34 of the semiconductor wafer 100 The upper surface of the pillars 34; (v) filling the gaps between the TPVs 158; and (vi) covering the TPVs 158.

As shown in FIG. 19I, the polymer layer 92 is ground from the front side to expose the front side (upper surface) of each micro-bump or metal post 34 and the front side (upper surface) of the TPVS 158 by, for example, mechanical polishing, and planarization polymerization The front side of the material layer 92, alternatively, the polymer layer 92 may be polished by a CMP process. When the polymer layer 92 is polished, a front end portion of each microbump or metal post 34 is allowed to be removed, and after polishing, The thickness t8 of the polymer layer 92 is between 250 μm and 800 μm.

Next, TISD 101 as in Figures 18D-18N may be formed on or over the front side of polymer layer 92, and on or over the microbumps or metal pillars 34 and on the front side of TPVS 158 via wafer or panel processing, and then , as shown in FIGS. 18O to 18R, the metal posts or bumps 122 are formed at the bottom of the plurality of openings 104a of the topmost polymer layer 104 (as shown in FIG. 19J ), and at the topmost interconnection wire metal layer of the TISD101 99 on.

Next, as shown in FIG. 19K, the carrier substrate 90 is removed through a process of lift-off, grinding or CMP grinding, and the base insulating layer 91 is exposed (not shown) from FIG. 19K. Next, the base insulating layer 91 and The bottom portion of the polymer layer 97 is removed through a grinding or CMP grinding process, and is exposed from the backside 158a of each TPVS 158 in Figure 19K, where the portion of the TPVs 158 with the copper layer is exposed as a plurality of metal pads. Alternatively, after grinding the polymer layer 92 as shown in FIG. 19I, and before forming the polymer layer 93 of the TISD 101, the carrier substrate 90 may be removed by a lift-off, grinding, or CMP grinding process from the structure shown in FIG. 19K. The base insulating layer 91 is exposed. Then, the bottom portion of the base insulating layer 91 and the polymer layer 97 can be removed by a grinding or CMP process to expose the backside 158a of each TPVS 158, wherein the portion of the TPVs 158 on the backside 158a with the copper layer is removed. exposed as multiple metal pads. Thereafter, TISD 101 as in Figures 18D-18N can be formed on or over the front side of polymer layer 92, and on or over microbumps or metal pillars 34 and on the front side of TPVS 158 via wafer or panel processing. Next, metal pillars or bumps 122 as shown in FIGS. 18O to 18R are formed at the bottom of the plurality of openings 104a in the topmost polymer layer 104 and on the topmost interconnect metal layer 99 of the TISD101 as shown in FIG. 19K .

After the carrier substrate 90, the bottom portion of the insulating base layer 91 and the polymer layer 97 in Fig. 19k are removed, and the package structure in Fig. 19K can be diced and separated into individual chip packages through a laser dicing process or a mechanical dicing process The structure (ie, the single-level encapsulation logic driver 300) is shown in FIG. 19L.

Second Embodiment of Chip Package with TPVS

FIGS. 19S to 19Z are schematic diagrams of a process for forming a chip package with TPVS according to the second embodiment of the present invention, the second embodiment shown in FIGS. 19S to 19Z and the first embodiment shown in FIGS. 19A to 19L The difference of one embodiment is that the polymer layer 97 is completely removed. For the same element numbers shown in Fig. 19A to Fig. 19L and Fig. 19S to Fig. 19Z, the same element is represented, so in Fig. 19S For the manufacturing process and description of components with the same component numbers in FIGS. 19Z to 19Z, reference may be made to the descriptions disclosed in FIGS. 19A to 19L.

For the second embodiment, as shown in FIG. 19S, the polymer layer 97 is formed on the base insulating layer 91 by spin coating, screen printing, dripping or molding, but does not have the plurality of openings 97a as shown in FIG. 19B Formed within the polymer layer 97, in this case, the polymer layer 97 may be a non-photosensitive material in addition to the material of FIG. 19B.

Next, a plurality of metal pillars or bumps may be formed on the polymer layer 97 as shown in FIGS. 19T to 19W. FIGS. 19T to 19W are process cross-sections of forming a plurality of TPVs above the carrier substrate in accordance with an embodiment of the present invention. Schematic.

Adhesion/seed layer 140 is formed on polymer layer 97 as shown in FIG. 19T.

Next, as shown in FIG. 19U, a photoresist layer 142 (eg, a positive-type photoresist layer) having a thickness between 5 μm and 500 μm is spin-coated or pressed to form a seed layer for electroplating on the adhesion/seed layer 140 On the photoresist layer 142, a plurality of openings 142a are formed in the photoresist layer 142 through processes such as exposure and development, and the seed layer for electroplating of the adhesion/seed layer 140 is exposed. These positions of the plurality of openings 142a are located between the plurality of semiconductor wafers 100 The gaps will be installed on the polymer layer 97 in the subsequent process, and may be arranged in the peripheral regions of the plurality of individual chip packages 300 in the subsequent process, wherein each peripheral region surrounds the semiconductor chip 100 to form a place where the individual chip packages 300 are placed. a central area.

Then, as shown in Figure 19V, the thicknesses range from 5µm to 300µm, 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, A copper layer 144 of between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm is electroplated on the seed layer for electroplating of the plurality of openings 142a on the adhesion/seed layer 140 .

Next, as shown in FIG. 19W, after the copper layer 144 is formed, most of the photoresist layer 142 can be removed, and then the adhesion/seed layer 140 not under the copper layer 144 is etched away, wherein the removed and etched The process may refer to the process of removing the photoresist layer 30 and etching the plating seed layer 28 and the adhesion layer 26 as disclosed in FIG. 15F, respectively, so that the adhesion/seed layer 140 and the electroplated copper layer 144 may be patterned to A plurality of TPVs 158 are formed on the polymer layer 97, and each TPVs 158 protrudes from the upper surface of the polymer layer 97 by a height between 5 μm and 300 μm, between 5 μm and 200 μm, between 5 μm and 150 μm, and between 5 μm and 150 μm. 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or heights greater than or equal to 50µm, 30µm, 20µm , 15µm or 5µm with a maximum dimension in cross section (e.g. diameter of a circle, diagonal of a square or rectangle) between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm , 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or dimensions greater than or equal to 150µm, 100µm , 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent TPVs158 have a space (spacing) dimension between 5µm to 300µm, 5µm to 200µm, 5µm to 150µm , 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or dimensions greater than or equal to 150µm, 100µm , 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Next, the steps for FOIT as shown in Fig. 19X may refer to the FOIT steps in Figs. 19G to 19J and Figs. 18A to 18R.

Next, as shown in FIG. 19Y, the carrier substrate 90 is removed through a process of lift-off, grinding, or CMP grinding, and the base insulating layer 91 is exposed (not shown) from FIG. 19X. Next, the base insulating layer 91 and The bottom portion of the polymer layer 97 is removed through a grinding or CMP grinding process, and is exposed from the backside 158a of each TPVS 158 in Figure 19K, where the portion of the TPVs 158 with the copper layer is exposed as a plurality of metal pads. Alternatively, after grinding the polymer layer 92 as shown in FIG. 19I, and before forming the polymer layer 93 of the TISD 101, the carrier substrate 90 may be removed by a lift-off, grinding, or CMP grinding process from the structure shown in FIG. 19X. The base insulating layer 91 is exposed. Then, the bottom portion of the base insulating layer 91 and the polymer layer 97 can be removed by a grinding or CMP process to expose the backside 158a of each TPVS 158, wherein the portion of the TPVs 158 on the backside 158a with the copper layer is removed. exposed as multiple metal pads. Thereafter, TISD 101 as in Figures 18D-18N can be formed on or over the front side of polymer layer 92, and on or over microbumps or metal pillars 34 and on the front side of TPVS 158 via wafer or panel processing. Next, metal pillars or bumps 122 as shown in FIGS. 18O to 18R are formed at the bottom of the plurality of openings 104a in the topmost polymer layer 104 as shown in FIG. 19Y and on the topmost interconnect metal layer 99 of the TISD 101 .

After the bottom of the polymer layer 97, the base insulating layer 91, and the carrier substrate 90 in FIG. 19Y are removed, the package structure in FIG. 19Y can be cut and separated into a plurality of individual chip packages (ie, single chip packages) through a laser dicing process or a mechanical dicing process. Layer encapsulates logical driver 300), as shown in Figure 19Z.

POP package with TISD driver

FIGS. 19M to 19O are schematic diagrams of the manufacturing process of a POP package according to an embodiment of the present invention. As shown in FIGS. 19M to 19O, when the topmost single-level package logic driver 300 shown in FIG. 19L is installed in a single-level package Bottom of logic driver 300 with TPVS 158 in polymer layer 92 to connect to circuits, interconnect metal structures, metal structures above the bottom back of a single level package logic driver 300 Pads, multiple metal pillars or bumps and/or multiple components, the process of POP packaging is as follows:

First, as shown in FIG. 19M, the bottom (only one of which is shown in the figure) of a plurality of single-level package logic drivers 300 has metal posts or bumps 122 mounted to a plurality of metal pads on the upper circuit carrier or substrate 110 On 109, the circuit carrier or substrate 110 is, for example, a PCB board, a BGA board, a flexible substrate or film, or a ceramic substrate, and an underfill material 114 can fill the gap between the circuit carrier or substrate 110 and the bottom of the single-layer package logic driver 300 The gap between, alternatively, the gap between the circuit carrier or substrate 110 and the gap with the bottom of the single level package logic driver 300 can be skipped. Next, surface-mount technology (SMT) can be used to mount and bond a plurality of upper single-level package logic drivers 300 (only one shown in the figure) to the underlying single-level package logic drivers 300, respectively.

For the SMT process, solder, solder paste or flux 112 may be first printed on the plurality of metal pads 158a of the TPVS 158 at the bottom of the single-level package logic driver 300, and then, as shown in FIG. 19N, the single-level package logic driver 300 on top There may be metal posts or bumps 122 disposed on the solder, solder paste or flux 112 . Next, a reflow or heating process enables the upper single-level package logic driver 300 to be fixed on the lower single-level package logic driver 300 , and then the underfill material 114 may be filled between the upper and lower single-level package logic drivers 300 Alternatively, the underfill material 114 may be skipped to fill the gap between the upper and lower single-level package logic drivers 300 .

In the next optional step, as shown in FIG. 19N, other metal pillars or bumps 122 of the plurality of single-level package logic drivers 300 as shown in FIG. 19L are mounted on the plurality of single-level package logic using the SMT process. On the TPVs 158 of the driver 300, or bonded to the TPVs 158 of the uppermost plurality of single-level package logic drivers 300, then the underfill material 114 may optionally be formed in the gap between the two, and this step may be repeated multiple times to form Three or more single-level packaged logic drivers 300 are stacked on the circuit carrier or substrate 110 .

Next, as shown in FIG. 19N, a plurality of solder balls 325 are mounted on the back surface of the circuit carrier or substrate 110, and then, as shown in FIG. 19O, the circuit carrier or substrate 110l is cut and separated by laser cutting or mechanical cutting into a plurality of individual substrate units 113, wherein the individual substrate units 113 are, for example, PCB boards, BGA boards, flexible circuit substrates or thin films, or ceramic substrates, so that i number of single-layer package logic drivers 300 can be stacked on the individual substrate units 113 , where the number of i is greater than or equal to 2, 3, 4, 5, 6, 7 or 8.

Alternatively, as shown in FIGS. 19P to 19R are schematic diagrams of a process for manufacturing a POP package according to an embodiment of the present invention, as shown in FIGS. 19P and 19Q, before being separated into a plurality of lower single-layer package logic drivers 300, a plurality of upper The metal studs or bumps 122 of the single-level package logic driver 300 can be fixed or mounted via SMT processes to the TPVS 158 (shown in FIG. 19K ) on a wafer or panel structure (pattern).

Next, as shown in FIG. 19Q, underfill material 114 may be filled in the gaps between each overlying single-level package logic driver 300 and the TPVS 158 of the wafer or panel structure (type) (shown in FIG. 19K ). , where the step of filling the underfill material 114 can be skipped (ignored).

In the next optional step, as shown in FIG. 19Q, other metal pillars or bumps 122 of the plurality of single-level package logic drivers 300 as shown in FIG. 19L are bonded to the single-level package logic drivers 300 on top using SMT mounting. On the TPVs 158, and then the underfill material 114 is optionally formed in the gap between, this step can be repeated several times to form a structure in which two or more single-level package logic drivers 300 are stacked on a wafer or panel ( type) on the TPVS158 (shown in Figure 19K).

Next, as shown in FIG. 19R, the TPVS 158 of the structure (type) of the wafer or panel (as shown in FIG. 19K ) is separated into a plurality of lower single-layer package logic drivers 300 by laser dicing or mechanical dicing, thereby, A number i of single-level package logic drives 300 are stacked together, where the number i is greater than or equal to 2, 3, 4, 5, 6, 7, or 8, and then the stacked single-level package logic drives 300 are stacked together. The metal pillars or bumps 122 of the bottom-most single-level package logic driver 300 of the layer-package logic driver 300 may be mounted on a plurality of metal pads 109 bonded to the circuit carrier or substrate 110 as shown in FIG. 19M, the circuit carrier or substrate 110 is, for example, a BGA substrate, then, underfill material 114 may be filled in the gap between the circuit carrier or substrate 110 and the bottommost single-level package logic driver 300, or the step of filling the circuit carrier or substrate 110 may be skipped and omitted . Next, a plurality of solder balls 325 can be mounted on the backside of the circuit carrier or substrate 110, and then the circuit carrier or substrate 110 can be laser-cut or mechanically cut as shown in FIG. PCB boards, BGA boards, flexible circuit substrates or films, or ceramic substrates), so that i number of single-level package logic drivers 300 can be stacked on a single substrate unit 113, where i number is greater than or equal to 2, 3 1, 4, 5, 6, 7 or 8.

The single-level package logic driver 300 with TPVS158 can be stacked vertically to form a standard type or standard size POP package. For example, the single-level package logic driver 300 may be square or rectangular with a certain width, length, and thickness, and a single level package logic driver 300 may be a The shape and size of the LLP logic driver 300 has an industry standard. For example, when the standard shape of the LLP logic driver 300 is a square, its width is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm with a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm, or 5mm, or, the standard form factor for single-package logic driver 300 is When rectangular, its width is greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and its length is greater than or equal to 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm , 30mm, 35mm, 40mm, 40mm or 50mm, and it has a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm.

Third Embodiment of Chip Package with TPVS

FIGS. 28A to 28G are schematic diagrams of the process of forming the chip package structure with TPVS according to the third embodiment of the present invention. As shown in FIG. 28A, a temporary substrate 590 (eg, a glass substrate or a silicon substrate) and a sacrificial substrate are provided. The bonding layer 591 is formed on the temporary substrate 590, and the temporary substrate 590 with the bonding layer 591 is easier to be debonded or peeled off. For example, the bonding layer 591 can be made of Light-To-Heat Conversion material, And formed on the temporary substrate 590 by screen printing, spin coating or gluing, the material of the LTHC may be a liquid ink containing carbon black and a binder in a solvent mixture. Next, an adhesion/barrier layer 26 may be formed on the sacrificial bonding layer 591 by sputtering or chemical vapor deposition. The adhesion layer 26a (eg, a titanium or titanium nitride layer) having a thickness between 1 nm and 50 nm is located A photoresist layer 15 may be formed on the seed layer 26b of the adhesion/barrier layer 26 on the adhesive bonding layer 591 and a seed layer 26b (eg, copper) on the adhesion layer 26a, wherein the photoresist layer A plurality of openings 15a may be formed in 15 and each opening 15a may expose the seed layer 26b of the adhesion/barrier layer 26, then a copper layer 158 may be electroplated in the opening 15 and on the seed layer of the adhesion/barrier layer 26 26b, to pattern a plurality of copper pillars having a circular shape.

Next, the photoresist layer 15 is removed from the seed layer 26b of the adhesion/barrier layer 26, as shown in FIG. 28B.

Next, as shown in FIG. 28C, a plurality of semiconductor wafers 100 (only one is shown in the figure) are provided, wherein the semiconductor wafer 100 has a polymer layer 136 on the active side (ie, on the bottom) of the semiconductor wafer 100, and A plurality of metal pads, wires, or connections 108 are located in openings in the polymer layer 136, wherein the bottom surface of each metal pad, wire, or connection 108 is coplanar with the bottom surface of the polymer layer 136, Each metal pad, wire or connection 108 may include a layer of copper or aluminum having a thickness between 1 and 10 microns, and in each semiconductor wafer 100, an adhesive layer 138 may be formed on the bottom surface of the polymer layer On and on the bottom surface of each metal pad, wire or connection line 108, each semiconductor chip 100 can be mounted and bonded to the temporary substrate 590 via the adhesive layer 138, so that each semiconductor chip 100 is adhered to the bonding on layer 591. Next, a polymer layer 92 may be formed on the upper surface of the sacrificial bonding layer 591, on the backside of each semiconductor wafer 100, and on each copper pillar by spin coating, screen printing, dripping, or casting. On top of 158, and formed in gaps between every two adjacent copper pillars 158 and in gaps between each semiconductor wafer 100 and copper pillars 158, polymer layer 92 includes, for example, Polyimide, phenylcyclobutene (BenzoCycloButene (BCB)), parylene, epoxy resin-based material or compound, photosensitive epoxy resin SU-8, elastomer or silicone.

Next, a CMP, grinding or polishing process is performed to remove a top portion of the polymer layer 92 and a top portion of each semiconductor wafer 100 , so that the backside of each semiconductor wafer 100 , the top of each copper pillar 158 and the polymer layer 92 are removed. The top portion of each copper pillar 158 is planarized, as shown in FIG. 28D , thereby exposing the top of each copper pillar 158 .

Next, the temporary substrate 590 can be peeled off from the semiconductor wafer 100, the polymer layer 92, and the copper pillars 158, eg, in this case, the sacrifice bonding layer 591 is LTHC and the temporary substrate 590 is glass, generating a laser beam 593 ( For example, a YAG laser with a wavelength of 1064 nm, an output power of 20 to 50 W, and a spot diameter of 0.3 mm at the focal point) passes through the temporary substrate 590 from the back of the temporary substrate 590 to the sacrificial bonding layer 591 , and takes, for example, 8.0 m The sacrificial bonding layer 591 is scanned at a speed of /s, so that the sacrificial bonding layer 591 can be disassembled and the temporary substrate 590 can be easily separated from the sacrificial bonding layer 591, and then an adhesive release tape (not shown) can be attached to the sacrificial bonding layer 591 The remaining bottom surface of the bonding layer 591, then, the adhesive release tape can be pulled from the front side of the vertical-through-via (VTV) wafer to expose each semiconductor die on each copper pillar 158. Adhesion layer 26a of adhesive layer 138 below 100 and adhesive/seed layer 26 below the bottom surface of polymer layer 92, followed by a CMP, grinding or polishing process to attach/seed layer 26, adhesive layer 138 and polymer layer 92 The bottom portion of each of the copper pillars 158 is removed to planarize the bottom of each copper pillar 158 , the bottom surface of the polymer layer 36 of each semiconductor die 100 , and the The bottom and bottom surfaces of polymer layer 92 are performed such that the bottom of each copper pillar 158 and the bottom of each metal pad, metal line or connection line 108 of each semiconductor wafer 100 are exposed.

Next, as shown in FIG. 28F, the package structure in FIG. 28E is turned over, and a front/top interconnect structure (TISDorFISD) for a logical driver or device can be formed on the semiconductor wafer 100, the copper pillars 158 and above polymer layer 92 , TISD or FISD 101 may have one (or more) interconnect metal layer 27 coupled to each metal pad, metal line or connection line 108 and each copper pillar of each semiconductor die 100 158, and there is one (or more) polymer layer 42 between every two adjacent interconnection wire metal layers 27, and the polymer layer 42 is located below the bottommost interconnection wire metal layer 27 or on the topmost layer Above the interconnect wire metal layer 27, wherein the upper interconnect wire metal layer 27 can pass through one of the polymer layers 42 (between the upper interconnect wire metal layer 27 and the lower interconnect wire metal layer 27) The opening is coupled to the underlying interconnect wire metal layer 27, and the bottommost polymer layer 42 may be interposed between the bottommost interconnect wire metal layer 27 and the polymer layer 92 and at the bottommost interconnect wire metal layer 27 and the front side of each semiconductor die 100 , wherein each opening in the bottommost polymer layer 42 may be located over or within a metal pad, wire, or connection line 108 of one of the semiconductor die 100 Above a copper pillar 158 , each interconnect metal layer 27 may extend horizontally across the boundary of each semiconductor chip 100 , and the uppermost interconnect metal layer 27 may have a plurality of metal pads located on the uppermost polymer layer, respectively The bottom of the corresponding opening 42a of the layer 42.

As shown in Figure 28F, in TISD or FISD 101, each polymer layer 42 may be polyimide, benzocyclobutene (BCB), parylene, epoxy-based materials or compounds, photoepoxy SU-8, elastomer or silicone, the thickness of the polymer layer 42 is, for example, between 0.3 µm and 30 µm, between 0.5 µm and 20 µm, between 1 µm and 10 µm, or between 0.5 µm and 5 µm between, or the thickness is greater than 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, each interconnecting wire metal layer 27 has a plurality of metal wires or connecting wires, each metal wire or connecting wire Including: (1) a copper layer 40 having one (or more) low portions in the openings in the polymer layer 42, the thickness of which is between 0.3µm and 20µm, and the copper layer 40 having a high Partly over the polymer layer 42, which has a thickness between 0.3 µm and 20 µm, (2) an adhesive layer 28a (eg, a titanium layer or a titanium nitride layer having a thickness between 1 nm and 50 nm) is located on each on the bottom and sidewalls of the lower portion(s) of the copper layer(s) 40 of the metal line or connection line, and on the bottom of the top copper layer 40 of each line or connection line, and (3) a seed A layer 28b (eg, copper) is interposed between the copper layer 40 of each wire or connection and the adhesive layer 28a, wherein the sidewalls of the top copper layer 40 of each wire or connection are not covered by each wire or connection. Covered by the adhesive layer 28a, each interconnecting metal layer 27 has a plurality of metal lines or connecting lines, the thickness of which is, for example, between 0.3µm and 30µm, between 0.5µm and 20µm, and between 1µm and 10µm. between 0.5µm and 5µm, or thicknesses greater than 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, and widths between 0.3µm and 30µm and 0.5µm Between 20µm, 1µm to 10µm or 0.5µm to 5µm, or widths greater than 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm.

Next, a plurality of metal bumps, pillars or pads 570 are formed in a matrix arrangement on the metal pads of the topmost interconnect metal layer 27 of the TISD or FISD101 and located in the topmost polymer layer 42 of the TISD or FISD101 In the corresponding opening 42a, each metal bump, post or pad 570 has several types, and the first type metal bump, post or pad 570 may include: (1) having a thickness between 1 nm and 50 nm An adhesive layer 26a (eg, a titanium or titanium nitride layer) is formed on the topmost interconnect metal layer 27 of the TISD or FISD 101, (2) a sub-layer 26b (eg, copper) is formed on the adhesive layer 26a, and (3) A copper layer 32 having a thickness between 20 µm and 100 µm is formed on the seed layer 26b. Alternatively, the second type metal bumps, pillars or pads 570 may include the above disclosed adhesive layer 26a, seed layer 26b and copper layer 32, and may further include a tin-containing solder layer 33 (with a thickness ranging from 20µm to 100µm) tin or tin-silver alloy) on the copper layer 32. Alternatively, the type 3 metal bumps, pillars or pads 570 may include a gold layer having a thickness between 3 and 15 μm.

Next, the structure in FIG. 28F can be diced or diced through a laser dicing process or mechanical dicing to produce a plurality of individual chip package structures 550 as shown in FIG. 28G. As shown in FIG. 28G, the chip package structure In 550, a plurality of semiconductor chips 100 can be coupled to each other through the interconnecting metal layers 27 of TISD or FISD 101. In the chip package structure 550, each copper pillar 158 can be used as a through package via (TPV), that is, Polymer perforated vias, provided as vertical connections to the TISD or FISD 101 interconnect metal layer 27 .

In each chip package structure 550, each semiconductor chip 100 may be a standard commercial FPGAIC chip 200, a DPIIC chip 410, an NVMIC chip 250 (eg, a NAND flash chip or a NOR flash chip), a dedicated I/O chip 265 , PCIC chip 269 (such as DSP chip, CPU chip, GPU chip, TPU chip or APU chip), HBMIC chip (such as DRAM chip 321, SRAM chip, MRAM chip or RRAM chip), dedicated control chip 260, dedicated control and I/O die 266, IAC die 402 (eg, analog IC die, hybrid module IC die, or radio frequency (RF) IC die), DCIAC die 267, or DCDI/OIAC die 268 are arranged in the arrangement of FIGS. 11A to 11N. In one of the standard commercialized logic drivers 300, the interconnect metal layer 27 of the TISD or FISD 101 can construct programmable interconnect lines 361 and fixed interconnect lines such as the inter-die interconnect lines 371 in FIGS. 11A to 11N. 364.

Alternatively, in each chip package structure 550, it may be a single chip package structure or chiplet, ie only one semiconductor die 100 as in Figure 28C may be provided therein, where only one semiconductor die 100 may be a standard commercial FPGAIC chip 200, DPIIC chip 410, NVMIC chip 250 (eg NAND flash chip or NOR flash chip), dedicated I/O chip 265, PCIC chip 269 (eg DSP chip, CPU chip, GPU chip, TPU chip or APU chip), HBMIC chip (such as DRAM chip 321, SRAM chip, MRAM chip or RRAM chip), dedicated control chip 260, dedicated control and I/O chip 266, IAC chip 402 (such as analog IC chip, hybrid module IC die or radio frequency (RF) IC die), DCIAC die 267 or DCDI/OIAC die 268.

Fourth Embodiment of Chip Package with TPVS

FIGS. 28H to 28I are schematic diagrams of the process of forming the chip package structure with TPVS according to the fourth embodiment of the present invention. As shown in FIG. 28H, after the CMP, grinding or polishing process in FIG. 28C is performed, an insulating dielectric The electrical layer 93 can be formed on the backside of each semiconductor wafer 100 and the polymer layer 92 , and each opening 93a in the insulating dielectric layer 93 can be positioned vertically above the copper pillars 158 , that is, on top of each copper pillar 158 may be located at the bottom of the opening 93a in the insulating dielectric layer 93, which may be polyimide, benzocyclobutene (BCB), parylene, epoxy-based materials or compounds, light Epoxy SU-8, elastomer or silicone, the thickness of the polymer layer 93 is, for example, between 0.3 μm and 30 μm or between 5 μm and 15 μm.

Next, a plurality of metal pads or bumps 583 with a thickness between 1 μm and 10 μm can be formed on top of the copper pillars 158 or on the upper surface of the insulating dielectric layer 93 in a matrix pattern, each metal pad or bump 583 There can be several types. The thickness of the first type metal pad or bump 583 is between 1 μm and 10 μm. The first type metal pad or bump 583 includes: (1) It has a thickness between 1 nm and 50 nm. An adhesive layer 26a (eg, a titanium or titanium nitride layer) is formed on the top of the copper pillar 158 or on the upper surface of the insulating dielectric layer 93, and (2) a sublayer 26b (eg, copper) is formed on the adhesive layer 26a, and (3) a copper layer 32 having a thickness between 1 µm and 10 µm is formed on the seed layer 26b. Alternatively, the second-type metal bumps, pillars or pads 570 may include the above-disclosed adhesive layer 26a, seed layer 26b and copper layer 32, and may further include a tin-containing solder layer 33 (with a thickness ranging from 1µm to 10µm) tin or tin-silver alloy) on the copper layer 32.

Next, the steps in FIGS. 28E to 28G are performed to form a plurality of chip package structures 550 as shown in FIG. 28I, each copper pillar 158 serving as a through package via (TPV), that is, a polymer Perforated vias to provide vertical connections between metal layers 27 as interconnects for TISD or FISD 101 and metal pads or bumps 583, which may be arranged in a matrix pattern, which may include multiple dummy metals Pads or bumps 583a, which are not connected to either semiconductor die 100, but have a mechanical function for subsequent POP packaging structures, these dummy metal pads or bumps 583a are formed on the bottom of the insulating dielectric layer 93 Surface and vertical locations are below the semiconductor wafer 100 , and each dummy metal pad or bump 583 a may not be connected to any copper pillar 158 .

Embodiment of chip package structure with bottom layer interconnection structure (Bottom Interconnection Scheme, onor of the logic drive (BISD)) and TPVS in (or on) logical drive

Alternatively, fan-out interconnect technology (FOIT) may be performed over the carrier substrate 90 to fabricate a bottom metal interconnect structure on the backside (BISD) of a single-level package logic driver 300 in a multi-chip package for use as described in Section 1. The first embodiment in Figures 20A to 20X, the description of BISD is as follows:

FIGS. 20A to 20M are schematic diagrams of processes for forming BISD on a carrier substrate according to an embodiment of the present invention. As shown in FIG. 20A, a base insulating layer 91 includes a silicon monoxide layer, a silicon nitride layer, a polymer layer or the like. The combined insulating layer 91 may be formed on the carrier substrate 90 shown in FIG. 18A.

Next, as shown in FIG. 20B, a polymer layer 97 (that is, an insulating dielectric layer) is formed on the insulating base layer 91 by spin coating, screen printing, dripping or molding, on the insulating base layer 91 A polymer layer 97 is formed, and a plurality of openings 97a are formed to expose the base insulating layer 91 in the polymer layer 97. The polymer layer 97 may include, for example, polyimide, benzocyclobutene (BenzoCycloButene (BCB)), parylene Toluene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the polymer layer 97 may include an organic material, such as a polymer or carbon-containing compound material, the polymer layer 97 can be a photosensitive material, and can be used as a photoresist layer for patterning a plurality of openings 97a therein, and forming the end portions of a plurality of metal plugs through subsequent processes, the polymer layer 97 can be coated, through Photomask exposure followed by development to form openings 97a therein, openings 97a in polymer layer 97 exposing upper surface regions of base insulating layer 91, followed by polymer layer 97 (ie, insulating dielectric layer) at a temperature Under curing (hardening), e.g. at a temperature greater than or equal to 100 ^o C, 125 ^o C, 150 ^o C, 175 ^o C, 200 ^o C, 225 ^o C, 250 ^o C, 275 ^o C or 300 ^o C, polymerization The thickness of the object layer 97 after curing is, for example, between 2 μm and 50 μm, between 3 μm and 50 μm, between 3 μm and 30 μm, between 3 μm and 20 μm, or between 3 μm and 15 μm, or The thickness is greater than or equal to 2µm, 3µm, 5µm, 10µm, 20µm or 30µm. Some dielectric particles or glass fibers can be added to the polymer layer 97. The material of the polymer layer 97 and its forming method can refer to the material of the polymer layer 36 and its method. The formation method is shown in Figure 15H.

Next, a relief process is performed on the polymer layer 97 and the exposed upper surface regions of the base insulating layer 91 to form a BISD 79 as shown in FIG. 20C to FIG. 20M, as shown in FIG. 20C, with a thickness of 0.001 μm Adhesion layer 81 between 0.7 μm, 0.01 μm and 0.5 μm, or between 0.03 μm and 0.35 μm may be sputtered on polymer layer 97 and on base insulating layer 91 . The material can include titanium, titanium-tungsten alloy, titanium nitride, chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials. The adhesive layer 81 can be formed by an ALD process, a CVD process or an evaporation process, for example, The adhesion layer can be deposited by CVD to form a Ti layer or a TiN layer (the thickness of which is, for example, between 1 nm and 200 nm or between 5 nm and 50 nm) on the polymer layer 97 and the exposed pluralities of the base insulating layer 91 on the upper surface area.

Next, as shown in FIG. 20C , a seed layer 83 for electroplating with a thickness between 0.001 μm and 1 μm, between 0.03 μm and 2 μm, or between 0.05 μm and 0.5 μm is sputtered on the adhesive layer 81 . The entire upper surface, alternatively, the seed layer 83 for electroplating can be deposited by atomic layer (ATOMIC-LAYER-DEPOSITION (ALD)) process, chemical vapor deposition (CHEMICAL VAPORDEPOSITION (CVD)) process, evaporation process, electroless plating or physical vapor deposition process formed by deposition. The seed layer 83 for electroplating is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the seed layer 83 for electroplating varies with the material of the metal layer electroplated on the seed layer 83 for electroplating. When using the seed layer 83, copper metal is the preferred material for the seed layer 83 for electroplating. For example, the seed layer 83 for electroplating is formed on or above the adhesive layer 81. For example, a copper seed layer can be chemically deposited by sputtering or CVD ( Its thickness is, for example, between 3 nm and 300 nm or between 10 nm and 120 nm) on the adhesive layer 81 .

As shown in FIG. 20D, a photoresist layer 75 (for example, a positive type photoresist layer) having a thickness between 5 μm and 50 μm is formed on the electroplating seed layer 83 by spin coating or pressing. Processes such as exposure, development, etc., form a plurality of trenches or a plurality of openings 75A in the photoresist layer 75 and expose the seed layer 83 for electroplating, using a 1X stepper, with a G-Line with a wavelength range of 434 to 438nm, and a wavelength range of intermediate A 1X contact aligner or a laser scanner with at least two of the H-Line at 403 to 407 nm and the I-Line at the wavelength range of 363 to 367 nm can be used to illuminate the photoresist layer 75 to expose the light The photoresist layer 75, that is, G-Line and H-Line, G-Line and I-Line, H-Line and I-Line or G-Line, H-Line and I-Line are illuminated on the photoresist layer 75, and then The exposed photoresist layer 75 is developed, and then oxygen ions (O ₂ plasma) or fluoride ions are used at 2000 PPM and oxygen, and the polymer material or other contaminants remaining in the plating seed layer 83 are removed, so that the photoresist layer 75 is Can be patterned to form a plurality of trenches or a plurality of openings 75a, in the photoresist layer 96 and exposing the seed layer for electroplating of the adhesion/seed layer 94, through subsequent steps (processes) to be performed to form metal pads, metal Lines or connecting lines are in the trenches or openings 75a and on the plating seed layer 83, and one of the trenches or openings 75a in the photoresist layer 75 may be connected with the trenches or openings 75a in the polymer layer 97. The areas of the plurality of openings 75a overlap.

Next, as shown in FIG. 20E, a metal layer 85 (eg, copper) is electroplated on the plating seed layer 83 (made of copper) exposed by the trenches or the plurality of openings 75A. Plating thickness between 5µm to 80µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 3µm to 20µm, 3µm to 15µm or Between 3µm and 10µm.

Next, as shown in FIG. 20F, after the metal layer 85 is formed, most of the photoresist layer 75 can be removed, and then the adhesive layer 81 and the electroplating seed layer 83 that are not under the metal layer 85 are etched and removed. The process of removing and etching can refer to the process of removing the photoresist layer 30 and etching the plating seed layer 28 and the adhesion layer 26 as disclosed in FIG. 15F, respectively. Therefore, the adhesion layer 81, the plating seed layer 83 and the electroplating Metal layer 85 may be patterned to form interconnect metal layer 77 on polymer layer 97 and within openings 94a in polymer layer 97, interconnect metal layer 77 forming metal plugs 77a within polymer layer The plurality of insulating layers a of 97 and the plurality of metal pads, metal lines or connecting lines 77b are on the polymer layer 97 .

Next, as shown in FIG. 20G , a polymer layer 87 (ie, an insulating or intermetal dielectric layer) is formed on the polymer layer 97 , the metal layer 85 , and the interconnecting wire metal in the plurality of openings 87 a of the polymer layer 87 . On the connection point of the layer 77, the thickness of the polymer layer 87 is between 3 μm and 30 μm or between 5 μm and 15 μm, and some dielectric particles or glass fibers can be added to the polymer layer 87. For the formation method, reference may be made to the material of the polymer layer 97 or the polymer layer 36 and the formation method thereof shown in Fig. 18D or Fig. 15H.

FIGS. 20C to 20F disclose the process of forming the interconnect metal layer 77, and the process of forming the polymer layer 104 can be alternately performed multiple times to manufacture the BISD 79 as shown in FIGS. 20H to 20L, such as the BISD 79 in FIGS. 20H to 20L. As shown, the BISD 79 includes an upper multiple interconnect metal layer 77 having multiple metal plugs 77 a in the plurality of openings 87 a of the polymer layer 87 and a plurality of metal plugs 77 a on the polymer layer 87 Metal pads, metal lines or connecting lines 77b, the upper multiple interconnecting line metal layer 77 can be connected to the lower multiple interconnecting line metal layer through metal plugs 77a in the upper photoresist layer 118 within the plurality of openings 87a of the polymer layer 87 77, 289 may include a bottommost plurality of interconnection wire metal layers 77, wherein the plurality of interconnection wire metal layers 77 have metal plugs 77a within the plurality of openings 97a of the polymer layer 97 and a plurality of metal pads on the polymer layer 97, Metal wire or connecting wire 77b.

As shown in FIG. 20L, a topmost metal layer 77 of interconnecting lines can be covered by a topmost polymer layer 87. A plurality of openings 87a in the topmost polymer layer 87 are located in the gaps between the semiconductor wafers 100, And in a subsequent process, the polymer layer 87 is arranged on the polymer layer 87, wherein the polymer layer 87 is arranged in the peripheral area of the single-layer packaged logic driver 300 in a subsequent process to complete the arrangement and arrangement, wherein each periphery of the semiconductor chip 100 is surrounded. The region is mounted and bonded to the middle region of a single-layer packaged logic driver 300, and the topmost polymer layer 87 after curing and before the subsequent polishing process has a thickness t9 between 3µm and 30µm or between 5µm and 15µm between.

Next, as shown in FIG. 20M, a CMP process and a mechanical polishing process are performed to planarize the upper surface of the topmost polymer layer 87 and the top surface of the topmost BISD 79, and the planarized thickness t10 of the topmost polymer layer 87 Between 3 µm and 30 µm or between 5 µm and 15 µm, the BISD 79 can therefore include a plurality of interconnecting wire metal layers 77 from 1 to 6 or 2 to 5 layers.

As shown in FIG. 20M, each of the plurality of interconnecting wire metal layers 77 of the BISD 79 is on the polymer layer 87 and the polymer layer 97, and the thickness of each plurality of interconnecting wire metal layers 77 is, for example, between 0.3 μm and 40 μm. , 0.5µm to 30µm, 1µm to 20µm, 1µm to 15µm, 1µm to 10µm, or 0.5µm to 5µm, or thickness greater than or equal to 0.3 µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, 7µm or 10µm, the line width of the metal layer 77 of the multiple interconnection lines of the BISD79 is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, and between 0.5µm and 30µm. 1µm to 20µm, 1µm to 15µm, 1µm to 10µm, or 0.5µm to 5µm, or thicknesses greater than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm , 7µm or 10µm, the thickness of each polymer layer 87 between two adjacent plural interconnecting metal layers 77 is between 0.3µm and 50µm, between 0.5µm and 30µm, between 1µm and 20µm between, 1µm to 15µm, 1µm to 10µm, or 0.5µm to 5µm, or thickness greater than or equal to 0.3µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, The thickness or height of the metal plugs 77A of the metal layer 77 of the plurality of interconnecting lines in the polymer layer 87 and an opening 87a is between 3 μm and 50 μm, between 3 μm and 30 μm, between 3 μm and 20 μm, and between 3 μm and 15 μm. or thickness greater than or equal to 3µm, 5µm, 10µm, 20µm or 30µm.

FIG. 20N is a top view of a metal plane according to an embodiment of the present invention. As shown in FIGS. 20M and 20N, the metal layers 77 of the plurality of interconnecting lines may include a metal plane 77c and a metal plane 77d respectively used as power planes for power supply. or a ground plane, wherein the thickness of metal plane 77c and metal plane 77d is, for example, between 5µm and 50µm, between 5µm and 30µm, between 5µm and 20µm, or between 5µm and 15µm, or The thickness is greater than or equal to 5µm, 10µm, 20µm or 30µm, and each metal plane 77c and metal plane 77d can be arranged in a staggered or crossed pattern, for example, can be arranged in a fork shape, that is, each metal plane 77c and the metal plane 77d have a plurality of parallel extending portions and a horizontal connecting portion connecting the horizontally extending portions, and the horizontally extending portions of a metal plane 77c and a metal plane 77d can be arranged on two adjacent other metal planes 77c and a metal plane Between the horizontally extending portions of 77d, alternatively, a plurality of interconnecting wire metal layers 77 may include a metal plane used as a heat sink, the thickness of which is, for example, between 5 µm and 50 µm, between 5 µm and 30 µm, between 5 µm and 5 µm. Between 20µm or 5µm to 15µm, or thickness greater than or equal to 5µm, 10µm, 20µm or 30µm.

Next, as shown in FIGS. 20O to 20R, the embossing process as shown in FIGS. 19O to 19F is performed on the BISD79 to form TPV. A schematic cross-sectional view of the process on the BISD, as shown in FIG. 200, the adhesion layer 140a with a thickness between 0.001 μm and 0.7 μm, between 0.01 μm and 0.5 μm, or between 0.03 μm and 0.35 μm is sputtered On the topmost polymer layer 87 and on the multiple interconnecting wire metal layers 77 located at the topmost bottom of the plurality of openings 87a in the topmost polymer layer 87, the material of the adhesive layer 140a may include titanium, titanium-tungsten alloy, titanium nitride , chromium, titanium-tungsten alloy layer, tantalum nitride or a composite of the above materials, the adhesion layer 140a can be formed by ALD process, CVD process or evaporation process, for example, the adhesion layer 140a can be deposited by sputtering or CVD A Ti layer Or the TiN layer is on the topmost polymer layer 87 and the plurality of interconnecting wire metal layers 77 (thickness, for example, between 1 nm and 200 nm or between 5 nm and 50 nm) located at the top of the topmost polymer layer 87 at the bottom of the plurality of openings 87a. )superior.

Next, as shown in FIG. 200 , a plating seed layer 140b having a thickness between 0.001 μm and 1 μm, between 0.03 μm and 2 μm, or between 0.05 μm and 0.5 μm is sputtered on the plating seed layer. The entire upper surface of 140b, alternatively, the seed layer 140b for electroplating can be deposited through atomic layer (ATOMIC-LAYER-DEPOSITION (ALD)) process, chemical vapor deposition (CHEMICAL VAPORDEPOSITION (CVD)) process, evaporation process, electroless plating or physical formed by vapor deposition. The electroplating seed layer 140b is beneficial to form a metal layer by electroplating on the surface. Therefore, the material type of the electroplating seed layer 140b varies with the material of the metal layer electroplated on the electroplating seed layer 140b. When a copper layer is electroplated in the electroplating When using the seed layer 140b, copper metal is the preferred material for the electroplating seed layer 140b. For example, when the electroplating seed layer 140b is formed on or above the adhesion layer 140a, a copper seed layer can be chemically deposited by sputtering or CVD. (The thickness is, for example, between 3 nm and 300 nm or between 10 nm and 120 nm) On the adhesive layer 140 a, the adhesive layer 140 a and the seed layer 140 b for electroplating can constitute the adhesive/seed layer 140 .

Next, as shown in FIG. 24P, a photoresist layer 142 (eg, a positive-type photoresist layer) having a thickness between 5 μm and 500 μm is spin-coated or pressed to form a seed layer for electroplating on the adhesion/seed layer 140 On the photoresist layer 140b, the photoresist layer 142 is exposed, developed and other processes to form a plurality of openings 142a in the photoresist layer 142 and expose the seed layer 140b for electroplating of the adhesion/seed layer 140, using a 1X stepper, with a wavelength range of 434 to 1X contact aligner or laser scanner for at least two of the G-Line at 438nm, H-Line with wavelengths ranging from 403 to 407nm, and I-Line with wavelengths ranging from 363 to 367nm can be used for illumination The photoresist layer 142 is exposed on the photoresist layer 142, that is, the G-Line with a wavelength range of 434-438 nm, an H-Line with a wavelength range of 403-407 nm, and an I-Line with a wavelength range of 363-367 nm wherein at least two kinds of light are irradiated on the photoresist layer 142, then the exposed photoresist layer 142 is developed, and then oxygen ions (O ₂ plasma) or fluorine-containing ions are used at 2000PPM and oxygen, and the remaining photoresist layer 142 is removed of polymer material or other contaminants such that the photoresist layer 142 can be patterned to form a plurality of openings 142a in the electroplating seed layer 140b and exposing the electroplating seed layer 140b of the adhesion/seed layer 140 in the photoresist layer 142 Each of the openings 142a overlaps with an opening 87A in the topmost polymer layer 87 and extends from an opening 87A in the topmost polymer layer 87 to a region or annular region surrounding an opening 87A in the topmost polymer layer 87, The annular region of the polymer layer 87 has a width between 1 μm and 15 μm, between 1 μm and 10 μm, or between 1 μm and 5 μm.

As shown in FIG. 20P, the openings 142A are located in the plurality of gaps between the semiconductor wafers 100, and are mounted and bonded on the topmost polymer layer 87 of the BISD 79 in a subsequent process, wherein the polymer layer 87 is arranged in a single layer The peripheral regions of the packaged logic driver 300 are arranged and arranged in successive processes, wherein each peripheral region surrounding the semiconductor chip 100 is mounted and bonded to the middle region of a single-layer packaged logic driver 300 .

As shown in Figure 20Q, thicknesses are between 5µm and 300µm, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between A copper layer 144 between 10 µm and 100 µm, between 10 µm and 60 µm, between 10 µm and 40 µm, or between 10 µm and 30 µm electroplating seed layer for electroplating of adhesion/seed layer 140 exposed in opening 142A 140b. ,

As shown in FIG. 20R, after the copper layer 144 is formed, most of the photoresist layer 142 can be removed, and then the plating seed layer 140b and the adhesion layer 140a that are not under the copper layer 144 are etched away, wherein the removal and The etching process can refer to the process of removing the photoresist layer 30 and etching the plating seed layer 28 and the adhesion layer 26 as disclosed in FIG. 15F, respectively, so that the adhesion/seed layer 140 and the electroplated copper layer 144 can be patterned Processed to form a plurality of TPVS 158 on the topmost plurality of interconnecting wire metal layers 77 and on the topmost polymer layer 87 surrounding the opening 87A in the topmost polymer layer 87 .

As shown in FIG. 21A, which is a top view of the TPVS according to the embodiment of the present invention, the area 53 surrounded by the dotted line has semiconductor wafers 100 that can be mounted and bonded. As shown in FIG. 21A, the TPVS 158 is located in the plural gaps between the semiconductor wafers 100, and is The subsequent process is to install and bond on the topmost polymer layer 87 of the BISD 79 , wherein the polymer layer 87 is arranged in the peripheral area of the single-layer package logic driver 300 to complete the arrangement and arrangement in the subsequent process, wherein each surrounding the semiconductor chip 100 is arranged and arranged. A peripheral area is mounted and bonded to the middle area of a single-level package logic driver 300 .

As shown in Figure 20R, each TPVs 158 protrudes from the upper surface of the polymer layer 87 of the BISD 79 by a height between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, and between 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or heights greater than or equal to 50µm, 30µm, 20µm, 15µm or 5µm, with a maximum dimension in cross-section (e.g. diameter of a circle, diagonal of a square or rectangle) between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or dimensions greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, two adjacent TPVs158 have a space (spacing) dimension between 5µm to 300µm, 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm, or dimensions greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Next, the subsequent FOIT steps are shown in Figures 20S to 20V. You can refer to the FOIT steps shown in Figures 18A to 18R. For the steps in Figures 18A to 18R and Figure 20S to The same component numbers shown in Figure 20V represent the same components, so the process and description of the components with the same component numbers in Figures 20S to 20V can refer to the descriptions disclosed in Figures 18A to 18R.

As shown in FIG. 20S, an adhesive material 88 is formed on the plurality of regions of the topmost polymer layer 97, followed by the semiconductor wafer shown in FIGS. 15G, 15H, 16I to 16L, and 17. The backside of 100 is bonded to polymer layer 97 by adhesive material 88 .

As shown in FIG. 20T, a polymer layer 92 having a thickness t7 between 250 μm and 1000 μm is disposed (by coating, printing and molding) on or over a polymer layer 87 and on the semiconductor wafer 100 or From above to a level: (i) filling the gaps between the semiconductor wafers 100 ; (ii) covering the upper surface of the semiconductor wafers 100 ; (iii) filling the gaps between the micro bumps or metal pillars 34 of the semiconductor wafer 100 (iv) covering the upper surface of the micro bumps or metal pillars 34 of the semiconductor wafer 100; (v) filling the gaps between the TPVs 158; and (vi) covering the TPVs 158.

As shown in FIG. 20UI, the polymer layer 92 is ground from the front side to expose the front side (upper surface) of each micro-bump or metal post 34 and the front side (upper surface) of the TPVS 158 by, for example, mechanical polishing, and planarization polymerization The front side of the material layer 92, alternatively, the polymer layer 92 may be polished by a CMP process. When the polymer layer 92 is polished, a front end portion of each microbump or metal post 34 is allowed to be removed, and after polishing, The thickness t8 of the polymer layer 92 is between 250 μm and 800 μm.

Next, as shown in FIG. 20V, the TISD 101 shown in FIGS. 18D-18N may be formed on or over the front side of the polymer layer 92, and on the micro bumps or metal pillars 34 through wafer or panel processing, as shown in FIG. 20V. and on or over the front side of TPVS 158, whereby interconnect metal layer 99 and polymer layer 93 and polymer layer 104 are on or over the front side of polymer layer 92 and on microbumps or metal pillars 34 and on On or over the front side of TPVS 158, each interconnect metal layer 99 includes an adhesion layer (refer to photoresist layer 142 herein) and a seed layer (refer to circuit carrier or substrate 110 herein) that make up adhesion/seed layer 94, Each interconnect metal layer 99 includes a metal layer 98 on the attach/seed layer 94, and then metal pillars or bumps 122 as shown in FIGS. 18O-18R can be formed in the topmost polymer layer 104 with a plurality of openings 104a The topmost interconnection wire metal layer 99 of the bottom TISD101.

Next, as shown in FIG. 20W, the bottoms of the carrier substrate 90, the base insulating layer 91 and the polymer layer 97 are removed by mechanical polishing or CMP process to form the structure as shown in FIG. 20W so that the bottommost polymer layer 87 and In the plurality of openings 97a of the polymer layer 97, the metal plugs 77a of the plurality of interconnecting wire metal layers 77 at the bottom of the BISD 79 are exposed, wherein the metal plug 77a of the plurality of interconnecting wire metal layers 77 at the bottommost end of the BISD 79 has a copper layer exposed. Its back side 77e, alternatively, after grinding the polymer layer 92 in FIG. 20U and before forming the polymer layer 93 of the TISD 101, the carrier substrate 90, the base insulating layer 91 and the bottom of the polymer layer 97, is removed by a mechanical grinding or CMP process. Divide, so that the polymer layer 87 at the bottom of the BISD 79 and the metal plugs 77 a of the metal layers 77 at the bottom of the BISD 79 in the polymer layer 87 and the plurality of openings 97 a of the polymer layer 97 are exposed, wherein the bottom of the BISD 79 is a plurality of interconnect lines. The metal plug 77a of the metal layer 77 has a copper layer exposed on its backside 77e and is arranged as a plurality of metal pads in a matrix.

As shown in FIG. 20W, after removing the carrier substrate 90, the base insulating layer 91 and the bottom of the polymer layer 97, the package structure of FIG. 20W can be cut and separated into a plurality of individual chip packages ( That is, the single-level encapsulation logic driver 300) is shown in FIG. 20X.

Alternatively, after the step of FIG. 20W, a plurality of solder bumps 583 may be formed on the plurality of connection pads 77e of the BISD 79 in the package structure disclosed in FIG. 20W by screen printing or ball bonding, and then through the process as shown in FIG. The solder bumps 583 are formed in a reflow process of FIG. The material of the solder bumps 583 can be lead-free solder, which includes tin-containing alloy, copper metal, silver metal, bismuth metal, indium metal, zinc metal, antimony metal or other metals. For example, the lead-free solder can include tin-silver- Copper (SAC) solder, tin-silver solder, or tin-silver-copper-zinc solder, one of the solder bumps 583 may be used to connect or couple a semiconductor chip 100 of the single-level package logic driver 300 (as shown in FIG. 11A ). The dedicated I/O chip 265 in Figure 11N) is sequentially connected to a plurality of external circuits or components other than the single-level package logic driver 300 through one of the micro-bumps 54 of the interconnect metal layer 99 of the TISD101, each solder bump Block 583 has a height from the back surface of BISD79 between 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm Between, between 10µm and 30µm, or greater than, greater than or equal to 75µm, 50µm, 30µm, 20µm, 15µm, or 10µm, each solder bump 583 has the largest diameter in cross-section view (eg, the diameter of a circle or diagonal of a square or rectangle) e.g. between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, Between 10µm and 40µm, between 10µm and 30µm, or greater than or equal to 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the minimum space (gap) between the closest solder bumps 583 For example, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the maximum diameter of the cross-sectional view of the plurality of solder bumps (for example, the diameter of a circle or the diagonal of a square or rectangle), for example, between 5µm to 200µm, 5µm to 150µm, 5µm to 120µm, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, 10µm to 30µm , or greater than or equal to 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm, the minimum space (gap) between the nearest solder bumps is, for example, between 5µm and 150µm, between 5µm and 120µm between, 10µm to 100µm, 10µm to 60µm, 10µm to 40µm, or 10µm to 30µm between µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm or 10µm.

Next, the package structure shown in FIG. 20Y is cut and separated into a plurality of individual chip package structures (ie, the single-layer packaged logic driver 300 ) as shown in FIG. 20Z through a laser or mechanical dicing process.

Programmable TPVs, metal pads and multiple metal pillars or bumps

As shown in Figures 20X and 19L, a TPVS 158 can be programmed by one or more memory cells 379 within one or more DPIIC chips 410, wherein one or more memory cells 379 can be controlled as shown in Figures 3A-3C Fig. 9 and Fig. 9 turn on or off (or pass or fail) of one or more cross point switches 379 distributed in one or more DPIIC wafers 410 to form one of TPVS 158 through Fig. 11A through Fig. 11N Any of a plurality of commercial standard FPGA IC chips 200 , a plurality of dedicated I/O chips 265 , a plurality of DRAM chips 321 , a plurality of processing IC chips and a plurality of computing IC chips 269 , a dedicated control chip 260 , a dedicated control chip in the single-layer package logic driver 300 and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268 signal channel, through one of the on-chip interconnect lines 371 provided by TISD101 and/or BISD79 or a plurality of programmable interconnect lines 361, therefore, TPVS158 can be programmed.

In addition, as shown in FIGS. 20X and 19L, one of the metal pillars or bumps 122 may be programmed through one or more memory cells 379 in one or more DPIIC chips 410, wherein one or more memory cells 379 The unit 379 can control the opening or closing (or pass or fail) of one or more cross-point switches 379 distributed in one or more DPIIC chips 410 as shown in FIGS. 8A-8C and 9 to form a A metal pillar or bump 122 to any of a plurality of commercial standard FPGA IC chips 200, a plurality of dedicated I/O chips 265, a plurality of DRAM chips 321, a plurality of processing ICs within the single-level package logic driver 300 in Figures 11A to 11N Signal channels of chip and complex computing IC chip 269, dedicated control chip 260, dedicated control chip and dedicated I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268, through intra-chip interaction provided by TISD101 and/or BISD79 One of the connecting lines 371 or a plurality of programmable interconnecting connecting lines 361, so that the metal pillars or bumps 122 can be programmed.

As shown in FIG. 20X, a metal pad 77e can be programmed by one or more memory cells 379 within one or more DPIIC chips 410, wherein one or more memory cells 379 can be controlled as shown in FIGS. 8A-8C and the opening or closing (or pass or fail) of one or more cross-point switches 379 distributed in one or more DPIIC chips 410 in FIG. 9 to form a metal pad 77e from one of them to FIG. 11A to the first Any of a plurality of commercial standard FPGA IC chips 200, a plurality of special-purpose I/O chips 265, a plurality of DRAM chips 321, a plurality of processing IC chips and a plurality of computing IC chips 269, a special-purpose control chip 260, a special-purpose control chip 260, a plurality of special-purpose control chips The signal channel of the control chip and the dedicated I/O chip 266, the DCIAC chip 267 or the DCDI/OIAC chip 268, through one of the on-chip interconnection lines 371 provided by TISD101 and/or BISD79 or a plurality of programmable interconnection lines 361, Therefore, the metal pads 77e can be programmed.

Interconnect cables for logical drives with TISD and BISD

21B to 21G are schematic cross-sectional views of various interconnection nets in a single-level package logic driver according to an embodiment of the present invention.

As shown in FIG. 21D, the interconnect metal layer 99 of the TISD 101 can connect one or more metal posts or bumps 122 to one semiconductor chip 100 and connect the semiconductor chip 100 to another semiconductor chip 100. For the first case, The interconnecting wire metal layer 99 and interconnecting wire metal layer 77, BISD79 and TPVS158 of TISD101 can form a first interconnecting wire net 411 and connect a plurality of metal pillars or bumps 122 to each metal pillar or bump 122 or other a metal post or bump 122, and connect the plurality of semiconductor chips 100 to each semiconductor chip 100 or another one of the semiconductor chips 100, and connect the plurality of metal pads 77e to each metal pad 77e or another metal The pads 77e, the plurality of metal pillars or bumps 122, the semiconductor chips 100 and the metal pads 77e can be connected together via the first interconnection net 411, which can be a signal bus A bus is used to transmit multiple signals, or a power or ground plane or a bus is used to transmit power or ground power.

As shown in FIG. 21B, for the second case, the interconnection wire metal layer 99 of the TISD101 can form a second interconnection wire mesh 412 to connect a plurality of metal pillars or bumps 122 to each metal pillar or bump 122 or other a metal stud or bump 122, and a plurality of micro-metal studs or bumps 34 of a semiconductor chip 100 are connected to each micro-metal stud or bump 34 or another micro-metal stud or bump 34, the metal The pillars or bumps 122 and the micro-metal pillars or bumps 34 can be connected together via a second interconnecting wire net 412, which can be a signal bus for transmitting multiple signals, or Power or ground planes or bus bars are used to carry power or ground power.

As shown in FIGS. 21B and 21C , for the third case, the interconnecting wire metal layer 99 of the TISD 101 can form a third interconnecting wire mesh 413 to connect one of the metal posts or bumps 122 to one of the semiconductor chips 100 The micro-metal pillars or bumps 34 and the third interconnecting wire mesh 413 can be signal buses for transmitting multiple signals, or power or ground planes or bus bars for transmitting power or ground power.

As shown in FIG. 21C, for the fourth case, the interconnect metal layer 99 of the TISD 101 may form the fourth interconnect interconnect network 414 that is not connected to any metal post or bump 122 of the single-level package logic driver 300, but Connected to the plurality of semiconductor chips 100 to each semiconductor chip 100 or to another semiconductor chip 100, the fourth interconnection net 414 may be a programmable interconnection line 361 of the in-chip interconnection lines 371 for signal transmission.

As shown in FIG. 21F, for the fifth case, the interconnect metal layer 99 of the TISD 101 may form a fifth interconnect interconnect network 415 that is not connected to any metal post or bump 122 of the single-level package logic driver 300, but A plurality of micro-metal posts or bumps 34 of a semiconductor device 4 are connected to each micro-metal post or bump 34 or another micro-metal post or bump 34, and the fifth interconnecting wire net 415 may be a signal bus bar ( bus) or connecting lines are used to transmit multiple signals, or power or ground bus bars are used to transmit power or ground power.

As shown in Figures 21C, 21D, and 21F, the plurality of interconnect metal layers 77 of BISD 79 can be connected to the interconnect metal layers 99 of TISD 101 through TPVS 158, eg, each of the BISD 79 in a first group A metal pad 77e can be sequentially connected to a semiconductor chip 100 through a plurality of interconnection wire metal layers 77 of BISD79, one or a plurality of interconnection wire metal layers 99 of TPVS158 and TISD101. Interconnection net 416 is provided, and is provided by a seventh interconnection net 417 as shown in Fig. 21D, and is provided by an eighth interconnection net 418 or a ninth interconnection net 419 in Fig. 21F. In addition, one of the metal pads 77e in the first group is further sequentially connected to one or more metal pillars or bumps through the plurality of interconnecting wire metal layers 77 of BISD79, one or more interconnecting wire metal layers 99 of TPVS158 and TISD101 Block 122, the connection is provided by the first cross-connection net 411, the sixth cross-connection net 416, the seventh cross-connection net 417, and the eighth cross-connection net 418, or a plurality of numbers within the first group The metal pads 77e can be connected to one or other metal pads 77e through the plurality of interconnecting wire metal layers 77 and one or more metal pillars or bumps 122 of the BISD79, and are sequentially passed through the plurality of interconnecting wire metal layers 77, One or more TPVs 158 and TISD 101 are interconnected by interconnecting wire metal layers 99, wherein the plurality of metal pads 77e in the first group can be divided into one or more first subgroups under the backside of a semiconductor chip 100, and One or more second subgroups are under the backside of the other semiconductor chip 100, and the connection is provided by the first interconnection net 411 and the eighth interconnection net 418, or, one or more interconnected nets in the first group. The plurality of metal pads 77e are not connected to any of the metal pillars or bumps 122 of the single level package logic driver 300 , the connection being provided by the ninth interconnection net 419 .

As shown in FIGS. 21B, 21D, and 21E, each metal pad 77e of the BISD 79 in the second group may not be connected to any of the multiple interconnect metal layers 77 of the single-level package logic driver 300, but The plurality of interconnecting metal layers 77 of BISD79, one or more TPVs158, and the interconnecting metal layers 99 of TISD101 are sequentially connected to one or more metal pillars or bumps 122. This connection method is defined by a tenth interconnection in FIG. 21B. The connection line 420 is provided by the eleventh interconnection line 421 in FIG. 21D and the twelfth interconnection line 422 in FIG. 21E. Alternatively, the plurality of metal pads 77E of the BISD 79 in the second group may not be connected Any one of the semiconductor chips 100 in the single-layer package logic driver 300, but connected to one or other metal pads 77e through the plurality of interconnection wire metal layers 77 of BISD79, and sequentially through the plurality of interconnection wire metal layers 77 of BISD79, a The interconnecting wire metal layers 99 of or TPVs 158 and TISD 101 are connected to one or more metal pillars or bumps 122, wherein the plurality of metal pads 77e in the second group can be divided into a first subgroup on a semiconductor chip Below the backside of the semiconductor chip 100 and a second subgroup is below the backside of the other semiconductor chip 100, and this connection is provided by the twelfth interconnection line 422 in FIG. 21E.

As shown in FIG. 21G, a plurality of interconnecting wire metal layers 77 in the BISD 79 may include a power plane 77c and a ground plane 77d for power supply as shown in FIG. 20N, and FIG. 21H is a bottom view of FIG. 21G, showing the present invention The layout of the plurality of metal pads of the logic driver in the embodiment, as shown in FIG. 21H, the metal pads 77E can be laid out in a matrix pattern on the backside of the single-level package logic driver 300, and some metal pads 77E can be perpendicular to the semiconductor chip 100 Aligned, a first group of metal pads 77E are arranged in a matrix in the middle area of the back surface of the chip package (ie, the single-level package logic driver 300 ), and a second group of metal pads 77E are arranged in a matrix in the chip package ( That is, the peripheral area of the back surface of the single-level package logic driver 300) surrounds the middle area. More than 90% or 80% of the metal pads 77E in the first group can be used for power supply or ground reference, and more than 50% or 60% of the metal pads 77E in the second group can be used for signal transmission. The set of metal pads 77E may be arranged in one or more rings, such as 1, 2, 3, 4, 5, or 6 rings, along the edge of the chip package (ie, the single-level package logic driver 300), with the second group of The pitch of the set of metal pads 77E may be smaller than the pitch of the first set of metal pads 77E.

Alternatively, as shown in FIG. 21G, a plurality of interconnect metal layers 77 such as a BISD 79 at the bottom end may include a heat dissipation plane for heat dissipation and one or more TPVS 158 may be formed on the heat dissipation plane as heat dissipation metal plugs.

POP packaging for drives with TISD and BISD

FIGS. 22A to 22F are schematic diagrams of a manufacturing process of a POP package according to an embodiment of the present invention. As shown in FIG. 22A, when the upper single-level package logic driver 300 (as shown in FIG. 20X ) is assembled and bonded to the lower Single-level package logic driver 300 (shown in FIG. 20X ), the lower single-level package logic driver 300b has BISD 79 coupled to the upper single-level package logic driver 300 via metal posts or bumps 122 provided by the upper single-level package logic driver 300 . The TISD101 of the layer-packaged logic driver 300, the manufacturing process of the POP package is as follows:

First, as shown in FIG. 22A, the metal posts or bumps 122 of a plurality of lower single-level package logic drivers 300 (only one is shown in the figure) themselves are mounted and bonded to the plurality of metal contacts on the top of the circuit carrier or substrate 110. Pads 109, such as PCB substrates, BGA substrates, flexible circuit substrates (or thin films), or ceramic circuit substrates, underfill material 114 may fill the gaps between circuit carriers or substrates 110 and between the bottom of the single-level package logic driver 300. The gap, or alternatively, the step of filling the underfill material 114 can be skipped. Next, surface-mount technology (SMT) can be used to install and bond a plurality of upper single-level package logic drivers 300 (only one is shown in the figure) to the lower single-level package logic driver 300, respectively. Solder, solder paste or flux 112 may be first printed on the metal pads 77E of the BISD 79 of the underlying single level package logic driver 300 .

Next, as shown in FIGS. 22A to 22B , the metal pillars or bumps 122 of the single-layer package logic driver 300 itself are disposed on the solder, solder paste or flux 112 , and then, as shown in FIG. 22B , the A reflow or heating process is performed so that the metal pillars or bumps 122 of the upper single-level package logic driver 300 are fixedly bonded to the metal pads 77E of the BISD 79 of the lower single-level package logic driver 300 , and then, underfill material 114 may be filled in the gap between the upper single-level package logic driver 300 and the lower single-level package logic driver 300, or the step of filling the underfill material 114 may be skipped.

In a subsequent optional step, as shown in FIG. 22B, the metal studs or bumps 122 of the other multiple single-level package logic drivers 300 (as shown in FIG. 20X ) themselves may use surface-mount technology , SMT) bonding to the metal pads 77E of the BISD 79 in the single-level package logic driver 300 of one of the plurality of single-level package logic drivers 300 above, and then the underfill material 114 is optionally formed therebetween, this step may This is repeated several times to form a single-level packaged logic driver 300 stacked on a circuit carrier or substrate 110 in a three-layer version or more.

Next, as shown in FIG. 22B, a plurality of solder balls 325 are formed on the backside of the circuit carrier or substrate 110 by ball mounting, and then, as shown in FIG. 22C, the circuit carrier or substrate 110 is separated by laser cutting or mechanical cutting into A plurality of individual substrate units 113 (eg, PCB boards, BGA boards, flexible circuit substrates or films, or ceramic substrates), so that i number of single-level package logic drivers 300 can be stacked on a single substrate unit 113, where i number of More than or equal to 2, 3, 4, 5, 6, 7 or 8.

Alternatively, FIGS. 22D to 22F are schematic diagrams of a process for manufacturing a POP package according to an embodiment of the present invention. As shown in FIGS. 22D and 22E, one of the plurality of single-level package logic drivers 300 is single-level package logic driver 300 The metal pillars or bumps 122 themselves are fixed or mounted on the metal pads 77E of the BISD79 at the wafer or panel level using SMT technology, wherein the BISD79 at the wafer or panel level is shown in Figure 20W, wherein the wafer Or the BISD 79 at the panel level is the package structure before cutting and separating into a plurality of lower single-layer package logic drivers 300 .

Next, as shown in FIG. 22E, the underfill material 114 may be filled in the gap between the single-level package logic driver 300 above and the wafer or panel level packaging structure in FIG. 20W, or the underfill material 114 may be filled steps can be skipped.

In a subsequent optional step, as shown in FIG. 22E, the metal studs or bumps 122 of the other multiple single-level package logic drivers 300 (as shown in FIG. 20X ) themselves may use surface-mount technology , SMT) is attached to the metal pad 77E of the BISD 79 in one of the above single-level package logic drivers 300, and then the underfill material 114 is optionally formed therebetween. This step may This is repeated several times to form the single-level package logic driver 300 stacked on the wafer or panel level package structure in Figure 20W of the two-layer type or more.

Next, as shown in FIG. 22F, the TPVS 158 of the structure (type) of the wafer or panel (as shown in FIG. 20X ) is separated into a plurality of lower single-layer package logic drivers 300 by laser dicing or mechanical dicing, thereby, i number of single-level package logic drives 300 are stacked together, where i number is greater than or equal to 2, 3, 4, 5, 6, 7, or 8, and then the stacked single-level package logic drives 300 are stacked together. The metal pillars or bumps 122 of the bottom-most single-level package logic driver 300 of the layer-package logic driver 300 may be mounted on a plurality of metal pads 109 bonded to the circuit carrier or substrate 110 as shown in FIG. 22A, the circuit carrier or substrate 110 is, for example, a BGA substrate, then the underfill material 114 may be filled in the gap between the circuit carrier or substrate 110 and the bottommost single-level package logic driver 300, or the step of filling the circuit carrier or substrate 110 may be skipped and omitted . Next, a plurality of solder balls 325 may be mounted on the backside of the circuit carrier or substrate 110, and then the circuit carrier or substrate 110 may be separated into individual substrate units 113 (eg, by laser cutting or mechanical cutting) as shown in FIG. 22C. PCB boards, BGA boards, flexible circuit substrates or films, or ceramic substrates), so that i number of single-level package logic drivers 300 can be stacked on a single substrate unit 113, where i number is greater than or equal to 2, 3 1, 4, 5, 6, 7 or 8.

The single level package logic driver 300 with TPVS158 can be stacked vertically to form a standard type or standard size POP package. For example, the single level package logic driver 300 may be square or rectangular with a certain width, length and thickness, and a single level package logic driver 300 may be a The shape and size of the layer-packaged logic driver 300 has an industry standard. For example, when the standard shape of the single-layer-packaged logic driver 300 is a square, its width is greater than or equal to 4mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm with a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm, or 5mm, or, the standard form factor for single-package logic driver 300 is When rectangular, its width is greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and its length is greater than or equal to 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm , 30mm, 35mm, 40mm, 40mm or 50mm, and it has a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm.

Interconnect cable for complex drivers with TISD and BISD

FIGS. 22G to 22I are schematic cross-sectional views of various connection types of multiple logic drivers in a POP package according to an embodiment of the present invention. As shown in FIG. 22G , in the POP package, each single-layer package logic driver 300 includes one or more TPVS158 is used to stack and connect as first inter-drive interconnects 461 to other or another upper single-level package logical driver 300 and/or a lower single-level package logical driver 300, without being connected or coupled to any semiconductor die 100 within the POP package structure, the formation of each first internal drive interconnection line 461 in each single-level package logic driver 300, from bottom to top, respectively are (i) a metal pad 77e of BISD79; (ii) a stacked portion of a plurality of interconnect metal layers 77 of BISD79; (iii) a TPVs 158; (iv) a stacked portion of interconnect metal layers 99 of TISD100 ; and (v) a stack of a metal stud or bump 122 .

Alternatively, as shown in FIG. 22G, a second internal drive interconnection line 462 in the POP package can provide a similar function to the first internal drive interconnection line 461, but the second internal drive interconnection line 462 can interact through the TISD101. The wire metal layer 99 is connected or coupled to one or more semiconductor chips 100 itself.

Alternatively, as shown in FIG. 22H, each single-level package logic driver 300 provides a third inter-drive interconnect 463 similar to the second inter-drive interconnect 462, but the third inter-drive interconnect 463 is not stacked to the A metal pillar or bump 122, which is arranged vertically above the third internal drive interconnection line 463, connects each single-level package logic driver 300 and an upper single-level package logic driver 300 or is connected to each single-level package logic driver 300 After packaging the logic driver 300 and the circuit carrier or substrate 110, the third internal drive interconnection line 463 may be coupled to another or a plurality of metal pillars or bumps 122, which are not vertically arranged above the third internal drive interconnection line 463, But vertically above a semiconductor die 100 , connected to each single-level package logic driver 300 and an upper single-level package logic driver 300 or to each single-level package logic driver 300 and substrate unit 113 .

Alternatively, as shown in FIG. 22H, each single-level package logic driver 300 may provide a fourth internal drive interconnection line 464 composed of the following parts, respectively (i) one of the multiple interconnection line metal layers 77 of the BISD 79 itself a horizontal distribution part; (ii) a self-TPVs 158 coupled to one or a plurality of metal pads 77e of the first horizontal distribution part vertically positioned on one or more self-contained semiconductor chips 100; (iii) an interconnection line of the self-TISD 101 A second horizontal distribution portion of the metal layer 99 connects or couples a TPVs 158 to one or more of its own semiconductor chips 100 , and the second horizontal distribution portion of the fourth internal drive interconnection line 464 may be coupled to the metal pillars or bumps 122 , it is not vertically arranged above its own TPVs 158, but is vertically arranged above its own one or more semiconductor chips 100, connecting each single-level package logic driver 300 and an upper single-level package logic driver 300 or connecting each single-level package logic driver 300. The layer encapsulates the logic driver 300 and the substrate unit 113 .

Alternatively, as shown in FIG. 22I, each single-level package logic driver 300 may provide a fifth internal drive interconnection line 465, which is composed of: (i) a plurality of interconnection line metal layers 77 of its own BISD79 The first horizontal distribution portion; (ii) one or more metal pads 77e of which TPVs 158 are connected to the first horizontal distribution portion are vertically positioned below one or more semiconductor chips 100; (iii) one or more of the interconnecting metal layers 99 of the TISD101 itself A second horizontal distribution portion connects or couples itself with a TPVs 158 to one or more semiconductor chips 100, and the fifth internal drive interconnection line 465 itself may not be coupled to any one of the metal pillars or bumps 122, including bonding in each single-level package The metal studs or bumps 122 on the logic driver 300 and an overlying metal stud or bump 122 of the single-level package logic driver 300, or the metal studs or bumps 122 bonded to each single-level package logic driver 300 and Metal pillars or bumps 122 on the substrate unit 113 .

Second Embodiment for Chip Package Structure with BISDs and TPVs

FIGS. 28J and 28K are schematic diagrams of a process for a chip package structure with BISDs and TPVs according to the second embodiment of the present invention. As shown in FIG. 28J, after performing the CMP, grinding or polishing process in FIG. 28C, A backside interconnections chemical driveor device (BISD) 79 for a logical driver or device may be formed on the backside of the semiconductor wafer 100, on the upper surface of the polymer layer 92, and on top of each copper pillar 158. The BISD 79 may be formed on top of each copper pillar 158. Include one (or more) interconnect metal layers 27 (coupled to each copper pillar 158 ) and/or one (or more) polymer layers 42 between each two adjacent interconnect metal layers 27 , below the bottommost interconnection wire metal layer 27 or above the uppermost interconnection wire metal layer 27, wherein the upper interconnection wire metal layer 27 can be coupled via openings in the polymer layer 42 therebetween Connected to the underlying interconnect metal layer 27, the bottommost polymer layer 42 may be interposed between the bottom most interconnect metal layer 27 and the polymer layer 92, between the bottom most interconnect metal layer 27 and each Between the backsides of the semiconductor wafers 100, where each opening in the bottommost polymer layer 42 may be located above the top of each copper pillar 158, meaning the top of each copper pillar 158 may be located in the bottommost polymer At the bottom of each opening in material layer 42 , each interconnect metal layer 27 may extend horizontally across the boundary of each semiconductor wafer 100 .

As shown in Figure 28J, in BISD79, each polymer layer 42 may be polyimide, benzocyclobutene (BCB), parylene, epoxy based materials or compounds, photoepoxy SU- 8. Elastomer or silicone resin, the thickness of the polymer layer 93 is, for example, between 0.3 µm and 30 µm, between 0.5 µm and 20 µm, between 1 µm and 10 µm, between 0.5 µm and 5 µm. or thickness greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, each interconnecting wire metal layer 27 may have a plurality of metal wires or connecting wires, each metal wire or connecting wire Including: (1) a copper layer 40 having one (or more) low portions in the openings in the polymer layer 42, the thickness of which is between 0.3µm and 20µm, and the copper layer 40 having a high Partly above the polymer layer 42, which has a thickness between 0.3 µm and 20 µm, (2) an adhesive layer 28a (eg, a titanium layer or a titanium nitride layer having a thickness between 1 nm and 50 nm) is located on each on the bottom and sidewalls of the lower portion(s) of the copper layer(s) 40 of the metal line or connection line, and on the bottom of the top copper layer 40 of each line or connection line, and (3) a seed A layer 28b (eg, copper) is interposed between the copper layer 40 of each wire or connection and the adhesive layer 28a, wherein the sidewalls of the top copper layer 40 of each wire or connection are not covered by each wire or connection. Covered by the adhesive layer 28a, each interconnecting wire metal layer 27 has a plurality of metal wires or connecting wires, the thickness of which is, for example, between 0.3 μm and 30 μm, between 0.5 μm and 20 μm, and between 1 μm and 10 μm. between 0.5µm and 5µm, or thicknesses greater than 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm, and widths between 0.3µm and 30µm and 0.5µm Between 20µm, 1µm to 10µm or 0.5µm to 5µm, or widths greater than 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm or 5µm.

Next, a plurality of metal pads or bumps 583 with a thickness between 1 µm and 10 µm are formed on the topmost interconnection wire metal layer 27 of BISD79, and each metal pad or bump 583 is located on the topmost layer of BISD79 In the corresponding opening 42a in the polymer layer 42, each metal pad or bump 583 has several types, and the first type metal pad or bump 583 with a thickness between 1 μm and 10 μm may include: (1 ) an adhesive layer 26a (eg, a titanium or titanium nitride layer) having a thickness between 1 nm and 50 nm is formed on the topmost interconnecting wire metal layer 27 of the BISD79, (2) a sub-layer 26b (eg, copper) Formed on the adhesive layer 26a, and (3) a copper layer 32 having a thickness between 1 µm and 10 µm is formed on the seed layer 26b. Alternatively, the second-type metal pads or bumps 583 may include the adhesive layer 26a, the seed layer 26b and the copper layer 32 disclosed above, and may further include a tin-containing solder layer (from tin or tin-silver alloy) on copper layer 32.

Next, the steps in FIGS. 28E to 28G may be performed to form a plurality of chip package structures as shown in FIG. 28K. In each chip package structure 550, each copper pillar 158 may serve as a package via Via (throughpackage via (TPV)), ie, polymer perforated via, provided as a vertical connection between the interconnecting wire metal layer 27 of TISD or FISD101 and the interconnecting wire metal layer 27 of BISD79, the interconnecting wire metal layer of TISD or FISD101 27. Copper pillar 158 and interconnect metal layer 27 of BISD 79 can be constructed as programmable interconnect 361 and fixed interconnect such as inter-die interconnect 371 in standard commercial logic driver 300 in FIGS. 11A to 11N Connection line 364.

Immersive IC Interactive Connectivity Environment (IIIE)

As shown in FIGS. 22G to 22I, the single-level package logic drivers 300 can be stacked to form a super-rich interconnect structure or environment, wherein their semiconductor chip 100 represents a commercial standard FPGA IC chip 200 with logic blocks and The commercial standard FPGAIC chip 200 of the complex crosspoint switch 379 is provided by Figures 8A to 8J, immersed in a super rich interactive wire structure or environment, that is, the programming 3D immersive IC interactive wire environment (IIIE), for A commercial standard FPGAIC chip 200 in which the logic driver 300 is single-layered, includes the following components for constructing a 3D interconnect structure or system: (1) a plurality of interconnect wires for the FISC 20 of the commercial standard FPGA IC chip 200 Layer 6, Interconnect metal layer 27 of SISC 29 of a commercial standard FPGAIC chip 200, Micro metal pillars or bumps 34 of a commercial standard FPGA IC chip 200, Interconnect metal of TISD 101 of a single-level package logic driver 300 Layer 99 and metal studs or bumps 122 between a single-level package logic driver 300 and the overlying single-level package logic driver 300 over the logic block and a plurality of crosspoint switches 379 of a commercial standard FPGAIC chip 200; ( 2) The logic of the plurality of cross-connect line metal layers 77 of the BISD 79 of a single-level package logic driver 300 and the metal pads 77e of the BISD 79 of a single-level package logic driver 300 of a plurality of cross-point switches 379 of a commercial standard FPGAIC chip 200 below the block; and (3) TPVs 158 of a single-level package logic driver 300 surround a plurality of cross-point switches 379 and logic blocks on a commercial standard FPGAIC chip 200, the programmable 3DIIIE provides a super-rich interconnect structure or The environment includes micro metal pillars or bumps 34 , SISC 29 and FISC 20 of each semiconductor chip 100 , TISD 101 , BISD 79 and TPVs 158 of each single level package logic driver 300 and metal pillars or between each two single level package logic drivers 300 The bumps 122, the horizontal interconnect structure or system can be programmed by the plurality of cross point switches 379 of each commercial standard commercial standard FPGAIC die 200 and the plurality of DPIIC die 410 of each single level package logic driver 300, in addition, The interconnect structure or system in the vertical direction can be programmed by a plurality of DPIIC chips 410 for each commercial standard commercial standard FPGAIC die 200 and each single level package logic driver 300 .

23A to 23B are conceptual diagrams of the interconnection lines between the plurality of logic blocks simulated from the human nervous system according to the embodiment of the present invention. For the same component numbers in Figures 23A and 23B as those in the above figures, please refer to the descriptions and specifications in the above figures. As shown in Figure 23A, the programmable 3DIIIE is similar to or similar to the human brain, as shown in Figure 23A. The logical blocks in Figure 6A are similar or similar to neurons or nerve cells, the plurality of interconnecting wire metal layers 6 of FISC 20 and/or the interconnecting wire metal layers 27 of SISC 29 are related or similar to a tree connecting neurons or nerve cells Dendrites 201, micro metal pillars or bumps 34 of a commercial standard commercial standard FPGAIC chip 200 for input of a logic block in a standard commercial standard FPGAIC chip 200 are connected to a commercial standard The small complex receivers 375 of the complex small I/O circuits 203 of the FPGAIC die 200 are similar or similar to postsynaptic cells at the ends of the dendrites. For a short distance between two logic blocks in a commercial standard FPGAIC chip 200, the interconnection metal layer 6 of the FISC 20 and the interconnection metal layer 27 of the SISC 29 can construct an interconnection 482, as in An axonal connection of one neuron or nerve cell 201 to another neuron or nerve cell 201, for long distances between two of the commercial standard FPGAIC chips 200, the interaction of the TISD101 of its single-layer packaged logic driver 300 The connection wire metal layer 99, the multiple interconnection wire metal layer 77 of the BISD 79 of the single-level package logic driver 300, and the TPVS 158 of the single-level package logic driver 300 can be constructed as one neuron or nerve cell 201 connected to another neuron or nerve cell Axon-like interconnects 482 of 201, a micro-metal post or bump 34 of a first commercial standard FPGAIC chip 200 connected to axon-like interconnects 482 can be programmed to connect to a second commercial standard FPGAIC The miniature drivers 374 of the plurality of miniature I/O circuits 203 of the wafer 200 are similar or similar to the presynaptic cells at the ends of the axons 482 .

To illustrate in more detail, as shown in FIG. 23A, a first 200-1 of a commercial standard FPGAIC chip 200 includes first and second LB1 and LB2 logic blocks like neurons, FISC 20 and SISC 29 like dendrites 481 coupled to the first and second LB1 and LB2 of the logic block and complex crosspoint switches 379 to program the first and second LB1 and LB2 of the logic block connected to the FISC20 and SISC29 for itself, commercialized A second 200-2 of standard FPGA IC chip 200 may include third and fourth LB3 and LB4 of logic block 210 like neurons, FISC 20 and SISC 29 like dendrites 481 coupled to the third and fourth logic block 210 The fourth LB3 and LB4 and the complex crosspoint switches 379 are programmed for the third and fourth LB3 and LB4 of the FISC 20 and SISC 29 connected to the logic block 210, a first 300-1 of the single level package logic driver 300 The first and second 200-1 and 200-2 of the commercial standard FPGAIC chip 200 can be included, and a third 200-3 of the commercial standard FPGAIC chip 200 can include a fifth LB5 of logic blocks like neurons , FISC20 and SISC29 like dendrites 481 are coupled to the fifth LB5 of the logic block and themselves plural crosspoint switches 379 can be programmed for their own FISC20 and SISC29 connected to the fifth LB5 of the logic block, commercial standard FPGAIC chip A fourth 200-4 of 200 may include a sixth LB6 of logic blocks like neurons, FISC 20 and SISC 29 coupled to logic blocks like dendrites 481 and a sixth LB6 of complex crosspoint switches 379 programmed for itself The sixth LB6 of the FISC 20 and SISC 29 connected to the logic block, a second 300-2 of the single-level package logic driver 300 may include the third and fourth 200-3 and 200-4 of the commercial standard FPGAIC chip 200, ( 1) Extending a first part from the logic block LB1 by a plurality of interconnecting wire metal layers 6 and interconnecting wire metal layers 27 of FISC20 and SISC29; (2) extending a micro bump or metal post 34 from the first part; (3) Extending from a micro bump or metal post 34, a second portion is provided by interconnect metal layer 99 and/or interconnect metal layer 77 of TISD 101, and/or a first portion of single-level package logic driver 300 BISD79 of 300-1; (4) extending from another micro-bump or metal post 34 of the second part; (5) a plurality of interconnecting wire metal layers 6 and interconnecting wire metal layers 27 provided by FISC20 and SISC29. The third part, extending from another micro bump or metal pillar 34 to the logic block LB2 can form an axon-like interconnecting line 482 , and the axon-like interconnecting line 482 can be arranged on the axon-like interconnecting line 482 according to the The complex pass/fail switch programming of the first 258-1 to the fifth 258-5 of the complex crosspoint switch 379 connects the first LB1 of the logic block 201 to the second LB2 to the sixth of the logic block 258 LB6, the first 258-1 of the plurality of pass/fail switches 258 can be arranged on the first 200-1 of the commercial standard FPGAIC die 200, the second 258-2 and the third of the plurality of pass/fail switches 258 258-3 may be arranged within a plurality of DPIIC die 410 of the first 300-1 of the single level package logic driver 300, and the fourth 258-4 of the plurality of pass/fail switches 258 may be arranged within a commercial standard FPGAIC die 200 In the third 200-3 of the plurality of pass/fail switches 258, the fifth 258-5 of the plurality of pass/fail switches 258 may be arranged in a plurality of DPIIC die 410 in the second 300-2 of the single-level package logic driver 300, a single layer The first 300-1 of packaged logic drivers 300 may have metal pads 77E coupled to the second 300-2 of single-level packaged logic drivers 300 through metal posts or bumps 122, or, a plurality of pass/no pass switches 258 The first 258-1 to the fifth 258-5 set on the axon-like interconnecting line 482 can be omitted, or the plural pass/no-pass switches 258 set on the dendritic-like interconnecting line 481 can be omitted.

In addition, as shown in Figure 23B, the axon-like interconnection line 482 can be identified as a tree-like structure comprising: (i) the trunk or stem connecting the first LB1 of the logical block; (ii) the trunk or stem from the The plural branches of the branches are used to connect their own trunk or stem to a second LB2 and a sixth LB6 of the logic block; (iii) the first 379-1 of the plural cross-point switches 379 is located in the trunk or stem and Each branch of itself is used to switch the connection between its own trunk or stem and its own branch; (iv) a plurality of branches branched from an own branch is used to connect an own branch to logic the fifth LB5 and sixth LB6 of the block; and (v) a second 379-2 of the complex crosspoint switches 379 located between an own branch and each own sub-branch for To switch connections between an own branch and an own sub-branch, the first 379-1 of the plurality of crosspoint switches 379 is provided in the plurality of DPIICs within the first 300-1 of a single-level package logic driver 300 Die 410, and the second 379-2 of the plurality of cross-point switches 379 may be disposed in the plurality of DPIIC die 410 in the second 300-2 of the single-level package logic driver 300, and each type of dendritic interconnection line 481 may include : (i) a trunk is connected to one of the first LB1 to the sixth LB6 of the logic block; (ii) a plurality of branches branching off from the trunk; (iii) the photoresist layer 9601 is provided on the trunk and itself Each branch is used to switch the connection between its own trunk and its own branch, and each logic block can be coupled to a plurality of dendritic interconnection lines 481 to form a plurality of interconnection lines metal layer 6 and SISC29 of FISC20 In the interconnect metal layer 27, each logic block may be coupled to the distal end of one or more axon-like interconnect lines 482, extending from other logic blocks, through dendritic-like interconnect lines 481 Extends from each logical block.

Combination of POP packages for logical drives and memory drives

As described above, the single level package logic driver 300 may be packaged with the semiconductor chip 100 as shown in FIGS. 11A to 11N , and a plurality of single level package logic drivers 300 may be incorporated into a mold with one or more memory drivers 310 In the group, the memory driver 310 can be suitable for storing data or applications, and the memory driver 310 can be separated into two types (as shown in Figures 24A to 24K), one is the non-volatile memory driver 322 and the other is the non-volatile memory driver 322. The volatile memory driver 323 is shown in FIG. 24A to FIG. 24K. FIG. 24A to FIG. 24K are schematic diagrams of plural combinations of POP packages for the logic input driver and the memory driver according to the embodiment of the present invention. For the structure and process of the memory driver 310, please refer to FIG. 14A In the description to FIG. 22I, the structure and process of the memory driver 310 are the same as the description and specifications of FIG. 14A to FIG. 22I, but the semiconductor chip 100 is a non-volatile memory chip for the non-volatile memory driver 322; And the semiconductor chip 100 is a volatile memory chip for the non-volatile memory driver 323 .

As shown in Fig. 24A, the POP package can be stacked only with the single-level package logic driver 300 on the substrate unit 113 as shown in Figs. The block 122 is mounted on the metal pads 77E of the single-level package logic drive 300 below its backside, but the metal studs or bumps 122 of the lowermost single-level package logic drive 300 are mounted on the metal pads or bumps 122 bonded on its substrate unit 113. on the metal pad 109 .

As shown in FIG. 24B, the POP package can be stacked only with the single-level packaged non-volatile memory driver 322 on the substrate unit 113 made as shown in FIGS. 14A-22I, an upper single-level packaged non-volatile memory driver 322 The metal studs or bumps 122 of the bulk driver 322 are mounted and bonded to the metal pads 77E of the single-level package non-volatile memory driver 322 below its backside, but the lowermost single-level package non-volatile memory driver 322 has a metal pad 77E. The metal pillars or bumps 122 are mounted on the metal pads 109 on the substrate unit 113 thereof.

As shown in FIG. 24C, the POP package can be stacked only with the single-level packaged volatile memory driver 323 on the substrate unit 113 made as shown in FIGS. 14A to 22I, an upper single-level packaged volatile memory driver The metal studs or bumps 122 of 323 are mounted on the metal pads 77E of the single-level package volatile memory driver 323 under its backside, but the metal studs or bumps of the lowermost single-level package volatile memory driver 323 Block 122 is mounted on metal pads 109 on top of its base unit 113 .

As shown in FIG. 24D, the POP package can stack a group of single-level package logic drivers 300 and a group of single-level package volatile memory drivers 323 made as shown in FIGS. 14A to 22I. The group of drivers 300 may be arranged above the substrate unit 113 and below the group of single-level package volatile memory drivers 323 , eg, two single-level package logic drivers 300 in the group may be arranged above the substrate unit 113 And below the two single-level packaged volatile memory drivers 323 of the group, the metal pillars or bumps 122 of a first single-level packaged logic driver 300 are mounted and bonded to the upper side (surface) of the substrate unit 113. Metal pads 109, a metal stud or bump 122 of the second single-level package logic driver 300 are mounted on the backside (underside) of the metal pad 77E of the first single-level package logic driver 300, a first The metal studs or bumps 122 of a single-level package volatile memory driver 323 are mounted on the metal pads 77E of a second single-level package logic driver 300 on its backside, and a second single-level package volatile memory driver 323 The metal studs or bumps 122 of the memory driver 323 can be mounted on the metal pads 77E of the first single-level package volatile memory driver 323 on the backside thereof.

As shown in FIG. 24E, POP packages may be stacked alternately with single-level package logic drivers 300 and single-level packaged volatile memory drivers 323 made as shown in FIGS. 14A-22I, eg, a first single-level package The metal studs or bumps 122 of the packaged logic driver 300 can be mounted on the metal pads 109 of the substrate unit 113 on the upper side (face) thereof, and the metal studs or bumps of the first single-layer packaged volatile memory driver 323 The block 122 is mounted on the metal pads 77E of the first single-level package logic drive 300 on its backside, and the metal studs or bumps 122 of a second single-level package logic drive 300 are mounted on the metal pads 77E on its backside. On the metal pads 77E of a single-level package volatile memory driver 323, and a second metal stud or bump 122 of the single-level package volatile memory driver 323 can be mounted on the backside of a second On the metal pad 77E of the single-level package logic driver 300 .

As shown in FIG. 24F, the POP package can stack a group of single-level package non-volatile memory drivers 322 and a group of single-level package volatile memory drivers 323 fabricated as shown in FIGS. 14A to 22I. A group of single-level package volatile memory drivers 323 may be arranged above the substrate unit 113 and below the group of single-level package non-volatile memory drivers 322, eg, two single-level package volatile memory drivers in the group The bulk driver 323 can be arranged above the substrate unit 113 and below the two single-level packaged non-volatile memory drivers 322 of the group, a metal stud or bump of the first single-level packaged volatile memory driver 323 Block 122 is fitted with metal pads 109 bonded to its upper (face) substrate unit 113, and a second metal stud or bump 122 of a single-level package volatile memory driver 323 is fitted with a first bonded on its backside On the metal pads 77E of the single-level package volatile memory driver 323, the metal studs or bumps 122 of a first single-level package non-volatile memory driver 322 are mounted on the backside of the second single-level package On the metal pads 77E of the volatile memory driver 323, and the metal pillars or bumps 122 of a second single-level packaging non-volatile memory driver 322 are mounted on the backside of the first single-level packaging non-volatile on metal pad 77E of the memory driver 322.

As shown in FIG. 24G, the POP package can stack a group of single-level package non-volatile memory drivers 322 and a group of single-level package volatile memory drivers 323 fabricated as shown in FIGS. 14A to 22I. The group of single-level package non-volatile memory drivers 322 can be arranged above the substrate unit 113 and below the group of single-level package volatile memory drivers 323, eg, two single-level package non-volatile memory drivers in the group The memory drivers 322 may be arranged above the substrate unit 113 and below the two single-level packaged volatile memory drivers 323 of the group, a metal pillar of the first single-level packaged non-volatile memory driver 322 or The bumps 122 are mounted on the metal pads 109 of the upper (surface) substrate unit 113, and the metal posts or bumps 122 of a second single-level packaged non-volatile memory driver 322 are mounted on the backside (bottom). side) the metal pads 77E of the first single-level package non-volatile memory driver 322, the metal studs or bumps 122 of the first single-level package volatile memory driver 323 are mounted on the backside of the second On the metal pads 77E of a single-level packaged non-volatile memory driver 322, and a second single-level packaged volatile memory driver 323 metal studs or bumps 122 can be mounted on the backside of the first one On the metal pad 77E of the single-level package volatile memory driver 323 .

As shown in FIG. 24H, POP packages may be stacked alternately with single-level packaged non-volatile memory drivers 322 and single-level packaged volatile memory drivers 323 made as shown in FIGS. 14A-22I, eg, a first The metal studs or bumps 122 of a single-level package volatile memory driver 323 can be mounted on the metal pads 109 of the substrate unit 113 on the upper side (face) thereof, and a first single-level package non-volatile memory The metal studs or bumps 122 of the bulk driver 322 are mounted on the metal pads 77E of the first single-level package volatile memory driver 323 on its backside, and a second single-level package volatile memory driver The metal pillars or bumps 122 can be mounted on the metal pads 77E of the second single-level package volatile memory driver 323 on its backside, a metal pillar of the second single-level package volatile memory driver 323 or The bumps 122 can be mounted on the metal pads 77E of the first single-level package non-volatile memory driver 322 on its backside, and the metal pillars of a second single-level package non-volatile memory driver 322 or The bumps 122 can be mounted on the metal pads 77E of the second single-level package volatile memory driver 323 on the backside thereof.

As shown in FIG. 24I, the POP package can stack a group of single-level package logic drivers 300, a group of single-level package non-volatile memory drivers 322, and a group of single-level packaged logic drivers 322 as shown in FIGS. 14A to 22I. Layer-encapsulated volatile memory drivers 323, the group of single-level encapsulation logic drivers 300 may be arranged above the substrate unit 113 and below the group of single-level encapsulation volatile memory drivers 323, and the single-level encapsulation volatile memory The group of drivers 323 can be arranged above the single-level package logic driver 300 and below the group of single-level package non-volatile memory drivers 322, eg, two single-level package logic drivers 300 in the group can be arranged on the substrate Above the cell 113 and below the two single-level package volatile memory drivers 323 of the group, the two single-level package volatile memory drivers 323 in the group may be arranged on the side of the single-level package logic driver 300 Above and below the two single-level packaged non-volatile memory drivers 322 of the group, the metal pillars or bumps 122 of a first single-level packaged logic driver 300 are mounted and bonded to its upper (face) substrate unit Metal pads 109 of 113, metal studs or bumps 122 of a second single-level package logic driver 300 are mounted on the backside (underside) of the metal pads 77E of the first COIP single-level package logic driver 300, The metal studs or bumps 122 of a first single-level package volatile memory driver 323 are mounted on the metal pads 77E of the second single-level package logic driver 300 on its backside, a second single-level package The metal studs or bumps 122 of the volatile memory driver 323 can be installed and bonded to the metal pads 77E of the first single-level packaged volatile memory driver 323 on its backside, a first single-level packaged non-volatile memory driver 323 The metal studs or bumps 122 of the memory driver 322 are mounted on the metal pads 77E of the second single-level package volatile memory driver 323 on its backside, and a second single-level package non-volatile memory The metal studs or bumps 122 of the driver 322 can be mounted and bonded to the metal pads 77E of the first single-level package non-volatile memory driver 322 on its backside.

As shown in FIG. 24J, the POP package can be alternated with the single-level package logic driver 300, the single-level package non-volatile memory driver 322, and the single-level package volatile memory driver 323 made as shown in FIGS. 14A-22I For example, the metal pillars or bumps 122 of a first single-level package logic driver 300 may be mounted on the metal pads 109 of the substrate unit 113 bonded to the upper side (surface) thereof, a first single-level package The metal studs or bumps 122 of the volatile memory driver 323 can be mounted and bonded to the metal pads 77E of the first single-level package logic driver 300 on the back (side) of the first single-level package logic driver 300, a first single-level package non-volatile The metal studs or bumps 122 of the memory driver 322 are mounted and bonded to the metal pads 77E of the first single-level package volatile memory driver 323 on its backside, a metal pillar of the second single-level package logic driver 300 Alternatively, the bumps 122 can be mounted on the metal pads 77E of the first single-level package non-volatile memory driver 322 on its backside, a metal stud or bump of the second single-level package volatile memory driver 323 The block 122 can be mounted on the metal pads 77E of a second single-level package logic driver 300 on its backside, and the metal studs or bumps 122 of a second single-level package non-volatile memory driver 322 can be mounted The metal pads 77E of the second single-level package volatile memory driver 323 on its backside are provided.

In each POP package structure as shown in FIGS. 24I and 24J, each single-level package non-volatile memory driver 322 may be packaged with one (or more) NVMIC chips 250 configured to store the resulting values and/or programming codes, the result values and/or programming codes are in a non-volatile manner to the programmable logic blocks 201 of each standard commercial FPGAIC chip 200 in each standard commercial logic driver 300, and/or Program the pass/fail switch 258 and/or the crosspoint switch 379, and to program the pass/fail switch 258 and/or the crosspoint switch 379 on each DPIIC die 410 of each standard commercial logic driver 300 , when each POP package structure is powered up, (1) the resulting values stored in one (or more) NVMIC chips 250 in each single-level package non-volatile memory driver 322 can be loaded into each standard In the memory cells 490 of each standard commercial FPGAIC chip 200 of the commercial logic driver 300 to be stored therein for programming the programmable logic of each standard commercial FPGAIC chip 200 in each standard commercial logic driver 300 The logic blocks 201, (2) the programming code stored in the one (or more) NVMIC chips 250 of each single-level package non-volatile memory driver 322 can be loaded into each of the standard commercial logic drivers 300. in the memory cells 362 of the standard commercial FPGAIC chips 200 to be stored therein and used to program the pass/fail switches 258 and/or intersections of each standard commercial FPGA IC chip 200 in each standard commercial logic driver 300 Switch 379, and (3) the programming code stored in one (or more) NVMIC chips 250 of each single-level package non-volatile memory driver 322 can be loaded into each DPIIC of each standard commercial logic driver 300 In the memory cell 362 of the die 410 for storage therein and for programming the pass/fail switch 258 and/or the crosspoint switch 379 of each DPIIC die 410 in each standard commercial logic driver 300.

As shown in Fig. 24K, the POP package can be stacked into three stacks, one stack with only the single-level package logic driver 300 on the substrate unit 113 as shown in Figs. 14A to 22I, and the other stack with only the single-level package The non-volatile memory driver 322 is on the substrate unit 113 made as shown in Figs. 14A to 22I, and the other one stacked only the single-level package of the volatile memory driver 323 is made as shown in Figs. 14A to 22I On the substrate unit 113, the process of this structure is formed on a circuit carrier or a substrate in three stacked structures of the single-level package logic driver 300, the single-level package non-volatile memory driver 322 and the single-level package volatile memory driver 323, such as For the component 110 in Figure 22A, solder balls 325 are mounted on the back of the circuit carrier or substrate, and then the circuit carrier or substrate 110 is cut into a plurality of individual substrate units 113 by laser cutting or mechanical cutting. The circuit carrier or substrate is, for example, a PCB substrate or a BGA substrate.

FIG. 24L is a top view of a plurality of POP packages according to an embodiment of the present invention, and FIG. 24K is a schematic cross-sectional view along the cutting line A-A. In addition, the plurality of I/O ports 305 can be installed and connected to one or more USB plugs, high-definition-multimedia-interface (HDMI) plugs, audio plugs, Internet plugs, power plugs, and and/or on the base unit 113 of the Video Graphics Array (VGA) plug inserted therein.

Application of logical drives

By using a commercial standard logic driver 300, an existing system design, manufacturing and/or product industry can be changed into a commercial system/product industry, such as the current commercial DRAM, or flash memory industry, a The system, computer, smart phone, or electronic device or device can be turned into a commercial standard hardware including a main memory driver 310 and a single-level package logic driver 300. FIGS. 25A to 25C are logic operations in an embodiment of the present invention. and schematic diagrams of various applications of memory drives. As shown in FIGS. 25A to 25C, the single-level package logic driver 300 has a large enough number of input/output (I/O) to support (support) the input/output ports for programming all or most applications/purposes 305. The I/Os of the single-level package logic driver 300 (provided by the metal pillars or bumps 122 ) support the I/O ports required for programming, eg, performing artificial intelligence (AI), machine learning, deep learning, Big data database storage or analysis, Internet of Things (IOT), virtual reality (VR), augmented reality (AR), automotive electronic graphics processing (CarGP), digital signal processing, microcontrollers and/or ) functions of a central processing (CP) or any combination of functions. Single-level package logic driver 300 may be suitable for (1) programming or configuration I/O for software or application developers to download application software or code stored in memory driver 310, connected through a plurality of I/O ports 305 or connectors or coupled to the complex I/Os of the single-level package logic driver 300, and (2) performing the complex I/Os connected or coupled to the complex I/Os of the single-level package logic driver 300 through the complex I/Os port 305 or connector /Os, executes the user's instruction, such as generating a Microsoft word file, or a powerpoint presentation file or an excel file, the plurality of I/Os ports 305 or connectors are connected or coupled to the plurality of corresponding single-level package logical drivers 300 I/Os, which may include one or more (2, 3, 4 or more) USB connections, one or more IEEE1394 connections, one or more Ethernet connections, one or more HDMI connections, one or more VGA connector, one or more power supply connectors, one or more audio source connectors or serial connectors such as RS-232 or communication (COM) connectors, wireless transceiver I/Os connectors and/or Bluetooth transceivers I/O connections, etc., a plurality of I/Os connection ports 305 or connectors can be arranged, placed, assembled or connected on a substrate, a flexible board or a motherboard, such as a PCB board, with an interconnecting wire structure (as shown in Figure 18W). (shown) silicon substrates, metal substrates with interconnected line structures, glass substrates with interconnected line structures, ceramic substrates with interconnected line structures, or flexible substrates or films with interconnected line structures. The single level package logic driver 300 may be assembled on a substrate, flex board or motherboard using its own metal post or bump 122 mounting bonding, flip chip packaging similar to chip packaging technology or COF packaging technology used in LCD driver packaging technology.

FIG. 25A is a schematic diagram of an application of an embodiment of the present invention for a logic driver or an FPGA IC module. As shown in FIG. 25A, a desktop or laptop computer, a mobile phone or a smart phone, or an AI robot 330 may include The programmable single-level packaging logic driver 300 includes a plurality of processors, such as a base frequency processor 301, an application processor 302, and other processors 303, wherein the application processor 302 may include a CPU, a A graphics processing unit (GPU), and other processors 303 may include a radio frequency (RF) processor, a wireless connection processor, and/or a liquid crystal display (LCD) control module. The single-level package logic driver 300 may further include the function of power management 304 to obtain the minimum available power demand power for each processor (301, 302 and 303) through software control. Each I/O port 305 can connect the metal pillars or groups of bumps 122 of the single-level package logic driver 300 to various external devices. For example, the I/O ports 305 can include I/O port 1 to connect to The wireless signal communication element 306 of the computer, mobile phone or robot 330, such as a global positioning system (GPS) element, a wireless-local-area-network (WLAN) element, Bluetooth devices or radio frequency (RF) devices, these I/O ports 305 include I/O port 2 to connect to various display devices 307 of computers or mobile phones or robots 330, such as LCD display devices or organic light emitting two Polar body display device, these I/O ports 305 include I/O port 3 to connect to a computer or camera 308 of a mobile phone or robot 330, these I/O ports 305 may include I/O port 4 to Connected to an audio setup 309 of a computer or mobile phone or robot 330, such as a microphone or a microphone, these I/O ports 305 or connectors are connected or coupled to logical drives. The corresponding plurality of I/Os may include I/O O port 5, such as a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) connector or an external link (Peripheral Components Interconnect express, PCIe) connector for memory drives, for connecting with a computer or a memory drive of a mobile phone or robot 330 , disk or device 310 communication, wherein the disk or device 310 includes hard disk drives, flash memory drives and/or solid state hard drives, these I/O ports 305 may include I/O port 6 to connect To the keyboard 311 of the computer or mobile phone or robot 330 , these I/O ports 305 may include I/O port 7 for connecting to the Ethernet network 312 of the computer or mobile phone or robot 330 .

Alternatively, FIG. 25B is a schematic diagram of an application of a logic driver or an FPGAIC module according to an embodiment of the present invention. The structure of FIG. 25B is similar to the structure of FIG. 25A, but the difference is that the computer or mobile phone or robot 330 has more A power management chip 313 is provided instead of the outside of the single-level package logic driver 300, wherein the power management chip 313 is suitable for each single-level package logic driver 300, wireless communication element 306, display device 307, camera via software control. 308, audio device 309, memory drive, disk or device 310, keyboard 311, and ethernet 312, placed (or set) in the lowest power demand state available.

Alternatively, FIG. 25C is a schematic diagram of the application of a logic driver or an FPGAIC module according to an embodiment of the present invention. As shown in FIG. 25C, a desktop or laptop computer, a mobile phone or a smart phone, or an AI robot 311 is in another Embodiments may include a plurality of single-level package logic drivers 300 that can be programmed as a plurality of processors, for example, a first single-level package logic driver 300 (ie, the one on the left) can be programmed as a base. Frequency processor 301, a second single-level package logical driver 300 (that is, the one on the right) can be programmed as an application processor 302, which includes 2 can include a CPU, a souther, a norther, and a graphics processing unit (GPU), The first single-level package logic driver 300 further includes a power management 304 function to enable the baseband processor 301 to obtain the lowest available power demand power through software control. The second single level package logical driver 300 includes a power management 304 function to enable the application processor 302 to obtain the lowest available power demand power via software control. The first and second single-level packaged logical drivers 300 further include various I/O ports 305 for connecting various devices in various connection methods/devices. The I/O port 1 on the package logic driver 300 is connected to the wireless signal communication element 306 of the computer or the mobile phone or the robot 330, such as a global positioning system (GPS) element, a wireless local area network wireless-local-area-network (WLAN) components, Bluetooth components, or radio frequency (RF) devices, these I/O ports 305 include I/O connections provided on the second single-level package logic driver 300 Port 2 is used to connect to various display devices 307 of computers or mobile phones or robots 330, such as LCD display devices or organic light-emitting diode display devices, these I/O ports 305 include logic provided in the second single-layer package I/O port 3 on the driver 300 to connect to a computer or camera 308 of a cell phone or robot 330, these I/O ports 305 may include I/O provided on a second single level package logical driver 300 Port 4 to connect to audio equipment 309 of a computer or, mobile phone or robot 330, such as a microphone or a sounder The /O port 5 is used to connect with the memory drive, disk or device 310 of a computer or mobile phone or robot 330, wherein the disk or device 310 includes a disk or solid state disk drive (SSD), these I/O O port 305 may include I/O port 6 provided on the second LLP logical driver 300 to connect to keyboard 311 of a computer or, cell phone or robot 330, these I/O ports 305 may contain settings I/O port 7 on the second LLP logical driver 300 for connection to the Ethernet 312 of the computer or, cell phone or robot 330. Each of the first and second single-level package logical drives 300 may have dedicated I/O ports 314 for data transfer between the first and second single-level package logical drives 300, computer or mobile phone or The robot 330 is further provided with a power management chip 313 instead of outside the first and second single-level package logic drivers 300, wherein the power management chip 313 is suitable for connecting each first and The second single-level package logical driver 300, wireless communication element 306, display device 307, camera 308, audio device 309, memory driver, disk or device 310, keyboard 311, and Ethernet network 312, placed (or set up) in the state with the lowest power demand available.

memory drive

The present invention also relates to commercialized standard memory drives, packages, packaged drives, devices, modules, hard disks, hard disk drives, solid-state disks or solid-state disk drives 310 (wherein 310 is hereinafter referred to as "drive", i.e. hereinafter Reference to "drive" means a commercial standard memory drive, package, packaged drive, device, module, hard drive, hard drive, solid state drive, or solid state drive), and drive 310 is a A plurality of commercial standard non-volatile memory IC chips 250 are used for data storage in a multi-chip package. FIG. 26A is a top view of a commercial standard memory driver according to an embodiment of the present invention. As shown in FIG. 26A, the memory driver 310 The first type can be a non-volatile memory driver 322, which can be used in a driver-to-driver assembly as shown in Figures 24A-24K, in a package with a plurality of high-speed, high-frequency wide non-volatile memory (NVM) ICs The chips 250 are arranged in a matrix with the semiconductor chips 100. The structure and process of the memory driver 310 can refer to the structure and process of the single-layer package logic driver 300, but the difference lies in the arrangement of the semiconductor chips 100 in Fig. 26A. The high-bandwidth non-volatile memory IC chip 250 may be a bare die type NAND flash memory chip, a NOR flash memory chip or a multiple chip package type flash memory chip, even if the data is stored in the memory driver 310 when the power is turned off. The non-volatile memory IC chip 250 within the commercial standard memory driver 310 may remain, or the high-speed, high-frequency non-volatile memory (NVM) IC chip 250 may be a bare die type non-volatile random access memory Bulk (NVRAM) IC chip or packaged non-volatile random access memory (NVRAM) IC chip, NVRAM can be Ferroelectric RAM (FRAM), magnetoresistive random access memory (Magnetoresistive RAM (MRAM)), Phase-change RAM (PRAM), each NAND flash chip 250 (or NOR flash memory chip) may have a standard memory density, internal volume or size greater than or Equal to 64Mb, 512Mb, 1Gb, 4Gb, 16Gb, 64Gb, 128Gb, 256Gb or 512Gb, where "b" is a bit, each complex NAND flash chip 250 (or NOR flash memory chip) can use advanced NAND flash Technology or next-generation process technology or design and manufacturing, for example, technology advanced than or equal to 45nm, 28nm, 20nm, 16nm and/or 10nm, where advanced NAND flash technology or NOR flash memory chips can be included in the plane Flash memory (2D-NAND) structure or three-dimensional flash memory (3DNAND) structure using a single single-level storage (SingleLevelCells (S LC) technology or multiple level cells (MLC) technology (for example, Double Level Cells DLC or triple Level cells TLC), the 3D NAND structure may include stacked layers (or levels) of multiple NAND memory cells, For example, a stack of layers greater than or equal to 4, 8, 16, 32 NAND memory cells (or NOR flash memory cells). Thus, a commercial standard memory drive 310 may have standard non-volatile memory with a memory density, capacity or size greater than or equal to 8MB, 64MB, 128GB, 512GB, 1GB, 4GB, 16GB, 64GB, 256GB or 512GB, where "B" stands for 8 bits.

FIG. 26B is a top view of another commercial standard memory driver according to an embodiment of the present invention. As shown in FIG. 26B, the second type of the memory driver 310 may be a non-volatile memory driver 322, which is used as shown in FIG. 24A. Figures to Figures 24K are driver-to-driver packages having a plurality of non-volatile memory IC chips 250, a plurality of dedicated I/O chips 265, and a dedicated control chip 260 for the semiconductor chip 100 as shown in Figure 26A, wherein the non-volatile The memory IC chip 250 and the dedicated control chip 260 can be arranged in a matrix. The structure and process of the memory driver 310 can refer to the structure and process of the single-layer package logic driver 300. The difference lies in the semiconductor chip 100 shown in FIG. 26B. The non-volatile memory IC chips 250 can be arranged around the dedicated control chip 260, each of the dedicated I/O chips 265 can be arranged along the edge of the memory driver 310, and the specifications of the non-volatile memory IC chips 250 can be Referring to the specification and description of the dedicated control chip 260 package in the memory driver 310 as described in FIG. 26A, please refer to the specification and description of the dedicated control chip 260 package in the single-level package logic driver 300 as shown in FIG. 11A, in Specifications and descriptions of the dedicated I/O chip 265 package in the memory driver 310 may refer to the specifications and descriptions of the dedicated I/O chip 265 package in the single-level package logic driver 300 as shown in FIGS. 11A to 11N .

FIG. 26C is a top view of another commercialized standard memory driver according to an embodiment of the present invention. As shown in FIG. 26C, the dedicated control chip 260 and a plurality of dedicated I/O chips 265 are combined into a single chip 266 (that is, the dedicated control chip 266). chip and dedicated I/O chip) to perform the above-mentioned control and multiple functions of the I/O chips 260 and I/O chips 265, the third type of the memory driver 310 may be the non-volatile memory driver 322, which is used for As shown in Figures 24A to 24K, the driver-to-driver package has a plurality of non-volatile memory IC chips 250, a plurality of dedicated I/O chips 265, and a dedicated control chip and a dedicated I/O chip 266 as shown in Figure 26A. For the semiconductor chip 100, the non-volatile memory IC chip 250, the dedicated control chip and the dedicated I/O chip 266 can be arranged in a matrix. The structure and process of the memory driver 310 can refer to the structure and The difference lies in the arrangement of the semiconductor chips 100 in Fig. 26C, the non-volatile memory IC chips 250 can surround the dedicated control chip and the dedicated I/O chip 266, and each of the plurality of dedicated I/O chips 265 can Arranged along the edge of the memory driver 310, the specifications of the non-volatile memory IC chip 250 can refer to the specifications of the dedicated control chip and the dedicated I/O chip 266 package in the memory driver 310 as described in FIG. 26A and For the description, please refer to the specification and description of the dedicated control chip and the dedicated I/O chip 266 package in the single-level package logic driver 300 as shown in FIG. 11B , and the specification and description of the dedicated I/O chip 265 package in the memory driver 310 Reference may be made to the specification and description of the dedicated I/O die 265 package in the single-level package logic driver 300 as shown in FIGS. 11A-11N.

FIG. 26D is a top view of a commercialized standard memory driver according to an embodiment of the present invention. As shown in FIG. 26D, the fourth type of the memory driver 310 may be a volatile memory driver 323, which is used as shown in FIG. 24A to The driver-to-driver package in Fig. 24K has a plurality of volatile memory (VM) IC chips 324, such as a high-speed, high-bandwidth complex DRAM chip such as one within the single-level package logic driver 300 in Figs. 11A-11N The logic block 201 is packaged or, for example, a high-speed, high-bandwidth cache SRAM chip for arranging the semiconductor chips 100 in a matrix. The structure and process of the memory driver 310 can refer to the structure and process of the single-layer package logic driver 300, but they are different. The difference lies in the arrangement of the semiconductor wafer 100 as shown in FIG. 26D. In a case, all of the volatile memory (VM) IC chips 324 in the memory driver 310 may be the plurality of DRAM chips 321, or, all the volatile memory (VM) IC chips 324 of the memory driver 310 may be SRAM chip. Alternatively, all of the volatile memory (VM) IC chips 324 of the memory driver 310 may be a combination of DRAM chips and SRAM chips.

FIG. 26E is a top view of another commercial standard memory driver according to an embodiment of the present invention. As shown in FIG. 26E, a fifth-type memory driver 310 can be a volatile memory driver 323, which can be used for example Figures 24A through 24K are driver-to-driver packages having a plurality of volatile memory (VM) IC chips 324, such as high-speed, high-bandwidth complex DRAM chips or high-speed, high-bandwidth cache SRAM chips, and multiple dedicated I/O chips 265 and a dedicated control chip 260 are used in the semiconductor chip 100, wherein the volatile memory (VM) IC chip 324 and the dedicated control chip 260 can be arranged in a matrix, and the structure and process of the memory driver 310 can refer to the single-layer package logic driver 300, but the difference lies in the arrangement of the semiconductor wafer 100 as shown in FIG. 26E. In this case, the location for mounting each of the plurality of DRAM chips 321 can be changed for mounting SRAM chips, and each of the plurality of dedicated I/O chips 265 can be surrounded by volatile memory chips, such as a plurality of DRAM chips 321 or SRAM chips, each D dedicated I/O chips 265 can be arranged along an edge of the memory driver 310, and all of the volatile memory (VM) IC chips 324 in the memory driver 310 in a row can be Either the plurality of DRAM chips 321, or all of the volatile memory (VM) IC chips 324 of the memory driver 310 can be SRAM chips. Alternatively, all of the volatile memory (VM) IC chips 324 of the memory driver 310 may be a combination of DRAM chips and SRAM chips. The specification of the dedicated control chip 260 packaged in the memory driver 310 can refer to the specification of the dedicated control chip 260 packaged in the single-level packaged logic driver 300 as shown in FIG. 11A . The specification of the /O die 265 may refer to the specification of the dedicated I/O die 265 packaged in the single-level package logic driver 300 as shown in FIGS. 11A through 11N.

26F is a top view of another commercialized standard memory driver according to an embodiment of the present invention. As shown in FIG. 26F, the dedicated control chip 260 and a plurality of dedicated I/O chips 265 are combined into a single chip 266 (that is, a dedicated control chip 266). control chip and dedicated I/O chip) to perform the above-mentioned control and multiple functions of the multiple I/O chips 260 and I/O chips 265, the sixth type of the memory driver 310 may be the volatile memory driver 323, which is used for In the driver-to-driver package as shown in Figures 24A-24K, the package has a plurality of volatile memory (VM) IC chips 324, such as high-speed, high-bandwidth complex DRAM chips as shown in Figures 11A-11N for single-level packaging logic A 324 package within the driver 300 or, for example, a high-speed, high-bandwidth cache SRAM chip, a plurality of dedicated I/O chips 265, and a dedicated control chip and a dedicated I/O chip 266 for the semiconductor chip 100, wherein volatile memory (VM) ) IC chips 324 and dedicated control chips and dedicated I/O chips 266 may be arranged in a matrix as shown in Figure 26F, the dedicated control chips and dedicated I/O chips 266 may be surrounded by volatile memory chips, wherein the volatile memory If the chip system is a plurality of DRAM chips 321 or SRAM chips, in one case all the volatile memory (VM) IC chips 324 in the memory driver 310 can be the plurality of DRAM chips 321, or, all the volatile memory (VM) IC chips 324 in the memory driver 310 The memory (VM) IC chips 324 may all be SRAM chips. Alternatively, all of the volatile memory (VM) IC chips 324 of the memory driver 310 may be a combination of DRAM chips and SRAM chips. The structure and process of the memory driver 310 can refer to the structure and process of the single-layer package logic driver 300, but the difference lies in the arrangement of the semiconductor chips 100 in FIG. 26F, each of the dedicated I/O chips 265 can be along the With the edge arrangement of the memory driver 310, the specification of the dedicated control chip and the dedicated I/O chip 266 packaged in the memory driver 310 can refer to the dedicated control chip packaged in the single-layer packaged logic driver 300 as shown in FIG. 11B. and the specification of the dedicated I/O chip 266, the specification of the dedicated I/O chip 265 packaged in the memory driver 310 may refer to the specification of the dedicated I/O chip 265 packaged in the single-level package logic driver 300 as shown in FIGS. 11A to 11N. Specification of I/O die 265, specification of DRAM die 321 packaged in memory driver 310 can be referred to the specification of DRAM die 321 packaged in single-level package logic driver 300 as shown in FIGS. 11A to 11N .

Alternatively, another type of memory driver 310 may include a combination of a non-volatile memory (NVM) IC chip 250 and a volatile memory chip, eg, as shown in FIGS. 26A-26C, for mounting a non-volatile memory (NVM) IC chip 250. Certain locations of the volatile memory IC die 250 can be changed for mounting a volatile memory die, such as a high-speed, high-bandwidth complex DRAM die 321 or a high-speed, high-bandwidth SRAM die.

FISC to FISC package for logical drives and memory drives

Alternatively, FIGS. 27A to 27C are schematic cross-sectional views of various packages for logic and memory drivers according to embodiments of the present invention. As shown in FIG. 27A, the metal studs or bumps 122 of the memory driver 310 may engage the metal studs or bumps 122 of the single-level package logic driver 300 to form a plurality of bonding connections 586 in the memory, the logical driver 310, and the logical driver. Between 300, for example, a plurality of solder balls or bumps (as shown in Figure 18R) of a logic and memory driver 300 and 310 provided by the fourth type of metal studs or bumps 122 are bonded to other logic and memory The copper layers of the first type metal pillars or bumps 122 of the bulk drivers 300 and 310 to form bond connections 586 between the memory, logical driver 310 and logical driver 300 .

For high-speed and high-bandwidth communication between semiconductor chips 100 in a single-level package of logic drivers 300, the semiconductor chips 100 are non-volatile, non-volatile memory IC chips 250 or volatile as shown in FIGS. 11A to 11N . A semiconductor die 100 of the memory driver 310 may be aligned with and vertically disposed over a semiconductor die 100 of the single-level package logic driver 300 of the semiconductor chip 100 , the memory IC die 324 .

As shown in FIG. 27A, the memory driver 310 may include a plurality of first stack portions provided by the interconnect metal layer 99 of the TISD 101 itself, wherein each first stack portion may be aligned and stacked on a bond connection point 586 or A semiconductor chip 100 and a bonding connection point 586 above and on itself, and for memory driver 310, a plurality of micro-bumps or metal pillars 34 can be aligned and stacked on or above the first stack portion itself, respectively and is located between a semiconductor chip 100 of itself and the first stacking part of itself, so as to connect a semiconductor chip 100 of itself to the first stacking part, respectively.

As shown in FIG. 27A, the single-level package logic driver 300 may include a plurality of second stack portions provided by the interconnect metal layers 99 of the TISD 101 itself, wherein each second stack portion may be aligned and stacked at a bond connection point 586 A semiconductor die 100 and a bonding connection point 586 under or under and on itself, in addition, for the single-level package logic driver 300, a plurality of micro-bumps or metal pillars 34 can be aligned and stacked on its own second The stacked portion is positioned under or below and between a semiconductor wafer 100 of itself and a second stacked portion of itself to connect a semiconductor wafer 100 of itself to the second stacked portion, respectively.

Thus, as shown in FIG. 27A, the stacked structure includes, from bottom to top, a micro bump or metal pillar 34 of the single-level package logic driver 300, a second stacked portion of the TISD 101 of the single-level package logic driver 300, a bond The connection point 586, a first stack portion of the TISD 101 of the memory driver 310, and the micro-bumps or metal pillars 34 of the memory driver 310 can be stacked vertically together to form a vertically stacked path 587 in a single-level package of the logic driver 300 Between the semiconductor chip 100 of the memory driver 310 and one of the semiconductor chips 100 of the memory driver 310, for signal transmission or power supply or ground transmission, in one aspect, the plurality of vertical stacking paths 587 have the number of connection points equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, for example, connected between a semiconductor chip 100 of a single-level package logic driver 300 and a semiconductor chip 100 of a memory driver 310 for parallel signal transmission, signal transmission or power supply or grounded delivery.

As shown in FIG. 27A, for each logic and memory driver 300 and 310, the drive capability, load, output capacitance, or input capacitance of the complex small I/O circuit 203 in FIG. 5B is between 0.01 pF and 10 pF. between 0.05pF and 5pF, between 0.01pF and 2pF, between 0.01pF and 1pF, or less than 10pF, 5pF, 3pF, 2pF, 1pF, 0.5pF or 0.1pF, plural small I The /O circuit 203 may be provided in a semiconductor die 100 for the vertical stacking path 287 , eg, a plurality of miniature I/O circuits 203 may constitute miniature ESD protection circuit 373 , miniature receiver 374 and miniature driver 375 .

As shown in FIG. 27A, the metal bumps 583 of the metal pads 77E of the BISD 79 of each logic and memory driver 300 and 310 themselves are used to connect the logic and memory drivers 300 and 310 to an external circuit. For each logic And the memory drivers 300 and 310 themselves can (1) be coupled to their own semiconductor chip 100 through the multiple interconnection wire metal layers 77 of their own BISD79; (2) through the multiple interconnection wire metal layers 77 of their own BISD79 according to A semiconductor die 100 sequentially coupled to other logic and memory drivers 300 and 310, one or more of its own TPVS 158, its own TISD 101 interconnect metal layer 99, one or more bond connections 586, other logic and memory Interconnect metal layer 99 of TISD 101 of drivers 300 and 310, and one or more micro-bumps or metal pillars 34 of other logic and memory drivers 300 and 310; or (3) a plurality of interconnect metal through its own BISD 79 Layer 77 is sequentially coupled to a metal bump 583 of the other logic and memory drivers 300 and 310, one or more TPVS 158, the interconnect metal layer 99 of its own TISD 101, one or more bond connections 586, other logic and Interconnect metal layers 99 of TISD 101 of memory drivers 300 and 310, one or more TPVS 158 of other logic and memory drivers 300 and 310, and a plurality of interconnect metal layers of BISD 79 of other logic and memory drivers 300 and 310 77.

Or, as shown in Fig. 27B and Fig. 27C, the structure of these two figures is similar to the structure shown in Fig. 27A, and the component drawing numbers shown in Fig. 27B and Fig. 27C are the same as those shown in Fig. 27A. For the component drawing numbers, please refer to the component specifications and descriptions disclosed in the above-mentioned FIG. 27A. The difference is that in FIGS. 27A and 27B, the memory driver 310 does not have the metal bumps 583, BISD79 and TPVS582, and FIG. 27A differs from FIG. 27C in that the single level package logic driver 300 does not have the metal bumps 583, BISD79 and TPVS582 for external connection.

As shown in FIGS. 27A to 27C, for the example of parallel signal transmission, the parallel vertical stacking paths 587 can be arranged between a semiconductor chip 100 of the single-level package logic driver 300 and a semiconductor chip 100 of the COIP memory driver 310 Among them, the semiconductor chip 100 is, for example, a GPU chip as shown in FIGS. 11F to 11N, and the semiconductor chip 100 is also a high-speed, high-bandwidth cache SRAM chip, a DRAM chip, or a chip for MRAM or NVMIC chip for RRAM, and the semiconductor chip 100 has a data bit bandwidth equal to or greater than 64, 128, 256, 512, 1024, 4096, 8K, or 16K, or, for the parallel signaling example, the parallel vertical stack path 587 It can be arranged between a semiconductor chip 100 of the COIP single-level package logic driver 300 and a semiconductor chip 100 of the COIP memory driver 310 , wherein the semiconductor chip 100 is, for example, the TPU chip in FIGS. 11F to 11N , and the semiconductor chip 100 is That is, a high-speed, high-bandwidth cache SRAM chip, a DRAM chip, or an NVM chip for MRAM or RRAM as shown in FIGS. 26A to 26F, and the semiconductor chip 100 has a data bit bandwidth equal to or greater than 64, 128, 256, 512, 1024, 4096, 8K or 16K.

Nonvolatile Programmable Logic Driver

FIG. 29A is a schematic cross-sectional view of a POP packaging structure for a first-type non-volatile programmable logic driver according to an embodiment of the present invention. As shown in FIG. 29A, in forming the first-type non-volatile programmable logic driver 610, NVM chip package structure 510 may have a plurality of solder bumps bonded to copper pillars 158 of logic chip package structure 520, which may be a single-layer chip package structure in Figure 28G or die 550, solder bumps After bonding the copper pillars 158 , solder joints 516 with a thickness between 20 μm and 100 μm are respectively produced therebetween, wherein the single-layer chip package structure or the semiconductor chip 100 of the small chip 550 is used as the logic chip package structure 520 . 8A to 8J of the FPGAIC chip, an underfill material 517 (eg, a polymer) may be formed between the NVM chip package structure 510 and the logic chip package structure 520 to encapsulate the solder joints 516, The NVM chip package structure 510 may include: (1) two non-volatile memory IC chips 250 stacked and bonded to each other via an adhesive layer 511 , which may be NAND flash memory as shown in FIGS. 11A to 11N . A bulk chip or a NOR flash memory chip, wherein the adhesive layer 511 can be silver paste or thermal paste, wherein the upper non-volatile memory IC chip 250 can traverse a boundary of the lower non-volatile memory IC chip 250 , (2) a circuit board 513 is located under the two non-volatile memory IC chips 250, and the lower non-volatile memory IC chip 250 is adhered to the upper surface of the circuit board 513 through an adhesive layer 524, and the adhesive layer 524 Can be silver paste or thermally conductive paste, (3) a plurality of bonding wires 514 to couple the non-volatile memory IC chip 250 to the circuit board 513, and (4) a potting polymer 515 over the circuit board 513, surrounding Non-volatile memory IC chip 250 and wire bond wires 514, the circuit board 513 may include one (or more) interconnect wire metal layers 518 coupling wire bond wires 514 to solder bond pads 516, and one (or more) The polymer layer 519 is located between every two adjacent interconnection wire metal layers 518, below the bottommost interconnection wire metal layer 518 or above the uppermost interconnection wire metal layer 518, wherein the upper interconnection wire The wire metal layer 518 can be coupled to the underlying interconnect wire metal layer 518 via openings in the polymer layer 519 therebetween, and the logic chip package structure 520 has metal bumps, posts or pads 570 that are adhesively bonded to the circuit board 530 to produce solder joints 521 with a thickness between 20 μm and 100 μm between the two, and an underfill material 522 (eg, polymer) can be formed between the logic chip package structure 520 and the circuit board 530 to encapsulate the The solder joints 521, a plurality of solder bumps or balls 523 may be arranged on the bottom of the circuit board 530 in a matrix pattern, except for F In addition to the PGAIC die 200, the semiconductor die 100 for the single-layer die package structure of the logic die package structure 520 or the chiplet 550 may be a CPU die, a GPU die, a TPU die, an APU die, or a DSP die.

In the first option, in the first type of non-volatile programmable logic driver 610, the circuit board 513 and the solder joints 516 can be covered by a thin-small-outline-package (TSOP) lead frame ( (not shown) instead, the lead frame has a low non-volatile memory IC chip 250 bonded thereon and each bond wire 514 can couple the non-volatile memory IC chip 250 to a plurality of inner leads of the lead frame One, the potting polymer 515 surrounds the non-volatile memory IC chip 250, the wirebond wires 514, and a plurality of inner wires of the lead frame whose outer wires are located outside the potting polymer 515 via solder The bumps are bonded to the copper pillars 158 of the logic chip package structure 520, where each outer lead can be connected to an inner lead. Thus, the non-volatile memory IC chip 250 can be coupled to the logic via the lead frame, one of the copper pillars 158 and one (or more) interconnect metal layers 27 of the TISD or FISD 101 of the logic chip package 520 in sequence The FPGAIC die 200 of the die package structure 520 .

In the second option, in the second type of non-volatile programmable logic driver 610, the NVM chip package structure 510 may be a chip scale package (CSP), wherein the NVM chip package structure 510 and the non-volatile The area ratio of the memory IC chip 250 is equal to or less than 1.5.

FIG. 29B is a schematic cross-sectional view of a POP package structure for a second type non-volatile programmable logic driver according to an embodiment of the present invention. The POP package structure 610 shown in FIG. 29B is similar to the POP package structure shown in FIG. 29A. The structure of Fig. 29A and Fig. 29B have the same component numbers. The disclosure of each element in Fig. 29B can refer to the disclosure description in Fig. 29A. The difference is that when the second type non-volatile programmable logic driver 610 in FIG. 29B is formed, a plurality of solder bumps of the NVM chip package structure 510 in FIG. 29A are adhesively bonded to the logic chip package structure 520. One of the metal pads or bumps 583, the logic chip package structure 520 may be the single-layer chip package structure or the chiplet 550 in FIG. 28I, and after bonding produces a solder joint 516 with a thickness between 20 μm and 100 μm in the Between the two, the semiconductor die 100 of the single-layer die package structure or die 550 used in the logic die package structure 520 may be the FPGAIC die 200 of FIGS. (substrate) can be formed between the NVM chip package structure 510 and the logic chip package structure 520 to enclose the solder joints 516, it should be noted that the logic chip package structure 520 can include a first set of dummy pads or bumps 583a are respectively bonded to a first set of solder bumps of the NVM chip package structure 510 to create a first set of solder joints 516a (which can be bonded to a ground reference voltage) and to create a second set of dummy pads or bumps 583a A second set of solder bumps are respectively bonded to the NVM chip package structure 510 to produce a second set of solder joints 516a (without any electrical function), wherein the first and second sets of solder joints 516a can be vertically positioned Above the FPGAIC die 200 of the logic chip package structure 520, in addition to the FPGAIC die 200, the semiconductor die 100 for the single-layer chip package structure of the logic die package structure 520 or the chiplet 550 may be a CPU die, a GPU die, a TPU chip, APU chip or DSP chip. However, in a first option, each external lead of the leadframe may be bonded to the metal pad or bump 583 of the logic chip package structure 520 via solder.

FIG. 29C is a schematic cross-sectional view of a POP packaging structure for a third-type non-volatile programmable logic driver according to an embodiment of the present invention. The POP packaging structure 610 shown in FIG. 29C is similar to the POP packaging structure shown in FIG. 29A. The structure of Fig. 29A and Fig. 29C have the same component numbers. The disclosure of each element in Fig. 29C can refer to the disclosure description in Fig. 29A. The difference is that, when forming the third type non-volatile programmable logic driver 610 in FIG. 29C, the single-layer chip package structure or chiplet 550 in FIG. 28G can be provided as an NVM chip package structure 510, wherein The semiconductor chip 100 used as the single-layer chip package structure or chiplet 550 of the NVM chip package structure 510 may be an NVMIC chip, such as a NAND flash memory chip or a NOR flash memory chip as shown in FIGS. 11A to 11N The chip, and without any copper pillars 158 in the polymer layer 92 of the single-layer chip package structure or chiplet 550 in FIG. 28G, which can be used as the NVM chip package structure 510, the NVM The metal bumps, pillars or pads 570 of the chip package structure 510 are adhesively bonded to the copper pillars 158 of the logic chip package structure 520, which may be the single layer chip package structure in FIG. 28G or the chiplet 550, bonded Solder junctions 516 with a thickness between 20 μm and 100 μm are then produced therebetween, and an underfill material 517 (eg, a polymer) can be formed between the NVM chip package structure 510 and the logic chip package structure 520 , including The solder joints 516 are held. Alternatively, the logic chip package structure 520 may be provided with a plurality of metal pads or bumps 583 as shown in FIG. 28I bonded to the metal bumps, posts or pads 570 to produce a thickness of between 20 μm and 100 μm as shown in FIG. 29B The solder joints 516 between the two, it should be noted that the metal pads or bumps of the logic chip package structure 520 may include a first set of multiple dummy pads or bumps 583a respectively bonded to the NVM chip A metal bump, post or pad 570 of package structure 510 to create a first set of solder joints 516a (which can be bonded to the ground reference voltage) as shown in Figure 29B and to create a second set of dummy pads or bumps 583a A second set of metal bumps, studs or pads 570 are respectively bonded to the NVM chip package structure 510 to produce a second set of solder joints 516a (without any electrical function) as shown in FIG. 29B, wherein the first The set and second set of solder joints 516a may be positioned vertically above the FPGAIC die 200 of the logic chip package structure 520, except for the FPGAIC die 200, for the single layer chip package structure of the logic chip package structure 520 or the die 550. The semiconductor die 100 may be a CPU die, a GPU die, a TPU die, an APU die, or a DSP die.

FIG. 29D is a schematic cross-sectional view of a POP packaging structure for a fourth type non-volatile programmable logic driver according to an embodiment of the present invention. The POP packaging structure 610 shown in FIG. 29D is similar to the POP packaging structure shown in FIG. 29A. The structure of Fig. 29A and Fig. 29D have the same component numbers. The disclosure of each element in Fig. 29D can refer to the disclosure description in Fig. 29A. The difference is that when the fourth type non-volatile programmable logic driver 610 is formed in FIG. 29D, the plurality of solder bumps of the NVM chip package structure 510 in FIG. 29D are adhesively bonded to the logic chip package structure 520. One of the metal pads or bumps 583, the logic chip package structure 520 may be the single-layer chip package structure in Figure 28K or the chiplet 550, which after bonding produces a solder joint 516 with a thickness between 20 μm and 100 μm in the Between the two, the semiconductor die 100 of the single-layer die package structure or die 550 used in the logic die package structure 520 may be the FPGAIC die 200 of FIGS. (substance) can be formed between the NVM chip package structure 510 and the logic chip package structure 520, encapsulating the solder joints 516, in addition to the FPGAIC chip 200, for a single-layer chip package structure or a small chip package structure for the logic chip package structure 520 The semiconductor die 100 of the die 550 may be a CPU die, a GPU die, a TPU die, an APU die, or a DSP die. However, in a first option, each external lead of the leadframe may be bonded to the metal pad or bump 583 of the logic chip package structure 520 via solder.

FIG. 29E is a schematic cross-sectional view of a POP package structure for a fifth type non-volatile programmable logic driver according to an embodiment of the present invention. The POP package structure 610 shown in FIG. The structure of the POP package structure is similar, and the component numbers in Fig. 29D and Fig. 29A are the same as those in Fig. 29E. The disclosure of each element in Fig. 29E can refer to the disclosure description in Fig. 29D and Fig. 29A. The difference between Fig. 29D and Fig. 29A and the POP package structure 610 in Fig. 29E is the single-layer chip package in Fig. 28G when the fifth-type non-volatile programmable logic driver 610 in Fig. 29E is formed. The structure or chiplet 550 can be provided as an NVM chip package structure 510, wherein the semiconductor chip 100 used as the single-layer chip package structure or chiplet 550 as the NVM chip package structure 510 can be an NVMIC chip, such as that shown in FIGS. NAND flash memory chip or NOR flash memory chip in Fig. 11N, and without any copper pillars 158 in the polymer layer 92 of the single-layer chip package structure or chiplet 550 in Fig. 28G, such a single-layer chip The package structure or chiplet 550 can be used as the NVM chip package structure 510, the metal bumps, posts or pads 570 of the NVM chip package structure 510 are adhesively bonded to the metal pads or bumps 583 of the logic chip package structure 520, the logic chip package Structure 520 may be the single-layer chip package structure in Figure 28K or die 550, with solder joints 516 between 20 μm and 100 μm thick after bonding, underfill material 517 (eg, polymerized) (substrate) can be formed between the NVM chip package structure 510 and the logic chip package structure 520, enclosing the solder joints 516. In addition to the FPGAIC die 200, the semiconductor die 100 of the single-layer die package structure or chiplet 550 for the logic die package structure 520 may be a CPU die, a GPU die, a TPU die, an APU die, or a DSP die.

FIG. 29F is a schematic cross-sectional view of a POP packaging structure for a sixth type non-volatile programmable logic driver according to an embodiment of the present invention. The POP packaging structure 610 shown in FIG. 29F is similar to the POP packaging structure shown in FIG. 29A. The structure of Fig. 29A and Fig. 29F have the same element numbers, wherein the disclosure of each element in Fig. 29F can refer to the disclosure description in Fig. 29A and Fig. 29D, Fig. 29A and Fig. 29D and Fig. 29D The difference between the POP package structures 610 in Fig. 29F is that when the sixth type non-volatile programmable logic driver 610 in Fig. 29F is formed, the non-volatile memory IC chip 250 (eg, Figs. 11A to 11N) NAND flash memory chip or NOR flash memory chip) can be provided in place of the NVM chip package structure 510 in Figure 29D, the non-volatile memory IC chip 250 can provide a plurality of solder bumps for bonding to logic One of the metal pads or bumps 583 of the chip package structure 520, the logic chip package structure 520 may be the single-layer chip package structure or the small chip 550 in FIG. 28K, and after bonding, a plurality of bonding contacts 531 are generated in two places. In between, each bonding contact 531 may include copper bumps 534 between the non-volatile memory IC chip 250 and the logic chip package structure 520 with a thickness between 10 μm and 100 μm, and a tin-containing metal A layer 535 is interposed between the copper bumps and the logic chip package structure 520, and an underfill material 532 (eg, a polymer) may be formed between the non-volatile memory IC chip 250 and the logic chip package structure 520, encapsulating the The bonding pads 531 , in addition to the FPGAIC chip 200 , the semiconductor chip 100 for the single-layer chip package structure of the logic chip package structure 520 or the chiplet 550 may be a CPU chip, a GPU chip, a TPU chip, an APU chip or a DSP chip wafer.

FIG. 29G is a schematic cross-sectional view of a POP packaging structure used in a seventh-type non-volatile programmable logic driver according to an embodiment of the present invention. The POP packaging structure 610 shown in FIG. 29G is similar to the POP packaging structure shown in FIG. 29E. The structure of Fig. 29A, Fig. 29D and Fig. 29G have the same element numbers, and the disclosure of each element in Fig. 29G can refer to the disclosure descriptions in Fig. 29A, Fig. 29D and Fig. 29E. The difference between the POP package structure 610 in FIG. 29E and the POP package structure 610 in FIG. 29G is the single-layer chip package structure or die in FIG. 28K when the seventh-type non-volatile programmable logic driver 610 in FIG. 29G is formed. 550 may be provided as an I/O chip package structure 540 between the NVM chip package structure 510 and the logic chip package structure 520, wherein the semiconductor chip used as a single layer chip package structure of the I/O chip package structure 540 or the chiplet 550 100 may be the dedicated I/O die 265 of FIGS. 11A-11N, and the I/O die package structure 540 may provide metal having a plurality of metal bumps, posts or pads 570 adhesively bonded to the logic die package structure 520 The pads or bumps 583, the I/O chip package structure 540 may be a single layer chip package structure as shown in Figure 28G or the chiplet 550, which after bonding results in solder joints 536 having a thickness between 20 μm and 100 μm. In between, an underfill material 537 (eg, a polymer) may be formed between the I/O chip package structure 540 and the logic chip package structure 520 , surrounding the solder joints 536 . Such a single-layer chip package structure or chiplet 550 can be used as an NVM chip package structure 510, the metal bumps, posts or pads 570 of the NVM chip package structure 510 are adhesively bonded to the metal pads of the I/O chip package structure 540 or Bumps 583, I/O chip package structure 540 may be a single layer chip package structure as shown in Figure 28G or dielet 550, with solder joints 541 between 20μm to 100μm thick after bonding , an underfill material 542 (eg, polymer) may be formed between the NVM chip package structure 510 and the I/O chip package structure 540 to encapsulate the solder joints 541 . Alternatively, the BISD 79 of the I/O chip package structure 540 can be omitted, as in the single-layer chip package structure or the structure of the chiplet 550 in FIG. 28G, and the NVM chip package structure has a plurality of metal bumps, posts or pads 570 The copper pillars 158 bonded to the I/O chip package structure 540 are adhesively bonded to produce solder joints 516 between the two as shown in FIG. 29C. Alternatively, the I/O chip package structure 540 may have the same structure as the single-layer chip package structure or die 550 in FIG. 28I, and the NVM chip package structure has a plurality of metal bumps, posts or pads 570 adhesively bonded to the I/O O the metal pads or bumps 583 of the chip package structure 540 to create the solder joints 516 between the two as shown in FIG. 29B. It should be noted that the metal pads or bumps of the I/O chip package structure 540 may include a plurality of dummy pads or bumps 583a of a first group respectively bonded to a metal bump, stud of the NVM chip package structure 510 . or pads 570 to create a first set of solder joints 516a (which can be bonded to a ground reference voltage) as shown in FIG. 29B and to create a second set of dummy pads or bumps 583a to be bonded to one of the NVM chip package structures 510, respectively A second set of metal bumps, posts or pads 570 to create a second set of solder joints 516a (without any electrical function) as shown in FIG. 29B, wherein the first and second sets of solder joints 516a can be Positioned vertically above the dedicated I/O chip 265 of the I/O chip package structure 540, the dedicated I/O chip 265 of the I/O chip package structure 540 may include a small I/O circuit 203 in sequence through the dedicated I/O One of the metal pads, wires or connecting lines 108 of the chip 265 , the metal layer 27 of the TISD or FISD 101 of the I/O chip package structure 540 , one of the solder contacts 536 , the BISD 79 of the logic chip package structure 520 The interconnection wire metal layer 27 of the logic chip package structure 520 , one of the copper pillars 158 of the logic chip package structure 520 , the interconnection wire metal layer 27 of the TISD or FISD101 of the logic chip package structure 520 , and one of the metal pads and wires of the FPGAIC chip 200 Or connecting line 108, coupled to a small I/O circuit 203 of the FPGAIC chip 200 of the logic chip package 520; the dedicated I/O chip 265 of the I/O chip package 540 may further include another small I/O circuit 203 is coupled to a small I/O circuit 203 of the non-volatile memory IC chip 250 of the NVM chip package 510 (sequentially via one of the metal pads, wires or connecting wires 108, I of the dedicated I/O chip 265 The interconnection wire metal layer 27 of the TISD or FISD101 of the /O chip package structure 540 , one of the copper pillars 158 of the I/O chip package structure 540 , the interconnection wire metal layer 27 of the BISD79 of the I/O chip package structure 540 , One of the solder contacts 541, the interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package structure 510, one of the metal pads, lines or connecting lines 108 of the non-volatile memory IC chip 250), each of which A dedicated I/O chip 265, FPGA IC chip 200 and miniature I/O circuit 203 of non-volatile memory IC chip 250 can be used as a miniature driver 374, miniature receiver 375 and miniature ESD protection circuit 373 in Figure 5B constituted, all of its miniature I/O circuits 203 are coupled to one of the metal pads, lines or wires 108 of each dedicated I/O chip 265 , FPGA IC chip 200 and non-volatile memory IC chip 250 Provided I/O pads 372, I/O The dedicated I/O chip 265 of the chip package structure 540 may include a large I/O circuit 341 coupled to one of the solder bumps or balls 523 (in turn via one of the metal pads, wires of the dedicated I/O chip 265 ) Or connection line 108, the interconnection line metal layer 27 of TISD or FISD101 of the I/O chip package structure 540, one of the solder contacts 536, the interconnection line metal layer 27 of the BISD79 of the logic chip package structure 520, the logic chip package One of the copper pillars 158 of the structure 520 , the interconnect metal layer 27 of the TISD or FISD 101 of the logic chip package structure 520 , one of the solder contacts 521 and the circuit board 530 , of which the large I/O of the dedicated I/O chip 265 The O circuit 341 can be composed of a large driver 274, a large receiver 275, and a large ESD protection circuit 273 as shown in FIG. 5A. All the large I/O circuits 341 are coupled to the metal pads of the dedicated I/O chip 265, line or I/O pads 272 provided by connection line 108) for external connections. Above the FPGAIC chip 200 of the logic chip package structure 520, in addition to the FPGAIC chip 200, the semiconductor chip 100 used for the single-layer chip package structure of the logic chip package structure 520 or the small chip 550 may be a CPU chip, a GPU chip, or a TPU chip , APU chip or DSP chip.

FIG. 29H is a schematic cross-sectional view of a POP packaging structure for an eighth type non-volatile programmable logic driver according to an embodiment of the present invention. As shown in FIG. 29H, in forming the eighth type non-volatile programmable logic driver 610, Metal bumps, posts or pads 570 of the HBM chip package 560 (which may be the single-layer chip package or die 550 in Figure 28K) can be attached to the logic chip package 520 (which may be the single-layer chip package in Figure 28K). The metal bumps, posts or pads 570 of the layer chip package structure or chiplet 550 ), resulting in solder contacts 536 between 20 μm and 100 μm thick, which serve as the core of the logic chip package structure 520 . The semiconductor wafer 100 of the single-layer chip package structure or chiplet 550 may be the FPGAIC chip 200 of FIGS. 8A to 8J, wherein the semiconductor chip 100 used as the single-layer chip package structure or chiplet 550 of the HBM chip package structure 560 It may be an HBMIC die 251, such as a DRAM die, SRAM die, MRAM die, or RRAM die. An underfill material 537 (eg, a polymer) may be formed between the HBM chip package structure 560 and the logic chip package structure 520 and encapsulate the solder contacts 536, an NVM chip package structure 510 (which may be shown in Figure 28G) The metal bumps, studs or pads 570 of the single-layer chip package structure or chiplet 550) can be adhered to the metal bumps or pads 583 of the HBM chip package structure 560 to produce solder joints having a thickness between 20 μm and 100 μm. Point 541 is in between, where the semiconductor chip 100 used as the single layer chip package structure of the NVM chip package structure 510 or the chiplet 550 can be a NAND flash chip or a NOR flash chip as in FIGS. 11A to 11N , and no copper pillars 158 are provided in the single-layer chip package structure or the polymer layer 92 of the chiplet 550 in the structure in FIG. 28G, this structure can be used as the NVM chip package structure 510, an underfill material 542 (eg polymer ) can be formed between the NVM chip package structure 510 and the HBM chip package structure 560 and encapsulate the solder contacts 541 . The metal pads or bumps 583 provided by the logic chip package structure 520 are adhered to the circuit board 530 to form solder contacts 521 with a thickness between 20 μm and 100 μm. ) may be formed between the logic chip package structure 520 and the circuit board 530 and enclose the solder contacts 521 , and a plurality of solder bumps or balls 523 may be provided on the bottom of the circuit board 530 in a matrix pattern. Alternatively, the BISD 79 of the HBM chip package structure 560 can be omitted, that is, the HBM chip package structure 560 has a structure similar to that of the single-layer chip package structure or the small chip 550 in FIG. 28G, and the metal bumps provided by the NVM chip package structure 510, Posts or pads 570 are attached to the copper posts 158 of the HBM chip package structure 560 and form solder contacts 516 therebetween as shown in Figure 29C. Alternatively, the HBM chip package structure 560 has a structure similar to that of the single-layer chip package structure or the small chip 550 in FIG. Metal pads or bumps 583 to form solder contacts 516 in Figure 29B therebetween. It should be noted that the metal pads or bumps 583 of the HBM chip package structure 560 may include a first set of dummy metal pads or bumps 583a respectively bonded to the metal bumps, studs or pads 570 of the NVM chip package structure 510 , to generate the solder contact 516a as shown in FIG. 29B, as the connection ground reference voltage, the metal pads or bumps 583 may further include a second set of dummy metal pads or bumps 583a respectively bonded to the NVM chip package structure 510 metal bumps, studs or pads 570 to create solder contacts 516b as shown in Figure 29B, these solder contacts 516b do not have any electrical function, wherein the first and second sets of solder contacts can be Vertically above the HBMIC chip 251 of the HBM chip package structure 560 . Communication between the FPGAIC chip 200 and the HBMIC chip 251 can be via a set of small I/O circuits 203 of the HBMIC chip 251 , a set of metal pads, wires or connecting lines 108 of the HBMIC chip 251 , TISD or TISD of the HBM chip package 560 . The interconnection wire metal layer 27 of the FISD101, the interconnection wire metal layer 27 of the BISD79 of the logic chip package structure 520, a set of metal pads, wires or connecting wires 108 of the FPGAIC chip 200, and a set of small I/O circuits of the FPGAIC chip 203 is provided, and its communication has a data bit width greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K or 16K, wherein each small I/O circuit 203 of the HBMIC chip 251 and the FPGAIC chip 200 can be used as shown in Figure 5B One of the miniature drivers 374 , miniature receivers and miniature ESD protection circuits 373 are constructed and coupled to the I/O provided by the metal pads, wires or wires 108 of each HBMIC chip 251 and FPGAIC chip 200 O pads 372, in addition to the FPGAIC die 200, the semiconductor die 100 for the single-layer die package structure of the logic die package structure 520 or the chiplet 550 may be a CPU die, GPU die, TPU die, APU die or DSP die.

FIG. 29I is a schematic cross-sectional view of a POP packaging structure for a ninth type non-volatile programmable logic driver according to an embodiment of the present invention. As shown in FIG. 29I, in FIG. 29I, the ninth type non-volatile programmable logic driver The POP package structure 610 is similar to the POP package structure in FIG. 29H, the component numbers in FIG. 29H and FIG. 29I are the same, and the disclosure of each component in FIG. 29I can refer to the disclosure description in FIG. 29H, The difference between the POP package structure 610 of the ninth type non-volatile programmable logic driver in FIG. 29I and the POP package structure in FIG. 29H is that when the POP package structure 610 of the ninth type non-volatile programmable logic driver is formed , a single-layer die package structure or die 550 as in FIG. 28K may be provided as an I/O die package structure 540 positioned between the NVM die package structure 510 and the HBM die package structure 560 for the I/O die package structure The semiconductor die 100 in the single-layer chip package structure of structure 540 or chiplet 550 may be a dedicated I/O die 265 of FIGS. 11A to 11N, metal bumps, posts or The pads 570 may be adhered to the metal pads or bumps 583 of the HBM chip package structure 560 (which may be the single-layer chip package structure or die 550 in Figure 28K) to produce a solder thickness between 20 μm and 100 μm Contact 558 bits are in between. An underfill material 559 (eg, a polymer) may be formed between the I/O chip package structure 540 and the logic chip package structure 520 and encapsulate the solder contacts 558 , metal bumps, pillars of the NVM chip package structure 510 Or the pads 570 can be adhered to the metal bumps or pads 583 of the I/O chip package structure 540 (which can be the single layer chip package structure or the chiplet 550 in Figure 28G) to produce a thickness between 20 μm and 100 μm. An underfill material 542 (eg, polymer) may be formed between the NVM chip package structure 510 and the I/O chip package structure 540 and encapsulate the solder contact 541 between the two. Alternatively, the BISD 79 of the HBM chip package structure 560 can be omitted, that is, the HBM chip package structure 560 has a structure similar to the single-layer chip package structure or the small chip 550 in Fig. 28G, the metal bumps of the I/O chip package structure 540, Posts or pads 570 may be adhered to the copper posts 158 of the HBM chip package structure 560 to form solder contacts therebetween as shown in Figure 29C. Alternatively, the BISD 79 of the I/O chip package structure 540 can be omitted, that is, the I/O chip package structure 540 has a similar structure to the single-layer chip package structure or chiplet 550 in FIG. 28G, and the NVM chip package structure 510 provides the Metal bumps, posts or pads 570 are attached to the copper posts 158 of the I/O chip package structure 540 and form solder contacts 516 therebetween as shown in Figure 29C. Alternatively, the I/O chip package structure 540 has a similar structure to the single-layer chip package structure or chiplet 550 in FIG. 28I, and the metal bumps, posts or pads 570 provided by the NVM chip package structure 510 are attached to the I/O chip The metal pads or bumps 583 of the package structure 540 form the solder contacts 516 in Figure 29B therebetween. It should be noted that the metal pads or bumps 583 of the I/O chip package structure 540 may include a first set of dummy metal pads or bumps 583a respectively bonded to the metal bumps, studs or contacts of the NVM chip package structure 510. Pads 570 to create solder contacts 516a as shown in Figure 29B as a connection to the ground reference voltage, metal pads or bumps 583 may additionally include a second set of dummy metal pads or bumps 583a respectively bonded to the NVM chip package Metal bumps, pillars or pads 570 of structure 510 to produce solder contacts 516b as shown in FIG. 29B, these solder contacts 516b do not have any electrical function, wherein the first and second sets of solder contacts The dots may be positioned vertically above the dedicated I/O die 265 of the I/O die package structure 540 . Alternatively, each HBM chip package structure 560 has a similar structure to the single-layer chip package structure or chiplet 550 in Figure 28I, and each I/O chip package structure 540 may be provided with metal bumps, posts, or pads 570 Attached to the metal pads or bumps 583 of the HBM chip package structure 560 to produce solder contacts 558 between the two as shown in Figure 29B, note that the metal pads or bumps of the HBM chip package structure 560 Block 583 may include a third set of dummy metal pads or bumps 583a respectively bonded to metal bumps, studs or pads 570 in I/O chip package structure 540 to produce solder contacts as shown in Figure 29B 516a, as a connection to the ground reference voltage, the metal pads or bumps 583 may further include a fourth set of dummy metal pads or bumps 583a respectively bonded to the metal bumps, studs or pads 570 of the I/O chip package structure 540 , to produce solder contacts 516a as shown in FIG. 29B, these solder contacts 516a do not have any electrical function, wherein the third and fourth sets of solder contacts can be positioned vertically on the HBMIC of the HBM chip package structure 560 Above wafer 251 . The dedicated I/O chip 265 of the I/O chip package structure 540 may include a small I/O circuit 203 in sequence through the interconnection wire metal layer 27 of the TISD or FISD 101 of the I/O chip package structure 540, one of which is soldered Point 558 , the interconnection wire metal layer 27 of BISD79 of the HBM chip package structure 560 , one of the copper pillars 158 of the HBM chip package structure 560 , the interconnection wire metal layer 27 of the TISD or FISD101 of the HBM chip package structure 560 , among which A solder pad 536 , the interconnect metal layer 27 of the TISD or FISD 101 of the logic chip package 520 and one of the metal pads, wires or wires 108 of the FPGAIC chip 200 are coupled to the FPGAIC chip of the logic chip package 520 A small I/O circuit 203 of 200; the dedicated I/O chip 265 of the I/O chip package structure 540 includes a small I/O circuit 203 through one of the metal pads of the I/O chip package structure 540, Wire or connecting wire 108, Interconnect wire metal layer 27 of TISD or FISD 101 of I/O chip package structure 540, one of the solder contacts 558, Interconnect wire metal layer 27 of BISD79 of HBM chip package structure 560, HBM chip One of the copper pillars 158 of the package structure 560 , the interconnecting wire metal layer 27 of the TISD or FISD 101 of the HBM chip package structure 560 and one of the metal pads, lines or connecting lines 108 of the HBMIC chip 251 are coupled to the HBM chip package A small I/O circuit 203 of the HBMIC chip 251 of the structure 560; the dedicated I/O chip 265 of the I/O chip package structure 540 includes a small I/O circuit 203 through the I/O chip package structure 540 in sequence A metal pad, wire or connecting line 108, the TISD of the I/O chip package structure 540 or the interconnection line metal layer 27 of the FISD 101, one of the copper pillars 158 of the I/O chip package structure 540, the I/O chip The interconnect metal layer 27 of the BISD79 of the package structure 540, one of the solder contacts 541, the interconnect metal layer 27 of the TISD or FISD101 of the NVM chip package structure 510, and one of the non-volatile memory IC chip 250 are Pads, wires or wires 108 are coupled to a small I/O circuit 203 of the non-volatile memory IC chip 250 of the NVM chip package 510, each of which is dedicated I/O chip 265, HBMIC chip 251, FPGAIC chip 200 and the small I/O circuit 203 of the non-volatile memory IC chip 250 can be constructed from a small driver 374, a small receiver 375, and a small ESD protection circuit 373 as shown in FIG. 5B, and are coupled to each Dedicated I/O chip 265, HBMIC chip 251, FP The I/O pads 372 provided by the metal pads, wires, or connecting wires 108 of the GAIC chip 200 and the non-volatile memory IC chip 250 . The dedicated I/O chip 265 of the I/O chip package structure 540 may include a large I/O circuit 341 in sequence through one of the metal pads, wires or connecting lines 108 of the dedicated I/O chip 265, the I/O chip The interconnection wire metal layer 27 of TISD or FISD101 of the package structure 540 , one of the solder contacts 558 , the interconnection wire metal layer 27 of BISD79 of the HBM chip package structure 560 , and one of the copper pillars 158 of the HBM chip package structure 560 , the interconnection wire metal layer 27 of the TISD or FISD101 of the HBM chip package structure 560, one of the solder contacts 536, the interconnection wire metal layer 27 of the TISD or FISD101 of the logic chip package structure 520, and the logic chip package structure 520. A copper pillar 158, the interconnect wire metal layer 27 of the BISD 79 of the logic chip package structure 520, one of the solder contacts 521 and the circuit board 530 are coupled to one of the solder bumps or balls 523 for external connection, The large I/O circuit 342 of the dedicated I/O chip 265 can be constructed by a large driver 274, a large receiver 275 and a large ESD protection circuit 273 as shown in FIG. 5A, and is coupled to the dedicated I/O The I/O pads 272 provided by one of the metal pads, wires, or connecting wires 108 of the chips 265 , other than the FPGAIC chip 200 , are used for the single-layer chip package structure of the logic chip package structure 520 or the chiplet 550 The semiconductor die 100 may be a CPU die, a GPU die, a TPU die, an APU die, or a DSP die.

FIG. 29J is a schematic cross-sectional view of a POP packaging structure for a tenth type non-volatile programmable logic driver according to an embodiment of the present invention. As shown in FIG. 29J, the tenth type non-volatile programmable logic driver is shown in FIG. 29J. In the POP package structure 610, the metal bumps, posts or pads 570 of the plurality of I/O chip package structures 540 (which may be the multi-chip package structure or the die 550 in Figure 28K) can be attached to the logic driver 300 ( It can be the metal pads or bumps 583 of the multi-chip package structure or the die 550 in Figure 28K to create the solder contacts 536 between the two with a thickness between 20 μm and 100 μm, which serve as logic drivers Each semiconductor die 100 of the multi-die package structure or die 550 of 300 has an arrangement as in FIGS. 11A-11N for one of the standard commercial logic drivers 300, each semiconductor die 100 may be a standard commercial FPGA IC Chip 200, DPIIC chip 410, NVMIC chip 250 (such as NAND flash memory chip or NOR flash memory chip), dedicated I/O chip 265, PCIC chip 269 (such as DSP chip, CPU chip, GPU chip, TPU chips or APU chips), HBM memory chips (eg, DRAM chips, SRAM chips, MRAM chips, or RRAM chips), dedicated control chips 260, dedicated control and I/O chips 266, IAC chips 402 (eg, analog IC chips) , a mixed mode IC chip or a radio frequency (RF) IC chip), a DCICA chip 267 or a DCDI/OIAC chip 268, wherein the semiconductor chip 100 in the single-layer chip package structure for the I/O chip package structure 540 or the chiplet 550 can be is a dedicated I/O die 265, an underfill material 537 (eg, a polymer) may be formed between the I/O die package 540 and the logic driver 300 and enclose the solder contacts 536, a plurality of NVM die packages Metal bumps, studs or pads 570 of 510 (which may be the single layer chip package structure or die 550 in Figure 28G) can be attached to the metal bumps or pads 583 of the I/O chip package structure 540 to produce Solder contacts 541 with a thickness between 20 μm and 100 μm are therebetween, wherein each semiconductor chip 100 of the single-layer chip package structure or chiplet 550 as the NVM chip package structure 510 has as shown in FIGS. 11A to 11N The NAND flash memory chip or NOR flash memory chip in the figure, and the single-layer chip package structure in FIG. 28G or the package structure in which the copper pillars 158 are not provided in the polymer layer 92 in the small chip 550 may also be As the NVM chip package structure 510 . An underfill material 542 (eg, polymer) may be formed between each NVM chip package structure 510 and the I/O chip package structure 540 and encapsulate the solder contacts 541 . The metal bumps, posts or pads 570 provided by the logic driver 300 are adhered to the circuit board 530 to produce solder contacts 521 with a thickness between 20 μm and 100 μm in between, and an underfill material 537 (such as a polymer (substrate) may be formed between the logic driver 300 and the circuit board 530 and enclose the solder pads 521, and a plurality of solder bumps or balls 523 may be disposed on the bottom of the circuit board 530 in a matrix pattern. Alternatively, the BISD 79 of the I/O chip package structure 540 may be omitted, ie, the I/O chip package structure 540 has a similar structure to the single-layer chip package structure or chiplet 550 in Figure 28G, and each NVM chip package structure 510 The provided metal bumps, posts or pads 570 are attached to the copper posts 158 of the I/O chip package structure 540 and form solder contacts 516 as shown in FIG. 29C therebetween. Alternatively, each I/O chip package structure 540 has a similar structure to the single-layer chip package structure or chiplet 550 in FIG. 28I, and the metal bumps, posts or pads 570 provided by each NVM chip package structure 510 are attached to the The metal pads or bumps 583 of the I/O chip package structure 540 form the solder contacts 516 in FIG. 29B therebetween. It should be noted that the metal pads or bumps 583 of the I/O chip package structure 540 may include a first set of dummy metal pads or bumps 583a respectively bonded to the metal bumps, studs or contacts of the NVM chip package structure 510. Pads 570 to create solder contacts 516a as shown in Figure 29B as a connection to the ground reference voltage, metal pads or bumps 583 may additionally include a second set of dummy metal pads or bumps 583a respectively bonded to the NVM chip package Metal bumps, pillars or pads 570 of structure 510 to produce solder contacts 516b as shown in FIG. 29B, these solder contacts 516b do not have any electrical function, wherein the first and second sets of solder contacts The dots may be positioned vertically above the dedicated I/O die 265 of the I/O die package structure 540 . In each I/O chip package structure 540, its dedicated I/O chip 265 may include a small I/O circuit 203 in sequence through the dedicated I/O chip 265's metal pads, wires or connecting lines 108, TISD or One of the interconnect metal layer 27 of the FISD101, the solder contact 536 between the I/O chip package structure 540 and the logic driver 300, the interconnect metal layer 27 of the BISD 79 of the logic driver 300, and the logic driver 300 Copper pillars 158 , interconnect metal layers 27 of TISD or FISD 101 of logic driver 300 , and metal pads, wires or wires 108 of each FPGAIC chip and/or PCIC chip 269 are coupled to each FPGAIC chip of logic driver 300 200 and/or a small I/O circuit 203 of the PCIC chip 269; the dedicated I/O chip 265 includes another small I/O circuit 203 in sequence via one of the metal pads, wires or The interconnecting wire metal layer 27 of the connecting wire 108, TISD or FISD 101, one of the copper pillars 158, the interconnecting wire metal layer 27 of the BISD 79, between each I/O chip package structure 540 and the NVM chip package structure 510 The solder pads 536 of the NVMIC chip package structure, the interconnection wire metal layer 27 of the TISD or FISD 101 of the NVM chip package structure, and the metal pads, wires or connection wires 108 of the NVMIC chip 250 are coupled to the vertical position at each I NVM chip package structure 510 over /O chip package structure 540 ; each of the above-mentioned dedicated I/O chips 265 , non-volatile memory IC chips 250 of NVM chip package structure 510 , and logic drivers of I/O chip package structure 540 In the FPGAIC chip 200 and/or the PCIC chip 269 of 300, each small I/O circuit 203 can be constructed by a small driver 374, a small receiver 375, and a small ESD protection circuit 373 as shown in FIG. 5B, and is coupled Connected to I/O pads 372 provided by metal pads, wires, or connecting wires 108 . In each I/O chip package structure 540, the dedicated I/O chip 265 may include a large I/O circuit 341 via one of the metal pads, wires or connecting lines 108, The interconnect metal layer 27 of the TISD or FISD 101, one of the solder contacts 536 between the logic driver 300 and each I/O chip package 540, the interconnect metal layer 27 of the BISD 79 of the logic driver 300, One of the copper pillars 158 of the logic driver 300, the interconnect metal layer 27 of the TISD or FISD 101 of the logic driver 300, one of the solder contacts 521 and the circuit board 530 are coupled to one of the solder bumps or balls 523, For external connections, where the large I/O circuit 342 of the dedicated I/O chip 265 may be constructed as a large driver 274, a large receiver 275, and a large ESD protection circuit 273 as shown in FIG. 5A, and is coupled to I/O pads 272 provided by one of the dedicated I/O chips 265 metal pads, wires, or connection wires 108 .

FIG. 29K is a schematic cross-sectional view of a POP packaging structure for an eleventh type non-volatile programmable logic driver according to an embodiment of the present invention. As shown in FIG. 29K, in FIG. 29K, the eleventh type non-volatile programmable logic driver The POP package structure 610 of the logic driver is similar to the POP package structure in Fig. 29J, and the component numbers in Fig. 29K and Fig. 29J are the same, and the disclosure of each element in Fig. 29K can refer to the disclosure in Fig. 29J It is explained that the difference between the POP package structure 610 of the eleventh type non-volatile programmable logic driver in Fig. 29K and the POP package structure in Fig. 29J is that in the eleventh type non-volatile programmable logic driver in Fig. 29K In the POP package structure 610 of the driver, the metal bumps, posts or pads 570 of the plurality of HBM chip package structures 560 (which may be the multi-die package structure or the die 550 in FIG. 28K) can be attached to the logic driver 300 (which Can be metal bumps, studs, or pads 570 of the multi-chip package structure or die 550 in Figure 28K to produce solder contacts 536 between 20 μm and 100 μm thick, where the logic Each semiconductor die 100 of the multi-die package structure or die 550 of the driver 300 has the arrangement as shown in FIGS. 11A-11N for one of the standard commercial logic drivers 300, each semiconductor die 100 may be a standard commercial FPGAIC chip 200, DPIIC chip 410, NVMIC chip 250 (such as NAND flash memory chip or NOR flash memory chip), dedicated I/O chip 265, PCIC chip 269 (such as DSP chip, CPU chip, GPU chip) , TPU chips or APU chips), HBM memory chips (such as DRAM chips, SRAM chips, MRAM chips, or RRAM chips), dedicated control chips 260, dedicated control and I/O chips 266, IAC chips 402 (such as analog ICs) die, mixed mode IC die or radio frequency (RF) IC die), DCICA die 267 or DCDI/OIAC die 268, where the semiconductor die 100 in the single layer die package structure or dielet 550 for the HBM die package structure 560 may be HBMIC chip 251, such as DRAM chip, SRAM chip, MRAM chip or RRAM chip, underfill material 537 (eg, polymer) can be formed between HBM chip package structure 560 and logic driver 300 and encapsulate the solder contacts 536. Metal bumps, studs or pads 570 of a plurality of I/O chip package structures 540 (which may be single layer chip package structures or die 550 in Figure 28K) can be adhered to metal bumps of HBM chip package structure 560 bumps or pads 583 to produce solder contacts 558 between 20 μm and 100 μm in thickness, where a single unit of the I/O chip package structure 540 is Each semiconductor die 100 of the layered die package structure or dielet 550 is an I/O die 265 . An underfill material 559 (eg, polymer) may be formed between each HBM chip package structure 560 and the I/O chip package structure 540 and encapsulate the solder contacts 558 . Metal bumps or pads 583 provided by logic driver 300 are adhered to circuit board 530 to produce solder contacts 521 between 20 μm and 100 μm thick, underfill material 537 (eg polymer) Solder pads 521 may be formed between the logic driver 300 and the circuit board 530 and encapsulated. Alternatively, the BISD 79 of the HBM chip package structure 560 may be omitted, that is, the HBM chip package structure 560 has a similar structure to the single-layer chip package structure or chiplet 550 in Figure 28G, and each I/O chip package structure 540 provides a Metal bumps, posts or pads 570 are attached to the copper posts 158 of the HBM chip package structure 560 and form solder contacts 516 therebetween as shown in Figure 29C. Alternatively, each HBM chip package structure 560 has a structure similar to the single-layer chip package structure or chiplet 550 in FIG. 28I, and the metal bumps, posts or pads 570 provided by each I/O chip package structure 540 are attached to the The metal pads or bumps 583 of the HBM chip package structure 560 form the solder contacts 516 in FIG. 29B therebetween. It should be noted that the metal pads or bumps 583 of the HBM chip package structure 560 may include a third set of dummy metal pads or bumps 583a respectively bonded to the metal bumps, studs or contacts of the I/O chip package structure 540. Pad 570 to generate a third set of solder pads 516a as shown in FIG. 29B as a connection ground reference voltage, metal pads or bumps 583 may further include a fourth set of dummy metal pads or bumps 583a respectively bonded to The metal bumps, pillars or pads 570 of the I/O chip package structure 540 to generate the fourth set of solder contacts 516b as shown in FIG. 29B, the fourth set of solder contacts 516b do not have any electrical function , wherein the first set and the second set of solder contacts can be positioned vertically above the HBMIC chip 251 of the HBM chip package structure 560 . In the HBM chip package structure 560 , the communication between the HBMIC chip 251 and one of the logic drivers 300 , the FPGAIC chip 200 and/or the PCIC chip 269 (located vertically below the HBMIC chip 251 ), can be performed by a set of small I/O circuit 203, a set of metal pads, wires or connecting lines 108 of HBMIC chip 251, interconnect metal layer 27 of TISD or FISD 101 of HBM chip package structure 560, between logic driver 300 and each HBM chip package A set of solder contacts 536 between the structures 560, the interconnect metal layer 27 of the TISD or FISD 101 of the logic driver 300, a set of metal pads of one of the FPGAIC die 200 and/or the PCIC die 269 of the logic driver 300, A set of small I/O circuits 203 of one of the FPGAIC chip 200 and/or the PCIC chip 269 of the line or connection line 108 and the logic driver 300 provides this communication with a one-bit width equal to or greater than 64,128,256,512,1024,2048,4096 , 8K or 16K, in one of the FPGAIC chip 200 and/or the PCIC chip 269 of the HBMIC chip 251 and the logic driver 300 of the HBM chip package structure 560, each small I/O circuit 203 can be as A miniature driver 374, a miniature receiver 375, and a miniature ESD protection circuit 373 are constructed and coupled to the I/O pads 372 provided by one of the metal pads, wires, or connection wires 108, at each I/O pad 372. In the /O chip package structure 540 , the dedicated I/O chip 265 may include a small I/O circuit 203 which is sequentially interconnected through the metal pads, wires or connecting wires 108 , TISD or FISD 101 of the dedicated I/O chip 265 . The wire metal layer 27 , the solder contact 536 between one of the HBM chip package structures 560 and the logic driver 300 , the interconnecting wire metal layer 27 of the BISD 79 of the HBM chip package structure 560 , one of the HBM chip package structure 560 Interaction of a copper pillar 158 , the interconnection metal layer 27 of the TISD or FISD 101 of the HBM chip package 560 , the solder contact 536 between the HBM chip package 560 and the logic driver 300 , and the TISD or FISD 101 of the logic driver 300 The wire metal layer 27 and the metal pads, wires or wires 108 of each FPGAIC chip and/or PCIC chip 269 are coupled to a small I/O of each FPGAIC chip 200 and/or PCIC chip 269 of the logic driver 300 Circuit 203; dedicated I/O chip 265 includes another small I/O circuit 203 in sequence via one of the metal pads, wires or connecting wires 108, TISD of the dedicated I/O chip 265 Or the interconnect metal layer 27 of FISD101, the solder contacts 536 between each I/O chip package structure 540 and one of the HBM chip package structures 560, the interconnect line metal of BISD 79 of the HBM chip package structure 560 Layer 27 , one of the copper pillars 158 of the HBM chip package structure 560 , one of the interconnect wire metal layers 27 of the TISD or FISD 101 of the one of the HBM chip package structure 560 and one of the metal of the HBMIC chip 251 of the HBM chip package structure 560 Pads, wires or wires 108 are coupled to the HBMIC die 251 of the HBM die package 560 located vertically below each I/O die package 540; 265. In the HBMIC chip 251 of the HBM chip package structure 560 and the FPGAIC chip 200 and/or the PCIC chip 269 of the logic driver 300, each small I/O circuit 203 can be a small driver 374, a small receiver as shown in FIG. 5B 375 and a small ESD protection circuit 373 are constructed and coupled to I/O pads 372 provided by metal pads, wires, or connecting wires 108 . In each I/O chip package structure 540, the dedicated I/O chip 265 may include a large I/O circuit 341 through one of the metal pads, wires or connecting lines 108, The interconnect metal layer 27 of the TISD or FISD101, one of the solder contacts 536 between one of the HBM chip package structures 560 and each I/O chip package structure 540, one of the BISD 79 of the HBM chip package structure 560 The interconnecting wire metal layer 27 , one of the copper pillars 158 of the HBM chip package structure 560 , the interconnecting wire metal layer 27 of the TISD or FISD101 of the one of the HBM chip package structure 560 , and the one of the HBM chip package structure 560 One of the solder contacts 536 with the logical driver 300 , the interconnecting wire metal layer 27 of the TISD or FISD101 of the logical driver 300 , one of the copper pillars 158 of the logical driver 300 , and the interconnecting wire of the BISD79 of the logical driver 300 The metal layer 27, one of the solder contacts 521, and the circuit board 530 are coupled to one of the solder bumps or balls 523 for external connections, wherein the large I/O circuits 342 of the dedicated I/O chip 265 can be made as A large driver 274, a large receiver 275, and a large ESD protection circuit 273 are constructed in FIG. 5A, and are coupled to those provided by one of the metal pads, wires or wires 108 of the dedicated I/O chip 265 I/O pads 272.

In each of the first, second and fourth type non-volatile programmable logic drivers 610 in FIGS. 29A , 29B and 29D, the NVM chip package structure 510 is positioned vertically above the logic package structure 520 The non-volatile memory IC chips 250 of the NVM chip package 510 can be used to store data or information for the FPGA IC chip 200 for configuring the logic package 520, one (each) of the non-volatile memory IC chips 250 of the NVM chip package 510 can be used As: (1) store the result values for the LUTs 210, each result value can be sequentially routed through one of the bonding wires of the NVM chip package structure 510, the circuit board 513 of the NVM chip package structure 510, and one of the solder contacts 516 , the interconnect wire metal layer 27 of the BISD 79 of the logic package structure 520 (optionally but specifically for the fourth type of non-volatile programmable logic driver 610 ), one of the copper pillars 158 of the logic package structure 520 and the logic The interconnect metal layer 27 of the TISD or FISD 101 of the package structure 520 is loaded into the memory unit 490 of the FPGAIC chip 200 of the logic package structure 520; one wire bond wire, the lead frame of the NVM chip package structure 510, the interconnect wire metal layer 27 of the BISD 79 of the logic package structure 520 (optionally but specifically for the fourth type of non-volatile programmable logic driver 610), One of the copper pillars 158 of the logic package structure 520 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the memory cells 490 of the FPGAIC chip 200 of the logic package structure 520; these result values are the same as Associated with the second input data set of the multiplexer 211 of the programmable logic block 201 of the FPGAIC chip 200 (shown in FIG. 6A ) of the logic package structure 520 and/or used to store the pass/fail switch 258 Or the programming code of the cross-point switch 379 is sequentially passed through one of the bonding wires of the NVM chip package structure 510 , the circuit board 513 , one of the solder contacts 516 , and the interconnection wire metal layer 27 ( Optionally but specifically for the fourth type of non-volatile programmable logic driver 610), one of the copper pillars 158 of the logic package structure 520 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 is loaded into the memory unit 362 of the FPGAIC chip 200 of the logic package structure 520 in FIG. 7A to FIG. 7C; or the first option, through one of the NVM chip package structures 510, wire bonding, NVM The lead frame of the chip package structure 510, the interconnect wire metal layer 27 of the BISD 79 of the logic package structure 520 (alternatively but specifically for the fourth type The non-volatile programmable logic driver 610), one of the copper pillars 158 of the logic package structure 520, and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into FIGS. 7A to 7C In the memory unit 362 of the FPGAIC chip 200 of the logic package structure 520, the pass/no pass switch 258 or the cross-point switch 379 of the FPGAIC chip 200 of the logic package structure 520 is controlled to be coupled or not coupled to the two programmable interconnection lines 361 , wherein the programmable interconnect 361 is provided via one (or more) copper pillars 158 of the logic package structure 520 and/or the interconnect metal layer 27 of the TISD or FISD 101 and/or BISD 79 of the logic package 520, and ( 2) For storing the data or information of the FPGAIC chip 200 of the operation logic package structure 520, through the result value of the LUTs 210 and the programming code configuration of the pass/fail switch 258 or the crosspoint switch 379 to have a specific operation or function.

For example, in each of the first, second, and fourth type non-volatile programmable logic drivers 610 in FIGS. 29A, 29B, and 29D, the non-volatile memory ICs above the NVM chip package structure 510 The chip 250 may be a NOR flash memory chip for storing the result values of the LUTs 210 to be downloaded to the memory cells 490 of the FPGAIC chip 200 of the logic package structure 520 through the paths disclosed above. The second input data set of the multiplexer 211 of the programmable logic block 201 of the FPGAIC chip 200 of the package structure 520 (shown in FIG. 6A ) is associated with and/or stored in the pass/fail switch 258 or crosspoint switch The programming code of 379 is downloaded to the memory cell 362 of the FPGAIC chip 200 of the logic package structure 520 through the path disclosed above to control the passage of the FPGAIC chip 200 of the logic package structure 520 as shown in FIGS. 7A to 7C. Two programmable interconnect lines 361 are/are not coupled or not coupled through switch 258 or crosspoint switch 379 , wherein programmable interconnect lines 361 pass through one (or more) copper pillars 158 and/or logic of logic package structure 520 Provided by the interconnect metal layer 27 of the TISD or FISD 101 and/or BISD 79 of the package structure 520 . However, the non-volatile memory IC chip 250 under the NVM chip package 510 may be a NAND flash memory chip for storing data or information for the operation of one of the FPGA IC chips 200 of the logic driver 300 via the LUTs 210 The resulting value and the programming code configuration of pass/fail switch 258 or crosspoint switch 379 enables FPGAIC die 200 to have a particular operation or function.

In each of the third and fifth type non-volatile programmable logic drivers 610 in FIGS. 29C and 29E, the non-volatile memory ICs of the NVM chip package structure 510 that are positioned vertically above the logic package structure 520 The chip 250 can be used to store data or information of the FPGAIC chip 200 used to configure the logic package 520, and the non-volatile memory IC chip 250 of the NVM chip package 510 can be used to: (1) store the result values for the LUTs 210 , each result value can be sequentially passed through the interconnection wire metal layer 27 of the TISD or FISD101 of the NVM chip package structure 510, one of the solder contacts 516, and the interconnection wire metal layer 27 of the BISD79 of the logic package structure 520 (optional is loaded specifically but specifically for the fifth type of non-volatile programmable logic driver 610 ), one of the copper pillars 158 of the logic package structure 520 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 to the memory cells 490 of the FPGAIC chip 200 of the logic package structure 520; these result values are combined with the multiplexer 211 of the programmable logic block 201 of the FPGAIC chip 200 of the logic package structure 520 (as shown in FIG. 6A ). associated with the second input data set, and/or used to store the programming code of the pass/fail switch 258 or the cross-point switch 379, through the interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package 510, One of the solder contacts 516 , the interconnect wire metal layer 27 of the BISD 79 of the logic package structure 520 (alternatively but specifically for the fifth type of non-volatile programmable logic driver 610 ), the one of the logic package structure 520 A copper pillar 158 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the memory cells 362 of the FPGAIC chip 200 of the logic package structure 520 in FIGS. 7A to 7C to control The pass/no pass switch 258 or the cross-point switch 379 of the FPGAIC chip 200 of the logic package structure 520 is coupled or not coupled to two programmable interconnection lines 361 , wherein the programmable interconnection line 361 passes through one of the logic package structure 520 (or A plurality of) copper pillars 158 and/or the interconnection wire metal layer 27 of the TISD or FISD 101 and/or BISD 79 of the logic package structure 520 are provided, and (2) are used to store the data of the FPGAIC chip 200 for operating the logic package structure 520 or information, through the resulting values of the LUTs 210 and the programming code configuration of the pass/fail switch 258 or crosspoint switch 379 to have a specific operation or function.

In the sixth type of non-volatile programmable logic driver 610 in FIG. 29F, the non-volatile memory IC chip 250 positioned vertically above the logic package structure 520 can be used to store the data used to configure the logic package structure 520. The data or information of the FPGA IC chip 200, the non-volatile memory IC chip 250 of the NVM chip package structure 510 can be used to: (1) store the result values for the LUTs 210, each result value can be sequentially passed through one of the bonding contacts 531. The interconnect metal layer 27 of the BISD79 of the logic package structure 520, one of the copper pillars 158 of the logic package structure 520, and the interconnect line metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the logic package structure Memory cell 490 of FPGAIC chip 200 of 520; these result values are associated with second input data of multiplexer 211 of programmable logic block 201 of FPGAIC chip 200 of logic package 520 (shown in FIG. 6A ). The set association, and/or the programming code for storing the pass/fail switch 258 or the crosspoint switch 379, is sequentially passed through one of the bonding contacts 531, the interconnection wire metal layer 27 of the BISD 79 of the logic package structure 520, One of the copper pillars 158 of the logic package structure 520 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the memory of the FPGAIC chip 200 of the logic package structure 520 in FIGS. 7A to 7C . In the unit 362, the pass/no pass switch 258 or the cross-point switch 379 of the FPGAIC chip 200 of the control logic package structure 520 is coupled or not coupled to the two programmable interconnection lines 361, wherein the programmable interconnection lines 361 pass through the logic package One (or more) copper pillar(s) 158 of structure 520 and/or interconnect metal layer 27 of TISD or FISD 101 and/or BISD 79 of logic package structure 520 are provided, and (2) are used to store operational logic package structure 520 The data or information of the FPGAIC chip 200 is configured through the result value of the LUTs 210 and the programming code configuration of the pass/fail switch 258 or the crosspoint switch 379 to have a specific operation or function.

In the seventh type of non-volatile programmable logic driver 610 in FIG. 29G, the non-volatile memory IC chip 250 of the NVM chip package structure 510 positioned vertically above the logic package structure 520 may be used for storage for To configure the data or information of the FPGA IC chip 200 of the logic package structure 520, the non-volatile memory IC chip 250 of the NVM chip package structure 510 can be used as: (1) to store the result values for the LUTs 210, and each result value can be sequentially passed through The interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package structure 510 , one of the solder contacts 541 , each interconnect metal layer 27 of the BISD 79 of the I/O chip package structure 540 (optionally), One of the copper pillars 158 of the I/O chip package structure 540 , each interconnect metal layer 27 of the TISD or FISD 101 of the I/O chip package structure 540 , one of the solder contacts 536 , BISD 79 of the logic package structure 520 The interconnect metal layer 27 of the logic package structure 520 , one of the copper pillars 158 of the logic package structure 520 and the interconnect line metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the memory of the FPGAIC chip 200 of the logic package structure 520 unit 490'; the result values are associated with the second input data set of the multiplexer 211 of the programmable logic block 201 of the FPGAIC chip 200 of the logic package structure 520 (shown in FIG. 6A), and/or The programming code for storing the pass/fail switch 258 or the cross point switch 379 is sequentially passed through the interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package 510, one of the solder contacts 541, and the I/O chip Each of the interconnect metal layers 27 of the BISD 79 of the package structure 540 (optionally), one of the copper pillars 158 of the I/O chip package structure 540 , each of the TISD or FISD 101 of the I/O chip package structure 540 The interconnect metal layer 27 , one of the solder contacts 536 , the interconnect metal layer 27 of the BISD 79 of the logic package structure 520 , one of the copper pillars 158 of the logic package structure 520 , and one of the TISD or FISD 101 of the logic package structure 520 The interconnect metal layer 27 is loaded into the memory unit 362 of the FPGAIC chip 200 of the logic package structure 520 in FIGS. 7A to 7C to control the pass/no pass switch 258 of the FPGAIC chip 200 of the logic package structure 520 or the cross-point switch 379 is coupled or not coupled to two programmable interconnect lines 361 , wherein the programmable interconnect lines 361 pass through one (or more) copper pillars 158 of the logic package structure 520 and/or the TISD of the logic package structure 520 or provided by the interconnecting wire metal layer 27 of FISD101 and/or BISD79, and (2) The data or information of the FPGAIC chip 200 for storing the operation logic package structure 520 is configured to have a specific operation or function through the result value of the LUTs 210 and the programming code configuration of the pass/fail switch 258 or the crosspoint switch 379 .

In the eighth-type non-volatile programmable logic driver 610 in FIG. 29H, the non-volatile memory IC chip 250 of the NVM chip package structure 510 positioned vertically above the logic package structure 520 can be used for storage for Configuring the data or information of the FPGA IC chip 200 of the logic package structure 520, the non-volatile memory IC chip 250 of the NVM chip package structure 510 can be used as: (1) to store the result values for the LUTs 210, and each result value can be sequentially passed through The interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package structure 510 , one of the solder contacts 541 , the interconnect metal layer 27 of the BISD 79 of the HBM package structure 560 (optionally), the HBM package structure 560 One of the copper pillars 158 , each interconnect metal layer 27 of the TISD or FISD 101 of the HBM package structure 560 , one of the solder contacts 536 , and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are Loaded into the memory cells 490 of the FPGAIC chip 200 of the logic package structure 520; these result values are combined with the multiplexer of the programmable logic block 201 of the FPGAIC chip 200 of the logic package structure 520 (as shown in FIG. 6A). The second input data set of 211 is associated with and/or used to store the programming code for pass/fail switch 258 or crosspoint switch 379, sequentially through the interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package 510 , one of the solder contacts 541 , the interconnecting wire metal layer 27 of the BISD79 of the HBM package structure 560 (optionally), one of the copper pillars 158 of the HBM package structure 560 , one of the TISD or FISD 101 of the HBM package structure 560 Each interconnect metal layer 27, one of the solder contacts 536 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the FPGAIC of the logic package structure 520 in FIGS. 7A-7C In the memory unit 362 of the chip 200, the pass/no pass switch 258 or the cross-point switch 379 of the FPGAIC chip 200 of the control logic package structure 520 is coupled or not coupled to two programmable interconnection lines 361, wherein the programmable interconnection Line 361 is provided via one (or more) copper pillar(s) 158 of logic package structure 520 and/or the interconnect wire metal layer 27 of TISD or FISD 101 and/or BISD 79 of logic package structure 520, and (2) for storage operations The data or information of the FPGAIC chip 200 of the logic package structure 520 is configured to have a specific operation or function through the result value of the LUTs 210 and the programming code configuration of the pass/fail switch 258 or the crosspoint switch 379 .

In the ninth type of non-volatile programmable logic driver 610 in FIG. 29I, the non-volatile memory IC chip 250 of the NVM chip package structure 510 positioned vertically above the logic package structure 520 can be used for storage for Configuring the data or information of the FPGA IC chip 200 of the logic package structure 520, the non-volatile memory IC chip 250 of the NVM chip package structure 510 can be used as: (1) to store the result values for the LUTs 210, and each result value can be sequentially passed through The interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package structure 510, one of the solder contacts 541, the interconnect metal layer 27 of the BISD 79 of the I/O chip package structure 540 (optionally), the I/O Interaction of one of the copper pillars 158 of the O chip package structure 540 , each of the interconnecting metal layers 27 of the TISD or FISD 101 of the I/O chip package structure 540 , one of the solder contacts 558 , and the BISD 79 of the HBM package structure 560 The connection wire metal layer 27 (optionally), one of the copper pillars 158 of the HBM package structure 560, each of the interconnecting wire metal layers 27 of the TISD or FISD 101 of the HBM package structure 560, one of the solder contacts 536 and The interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 is loaded into the memory cells 490 of the FPGAIC chip 200 of the logic package structure 520; 6A) associated with the second input data set of the multiplexer 211 of the programmable logic block 201, and/or used to store the programming code for the pass/fail switch 258 or the crosspoint switch 379, in sequence Via the interconnect metal layer 27 of the TISD or FISD 101 of the NVM chip package 510, one of the solder contacts 541, the interconnect metal layer 27 of the BISD 79 of the I/O chip package 540 (optionally), I One of the copper pillars 158 of the /O chip package structure 540 , each interconnection wire metal layer 27 of the TISD or FISD 101 of the I/O chip package structure 540 , one of the solder contacts 558 , and the BISD 79 of the HBM package structure 560 Interconnect metal layer 27 (optional), one of the copper pillars 158 of the HBM package structure 560, each of the interconnect metal layers 27 of the TISD or FISD 101 of the HBM package structure 560, one of the solder contacts 536 and the interconnect metal layer 27 of the TISD or FISD 101 of the logic package structure 520 are loaded into the memory cells 362 of the FPGAIC chip 200 of the logic package structure 520 in FIGS. 7A to 7C to control the logic package structure 520 Pass/fail switch 258 or intersection of FPGAIC chip 200 The switch 379 is coupled or not coupled to two programmable interconnection lines 361 , wherein the programmable interconnection lines 361 pass through one (or more) copper pillars 158 of the logic package structure 520 and/or the TISD or FISD 101 of the logic package structure 520 and and/or provided by the interconnect metal layer 27 of the BISD 79, and (2) for storing data or information of the FPGAIC chip 200 operating the logic package structure 520, the result value via the LUTs 210 and the pass/fail switch 258 or crosspoint switch The 379's programming code configures it for a specific operation or function.

In the tenth type non-volatile programmable logic driver 610 in FIG. 29J, the non-volatile memory IC chip 250 of each NVM chip package structure 510 vertically above the logic driver 300 can be used for storage In configuring the data or information of the FPGA IC chip 200 of the logic driver 300, the non-volatile memory IC chip 250 of each NVM chip package structure 510 can be used to: (1) store the result values for the LUTs 210, and each result value can be sequence through the interconnection wire metal layer 27 of the TISD or FISD 101 of each NVM chip package structure 510 , one of the solder contacts 541 under each NVM chip package structure 510 Interconnect wire metal layer 27 of BISD 79 of one of the I/O chip packages 540 (optionally), one of the copper pillars 158 of one of the I/O chip packages 540, one of the I/O Each interconnection wire metal layer 27 of the O chip package structure 540 TISD or FISD 101 , one of the solder contacts 536 under one of the I/O chip package structures 540 , each interconnection wire of the BISD 79 of the logic driver 300 The metal layer 27 and the interconnect metal layer 27 of the TISD or FISD 101 of the logical driver 300 are loaded into the memory cell 490 of one of the FPGAIC chips 200 of the logical driver 300 ; associated with the second input data set of the multiplexer 211 of the programmable logic block 201 of an FPGAIC chip 200 (shown in FIG. 6A) and/or used to store the pass/fail switch 258 or crosspoint switch 379 of programming codes are sequentially passed through the interconnection wire metal layer 27 of the TISD or FISD 101 of each NVM chip package structure 510, one of the solder contacts 541 under each NVM chip package structure 510, one of the I The interconnection wire metal layer 27 (optional) of the BISD 79 of the /O chip package structure 540 , one of the copper pillars 158 of one of the I/O chip package structures 540 , one of the I/O chip package structures 540 Each interconnect metal layer 27 of the TISD or FISD 101, one of the solder contacts 536 under one of the I/O chip package structures 540, each interconnect metal layer 27 of the BISD 79 of the logic driver 300 , one of the copper pillars 158 of the logical driver 300 and the interconnect metal layer 27 of the TISD or FISD 101 of the logical driver 300 are loaded into the memory of the FPGAIC chip 200 of one of the logical drivers 300 in FIGS. 7A to 7C in the body unit 362 to control the pass/no pass switch 258 or The cross-point switch 379 is coupled or not coupled to two programmable interconnect lines 361 , wherein the programmable interconnect lines 361 pass through one (or more) copper pillars 158 of the logic driver 300 and/or the TISD or FISD 101 of the logic driver 300 and and/or provided by the interconnect metal layer 27 of the BISD 79, and (2) for storing data or information of one of the FPGAIC chips 200 operating the logic driver 300, the result value via the LUTs 210 and the pass/fail switch 258 or crossover The programming code of the point switch 379 is configured to have a specific operation or function.

For example, in the tenth type non-volatile programmable logic driver 610 in FIG. 29J, the non-volatile memory IC chip 250 above the NVM chip package structure 510 on the left can be a NOR flash memory chip for The result values of the LUTs 210 are stored to be downloaded to the memory unit 490 of one of the FPGAIC chips 200 of the logic driver 300 through the paths disclosed above. 6A) associated with the second input data set of the multiplexer 211 of the programmable logic block 201) and/or storing the programming code of the pass/fail switch 258 or the crosspoint switch 379 for the above disclosure The path is downloaded to one of the FPGAIC chips 200 of the logic driver 300 as the memory cell 362 in FIGS. 7A to 7C to control the pass/fail switch 258 of one of the FPGAIC chips 200 of the logic driver 300 or the crosspoint switch 379 is coupled or not coupled to two programmable interconnect lines 361 , wherein the programmable interconnect lines 361 pass through one (or more) copper pillars 158 of the logic driver 300 and/or the TISD or FISD 101 of the logic driver 300 and/or provided by the interconnect metal layer 27 of the BISD 79 . However, the non-volatile memory IC chip 250 of the NVM chip package structure 510 on the right may be a NAND flash memory chip for storing data or information for the operation of one of the FPGA IC chips 200 of the logic driver 300 via the LUTs 210 The resulting value of , and the programming code configuration of pass/fail switch 258 or crosspoint switch 379 enables FPGAIC die 200 to have a particular operation or function.

In the eleventh type of non-volatile programmable logic driver 610 in FIG. 29K, the non-volatile memory IC chip 250 of each NVM chip package 510 positioned vertically above the logic driver 300 can be used for storage The data or information used to configure the FPGA IC chip 200 of the logic driver 300, the non-volatile memory IC chip 250 of each NVM chip package 510 can be used to: (1) store the result values for the LUTs 210, each result value can be The interconnection wire metal layer 27 of the TISD or FISD 101 of one of the NVM chip package structures 510, one of the solder contacts 541 located under each of the NVM chip package structures 510, and one of the solder contacts 541 located under each of the NVM chip package structures 510. Interconnect wire metal layer 27 (optional) of BISD 79 of one of the I/O chip packages 540 below 510 , one of the copper pillars 158 of one of the I/O chip packages 540 , one of Each interconnect metal layer 27 of the TISD or FISD 101 of the I/O chip package structure 540, one of the solder contacts 558 under one of the I/O chip package structures 540, one of the I/O chip packages 540 O the interconnecting wire metal layer 27 (optionally) of the BISD79 of one of the HBM chip package structures 560 under the chip package structure 540 , one of the copper pillars 158 of the HBM chip package structure 560 , the HBM chip package structure 560 Each interconnect metal layer 27 of the TISD or FISD 101 , one of the solder contacts 536 under one of the HBM chip package structures 560 and each interconnect metal layer 27 of the BISD 79 of the logic driver 300 , and logic The interconnect metal layer 27 of the TISD or FISD 101 of the driver 300 is loaded into the memory cell 490 of one of the FPGAIC chips 200 of the logic driver 300 ; Associated with the second input data set of the multiplexer 211 of the programmable logic block 201 (shown in FIG. 6A ) and/or used to store the programming code for the pass/fail switch 258 or the crosspoint switch 379, The interconnection wire metal layer 27 of the TISD or FISD 101 of one of the NVM chip package structures 510, one of the solder contacts 541 under each of the NVM chip package structures 510, one of the I/O chip packages, in sequence Interconnect wire metal layer 27 of BISD 79 of structure 540 (optional), one of copper pillars 158 of one of the I/O chip package structures 540, TISD or FISD 101 of one of the I/O chip package structures 540 Each of the interconnect metal layers 27, one of the solder contacts 558 under one of the I/O chip package structures 540, one of the An interconnecting wire metal layer 27 (optional) of the BISD 79 of one of the HBM chip package structures 560 under an I/O chip package structure 540 , one of the copper pillars 158 of the HBM chip package structure 560 , the HBM chip package Each interconnect metal layer 27 of the TISD or FISD 101 of the structure 560 , one of the solder contacts 536 under one of the HBM chip package structures 560 , and each interconnect metal layer 27 of the BISD 79 of the logic driver 300 , one of the copper pillars 158 of the logical driver 300 and the interconnect metal layer 27 of the TISD or FISD 101 of the logical driver 300 are loaded into the memory of the FPGAIC chip 200 of one of the logical drivers 300 in FIGS. 7A to 7C In the body unit 362 , to control the pass/no pass switch 258 or the cross-point switch 379 of one of the FPGAIC chips 200 of the logic driver 300 is coupled or not coupled to two programmable interconnection lines 361 , wherein the programmable interconnection line 361 Provided via one (or more) copper pillar(s) 158 of logical drive 300 and/or the interconnect metal layer 27 of TISD or FISD 101 and/or BISD 79 of logical drive 300 , and (2) for storing and operating logical drive 300 The data or information of one of the FPGAIC chips 200 is configured through the result value of the LUTs 210 and the programming code of the pass/fail switch 258 or the crosspoint switch 379 to have a specific operation or function.

For example, in the eleventh type of non-volatile programmable logic driver 610 in FIG. 29K, the non-volatile memory IC chip 250 on the NVM chip package structure 510 on the left can be a NOR flash memory chip, with The result values stored in the LUTs 210 are downloaded to the memory unit 490 of one of the FPGAIC chips 200 of the logic driver 300 through the path disclosed above, and the result values are the same as those of the one of the FPGAIC chips 200 of the logic driver 300 ( 6A) associated with the second input data set of the multiplexer 211 of the programmable logic block 201), and/or store the programming code of the pass/fail switch 258 or the crosspoint switch 379 for passing through the above-mentioned The exposed path is downloaded to one of the FPGAIC chips 200 of the logic driver 300 as the memory cell 362 in FIGS. 7A to 7C to control the pass/fail switch of one of the FPGAIC chips 200 of the logic driver 300 258 or the cross-point switch 379 is coupled or not coupled to two programmable interconnect lines 361, wherein the programmable interconnect lines 361 pass through one (or more) copper pillars 158 of the logic driver 300 and/or the TISD or TISD of the logic driver 300. Provided by the interconnect metal layer 27 of FISD101 and/or BISD79. However, the non-volatile memory IC chip 250 of the NVM chip package structure 510 on the right may be a NAND flash memory chip for storing data or information for the operation of one of the FPGA IC chips 200 of the logic driver 300 via the LUTs 210 The resulting value of , and the programming code configuration of pass/fail switch 258 or crosspoint switch 379 enables FPGAIC die 200 to have a particular operation or function.

Therefore, users or developers with creative or application concepts or ideas can purchase one of the first to eleventh types of non-volatile programmable logic drivers 610 shown in FIGS. 29A to 29K to develop or write software code, data, or programs (ie, result values in LUTs and/or programming codes with/without switches or crosspoint switches) are loaded into the non-volatile memory IC chips 250 of the NVM chip package 510 for implementing them creative or application concept or idea. The developed software code, data or program can be downloaded from the non-volatile memory IC chip 250 of the NVM chip package 510 to the logic chip package 520 via the interconnect metal layer 27 of the TISD or FISD 101 of the logic chip package 520 The programmable logic circuit in the FPGAIC chip 200, the memory cell 490 in the cell or block 201 and/or the memory cell 362 downloaded to the programmable interconnection wire.

In the logic chip package structure 520 of each of the first to ninth type non-volatile programmable logic drivers 610 in FIGS. 29A to 29I or each of the tenth type in FIGS. 29J to 29K In the logic driver 300 to the eleventh type non-volatile programmable logic driver 610, its FPGAIC chip 200 may include an on-chip security circuit for design security, and the on-chip security circuit is used for The programming password that protects the result values in the LUTs 210 in the FPGAIC die 200 and protects the pass/fail switch 258 or the crosspoint switch 379 in the FPGAIC die 200 is not copied or restored via a restore process. The FPGAIC chip 200 may include multiple dedicated non-volatile memory elements configured to store 128, 256, 512 or 1024 bit decryption keys, so that the on-chip security circuit can decrypt and communicate with the lookup table (LUT) 210 of the FPGAIC chip 200 The resulting value of the FPGAIC chip 200 and the encrypted data associated with the programming code of the pass/fail switch 258 or the crosspoint switch 379 of the FPGAIC chip 200 provide on-chip bitstream decryption, the encrypted data from Figures 29A-29I Type 1 to Type 10 non-volatile programmable logic drivers 610 are loaded into the non-volatile memory cells of the non-volatile memory IC chip 250 of the NVM chip package structure 510 as decrypted data. The decrypted data associated with the result value of the lookup table (LUT) 210 of the FPGAIC chip 200 can be passed and stored in the memory cell 490 of the FPGAIC chip 200 in FIG. 6A, and the pass/fail switch of the FPGAIC chip 200 258 or the encryption data associated with the programming code of the crosspoint switch 379 can be passed through and stored in the memory unit 362 of the FPGAIC chip 200 in FIGS. 7A-7C. Thus, the programmable logic blocks or circuits 201 of the FPGAIC chip 200 and the programming interconnection lines 361 can be configured. The decryption key can be created from a source of true randomness. Each dedicated non-volatile memory element of FPGAIC chip 200 may include an MRAM cell or RRAM cell configured to store the decryption key. Alternatively, each dedicated non-volatile memory device may include a MOS transistor (which is electrically floating) with a gate terminal configured to store the decryption key. Alternatively, each FPGAIC chip 200 may include a plurality of metal connection lines 431, each metal connection line 431 having a narrow neck 432 configured as an electronic fuse for one of the dedicated non-volatile memory elements, namely the 30A Figure 30B shows the e-fuse, wherein Figure 30A is a schematic diagram of an operation block of a fuse according to an embodiment of the present invention, and Figure 30B is a top view of the structure of an electronic fuse (e-fuse) according to an embodiment of the present invention. . A pair of retaining bars 434 may be formed of metal on opposite sides of the electronic fuse 432, extend along the electronic fuse 432 to protect the electronic fuse 432 from damage, and are in a non-volatile state when the electronic fuse 432 is programmed. One end of the fuse 432 can be switched and coupled to a node N51 at the power supply voltage or the ground reference voltage via a switch 433 of the FPGAIC chip 200, so a high current can be selectively generated to flow through the electronic fuse 432 to cut off or If the electronic fuse 432 is damaged, after the electronic fuse 432 is programmed, the terminal of the electronic fuse 432 can be switched to be coupled to a node N52 via the switch 433 to be coupled to the on-chip safety circuit. Alternatively, the FPGAIC chip 200 can include a plurality of anti-fuses 435 configured as one of the dedicated non-volatile memory elements, wherein each anti-fuse 435 can be composed of two anti-fuses 435 in FIG. 30A and FIG. 30C An electrode 436, an electrode 437 and an oxide window 438 (between the electrode 436 and the electrode 437) are formed, wherein FIG. 30C is a schematic cross-sectional view of the anti-fuse 435 in an embodiment of the present invention, in one of the Antifuse 435 is programmed in a non-volatile state, one of electrode 436 and electrode 437 can be switched via switch 433 to be coupled to a node N51 at power supply voltage or ground reference voltage, so a high voltage can be Applied between electrode 436 and electrode 437 to break the oxidation window 438 . After one of the anti-fuses 435 is programmed, one of the electrode 436 and the electrode 437 can be switched to be coupled to a node N52 via the switch 433 to be coupled to the on-chip safety circuit. Both the electrode 436 and the electrode 437 can be made of metal or Alternatively, one of the electrodes 436 and 437 is made of metal, and the other of the electrodes 436 and 437 is made of polysilicon. Alternatively, each dedicated non-volatile memory element may be replaced by having a dedicated random access memory (RAM) unit for storing the decryption key, wherein the dedicated random access memory unit may be powered by an externally connected battery Powered on, the decryption key can only be programmed into the FPGAIC die 200 (one of the) through a special port of the FPGAIC die 200 (the one of the).

FIG. 29L is a schematic cross-sectional view of a POP package structure according to an embodiment of the present invention. As shown in FIG. 29L, in forming a POP package structure 611, the plurality of single-layer chip package structures or chiplets 550 in FIG. 28K can be It is provided that the interconnect wire metal layer 27 of TISD or FISD 101 or BISD 79 has the same circuit layout as copper pillars 158 , and the semiconductor die 100 of the single layer die package structure or die 550 may be the same. The metal bumps, pillars or pads 570 provided by the upper single-layer chip package structure or the chiplet 550 can be adhered to the metal pads or bumps 583 of the lower single-layer chip package structure or the chiplet 550 to form a thickness between A solder joint 526 between 20 μm and 100 μm in between, an underfill material 527 (eg, a polymer) can be formed between the overlying and underlying single-layer chip package structures or dielets 550 and encapsulated Hold the solder contact 526. The metal bumps, pillars or pads 570 provided by the bottommost single-layer chip package structure or chiplet 550 can be adhered to the circuit board 530 to form a solder contact 526 therebetween, and an underfill material 527 (such as a polymer) may be formed between the bottommost single-layer die package structure or die 550 and the circuit board 530 and encapsulate the solder contacts 526. Each semiconductor chip 100 may be an FPGAIC chip, a DPIIC chip, an NVMIC chip (eg, a NAND or NOR flash memory chip), a dedicated I/O chip, a PCIC chip (eg, a DSP chip, a CPU chip, a TPU chip, or an APU chip) ), HBM chips (eg, DRAM chips, SRAM chips, MRAM chips, or RRAM chips), dedicated control chips, dedicated control and I/O chips, and I/O chips, IAC chips (eg, analog IC chips, hybrid module IC chips) , RFIC wafer), DCIAC wafer or DCDI/OIAC wafer.

As shown in FIG. 29L, each single chip package structure or chiplet 550 may include a bypass interconnection line 528 as shown in FIG. 28L for coupling to the semiconductor of the first single chip package structure or chiplet 550. Die 100 (above each single die package or dielet 550 ) to semiconductor die 100 of a second single die package or dielet 550 or coupled to a circuit board located below the single die package or dielet 550 530 (ie, the semiconductor die 100 not coupled to a single die package or die 550), the bypass interconnect 528 of each single die package or die 550 may have a higher end point on the die on one of the metal pads or bumps 583 of the package structure or chiplet 550 and having a lower end on one of the metal bumps, studs or pads 570 of the single chip package structure or chiplet 550, wherein the horizontal distance between the upper end point and the lower end point may be greater than or equal to the largest lateral dimension of one of the metal bumps, posts or pads 570 of the single chip package structure or die 550, or Greater than or equal to the spacing between two adjacent metal bumps, studs or pads 570 of the single chip package structure or chiplet 550 , wherein the higher end point can pass through one of the BISD79 of the single chip package structure or chiplet 550 in sequence The interconnect metal layer 27, one of the copper pillars of the single chip package structure or chiplet 550 and the interconnect line metal layer 27 of the TISD or FISD 101 of the single chip package structure or chiplet 550 are coupled to the lower terminal; The semiconductor chip 100 of the first single-chip package structure or chiplet 550 can pass through the interconnection wire metal layer 27 of the TISD or FISD101 of the first single-chip package structure or chiplet 550 , between the first single-chip One of the solder joints 526 between the package or die 550 and each single die package or die 550, the bypass interconnect 528 of each single die package or die 550, the second One of the solder joints 526 between a single chip package structure or die 550 and each of the single chip package structures or chiplets 550 , each interconnection line of the BISD 79 of the second single chip package structure or die 550 The metal layer 27, one of the copper pillars 158 of the second single chip package structure or chiplet 550 and the interconnection wire metal layer 27 of the TISD or FISD 101 of the second single chip package structure or chiplet 550 are coupled to the second single chip package structure or chiplet 550 The semiconductor die 100 of a single chip package structure or die 550; or the semiconductor die 100 of the first single die package structure or die 550 may be based on the interaction of the TISD or FISD 101 via the first single die package structure or die 550 wire metal layer 27, one of the solder joints 526 between the first single chip package structure or chiplet 550 and each single chip package structure or chiplet 550, each single chip package structure The bypass interconnects 528 of the or die 550 and the solder contacts 526 between the circuit board 530 and each single die package structure or die 550 are coupled to the circuit board 530, with One of the solder joints 526 between the chip package structure or chiplet 550 and each single chip package structure or chiplet 550 to between the second single chip package structure or chiplet 550 and each single chip package structure or The horizontal distance between one of the solder contacts 526 between the chiplets 550 or the horizontal distance between the circuit board 530 and each single chip package structure or chiplet 550 may be greater than or equal to that between the second one The largest lateral dimension of one of the solder contacts 526 between the single chip package or die 550 and each single chip package or die 550, or between the circuit board 530 and each single chip package or chiplet The largest lateral dimension of one of the solder contacts 526 between 550 may be greater than or equal to every two adjacent solders between the second single chip package structure or die 550 and each single chip package structure or chiplet 550 The spacing between the contacts 526 is greater than or equal to the distance between the circuit board 530 and each single chip package structure or chiplet 550 . In addition, the POP package 611 may include a power or ground bus 529 coupled to the semiconductor die 100 of each single chip package or die 550 and coupled to the solder bumps or balls 523 located under the circuit board 530, each Each interconnect metal layer 27 of BISD 79, one (or more) copper pillar(s) 158, each interconnect metal layer 27 of TISD or FISD 101 of a single chip package structure or die 550 may be provided as a power or ground bus Row 529 to deliver the power supply voltage or ground reference voltage to the semiconductor die 100 of each single die package structure or die 550 .

Fin Field Effect Transistor (FinFieldEffectTransistor, FinFET)

31A is a schematic structural diagram of a fin field effect transistor (FinFET) according to an embodiment of the present invention, and FIG. 31B is a schematic cross-sectional view of the FinFET along the BB section line in FIG. 31A according to an embodiment of the present invention, as shown in FIGS. 31A and 31A. As shown in FIG. 31B, a fin field effect transistor 4 can be formed on a P-type or N-type semiconductor substrate 2 (ie, a silicon substrate), in this case, the P-type silicon substrate provides a ground reference voltage Vss. P-type silicon substrate 2, the fin field effect transistor 4 may include:

(1) The P-type strip 731 is formed with a P-type well 732 in the P-type silicon substrate 2 and a P-type fin 733 vertically protruding from the upper surface of the P-type well 732 and extending toward a first direction, wherein The P-type well 732 may have a depth d1 _wP between 0.3 and 5 μm and a width w1 _wP between 20 nm and 1 μm, wherein the P-type fin 733 may have a height h1 _fP between 10 and 200 nm and a The width w1 _{fP is} between 1 and 100 nm.

(2) A field oxide 729 (eg, silicon oxide) is located on the P-type well 732 and above the P-type silicon substrate 2 , wherein the field oxide 729 may have a thickness tox ₁ ranging from 20 to 500 nm time, where the field oxide 729 can be used as a shallow trench isolation layer;

(3) A gate electrode 737 extends laterally toward a second direction (substantially perpendicular to the first direction), extending from one sidewall of the P-type fin 733 to the other sidewall of the P-type fin 733 and located in the field oxide 729 above, the gate 737 may have a gate length Lg _N1 located above the P-type fin 733 and the gate length Lg _N1 may be less than or equal to 10 nm, wherein the gate 737 may include a functional metal layer 738 Above the P-type fin 733 and on two opposite sidewalls of the P-type fin 733 and above the field oxide 729, wherein the working functional metal layer 738 may be titanium with a thickness between 2nm and 20nm layer, tantalum layer, titanium nitride layer or tantalum nitride layer, and a conductive metal layer 739 is located on the working functional metal layer 738, located above the P-type fin 733, and located on opposite sides of the P-type fin 733 and above the field oxide 729, wherein the conductive metal layer 739 may be an aluminum-containing metal layer with a thickness between 10 and 100 nm.

(4) A gate oxide 740 extends laterally toward the second direction, from one sidewall of the P-type fin 733 to the other sidewall of the P-type fin 733 and on the field oxide 729, the gate oxide 740 is provided on the On opposing sidewalls and tops of P-type fins 733 , between gate 737 and the opposing sidewalls and tops of P-type fins 733 , and between gate 737 and field oxide 729 , where gate oxide 740 may be A hafnium oxide (HfO) layer of tantalum oxide (TaO) having a physical thickness less than 4.5 nm, 3 nm, 2 nm, or between 1 nm and 3.5 nm.

Gate-All-AroundField-Effect-Transistor (GAAFET)

FIG. 32A is a schematic diagram of the structure of the gate full-ring transistor in the embodiment of the present invention, and FIG. 32B is a schematic cross-sectional view of the gate full-ring transistor along the section line CC in FIG. 32A, as shown in FIGS. 32A and 32A. As shown in FIG. 32B, the gate full ring transistor 4 may be formed on a P-type or N-type semiconductor substrate 2 (eg, a silicon substrate). In this case, the gate full ring transistor 4 provides a connection to the ground reference voltage Vss The P-type silicon substrate 2, the gate full ring transistor 4 may include:

(1) The P-type strip 831 is formed with a P-type well 832 in the P-type silicon substrate 2 and a P-type fin 833 vertically protruding from the upper surface of the P-type well 832 and extending toward a first direction, wherein The P-type well 832 may have a depth d2 _wP between 0.3 and 5 μm and a width w2 _wP between 50 nm and 1 μm, wherein the P-type fin 833 may have a height h2 _fP between 10 and 200 nm and a The width w2 _fP ranges from 1 to 100 nm, wherein the longitudinal openings 833 a may be formed in the P-type fins 833 , and each longitudinal opening 833 a extending along the first direction is parallel to each other, so as to form a plurality of mutually parallel longitudinal directions of the p-type fins 833 _{portion 833b, wherein each longitudinal opening 833a has a width sg 1} between 5 and 20 nm, or between 10 and 200 nm, or between 1 and 100, and the width sg ₁ is between the P-type fins 833 space between every two adjacent longitudinal portions 833b.

(2) A field oxide 829 (such as a silicon oxide layer) is located on the P-type well 832 and above the P-type silicon substrate 2, wherein the field oxide 829 may have a thickness tox ₂ between 20 and 500 nm, Wherein the field oxide 829 can be used as a shallow trench isolation layer;

(3) A gate 837 includes a functional metal layer 838 located above the P-type fin 833 and on two opposite sidewalls of the P-type fin 833 (in each longitudinal opening 833a in the P-type fin 833 ) and located above the field oxide 829, wherein the working functional metal layer 838 may be a titanium layer, a tantalum layer, a titanium nitride layer or a tantalum nitride layer with a thickness between 2nm and 20nm, and a conductive metal layer 839 on the working functional metal layer 838, above the P-type fin 833, on opposite sides of the P-type fin 833 (in each longitudinal opening 833a in the P-type fin 833), and in the field oxide Above 829, wherein the conductive metal layer 839 can be an aluminum-containing metal layer with a thickness between 10 and 100 nm, wherein the gate 837 can have a gate length LgN2 is positioned above the P-type fin 833 and the gate is The length LgN2 may be less than or equal to 10 nm, where the gate 837 may be, and.

(4) A gate oxide 840 on top of the P-type fin 833, on opposite sidewalls of the P-type fin 833, in each longitudinal opening 833a in the P-type fin 833, and on the field oxide 829 , the gate oxide 840 may be provided between the gate 837 and the P-type fin 833 and between the gate 837 and the field oxide 829, wherein the gate oxide 840 may have a physical thickness of less than 4.5nm, 3nm , 2 nm, or a hafnium oxide (HfO) layer of tantalum oxide (TaO) between 1 nm and 3.5 nm.

Therefore, as shown in FIGS. 32A to 32B , each longitudinal portion 833b of the P-type fin 833 can be covered by the gate oxide 840 , the working functional metal layer 838 of the gate 837 and the conductive metal layer 839 of the gate 837 . wrap around.

programmable logic block

FIG. 33 is a schematic block diagram of a programmable logic block (LB) according to an embodiment of the present invention. The first type programmable logic block (LB) has the structure shown in FIG. 6A . Alternatively, in each embodiment of this page, the first type programmable logic block (LB) may be replaced by the second type programmable logic block (LB) 201 in FIG. 33, as shown in FIG. 33 , the second type programmable logic block (LB) 201 may include: (1) two logic gate OR circuits 2031, each of which may refer to a circuit in FIG. 6A and has three in a first data set The data inputs are respectively coupled to the three data inputs A0-A2 of the second type programmable logic block (LB) 201, wherein each of the two gate OR circuits 2031 can be selected from a first data set according to the first data set. Selected input data from multiple result values in two data sets (these second data sets are stored in memory 490) as a data output, (2) a fixed line addition unit with two-bit data input (ie full adder), each coupled to one of the logic gates or a data output of circuit 2031, wherein the adder unit 2016 can be configured to couple its carry-indata input to the second type The data input of the programmable logic block (LB) 201 is Cin and a carry data output from the previous stage addition unit 2016, and its two data inputs are added as its two data outputs, one of which can be configured as an addition sum A first data output of , and a second data output that can be configured as an addition carry is coupled to the data output Cout of the second programmable logic block (LB) 201 and passed to the next-stage addition unit 2016 (3) a multiplexer 2032 (ie, LUT selection multiplexer), a data input in a first input data group is coupled to the second type programmable logic block (LB) 201 A data input A3 and two data inputs in a second set of input data sets are coupled to one of the data outputs of the logic gate OR circuit 2031, wherein the multiplexer 2032 can select from the second input data set according to the first input data set An input data in the input data set is selected as a data output, (4) a multiplexer 2033 (ie an addition-selection multiplexer) has a data input in the first input data set coupled to storage A programming code for memory cells (not shown) in the second type programmable logic block (LB) 201 and two data inputs in a second input data set, one of which can be coupled to a fixed The first data output of the line addition unit 2016 and others can be coupled to the data outputs of the multiplexer 2032, wherein the multiplexer 2033 can select an input data from the second input data set as a data output according to the first input data set , which can be asynchronous, (5) the D-type flip-flop circuit 2034 has a first data input coupled to the data output of the multiplexer 2033 to be registered or stored therein and a second data input coupled to a clock A clock signal clk on the bus bar 2035, wherein the D-type flip-flop circuit 2034 can output according to the second data The in-sync generates a data input associated with the first data input and the data output of the D-type flip-flop circuit 2034 can be synchronized with the clock signal clk, and (6) a multiplexer 2036 (ie, a sync selection multiplexer) in A data input in a first input group is coupled to a memory cell (not shown) of the second type programmable logic block (LB) 201 and two data inputs in a second input data group, wherein One can be coupled to the data output of the multiplexer 2033 and the other can be coupled to the data output of the D-type flip-flop circuit 2034, wherein the multiplexer 2036 can select one from the second input data set according to the first input data set. The input data is used as a data output, which can be used as a data output Dout of the second type programmable logic block (LB) 201, and the memory cells of each multiplexer 2033 and multiplexer 2036 can be on-chip volatile memory A body cell (which can refer to memory cell 398 in Figure 1A or 1B) or an on-chip non-volatile memory cell, such as a floating gate non-volatile memory cell, RRAM cell, MRAM cell or FRAM cells to hold or store the programming code for each multiplexer 2033 and 2036. Each of the multiplexers 2033 and 2036 each has a data input in the first input data set (which is associated with a data input of the memory cells of each multiplexer 2033 and 2036 (ie, configuration programming memory (CPM) data) ) associated with ), such as one of the first data output Out1 and the second data output Out2 of the memory cell 398 in FIG. 1A or FIG. 1B . As each FPGAIC chip 200 in each chip package structure 550 and logic drivers 300 and 610 in this page may be provided with a second type programmable logic block (LB) 201 for each multiplexer 2033 and The data stored in the memory cells of 2036 may be transferred from the data stored in the multiple non-volatile memory cells of the non-volatile memory chips 250 in each chip package structure 550 and logic drives 300 and 610.

FIG. 34 is a schematic block diagram of a programmable logic unit or device according to an embodiment of the present invention. Alternatively, in each embodiment of this page, the first type programmable logic block (LB) may be replaced by the third type programmable logic block (LB) 201 in FIG. 33, as shown in FIG. 34 , the third type programmable logic block (LB) 201 may include a logic operator or circuit 2037 having a 4-bit data input in a first input data set respectively coupled to the third type programmable logic block (LB) ) 201 4 data inputs A0-A3 and a carry-in data input in the first input data group are coupled to a data input Cin of the third type programmable logic block (LB) 201, wherein the logic The operator or circuit 2037 is configured to select a first data input as a first data output from a plurality of result values in a second input data set according to the first input data set, wherein the result values are stored in the plurality of first data outputs a memory unit, and selects a second data input from a plurality of result values in a second input data set as a second data output according to the first input data set, wherein the result values are stored in a plurality of second memories unit (not shown). For example, when a logical operator or circuit 2037 performs an addition operation, the logical operator or circuit 2037 may be configured to obtain its carry data input from the carry data output of another logical operator or circuit 2037 in the previous stage to account for the phase Two of the 4-bit data inputs are added as the first data output for the summation of the addition, and the second data output is used for the addition carry at the data output Cout of the third type programmable logic block (LB) 201, It can be associated with one of the carry data inputs of another logic operator or circuit 2037 in the next stage. In another embodiment, when the logic operator or circuit 2037 performs a logic operation, the logic operator or circuit 2037 may be configured to select a data input from a plurality of result values in the second input data set according to the first input data set, As the first data output for logic operations, each of the first and second memory cells for the logic operator or circuit 2037 may be an on-chip volatile memory cell (which can be referred to in Figure 1A or Section 2037). Memory cell 398 in Figure 1B) or an on-chip non-volatile memory cell, such as a floating-gate non-volatile memory cell, RRAM cell, MRAM cell, or FRAM cell, is reserved or stored for use in The result value of the logic operator OR circuit 2037, when each FPGAIC chip 200 in each chip package structure 550 and logic drivers 300 and 610 in this page is provided with a third-type programmable logic block (LB) 201 , the resultant values stored in the first and second memory cells for the logic operator or circuit 2037 may vary from a plurality of non-volatile memory chips 250 stored in each chip package 550 and logic drivers 300 and 610 data in a non-volatile memory cell.

As shown in FIG. 34, the third-type programmable logic block (LB) 201 may further include: (1) a cascade circuit 2038 provides a first data input with a logic gate (which is related to the third A data input Cas_in in type programmable logic block (LB) 201 is associated) for cascading data from another third type programmable logic block (LB) in the previous stage via one (or more) hardwires ) 201 (which may have the same structure as in Fig. 34) a data output Cas_out transmitted and a second data input associated with the first data output of the logic operator OR circuit 2037 in which the logic of the cascade circuit 2033 The gate can perform AND or OR logic operation on the first and second data inputs, as a data output of the cascade circuit 2033, wherein the data output of the cascade circuit 2033 can be asynchronous, (2) D-type flip-flop circuit 2039 The first data input is coupled to the data output of the cascade circuit 2038 to be registered or stored therein, and a second data input is coupled to the clock bus 2040 on the third-type programmable logic block (LB) 201 A clock signal, wherein the D-type flip-flop circuit 2039 can be generated synchronously according to the second data input, a data output associated with the first data input and the data output of the D-type flip-flop circuit 2039 can be synchronized with the clock signal, ( 3) A set/reset control circuit 2041 is coupled to the D-type flip-flop circuit 2039 to be respectively coupled to the two data inputs F0 and F1 of the third-type programmable logic block (LB) 201 to Setting, resetting or not changing the D-type flip-flop circuit 2039, and (4) a clock control circuit 2042 can be coupled to the D-type flip-flop circuit 2039 via the clock bus 2040, wherein the clock control circuit 2042 can be respectively coupled according to The two data inputs CLK0 and CLK1 to the third type programmable logic block (LB) 201 generate clock signals in one of several modes. For example, the clock control circuit 2042 thereof can be controlled to be enabled or disabled according to the data input CLK0, and in one mode the clock signal can be controlled according to the data input CLK1 of the third type programmable logic block (LB) 201 to be The same reference clock; in another mode, the clock signal can be inverted to the reference clock according to the data input CLK1 of the third-type programmable logic block (LB) 201 .

As shown in FIG. 34, the third-type programmable logic block (LB) 201 may further include a multiplexer 2043 (ie, a synchronous selection multiplexer), and a data input in a first input data set is coupled to A memory cell (not shown) of the third type programmable logic block (LB) 201 and two data inputs in a second input data group, one of which can be coupled to the data output of the cascade circuit 2038 And other can be coupled to the data output of the D-type flip-flop circuit 2039, wherein the multiplexer 2043 can select an input data from the second input data group according to the first input data group as a data output, which can be used as the third type A data output Dout of the programmable logic block (LB) 201, the third type programmable logic block (LB) 201 may further include a data output Cas_out for cascading data, coupled to the data output of the cascading circuit 2038 , and the data output Cas_out of the third-type programmable logic block (LB) 201 may further include a data output Cas_out that can be hard-wired to another third-type programmable logic block (LB) in the lower level through one (or more) hard-wired ) 201 is input to Cas_in, and the third type programmable logic block (LB) 201 has the same structure as in FIG. 34 .

Coarse-GrainedReconfigurableArchitecture(CGRA)

FIG. 35 is a schematic diagram of a plurality of CGRAs in matrix form in another embodiment of the present invention. In each embodiment on this page, the first type programmable logic block (LB) 201 can be The CGRA 2041 replaces and has a plurality of coarse-grained reconfigurable (CGR) units 2042 (ie functional unit blocks (FUBs)), units or elements arranged in a matrix, a plurality of programmable interconnect lines 361 (each ) between two adjacent CGA cells 2042, and a plurality of cross-point switches 379 (each) have the same disclosure as in Figure 7B and have top, left, bottom and right endpoints coupled to the top , four programmable interconnect lines 361 at left, bottom and right. As shown in FIG. 35, each CGA unit 2042 may include: (1) the functional unit (FU) 2043 includes a complex number of hard macros (hard macros), such as DSP segments, GPU hard cores, MU hard cores, and multiplexer hard cores , Addition hard core, Multiplication hard core, Arithmetic logic unit (ALU) hard core, Shift circuit hard core, Compare circuit hard core, Floating point calculation hard core, Register or flip-flop hard core and/or I/O interface Hard cores, where each hard core can be designed, programmed and implemented using fixed hard wires (metal wires or connecting wires) for the circuit, where the functional units 2043 can have a first set of input points 2044 that can be interconnected via one of the programmable Line 361 is coupled to one of the cross-point switches 379, (2) a register block 2045 has a plurality of registers or D-type flip-flop circuits 2039, each for registering or temporarily storing a data output from the functional unit 2043 therein The associated data is stored in each register or D-type flip-flop circuit 2039 through one (or more) programmable interconnect lines 361 according to the clock signal to be distributed or accessed in the next stage To another CGR unit (or units) 2042, where the first set of input points 2044 of the functional unit 2043 may be coupled from the register block 2045 in the other (or more) CGR unit(s) 2042 in the previous stage via self-coupling One (or more) cross-point switches 379 of one (or more) programmable interconnect lines 361 receive data, (3) registered file memory block 2046 has a plurality of memory cells, each of which may be a Or the SRAM cell in Figure 1B (with the same disclosure description) for temporarily storing therein a register file associated with the data output of the functional unit 2043 during one of the time periods, and according to the clock signal The data stored in the SRAM unit is passed to one of the second set of input points 2047 of its functional unit 2043, (4) a program counter ((PC)) 2048 (ie, the instruction pointer) has a plurality of first A memory unit, such as an instruction address register for temporarily storing a plurality of instruction addresses therein, one (or more) arithmetic logic unit(s) pointing to its functional unit 2043 in the program sequence, and (5) an instruction memory The bank block or segment 2049 has a plurality of second memory cells, each of which may be an SRAM cell (with the same disclosure description) in Fig. 1A or Fig. 1B, for temporarily storing a plurality of instruction sets, the instructions A group is a machine language or binary numeric code that can be translated from assembly language (such as MOV, ADD, or SUB), each associated by its functional unit 2043 with an instruction address stored in a program calculator (PC) 2048 Linked data is acquired to indicate that one (or more) arithmetic logic unit in functional unit 2043 pairs The data at the first and second sets of input points 2044 and 2047 perform a particular one (or more) operation or logic function when each FPGAIC die 200 and logic driver in each die package structure 550 in the page 300 and 610 provide the instruction address stored in the first memory unit of the Program Calculator (PC) 2048 and the instruction set stored in the second memory unit of the instruction memory block or segment 2049 with the CGRA2041. Data transfer from a plurality of non-volatile memory cells of non-volatile memory chips 250 stored in each FPGAIC chip 200 and logic drivers 300 and 610 in each chip package structure 550.

Miscellaneous

Therefore, each FPGA IC chip 200 in this page can be regarded as a configurable, reconfigurable, programmable IC chip, and each standard commercial logic driver 300 and chip package structure 500 in this page can be regarded as a non- Volatile Configurable, Reconfigurable and Programmable Devices. Each standard commercial FPGA IC die 200 on this page has standard common features, quantities or specifications: (1) a programmable logic block, cell or element 201 comprising: (i) a plurality of system gates, the quantity of which is Greater than or equal to 2M, 10M, 20M, 50M or 100M; (ii) multiple programmable logic cells or elements, the number of which is greater than or equal to 64K, 128K, 512K, 1M, 4M or 8M, (iii) multiple hard cores , for example, including DSP fragments, GPU hard cores, MU hard cores, multiplexer hard cores, addition hard cores, multiplication hard cores, arithmetic logic unit (ALU) hard cores, displacement circuit hard cores, comparison circuit hard cores, Floating-point computing hard cores, register or flip-flop hard cores, and/or I/O interface hard cores, wherein each hard core is a circuit designed, compiled and implemented with fixed hard wires, and/or (iv) has bits Multiple blocks of memory with a quantity equal to or greater than 1M, 10M, 50M, 100M, 200M or 500M; (2) Input quantity of each programmable logic block 201 or operator: greater than or equal to 4, 8, 16 ,32,64,128 or 256; (3) Power supply voltage: between 0.1V to 8V, between 0.1V to 6V, between 0.1V to 2.5V, between 0.1V to 2V , between 0.1V and 1.5V or between 0.1V and 1V; (4) I/O metal pads in layout, location, quantity and function.

Conclusion and advantages

Therefore, the existing logic ASIC or COTIC chip industry can be transformed into a commercial logic operation IC chip industry by using the commercial standard logic driver 300, such as the existing commercial DRAM or commercial flash memory IC chip industry, for the same innovation Applications Since the performance, power consumption, and engineering and manufacturing costs of the commercial standard logic driver 300 are comparable to or equal to that of an ASICIC die or a COTIC die, the commercial standard logic driver 300 can be used as a replacement for designing an ASICIC die or a COTIC die, existing logic ASICIC chip or COTIC chip design, manufacture and/or production (including including fabless IC chip design and production companies, IC fabs or build-to-order (can be productless), companies and/or), vertically integrated IC chip design , manufacturing and production companies) Variable Imaging is a company that designs, manufactures and/or manufactures existing commercial DRAM or flash memory IC chips; or is a company that designs, manufactures and/or produces DRAM modules; Or companies that design, manufacture and/or produce memory modules, flash USB sticks or drives, flash solid state drives or hard disk drives. Existing logic IC chip or COTIC chip design and/or manufacturing companies (including fabless IC chip design and production companies, IC fabs or build-to-order manufacturing (can be product-free), companies and/or), vertically integrated IC chips A company that designs, manufactures, and produces) can become a company with the following industry models: (1) a company that designs, manufactures, and/or sells a plurality of commercialized standard FPGAIC chips 200; and (or) (2) designs, manufactures, and/or ) A company that sells the commercialized standard logic driver 300. Individuals, users, customers, software developers and application developers can purchase this commercialized standard logic operator and write the source code of the software for the application he/she expects Perform programming, for example, in artificial intelligence (Artificial Intelligence, AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (Internet Of Things, IOT), virtual reality (VR), augmented reality (AR) ), automotive electronic graphics processing (GP). The logic operator can be programmed to perform functions such as graphics chips, baseband chips, Ethernet chips, wireless chips (eg, 802.11ac) or artificial intelligence chips. This logic operator can be programmed to perform artificial intelligence, machine learning, deep learning, big data database storage or analysis, Internet of Things (IOT), virtual reality (VR), augmented reality (AR), automotive Electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) functions or any combination of them.

The present invention discloses a commercial standard logic driver. The commercial standard logic driver is a multi-chip package used to achieve computing and/or processing functions through field programming. The chip package includes several FPGA IC chips and one or more can Non-volatile memory IC chips used in different logic operations. The difference between the two is that the former is a computing/processor with logic operation function, while the latter is a data storage device with memory function. This commercial standard The non-volatile memory IC chip used in the logical drive is similar to using a commercial standard solid state storage hard disk (or drive), a data storage hard disk, a data storage floppy disk, a Universal Serial Bus (USB) ) flash memory disk (or drive), a USB drive, a USB memory stick, a flash memory disk or a USB memory.

The present invention discloses a commercial standard logical driver, which can be arranged in a hot-swap device, so that when a host is running, the hot-swap device can be inserted into the host and communicated with the host under the condition of uninterrupted power supply. coupled so that the host can cooperate with the logical drive in the hot-plug device.

Another aspect of the present invention further discloses a method for reducing the cost of NRE, and the method realizes innovation and application on semiconductor IC chips through commercialized standard logic drivers. Persons, users or developers with innovative ideas or innovative applications need to purchase this commercial standard logical drive and a development or writing software source code or program that can write (or load) this commercial standard logical drive for Realize his/her innovative idea or innovative application. Compared with the method realized by developing an ASIC chip or COTIC chip, the realized method provided by the present invention can reduce the NRE cost by more than 2.5 times or more than 10 times. For advanced semiconductor technologies or next-generation technologies (eg, to less than 30 nanometers (nm) or 20 nanometers (nm)), the cost of NRE for ASIC wafers or COT wafers increases substantially, for example, by over US$500 10,000 yuan, 10 million yuan, or even more than 20 million yuan, 50 million yuan or 100 million yuan. 16nm technology or process generations such as ASIC chips or COTIC chips require masks in excess of $2 million, $5 million or $10 million if logic drivers are used to achieve the same or similar Innovations or applications can reduce this NRE cost by less than $10 million, or even less than $7 million, $5 million, $3 million, $2 million, or $1 million. The present invention stimulates innovation and lowers barriers to innovation in implementing IC chip designs and barriers to using advanced IC processes or next process generations, such as using more advanced IC process technologies than 30nm, 20nm or 10nm .

The present invention further discloses a way to change the logic ASIC chip or COT chip hardware industry model into a software industry model through commercialized standard logic operators. On the same innovation and application, the performance, power consumption, engineering and manufacturing cost of standard commercial logic drivers should be better or the same as existing ASIC chips or COTIC chips, and the design company or supplier of existing ASIC chips or COTIC chips can be turned into software Developers or suppliers, and become the following industry models: (1) Become a software company to develop or sell software for its own innovations and applications, and then allow customers to install the software on their own commercial standard logic operators and/or (2) is still a hardware company that sells hardware without designing and producing ASIC chips or COTIC chips. For innovative or new applications, self-developed software can be installed in one or more non-volatile memory IC chips in standard commercial logic drives that are sold and then sold to their customers or users. They can also write software source code in a standard commercial logic driver (that is, install the software source code in a non-volatile memory IC chip in a standard commercial logic driver) for the desired purpose, such as in artificial intelligence (AI) , Machine Learning, Internet of Things (IOT), Virtual Reality (VR), Augmented Reality (AR), Electronic Graphics Processing (GP), Digital Signal Processing (DSP), Microcontroller (MC) or Central Processing Controller (CP) and other functions. A company that designs, manufactures, and/or products for systems, computers, processors, smart phones, or electronic instruments or devices can become: (1) a company that sells commercialized standard hardware, which, for the purposes of the present invention, is The type of company is still a hardware company, and the hardware includes memory drives and logical drives; (2) The system and application software are developed for users and installed in the user's own commercial standard hardware. For the present invention For example, this type of company is a software company; (3) installs system and application software or programs developed by a third party in commercial standard hardware and sells software download hardware. For the present invention, this type of company is a hardware company.

Another aspect of the present invention discloses a development kit or tool as a user or developer using (via) a commercial standard logic driver to implement an innovative technology or application technology, a user or developer with innovative technology, new application concepts or ideas Users can purchase commercial standard logic drivers and use corresponding development kits or tools for development, or write software source code or programming and load them into a plurality of non-volatile memory chips in commercial standard logic drivers, as the realization of his ( or her) innovative technology or application concept ideas.

For the first case, the multi-chip package structure includes: the first chip package structure includes a first semiconductor IC die, a first polymer layer outside and from the sidewalls of the first semiconductor integrated circuit (IC) die a first metal pillar in the first polymer layer in the extended space, and a first interconnect structure, a first polymer layer and a first metal pillar under the first semiconductor IC chip, wherein the first An upper surface of the polymer layer, the upper surface of the first semiconductor integrated circuit (IC) chip and the upper surface of the first metal pillar are coplanar, wherein the first interconnection line structure includes a first interconnection line metal layer Below the first semiconductor IC die, the first polymer layer, and the first metal pillar, wherein the first interconnect metal layer includes a metal interconnect across the boundary of the underlying first semiconductor integrated circuit (IC) die , a second interconnecting wire metal layer is located under the first interconnecting wire metal layer and a first insulating dielectric layer is between the first and second interconnecting wire metal layers, wherein the first semiconductor IC chip is The first interconnect metal layer is coupled to the first metal pillar, wherein the first semiconductor IC chip includes a plurality of volatile memory cells and a multiplexer, and the volatile memory cells can be configured to store and use multiple LUTs. first data associated with a result value, and the multiplexer includes a first set of input points for a first set of input data of a logical operation, wherein the multiplexer is configurable from the first set of input data according to the first set of input data One data from the two input data sets is selected as an output data for logic operation; a first metal bump is located under the first chip package structure, wherein the first metal bump is coupled to the second interconnect metal layer; and a non-volatile memory IC chip located above the first chip packaging structure, wherein the non-volatile memory IC chip is sequentially coupled to the first semiconductor IC chip through the first metal pillar and the first interconnecting wire metal layer, The non-volatile memory IC chip includes a plurality of non-volatile memory cells configured to store second data associated with a plurality of result values of the LUT, wherein the first data is associated with the second data.

In the first case: In the first aspect, the multi-die package structure is configured for a non-volatile programmable logic device for use as an ASIC die.

In the first case: In the second aspect, the first semiconductor IC chip includes a plurality of on-chip dedicated non-volatile memory elements and an on-chip security circuit, the on-chip dedicated non-volatile memory elements can be configured to store The third data, and the on-chip security circuit is configured to decrypt encrypted data associated with the second data from the non-volatile memory IC chip according to the third data. The first semiconductor IC chip includes two electrodes and an oxide window located between the two electrodes, wherein the two electrodes and the oxide window are configured as a primary anti-fuse for dedicated non-volatile memory elements on a plurality of chips, the first The semiconductor IC chip includes a plurality of second non-volatile memory cells configured as on-chip dedicated non-volatile memory elements.

In a third case: in the third aspect, the first metal bump includes a solder layer having a thickness between 20 and 100 μm, the first metal pillar includes a copper layer having a thickness between 10 and 100 μm, The first chip package structure may further include a metal pad on the upper surface of the first metal pillar, wherein the metal pad with a thickness between 1 and 10 μm is coupled to the non-volatile memory IC chip, and the metal pad is connected to the non-volatile memory IC chip. The pads include a copper layer with a thickness between 1 and 10 μm.

In the first case: in the fourth aspect, the first chip package structure further includes a metal pad vertically positioned above the first semiconductor IC chip, wherein the metal pad includes a thickness of between 1 and 10 μm. copper layer.

For the first case: In the fifth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is positioned over the first chip package structure , wherein the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, wherein the second chip package structure Including a second polymer layer located outside the sidewall of the non-volatile memory IC chip and extending outwardly from the sidewall in the space, wherein the upper surface of the second polymer layer and the upper surface of the non-volatile memory IC chip Coplanar, and the second interconnection structure is located below the non-volatile memory IC chip and the second polymer layer, wherein a third interconnection metal layer includes a metal interconnection located across the underlying non-volatile memory IC chip. At the boundary of the volatile memory IC chip, a fourth interconnecting line metal layer is located under the third interconnecting line metal layer and a second insulating dielectric layer is between the third and fourth interconnecting line metal layers, The non-volatile memory IC chip is sequentially coupled to the first semiconductor through the third interconnection wire metal layer, the fourth interconnection wire metal layer, the second metal bump, the first metal pillar and the first interconnection wire metal layer IC chips.

In the first case: In the sixth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package structure Above, wherein the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, wherein the multi-chip package structure A third chip package structure is included between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump is interposed therebetween. Between the first and third chip package structures, wherein the third metal bump is coupled to the third chip package structure to the first chip package structure, wherein the second metal bump is coupled to the second chip package structure to the third chip package structure , the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second metal pillar on the second In the polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting wire structure is located on the second semiconductor IC chip, Below the second polymer layer and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the second semiconductor IC chip below, a fourth interconnect line metal layer Below the third interconnect metal layer and a second insulating dielectric layer between the third and fourth interconnect metal layers, wherein the third metal bump is coupled to the fourth interconnect metal layer, the second The metal pillar includes a copper layer with a thickness between 10 and 100 microns, and the non-volatile memory IC chip is sequentially passed through the second metal bump, the second metal pillar, the third metal bump, the first metal pillar and the first metal pillar. The interconnect metal layer is coupled to the first semiconductor IC chip. The third metal bump includes a solder layer with a thickness between 20 and 100 microns, the second metal pillar includes a copper layer with a thickness between 10 and 100 microns, and the third chip package structure further includes a metal pad located on the On the upper surface of the second metal pillar, the metal pad is connected to the second metal bump and has a thickness of 1 to 10 microns, and the metal pad on the upper surface of the second metal pillar includes a thickness of 1 to 10 microns between the copper layers.

In the first case: In the seventh aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located on the first chip package structure Above, wherein the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, wherein the multi-chip package structure A third chip package structure is included between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump is interposed therebetween. Between the first and third chip package structures, wherein the third metal bump is coupled to the third chip package structure to the first chip package structure, wherein the second metal bump is coupled to the second chip package structure to the third chip package structure , the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second metal pillar on the second In the polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting wire structure is located on the second semiconductor IC chip, Below the second polymer layer and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the second semiconductor IC chip below, a fourth interconnect line metal layer Below the third interconnect metal layer and a second insulating dielectric layer between the third and fourth interconnect metal layers, wherein the third metal bump is coupled to the fourth interconnect metal layer, multi-chip The package structure further includes a fourth metal bump between the first and third chip package structures and is vertically positioned above the second semiconductor IC chip, and the third chip package structure further includes a metal pad vertically positioned on the second semiconductor IC Above the IC chip, wherein the metal pads positioned vertically above the second semiconductor IC chip are bonded to one of the fourth metal bumps and have a thickness between 1 and 10 microns, and the metal positioned vertically above the second semiconductor IC chip The pads include a copper layer having a thickness between 1 and 10 microns.

In the first case: In the eighth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located on the first chip package structure Above, wherein the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, wherein the multi-chip package structure A third chip package structure is included between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump is interposed therebetween. Between the first and third chip package structures, wherein the third metal bump is coupled to the third chip package structure to the first chip package structure, wherein the second metal bump is coupled to the second chip package structure to the third chip package structure , the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second metal pillar on the second In the polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting wire structure is located on the second semiconductor IC chip, Below the second polymer layer and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the second semiconductor IC chip below, a fourth interconnect line metal layer Below the third interconnecting wire metal layer and a second insulating dielectric layer is between the third and fourth interconnecting wire metal layers, wherein the third metal bump is coupled to the fourth interconnecting wire metal layer. The multi-chip package structure further includes a fourth metal bump between the first and third chip package structures, wherein the first chip package structure further includes a third metal pillar in the first polymer layer, wherein the first polymer The upper surface of the material layer, the upper surface of the first semiconductor IC chip, the upper surface of the first metal pillar and the upper surface of the third metal pillar are coplanar, wherein the second semiconductor IC chip is sequentially connected through the third interconnecting wire metal layer, the first metal pillar and the third metal pillar. The four interconnected metal layers, the fourth metal bump, the third metal pillar and the first interconnected metal layer are coupled to the first semiconductor IC chip.

In the first case: In the ninth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package structure Above, wherein the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, wherein the multi-chip package structure A third chip package structure is included between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump is interposed therebetween. Between the first and third chip package structures, wherein the third metal bump is coupled to the third chip package structure to the first chip package structure, wherein the second metal bump is coupled to the second chip package structure to the third chip package structure , the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second metal pillar on the second In the polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting wire structure is located on the second semiconductor IC chip, Below the second polymer layer and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the second semiconductor IC chip below, a fourth interconnect line metal layer Below the third interconnecting wire metal layer and a second insulating dielectric layer is between the third and fourth interconnecting wire metal layers, wherein the third metal bump is coupled to the fourth interconnecting wire metal layer. The second semiconductor IC chip is a dedicated I/O chip, and the multi-chip package structure further includes a fourth metal bump located between the first and third chip package structures, wherein the first chip package structure further includes a third The metal pillar is in the first polymer layer, wherein the upper surface of the first polymer layer, the upper surface of the first semiconductor IC chip, the upper surface of the first metal pillar and the upper surface of the third metal pillar are coplanar, and the special The I/O chip includes a driver sequentially coupled to the first semiconductor IC through the third interconnection wire metal layer, the fourth interconnection wire metal layer, the fourth metal bump, the third metal pillar and the first interconnection wire metal layer The chip, wherein the driver has a driving capability between 0.1 and 2pF, the multi-chip package structure further includes a fourth metal bump between the second and third chip package structures, wherein a plurality of second metal bumps The block is interposed between the second and third chip package structures, wherein the third chip package structure further includes a third metal post in the second polymer layer, wherein the upper surface of the second polymer layer, the dedicated I/O The upper surface of the O chip, the upper surface of the second metal pillar, and the upper surface of the third metal pillar are coplanar, wherein the dedicated I/O chip includes a driver through the third interconnection wire metal layer, the third metal pillar and the A fourth metal bump is coupled to the non-volatile memory IC chip, wherein the driver has a driving capability between 0.1 and 2 pF, and the multi-chip package structure further includes a fourth metal bump between the first and the Between the third chip package structures, wherein the first chip package structure further includes a third metal pillar in the first polymer layer, wherein the upper surface of the first polymer layer, the upper surface of the first semiconductor IC chip, the first polymer layer The upper surface of a metal pillar and the upper surface of the third metal are coplanar, wherein the dedicated I/O chip includes a driver sequentially passing through the third interconnecting wire metal layer, the fourth interconnecting wire metal layer, the fourth metal bump, The third metal pillar, the first interconnect metal layer and the second interconnect metal layer are coupled to the first metal bump, wherein the driver has a driving capability greater than 2pF.

In the first case: In the tenth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located on the first chip package structure Above, the multi-chip package structure further includes a second metal bump located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bump, and the second chip package structure It is a BGA chip package structure, which includes a circuit board, wherein the non-volatile memory IC chip is coupled to the second metal bump through the circuit board, wherein the second metal bump is one of a plurality of metal bumps Under the second chip package structure, a plurality of metal bumps are arranged in a matrix form.

In the first case: In the eleventh aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the second chip package structure is a thin-small-outline-package (TSOP), which includes a lead frame and has a non-volatile memory IC chip bonded thereon, and a potting material The lead frame and the non-volatile memory IC chip are wrapped, wherein the non-volatile memory IC chip is coupled to the first chip package structure through the lead frame.

In the first case: In the twelfth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the second chip package structure is a chip level package structure (CSP), wherein the area ratio between the chip level package structure and the non-volatile memory IC chip is equal to or less than 1.5.

In the first case: in the thirteenth aspect, the first chip package structure further includes a second interconnecting wire structure located above the first semiconductor IC chip, the first polymer layer and the first metal pillar, wherein The second interconnect structure includes a third interconnect metal layer over the first semiconductor IC chip, the first polymer layer and the first metal pillar, and a second insulating dielectric layer over the third interconnect above the interconnect metal layer, wherein the third interconnect metal layer includes a metal interconnect straddle a boundary of the underlying first semiconductor IC chip, wherein the non-volatile memory IC chips are sequentially connected through the third interconnect The wire metal layer, the first metal post and the first interconnecting wire metal layer are coupled to the first semiconductor IC chip.

In the first case: In the fourteenth aspect, the first semiconductor IC chip is an FPGAIC chip, and the non-volatile memory IC chip is a NAND flash memory chip or a NOR flash memory chip.

In a second case, the multi-chip package structure includes: the first chip package structure includes a first semiconductor IC die, a first polymer layer located outside the sidewalls of the first semiconductor integrated circuit (IC) die and extending from the sidewall of the first semiconductor integrated circuit (IC) die. In the space where it extends, the first metal pillar in the first polymer layer, and the first interconnecting line structure, the first polymer layer and the first metal pillar under the first semiconductor IC chip, wherein the first An upper surface of a polymer layer, an upper surface of a first semiconductor integrated circuit (IC) chip, and an upper surface of the first metal pillar are coplanar, wherein the first interconnection line structure includes a first interconnection line metal layer under the first semiconductor IC chip, the first polymer layer, and the first metal pillar, wherein the first interconnect metal layer includes a metal interconnect line across the underlying first semiconductor integrated circuit (IC) chip. boundary, a second interconnecting wire metal layer is located under the first interconnecting wire metal layer and a first insulating dielectric layer is between the first and second interconnecting wire metal layers, wherein the first semiconductor IC chip The metal layer is coupled to the first metal column through the first interconnection wire, wherein the first semiconductor IC chip includes a plurality of volatile memory cells and a multiplexer, and the volatile memory cells can be configured to store and store a plurality of programming codes. The associated first data, a switch, a first programmable interconnection line coupled to the switch, and a second programmable interconnection line coupled to the switch, wherein the switch relationship is used to control the first data according to the first data. A connection between a programmable interconnection line and a second programmable interconnection line; a first metal bump is located under the first chip package structure, wherein the first metal bump is coupled to the metal layer of the second interconnection line ; and a non-volatile memory IC chip located above the first chip package structure, wherein the non-volatile memory IC chip is sequentially coupled to the first semiconductor IC chip through the first metal pillar and the first interconnecting wire metal layer , wherein the non-volatile memory IC chip includes a plurality of non-volatile memory cells configured to store second data associated with a plurality of programming codes, wherein the first data is associated with the second data.

In the second case: In the first aspect, the multi-die package structure is configured for a non-volatile programmable logic device as an ASIC die.

In the second case: In the second aspect, the first semiconductor IC chip includes a plurality of on-chip dedicated non-volatile memory elements and an on-chip security circuit, the on-chip dedicated non-volatile memory elements can be configured to store The third data, and the on-chip security circuit is configured to decrypt encrypted data associated with the second data from the non-volatile memory IC chip according to the third data.

In a second case: In the second aspect, the first semiconductor IC chip includes a plurality of on-chip dedicated non-volatile memory elements configured to store third data and an on-chip security circuit configured to The third data decrypts the encrypted data (associated with the second data from the non-volatile memory IC chip), the first semiconductor IC chip includes two electrodes and an oxidation window between the two electrodes, wherein the two electrodes and oxide windows configured as primary anti-fuses for dedicated non-volatile memory devices on multiple chips.

In the second case: In the fourth aspect, the first semiconductor IC chip includes a plurality of on-chip dedicated non-volatile memory elements configured to store third data and an on-chip security circuit configured to The third data decrypts the encrypted data (associated with the second data from the non-volatile memory IC chip), the first semiconductor IC chip includes a plurality of second non-volatile memory cells configured as on-chip dedicated non-volatile memory memory components.

In the second case: in the fifth aspect, the first metal bump includes a solder layer having a thickness between 20 and 100 μm, the first metal pillar includes a copper layer having a thickness between 10 and 100 μm, The first chip package structure may include a metal pad on the upper surface of the first metal pillar, wherein the metal pad with a thickness of 1 to 10 μm is coupled to the non-volatile memory IC chip, the metal pad A copper layer with a thickness between 1 and 10 μm is included.

In the second case: In the sixth aspect, the first chip package structure further includes a metal pad vertically above the first semiconductor IC chip, wherein the metal pad includes a thickness between 1 and 10 microns copper layer.

For the second case: In the seventh aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is positioned over the first chip package structure , wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through a plurality of second metal bumps, wherein the second chip package structure is The chip package structure includes a second polymer layer located outside the sidewall of the non-volatile memory IC chip and extending outward from the sidewall in the space, wherein the upper surface of the second polymer layer and the non-volatile memory IC chip The upper surface of the second interconnection line is coplanar, and the second interconnection line structure is located under the non-volatile memory IC chip and the second polymer layer, wherein a third interconnection line metal layer includes a metal interconnection line spanning bit At the boundary of the underlying non-volatile memory IC chip, a fourth interconnect metal layer is located below the third interconnect metal layer and a second insulating dielectric layer is located between the third and fourth interconnect metal layers wherein the non-volatile memory IC chip is sequentially coupled to the first semiconductor IC chip through the third interconnecting wire metal layer, the fourth interconnecting wire metal layer, the first metal pillar and the first interconnecting wire metal layer.

In the second case: In the eighth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package structure Above, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, wherein many The chip package structure includes a third chip package structure between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump The block is interposed between the first and third chip package structures, wherein the third metal bumps are coupled to the third chip package structure to the first chip package structure, wherein each of the second metal bumps is coupled to the second chip package structure to A third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second polymer layer The metal column is in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal column are coplanar, and the second interconnecting line structure is located on the first Below the two semiconductor IC chips, the second polymer layer and the second metal pillars, wherein a third interconnecting metal layer includes a metal interconnecting line across the boundary of the second semiconductor IC chip below, a fourth interconnecting The connection line metal layer is located under the third interconnection line metal layer and a second insulating dielectric layer is between the third and fourth interconnection line metal layers, wherein the third metal bump is coupled to the fourth interconnection line The metal layer, the second metal pillar includes a copper layer with a thickness between 10 and 100 microns, the non-volatile memory IC chip is sequentially passed through the second metal bump, the second metal pillar, the third metal bump, the first The metal pillar and the first interconnecting wire metal layer are coupled to the first semiconductor IC chip, the third metal bump includes a solder layer with a thickness between 20 and 100 microns, and the second metal pillar includes a thickness between 10 and 100 microns the copper layer between, the third chip package structure includes a metal pad on the upper surface of the second metal pillar, wherein the metal pad is bonded to one of the second metal bumps and has a thickness of 10 to 100 Å microns, the metal pad includes a copper layer having a thickness of between 1 and 10 microns.

In the second case: In the ninth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package structure Above, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, wherein many The chip package structure includes a third chip package structure between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump The block is interposed between the first and third chip package structures, wherein the third metal bump is coupled to the third chip package structure to the first chip package structure, wherein each of the second metal bumps is coupled to the second chip package structure to the first chip package structure. Three-chip package structure, the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second metal layer The pillar is in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting line structure is located on the second Below the semiconductor IC chip, the second polymer layer and the second metal pillar, wherein a third interconnection metal layer includes a metal interconnection line across the boundary of the second semiconductor IC chip below, a fourth interconnection The line metal layer is located under the third interconnection line metal layer and a second insulating dielectric layer is between the third and fourth interconnection line metal layers, wherein the third metal bump is coupled to the fourth interconnection line metal layer layer, the third chip package structure further includes a metal pad vertically above the second semiconductor IC chip, wherein the metal pad is bonded to one of the second metal bumps and has a thickness between 1 and 10 microns, the The metal pads include a copper layer having a thickness between 1 and 10 microns.

In the second case: In the tenth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package structure Above, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, wherein many The chip package structure includes a third chip package structure between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal bump The block is interposed between the first and third chip package structures, wherein the third metal bumps are coupled to the third chip package structure to the first chip package structure, wherein each of the second metal bumps is coupled to the second chip package structure to A third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and a second polymer layer The metal column is in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal column are coplanar, and the second interconnecting line structure is located on the first Below the two semiconductor IC chips, the second polymer layer and the second metal pillars, wherein a third interconnecting metal layer includes a metal interconnecting line across the boundary of the second semiconductor IC chip below, a fourth interconnecting The connection line metal layer is located under the third interconnection line metal layer and a second insulating dielectric layer is between the third and fourth interconnection line metal layers, wherein the third metal bump is coupled to the fourth interconnection line metal layer. The multi-chip package structure further includes a fourth metal bump located between the first and third chip package structures, wherein the first chip package structure further includes a third metal post in the first polymer layer, wherein the first chip package structure The upper surface of a polymer layer, the upper surface of the first semiconductor IC chip, the upper surface of the first metal pillar, and the upper surface of the third metal pillar are coplanar, wherein the second semiconductor IC chip is sequentially metallized through the third interconnecting wire The layer, the fourth interconnecting wire metal layer, the fourth metal bump, the third metal pillar and the first interconnecting wire metal layer are coupled to the first semiconductor IC chip.

In the second case: In the eleventh aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, wherein The multi-chip package structure includes a third chip package structure between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal The bumps are interposed between the first and third chip package structures, wherein the third metal bumps are coupled to the third chip package structure to the first chip package structure, wherein each of the second metal bumps is coupled to the second chip package structure To a third chip package structure, the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and the first Two metal pillars are in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting line structure is located at Below the second semiconductor IC chip, the second polymer layer, and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the lower second semiconductor IC chip, a fourth interconnect line The interconnect metal layer is located under the third interconnect metal layer and a second insulating dielectric layer is between the third and fourth interconnect metal layers, wherein the third metal bump is coupled to the fourth interconnect wire metal layer. The multi-chip package structure further includes a fourth metal bump located between the first and third chip package structures, wherein the first chip package structure further includes a third metal post in the first polymer layer, wherein the first chip package structure The upper surface of a polymer layer, the upper surface of the first semiconductor IC chip, the upper surface of the first metal pillar, and the upper surface of the third metal pillar are coplanar, wherein the second semiconductor IC chip is sequentially metallized through the third interconnecting wire The layer, the fourth interconnection wire metal layer, the fourth metal bump, the third metal pillar and the first interconnection wire metal layer are coupled to the first semiconductor IC chip, wherein the driver has a driving capability between 0.1 to 2pF , wherein a plurality of second metal bumps are interposed between the second and third chip package structures, wherein the third chip package structure further includes a third metal pillar in the second polymer layer, wherein the second polymer The upper surface of the layer, the upper surface of the dedicated I/O chip, the upper surface of the second metal pillar and the upper surface of the third metal pillar are coplanar, wherein the dedicated I/O chip includes a driver in sequence through the third interconnection wire metal The layer, the third metal pillar and one of the second metal bumps are coupled to the non-volatile memory IC chip, wherein the driver has a driving capability between 0.1 and 2 pF.

In the second case: In the twelfth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, wherein The multi-chip package structure includes a third chip package structure between the first and second chip package structures, wherein the second chip package structure is coupled to the first chip package structure through the third chip package structure, and a third metal The bumps are interposed between the first and third chip package structures, wherein the third metal bumps are coupled to the third chip package structure to the first chip package structure, wherein each of the second metal bumps is coupled to the second chip package structure To a third chip package structure, the third chip package structure includes a second semiconductor IC chip, a second polymer layer located outside the sidewall of the second semiconductor IC chip and extending outwardly from the sidewall in the space, and the first Two metal pillars are in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the second semiconductor IC chip and the upper surface of the second metal pillar are coplanar, and the second interconnecting line structure is located at Below the second semiconductor IC chip, the second polymer layer, and the second metal pillar, a third interconnect metal layer includes a metal interconnect line across the boundary of the lower second semiconductor IC chip, a fourth interconnect line The interconnect metal layer is located under the third interconnect metal layer and a second insulating dielectric layer is between the third and fourth interconnect metal layers, wherein the third metal bump is coupled to the fourth interconnect wire metal layer. The multi-chip package structure further includes a fourth metal bump located between the first and third chip package structures, wherein the first chip package structure further includes a third metal post in the first polymer layer, wherein the first chip package structure The upper surface of a polymer layer, the upper surface of the first semiconductor IC chip, the upper surface of the first metal pillar, and the upper surface of the third metal pillar are coplanar, wherein the second semiconductor IC chip is sequentially metallized through the third interconnecting wire The layer, the fourth interconnection wire metal layer, the fourth metal bump, the third metal pillar and the first interconnection wire metal layer are coupled to the first semiconductor IC chip, wherein the driver has a driving capability between 0.1 to 2pF , the multi-chip package structure further includes a fourth metal bump between the second and third chip package structures, wherein a plurality of second metal bumps are between the second and third chip package structures, The third chip package structure further includes a third metal pillar in the second polymer layer, wherein the upper surface of the second polymer layer, the upper surface of the dedicated I/O chip, the upper surface of the second metal pillar and the third The upper surfaces of the metal pillars are coplanar, wherein the dedicated I/O chip includes a driver sequentially through the third interconnection line metal layer, the fourth interconnection line metal layer, the fourth metal bump, the third metal pillar, and the first interconnection The connecting wire metal layer and the second interconnecting wire metal layer are coupled to the first metal bump, wherein the driver has a driving capability greater than 2pF.

In the second case: In the thirteenth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the multi-chip package structure further includes a plurality of second metal bumps located under the second chip package structure, wherein the second chip package structure is coupled to the first chip package structure through the second metal bumps, the first The two-chip package structure is a BGA chip package structure, which includes a circuit board coupling the non-volatile memory IC chip to the second metal bumps, wherein the second metal bumps are arranged in a matrix.

In the second case: In the fourteenth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the second chip package structure is a thin-small-outline-package (TSOP), which includes a lead frame and has a non-volatile memory IC chip bonded thereon, and a potting material The lead frame and the non-volatile memory IC chip are wrapped, wherein the non-volatile memory IC chip is coupled to the first chip package structure through the lead frame.

In the second case: In the fifteenth aspect, the non-volatile memory IC chip can be provided via a second chip package structure in the multi-chip package structure, wherein the second chip package structure is located in the first chip package Above the structure, wherein the second chip package structure is a chip level package structure (CSP), wherein the area ratio between the chip level package structure and the non-volatile memory IC chip is equal to or less than 1.5.

In the second case: in the sixteenth aspect, the first chip package structure further includes a second interconnecting wire structure located above the first semiconductor IC chip, the first polymer layer and the first metal pillar, wherein The second interconnect structure includes a third interconnect metal layer over the first semiconductor IC chip, the first polymer layer and the first metal pillar, and a second insulating dielectric layer over the third interconnect above the interconnect metal layer, wherein the third interconnect metal layer includes a metal interconnect straddle a boundary of the underlying first semiconductor IC chip, wherein the non-volatile memory IC chips are sequentially connected through the third interconnect The wire metal layer, the first metal post and the first interconnecting wire metal layer are coupled to the first semiconductor IC chip.

In the second case: In the seventeenth aspect, the first semiconductor IC chip is an FPGAIC chip, and the non-volatile memory IC chip is a NAND flash memory chip or a NOR flash memory chip.

In a third case, a chip package structure includes a semiconductor IC chip, a first polymer layer located outside and extending from sidewalls of the semiconductor integrated circuit (IC) chip in a space extending therefrom, within the first polymer layer The first metal pillar in the material layer, wherein an upper surface of the first polymer layer, the upper surface of the semiconductor integrated circuit (IC) chip and the upper surface of the first metal pillar are coplanar, and an interconnecting wire structure is located Below the semiconductor integrated circuit (IC) chip, the first polymer layer and the first metal pillar, wherein the first interconnecting wire structure includes a first interconnecting wire metal layer located on the semiconductor IC chip, the first polymer layer and below the first metal pillar, wherein the first interconnect metal layer includes a metal interconnect line across the boundary of the underlying semiconductor integrated circuit (IC) chip, and a second interconnect metal layer is located on the first interconnect line A first insulating dielectric layer is located under the metal layer of the interconnection line and between the first and second metal layers of the interconnection line, and a first metal bump is located under the structure of the interconnection line, wherein the first metal bump including a solder layer and having a height between 20 and 100 microns; a second polymer layer overlying the semiconductor integrated circuit (IC) wafer, the first polymer layer and the first metal pillar, wherein the second polymer layer A first opening in the material layer is located above the first metal column; and the first metal pad is located on the upper surface of the first metal column, wherein the upper surface of the first metal column is located at the bottom of the first opening, Wherein the first metal pad includes a copper layer with a thickness between 1 and 10 microns, wherein the first metal pad is coupled to a semiconductor integrated circuit (IC) chip through a first metal pillar and a first interconnecting wire metal layer .

In the third case: in the first aspect, the first metal pad is further coupled to the first metal bump through the first metal pillar, the first interconnection wire metal layer and the second interconnection wire metal layer, the first A metal bump is sequentially coupled to the semiconductor integrated circuit (IC) chip through the second interconnect metal layer and the first interconnect metal layer.

In the third case: In the second aspect, the chip package structure further includes a second metal pillar located in the first polymer layer, wherein the upper surface of the first polymer layer, the semiconductor integrated circuit (IC) The upper surface of the chip, the upper surface of the first metal pillar and the upper surface of the second metal pillar are coplanar, the second metal bump is located under the interconnecting wire structure, wherein the first metal bump includes a solder layer and its height between 20 and 100 microns; and a second metal pad is located on the upper surface of the second metal pillar, wherein the upper surface of the first metal pillar is located at the bottom of a first opening in the second polymer layer; Wherein the second metal pad includes a copper layer with a thickness between 1 and 10 microns, wherein the second metal pad is coupled through the second metal pillar, the first interconnecting wire metal layer and the second interconnecting wire metal layer The second metal bump, wherein the second metal pad is not connected to any semiconductor integrated circuit (IC) chip in the chip package structure.

In the third case: In the third aspect, the semiconductor integrated circuit (IC) chip includes a standard commercial FPGA IC chip, a dedicated control chip, a dedicated I/O chip, a dedicated control and I/O chip, a CPU chip, DSP chips, GPU chips, TPU chips or APU chips, IAC chips, ASIC chips, NAND or NOR flash non-volatile memory chips, HBM chips (eg DRAM chips, SRAM chips, MRAM chips or RRAM chips), analog IC chips , Hybrid module IC chips, RFIC chips).

In a fourth case, a chip package structure includes a semiconductor IC chip, a polymer layer in a space beyond and extending from sidewalls of the semiconductor integrated circuit (IC) chip, a polymer layer in the polymer layer The first metal pillar, wherein an upper surface of the polymer layer, the upper surface of the semiconductor integrated circuit (IC) chip and the upper surface of the first metal pillar are coplanar, and a first interconnecting wire structure is located on the semiconductor IC The circuit (IC) chip, the polymer layer and the bottom of the first metal pillar, wherein the first interconnection line structure includes a first interconnection line metal layer located under the semiconductor IC chip, the polymer layer and the first metal pillar, Wherein the first interconnect metal layer includes a metal interconnect line spanning the boundary of the underlying semiconductor integrated circuit (IC) chip, a second interconnect line metal layer is located under the first interconnect line metal layer and a The first insulating dielectric layer is between the first and second interconnecting metal layers, a first metal bump is located under the first interconnecting structure, wherein the first metal bump includes a solder layer and its height is between 20 and 100 microns; a second interconnect structure is located over the semiconductor integrated circuit (IC) chip, the polymer layer and the first metal pillar, wherein the second interconnect structure includes a second insulating Dielectric layers are located on the semiconductor integrated circuit (IC) chip and polymer layer, a third interconnect metal layer is located over the second insulating dielectric layer and a third insulating dielectric layer is located on the third interconnect on a metal layer of interconnects, wherein the third layer of interconnect metal includes a metal interconnect spanning a boundary above the semiconductor integrated circuit (IC) die, wherein the first interconnect in the third insulating dielectric layer The opening is located above the metal layer of the third interconnection line, and the first metal pad located on the metal layer of the third interconnection line is located at the bottom of the first opening, wherein the first metal pad has a thickness of 1 to a copper layer between 10 microns, wherein the first metal pad is coupled to the semiconductor integrated circuit (IC) chip through the third interconnection wire metal layer, the first metal pillar and the first interconnection wire metal layer.

In a fourth case: In the first aspect, the first metal pad is additionally passed through the third interconnection wire metal layer, the first metal pillar, the first interconnection wire metal layer, and the second interconnection wire metal layer in sequence coupled to the first metal bump.

In a fourth case: In the second aspect, the first metal bump is coupled to a semiconductor integrated circuit (IC) chip via the first interconnect metal layer and the second interconnect metal layer in sequence.

In the fourth case: In the third aspect, the chip package structure further includes a second metal pillar located in the polymer layer, wherein the upper surface of the polymer layer, the upper surface of the semiconductor integrated circuit (IC) chip , the upper surface of the first metal column and the upper surface of the second metal column are coplanar, the second metal bump is located under the interconnecting line structure, wherein the first metal bump includes a solder layer and its height is between 20 and between 100 microns; and a second metal pad located on the third interconnect metal layer is located at the bottom of a first opening in the second polymer layer; wherein the second metal pad includes a thickness of 1 to a copper layer between 10 microns, wherein the second metal pad is coupled to the second metal bump through the third interconnection line metal layer, the second metal pillar, the first interconnection line metal layer and the second interconnection line metal layer A block in which the second metal pad is not connected to any semiconductor integrated circuit (IC) chip in the chip package structure.

In the fourth case: In the fourth aspect, the semiconductor integrated circuit (IC) chip includes a standard commercial FPGA IC chip, a dedicated control chip, a dedicated I/O chip, a dedicated control and I/O chip, a CPU chip, DSP chips, GPU chips, TPU chips or APU chips, IAC chips, ASIC chips, NAND or NOR flash non-volatile memory chips, HBM chips (eg DRAM chips, SRAM chips, MRAM chips or RRAM chips), analog IC chips , Hybrid module IC chips, RFIC chips).

In a fifth case, a chip package structure includes a semiconductor IC chip, a polymer layer in a space beyond and extending from a sidewall of the semiconductor integrated circuit (IC) chip, a polymer layer in the polymer layer The first metal pillar, wherein an upper surface of the polymer layer, the upper surface of the semiconductor integrated circuit (IC) chip and the upper surface of the first metal pillar are coplanar, and a first interconnecting wire structure is located on the semiconductor IC The circuit (IC) chip, the polymer layer and the bottom of the first metal pillar, wherein the first interconnection line structure includes a first interconnection line metal layer located under the semiconductor IC chip, the polymer layer and the first metal pillar, Wherein the first interconnect metal layer includes a metal interconnect line spanning the boundary of the underlying semiconductor integrated circuit (IC) chip, a second interconnect line metal layer is located under the first interconnect line metal layer and a The first insulating dielectric layer is between the first and second interconnecting metal layers, a first metal bump is located under the first interconnecting structure, wherein the first metal bump includes a solder layer and its height is between 20 and 100 microns; a second interconnect structure is located over the semiconductor integrated circuit (IC) chip, the polymer layer and the first metal pillar, wherein the second interconnect structure includes a second insulating Dielectric layers are located on the semiconductor integrated circuit (IC) chip and polymer layer, a third interconnect metal layer is located over the second insulating dielectric layer and a third insulating dielectric layer is located on the third interconnect on a metal layer of interconnects, wherein the third layer of interconnect metal includes a metal interconnect spanning a boundary above the semiconductor integrated circuit (IC) die, wherein the first interconnect in the third insulating dielectric layer The opening is located above the metal layer of the third interconnection line, and the first metal pad located on the metal layer of the third interconnection line is located at the bottom of the first opening, wherein the first metal pad has a thickness of 1 to a copper layer between 10 microns, wherein the first metal pad is coupled to the semiconductor integrated circuit (IC) chip through the third interconnection wire metal layer, the first metal pillar and the first interconnection wire metal layer.

In a fifth case: In the first aspect, the first metal bump is positioned vertically below the first metal pillar.

In a fifth case: In the second aspect, the first metal bumps are positioned vertically below the semiconductor integrated circuit (IC) wafer.

In a fifth case: In the third aspect, the first metal bump is not positioned vertically below the first metal pillar.

In a fifth case: In the fourth aspect, the chip package structure further includes a second interconnecting wire structure located above the semiconductor IC chip, the polymer layer and the first metal pillar, wherein the second interconnecting wire structure includes A second insulating dielectric layer is on the semiconductor IC chip and the polymer layer, a third interconnecting wire metal layer is on the second insulating dielectric layer, and a third insulating dielectric layer is on the third interconnecting wire metal layer layer, wherein the third interconnect metal layer includes a metal interconnect across a boundary of the underlying semiconductor IC chip, wherein an opening in the third insulating dielectric layer is located at the third interconnect metal A metal pad above the layer and located on the third interconnect metal layer is located at the bottom of the opening, wherein the metal pad includes a copper layer having a thickness between 1 and 10 microns, wherein the metal pad is The third interconnect metal layer is coupled to the first metal column, and the metal pad is vertically positioned above the first metal column.

In a fifth case: In the fifth aspect, the chip package structure further includes a second interconnecting wire structure located above the semiconductor IC chip, the polymer layer and the first metal pillar, wherein the second interconnecting wire structure includes A second insulating dielectric layer is on the semiconductor IC chip and the polymer layer, a third interconnecting wire metal layer is on the second insulating dielectric layer, and a third insulating dielectric layer is on the third interconnecting wire metal layer layer, wherein the third interconnect metal layer includes a metal interconnect across a boundary of the underlying semiconductor IC chip, wherein an opening in the third insulating dielectric layer is located at the third interconnect metal A metal pad above the layer and located on the third interconnect metal layer is located at the bottom of the opening, wherein the metal pad includes a copper layer having a thickness between 1 and 10 microns, wherein the metal pad is The third interconnect metal layer is coupled to the first metal column, and the metal pad is vertically positioned above the semiconductor IC chip.

In the fifth case: In the sixth aspect, the chip package structure further includes a second interconnecting wire structure located above the semiconductor IC chip, the polymer layer and the first metal pillar, wherein the second interconnecting wire structure includes A second insulating dielectric layer is on the semiconductor IC chip and the polymer layer, a third interconnecting wire metal layer is on the second insulating dielectric layer, and a third insulating dielectric layer is on the third interconnecting wire metal layer layer, wherein the third interconnect metal layer includes a metal interconnect across a boundary of the underlying semiconductor IC chip, wherein an opening in the third insulating dielectric layer is located at the third interconnect metal A metal pad above the layer and located on the third interconnect metal layer is located at the bottom of the opening, wherein the metal pad includes a copper layer having a thickness between 1 and 10 microns, wherein the metal pad is The third interconnect metal layer is coupled to the first metal pillar, and the metal pad is not positioned vertically above the first metal pillar.

In a fifth case: In the seventh aspect, the chip package structure further includes a second interconnecting wire structure located above the semiconductor IC chip, the polymer layer and the first metal pillar, wherein the second interconnecting wire structure includes A second insulating dielectric layer is on the semiconductor IC chip and the polymer layer, a third interconnecting wire metal layer is on the second insulating dielectric layer, and a third insulating dielectric layer is on the third interconnecting wire metal layer layer, wherein the third interconnect metal layer includes a metal interconnect across a boundary of the underlying semiconductor IC chip, wherein an opening in the third insulating dielectric layer is located at the third interconnect metal A metal pad above the layer and located on the third interconnect metal layer is located at the bottom of the opening, wherein the metal pad includes a copper layer having a thickness between 1 and 10 microns, wherein the metal pad is The third interconnect metal layer is coupled to the first metal pillar, and a horizontal distance between the metal pad and the first metal bump is greater than a maximum lateral dimension of the first metal bump.

In the fifth aspect: in the eighth aspect, the chip package structure further includes a second metal pillar located in the polymer layer, wherein the upper surface of the polymer layer, the upper surface of the semiconductor integrated circuit (IC) chip , The upper surface of the first metal column and the upper surface of the second metal column are coplanar, wherein the second metal column is coupled to the semiconductor integrated circuit (IC) chip through the first interconnecting wire metal layer.

In the fifth case: In the ninth aspect, the semiconductor integrated circuit (IC) chip includes a standard commercial FPGA IC chip, a dedicated control chip, a dedicated I/O chip, a dedicated control and I/O chip, a CPU chip, DSP chips, GPU chips, TPU chips or APU chips, IAC chips, ASIC chips, NAND or NOR flash non-volatile memory chips, HBM chips (eg DRAM chips, SRAM chips, MRAM chips or RRAM chips), analog IC chips , Hybrid module IC chips, RFIC chips).

The limitation of the scope of protection is only defined by the scope of the patent application. The scope of protection is intended and should be construed broadly based on the general meaning of the terms used in the scope of the patent application. The scope of the patent is explained, and all structural and functional equivalents are also included in the explanation.

Unless otherwise stated, all measurements, values, grades, locations, degrees, sizes and other specifications recited in this patent specification, including in the claims below, are approximate or nominal and not necessarily exact ; which are intended to have a reasonable range of functions associated therewith and are consistent with those conventionally used in the art with respect to them.

Nothing in what has been stated or illustrated is intended or should be construed to result in the exclusive use of any component, step, feature, object, benefit, advantage or equivalent disclosed, whether or not recited in the claim.

447: Transistor 448: Transistor 449: Switch 451: word line 452: bit line 453: bit line 258: Pass/No Pass switch 222: Transistor 223: Transistor 533: Pass/No Pass Switch Inverter 292: Tri-state buffer 293: Transistor 294: Transistor 295: Transistor 296: Transistor 297: Inverter 398: SRAM cell 446: memory unit 379: Crosspoint Switch 211: Multiplexer 215: Tri-state buffer 216: Tri-state buffer 217: Tri-state buffer 218: Tri-state buffer 219: reverser 220: reverser 207: Inverter 208: Inverter 231: Transistor 232: Transistor 233: Inverter 272: I/O pads 273: Electrostatic Discharge (ESD) Protection Circuits 274: Large Drive 275: Large Receiver 341: Large I/O Circuits 282: Diode 283: Diode 281: Node 285: Transistor 286: Transistor 287:Non and (NAND) gate 288: Non-OR (NOR) gate 289: Inverter 290:Non and (NAND) gate 291: Inverter 372: I/O pads 373: Electrostatic Discharge (ESD) Protection Circuits 374: Small Drive 375: Small Receiver 203: Small I/O Circuits 382: Diode 383: Diode 381: Node 385: Transistor 386: Transistor 387:Non and (NAND) gate 388: Non-OR (NOR) gate 389: Inverter 391: Inverter 390:Non and (NAND) gate 210: Lookup Table (LUT) 201: Programmable Logic Block (LB) 490: Memory Unit 212: AND (AND) gate 213: Non-and (NAND) gate 214:Non and (NAND) gate 236: AND (AND) gate 237: AND (AND) gate 238: Mutually exclusive OR (ExOR) gate 234: AND (AND) gate 239: AND (AND) gate 242: Mutually exclusive OR (ExOR) gate 253: AND (AND) gate 361: Programmable Interaction Cable 362: Memory Unit 262: Memory Unit 364: Fixed interactive connection line 200: Standard commercial FPGAIC chips 502: Inter-chip interconnection lines 206: Ground Pad 2: Semiconductor substrate 395: Memory array block 279: Bypass Interconnect Line 278: Area 455: Connect Block (CB) 456: Switch Block (SB) 276: Repair with input switch array 277: Repair with output switch array 410: Integrated Circuit (IC) Chips 423: Memory Array Block 205: Power pad 265: a chip dedicated to input/output (I/O) 300: Standard Commercial Logic Drive 250: Non-Volatile Memory (NVM) Integrated Circuit (IC) Chips 260: Dedicated control chip 371: Inter-chip interconnection line 321:NVM:IC chip 266: Dedicated control chip and dedicated I/O chip 402: IAC wafer 267: DCIAC wafer 268: DCDI/OIAC wafer 269: PCIC chip 324: Volatile (VM) Integrated Circuit (IC) Chips 251: High-speed and high-bandwidth memory (HBM) integrated circuit (IC) chips 271: External circuit 360: Control Cube 340: Buffer/Drive Unit 337: Control Unit 586: Splice connection point 336: Switch 454: word line 4: Semiconductor components 20: Interconnecting Line Structure/FISC 6: Interconnect wire metal layer 10: Metal plug 8: Metal pads, wires and connecting wires 12: Insulating dielectric layer 12a: Bottom distinguishing etch stop layer 15: Photoresist layer 15a: Grooves or multiple openings 12d: groove or multiple openings 18: Adhesive layer 22: Seed layer for electroplating 24: Copper metal layer 12e: Dielectric layer 12g: Top low-dielectric SiOC layer 12f: Intermediate differentiated etch stop layer 12h: Top layer distinguishes etch stop layer 12i: Groove or top opening 17: Second photoresist layer 17a: Grooves or multiple openings 12j: Holes or bottom openings 16: Metal pads 14: Protective layer 14a: Opening 26: Adhesive layer 28: Seed Layer 30: photoresist layer 30a: Opening 32: metal layer/copper layer 34: Micro bumps or metal pillars 36: Polymer layer 38: photoresist layer 38a: Grooves or multiple openings 40: Metal layer 27 Interconnect wire metal layer 42: Polymer layer 51: Polymer layer 29: SISC 42a: Opening 27a: Metal plug 27b: Metal pads, wires or connecting wires 51a: Opening 202: Programmable Interaction Cable 44: Adhesive layer 46: Seed layer for electroplating 48: photoresist layer 48a: Opening 50: Copper metal layer 100: Semiconductor wafer 90: carrier substrate 88: Adhesive material 92: polymer layer 93: Polymer layer 93a: Opening 94: Adhesion/Seed Layer 96: photoresist layer 96a: Opening 98: Metal layer 99: Interconnect wire metal layer 99a: Metal plug 104: Polymer Layer 104a: Opening 101:TISD 99b: Metal pads, wires or connecting wires 116: Adhesion/Seed Layer 118: photoresist layer 118a: Opening 120: metal layer 122: Metal pillars or bumps 126: Flexible circuit board or film 148: Polymer Layer 146: Copper Bonding Wire 150: Polymer protective layer 152: Solder layer 154: tin gold alloy 156: polymer material 158:TPVs 91: Insulation layer 97: Polymer layer 97a: Opening 140: Adhesion/Seed Layer 142: photoresist layer 142a: Opening 144: Copper layer 158a: Back 110: Circuit carrier or substrate 109: Metal Pad 114: Underfill material 112: Solder, Solder Paste or Flux 325: Solder Ball 113: Substrate unit 79: BISD 81: Adhesive layer 83: Seed layer for electroplating 75: photoresist layer 75a: Opening 85: Metal layer 77: Interconnect wire metal layer 94a: Opening 77a: Metal plug 77b: Metal pads, wires or connecting wires 87: Polymer layer 87a: Opening 77c: Metal Flat 77d: Metal Flat 140b: Seed layer for electroplating 140a: Adhesive layer 53: Area 77e: Pad 583: Solder/Metal Bumps 54: Micro bumps 411: First Interactive Connection Wire Net 412: Second Interactive Connection Net 413: Third Interconnection Wire Net 414: Fourth Interconnection Net 415: Fifth Interconnection Wire Net 416: Sixth Interconnection Wire Net 417: Seventh Interconnection Wire Net 418: The Eighth Interconnection Network 419: Ninth Interconnection Network 420: Tenth Interconnection Line 421: Eleventh Interconnect Line 422: Twelfth Interconnect Line 461: Internal drive interactive connection line 462: Second internal drive interactive connection line 463: The third internal drive interactive connection line 464: Fourth internal drive interaction connection line 482: Interactive Connection Line 201: Neuron or nerve cell 481:Dendrite 322: Non-volatile memory drive 323: Volatile Memory Drive 305: I/Os port 301: Baseband processor 330: Desktop or Laptop, Mobile or Smartphone or AI Robot 302: Application Processor 303: Other processors 304: Power Management 306: Wireless Signal Communication Components 308: Camera 307: Display device 309: Audio Settings 310: Memory drive, disk or device 311: Keyboard 312: Ethernet 314: I/O port 313: Power management chip 587: stack path 610: Nonvolatile Programmable Logic Driver/POP Package Structure 510:NVM chip package structure 520: Logic chip package structure 550: Single-layer chip package structure or small chip 516: Solder Joints 517: Underfill material 511: Adhesive layer 513: circuit board 524: Adhesive layer 514: Wire Wire 515: Molded Polymer 519: Polymer Layer 518: Interconnect wire metal layer 570: Metal bumps, posts or pads 530: circuit board 521: Solder Joints 522: Underfill material 523: Solder bumps or balls 92: polymer layer 531: junction contacts 534: Copper bumps 535: Tin-containing metal layer 532: Underfill material 540: I/O Chip Package Structure 536: Solder Joints 542: Solder Joints 541: Underfill material 108: Metal pads, wires or connecting wires 536: Solder Contacts 560:HBM chip package structure 558: Solder Contacts 559: Underfill material 537: Underfill material 431: Metal connecting wire 432: Neck 434: Barrier 433: switch 435: Anti-fuse 436: Electrodes 437: Electrodes 438: Oxidation window 611: POP package structure 526: Solder Contact 527: Underfill material 528: Bypass Interconnect Line 529: Busbar 733: P-fin 732: P-well 729: Field Oxide 737: Gate 738: Metal Layer 739: Conductive metal layer 740: gate oxide 832: P-well 831: P-strip 833: P-fin 833a: Opening 833b: Longitudinal section 829: Field Oxide 837: Gate 838: Working functional metal layer 839: Conductive metal layer 840: gate oxide 2031: Logic Gate OR Circuits 2016: Addition Unit 2032: Multiplexer 2033: Multiplexer 2034: D-type flip-flop circuit 2036: Multiplexer 2037: Logic Operators or Circuits 2039: D-Type Flip-Flop Circuits 2038: Coupling Cascade Circuit 2040: Clock Bus 2041: Set/Reset Control Circuit 2042: Clock Control Circuit 2043: Multiplexer 2042: Large Granular Reconfiguration Unit 2043: Functional Unit (FU) 2044: input point 2046: Register file memory block

The drawings disclose illustrative embodiments of the invention. It does not describe all embodiments. Other embodiments may additionally or alternatively be used. Details that are obvious or unnecessary may be omitted to save space or to illustrate more efficiently. Rather, some embodiments may be practiced without disclosing all details. When the same numbers appear in different drawings, they refer to the same or similar components or steps.

Aspects of the present invention may be more fully understood when the following description is read in conjunction with the accompanying drawings, which are to be regarded in an illustrative rather than a restrictive nature. The drawings are not necessarily to scale, emphasizing the principles of the invention.

1A and 1B are circuit diagrams of various types of complex memory cells according to an embodiment of the present invention.

2A to 2F are circuit diagrams of various types of pass/no-pass switches in embodiments of the present invention.

3A to 3D are block diagrams of various types of complex cross-point switches according to embodiments of the present invention.

FIG. 4A and FIGS. 4C to 4J are circuit diagrams of various types of complex multiplexers in the embodiments of the present invention.

FIG. 4B is a circuit diagram of a tri-state buffer in the multiplexer according to the embodiment of the present invention.

FIG. 5A is a circuit diagram of a large I/O circuit in an embodiment of the present invention.

FIG. 5B is a circuit diagram of a small and medium-sized I/O circuit according to an embodiment of the present invention.

FIG. 6A is a schematic diagram of a programmable logic operation block according to an embodiment of the present invention.

FIG. 6B is a circuit diagram of a logic operation operation unit in an embodiment of the present invention.

FIG. 6C is a look-up table of the logical operation unit of FIG. 6B according to an embodiment of the present invention.

FIG. 6C is a look-up table of the calculation operation unit of FIG. 6E in the embodiment of the present invention.

FIG. 6E is a circuit diagram of a computing operation unit in an embodiment of the present invention.

FIGS. 7A to 7C are block diagrams of programming of a plurality of programmable interconnect lines via pass/no pass switches or crosspoint switches in accordance with an embodiment of the present invention.

Figures 8A to 8H are top views of various arrangements of commercial standard FPGAIC chips in embodiments of the present invention.

8I to 8J are block diagrams of various repair algorithms according to embodiments of the present invention.

FIG. 9 is a block top view of a dedicated programmable interconnection (DPI) on an integrated circuit (IC) chip according to an embodiment of the present invention.

FIG. 10 is a block top view of a dedicated input/output (I/O) chip in accordance with an embodiment of the present invention.

11A to 11N are top views of various types of logical drive arrangements in an embodiment of the present invention.

12A to 12C are block diagrams of various types of connections between multiple chips in a logic driver according to an embodiment of the present invention.

13A to 13B are block diagrams for loading data into a plurality of memory cells in an embodiment of the present invention.

FIG. 14A is a cross-sectional view of a semiconductor wafer according to an embodiment of the present invention.

FIGS. 14B to 14H are cross-sectional views illustrating the formation of the first interconnect structure by a single damascene process according to an embodiment of the present invention.

FIGS. 14I to 14Q are cross-sectional views illustrating the formation of the first interconnect structure by a double damascene process according to an embodiment of the present invention.

FIGS. 15A to 15H are cross-sectional views of the process of forming micro bumps or micro metal pillars on a wafer according to an embodiment of the present invention.

FIGS. 16A to 16L and FIG. 17 illustrate the process of forming a second interconnecting line structure on a protective layer and forming a plurality of micro metal pillars or micro bumps on the second interconnecting line metal layer in accordance with an embodiment of the present invention Sectional drawing.

18A to 18W are schematic diagrams of the process of forming a single-level package logic driver according to FOIT in the implementation of the present invention.

FIGS. 19A to 19L are cross-sectional schematic diagrams of a process for forming a single-level package logic driver according to TPVS and FOIT according to an embodiment of the present invention.

19A to 19L are schematic cross-sectional views of a package-to-package (POP) packaging process according to an embodiment of the present invention.

FIGS. 19S to 19Z are cross-sectional schematic diagrams of a process of forming a single-level package logic driver according to TPVS and FOIT according to an embodiment of the present invention.

20A to 20M are schematic diagrams of a process of forming a BISD on a carrier substrate according to an embodiment of the present invention.

FIG. 20N is a top view of the metal plane in the embodiment of the present invention.

20O to 20R are schematic cross-sectional views of the process of forming a plurality of package vias (TPVs) on the BISD according to the embodiment of the present invention.

FIGS. 20S to 20Z are schematic cross-sectional views of a process for forming a single-level package logic driver according to an embodiment of the present invention.

21A to 21B are top views of the TPVS in the embodiment of the present invention.

FIGS. 21B to 21G are schematic cross-sectional views of various interconnected interconnection nets in a single-layer packaged logic driver according to an embodiment of the present invention.

FIG. 21H is a bottom view of FIG. 25G, which is a schematic diagram of the layout of the plurality of metal pads in the logic driver according to the embodiment of the present invention.

22A to 22I are schematic diagrams of a process for manufacturing a POP package in an embodiment of the present invention.

FIGS. 23A to 23B are conceptual diagrams of the interconnection lines between the plurality of logic blocks simulated from the human nervous system according to the embodiment of the present invention.

24A to 24K are schematic diagrams of multiple combinations of POP packages used for logic operations and memory drivers according to an embodiment of the present invention.

FIG. 24L is a top view of a plurality of POP packages according to an embodiment of the present invention, and FIG. 24K is a schematic cross-sectional view along the cutting line A-A.

25A to 25C are schematic diagrams of various applications of logic operations and memory drivers in embodiments of the present invention.

FIGS. 26A to 26F are top views of various commercial standard memory drives according to embodiments of the present invention.

27A to 27C are schematic cross-sectional views of various packages for logic and memory drivers according to embodiments of the present invention.

28A to 28G are schematic diagrams of the process of forming the chip package structure with TPVs according to the third embodiment of the present invention.

FIG. 28J and FIG. 28K are schematic diagrams of a process for a chip package structure with BISDs and TPVs according to the second embodiment of the present invention.

FIG. 28L is a schematic diagram of a process for forming BISD and TPVs in an embodiment of the present invention.

FIGS. 29A to 29K are schematic cross-sectional views of various types of non-volatile programmable logic drivers in POP packages according to embodiments of the present invention, as an ASIC chip.

FIG. 29L is a schematic cross-sectional view of a POP packaging structure according to an embodiment of the present invention.

FIG. 30A is a schematic diagram of an operation block of a fuse according to an embodiment of the present invention.

FIG. 30B is a top view of the structure of an electronic fuse (e-fuse) according to an embodiment of the present invention.

FIG. 30C is a schematic cross-sectional view of the anti-fuse 435 according to an embodiment of the present invention.

FIG. 31A is a schematic structural diagram of a fin field effect transistor (FinFET) according to an embodiment of the present invention.

FIG. 31B is a schematic cross-sectional view of the FinFET along the section line B-B in FIG. 31A according to an embodiment of the present invention.

FIG. 32A is a schematic diagram of a structure of a gate full ring transistor in an embodiment of the present invention.

FIG. 32B is a schematic cross-sectional view of the structure of the gate full-ring transistor along the section line C-C in FIG. 32A.

FIG. 33 is a block diagram of a programmable logic block (LB) according to an embodiment of the present invention.

FIG. 34 is a schematic block diagram of a programmable logic unit or device according to an embodiment of the present invention.

FIG. 35 is a schematic diagram of a plurality of CGRAs in matrix form according to another embodiment of the present invention.

FIG. 36 is a trend diagram of the relationship between non-recurring engineering (NRE) costs and technology nodes disclosed in the present invention.

While certain embodiments have been depicted in the drawings, those skilled in the art will appreciate that the depicted embodiments are illustrative and that variations of the embodiments shown may be contemplated and implemented within the scope of the present invention. and other embodiments described herein.

79: BISD

42: Polymer layer

27: Interconnect wire metal layer

92: polymer layer

101:TISD

521: Solder Joints

523: Solder bumps or balls

136: polymer layer

108: Metal pads, wires or connecting wires

200:FPGAIC chip

250: NVMIC chip

534: Copper bumps

535: Tin-containing metal layer

531: junction contacts

532: Underfill material

520: Logic chip package structure

530: circuit board

610: Nonvolatile Programmable Logic Driver

Claims (28)

A multi-chip package structure, including: A first interconnection line structure includes a first interconnection line metal layer, a second interconnection line metal layer over the second interconnection line metal layer, and a first insulating dielectric layer over the second interconnection line metal layer between an interconnecting metal layer and the second interconnecting metal layer; A Field Programmable Gate Array (FPGA) integrated circuit (IC) chip is positioned above the first interconnect structure, wherein the Field Programmable Gate Array (FPGA) ) integrated circuit (IC) chip is coupled to the second interconnection line metal layer, wherein the first interconnection line structure includes an interconnection line metal line located under the field programmable logic gate array IC chip and straddles a boundary of the field programmable logic gate array integrated circuit chip; A metal connection channel is located above the first interconnecting line structure and is located on the same level as the FPGA IC chip, wherein the metal connection channel is located in the FPGA In a space extending in a horizontal direction outside a side wall of the bulk circuit chip, wherein the metal connection channel provides a connection in a vertical direction perpendicular to the horizontal direction, wherein the metal connection channel is through the second interconnection line The metal layer is coupled to the FPGA IC chip, wherein the metal connection channel includes a copper layer with a thickness between 5 and 300 microns; and A non-volatile memory circuit (IC) chip is positioned above the FPGA IC chip, wherein the non-volatile memory circuit chip passes through the metal connection channel and the second interconnection in sequence The wire metal layer is coupled to the field programmable logic gate array IC chip. The multi-chip package structure as claimed in claim 1, wherein the field programmable logic gate array integrated circuit chip includes a configurable circuit and a volatile memory unit for storing the first data therein, wherein the The first data is used for configuring the configurable circuit, wherein the non-volatile memory circuit chip includes a non-volatile memory cell for storing second data therein, wherein the first data is associated with the second data . As claimed in the multi-chip package structure of claim 2 of the claimed scope, the configurable circuit is a reconfigurable circuit. As claimed in the multi-chip package structure of claim 2, the volatile memory cell includes a static random-access-memory (SRAM) cell. As claimed in the multi-chip package structure of claim 1, the field programmable logic gate array integrated circuit chip includes a configurable logic circuit and a volatile memory unit for storing the first data therein, wherein the The first data is used to configure the configurable logic circuit, wherein the non-volatile memory circuit chip includes a non-volatile memory cell for storing second data therein, wherein the first data is related to the second data link. As claimed in the multi-chip package structure of claim 5, the configurable logic circuit is a reconfigurable circuit. As claimed in the multi-chip package structure of claim 5, the configurable logic circuit includes a selection circuit, the selection circuit having a first set of input points for a first input data set for a logic operation and having a The second set of input points is used for a second set of input data having data associated with the first data, wherein the first data is used for a look-up table (LUT) ) is associated with a result value of ), wherein the selection circuit is configured to select an input data from the second input data set based on the first input data set as output data for the logic operation. As claimed in the multi-chip package structure of claim 5, the volatile memory cell includes a static random access memory cell. As claimed in the multi-chip package structure of claim 1, the field programmable logic gate array integrated circuit chip includes a configurable interconnect circuit and a first volatile memory unit for storing the first data in wherein the first data is used for configuring the configurable interconnect circuit, wherein the first non-volatile memory circuit chip includes a first non-volatile memory unit for storing the second data therein, Wherein the first data is associated with the second data. As claimed in the multi-chip package structure of claim 9, the reconfigurable interconnect circuit is a reconfigurable circuit. The multi-chip package structure as claimed in claim 9, wherein the configurable interconnecting line circuit comprises a first conductive interconnecting line, a second conductive interconnecting line and a configurable switching circuit, the configurable interconnecting line The switch circuit has a first input point coupled to the first conductive interconnection line, a first input point coupled to the second conductive interconnection line, and a second input point for input and the first Data associated data, wherein the configured switch circuit is configured to control the coupling between the first conductive interconnection line and the second conductive interconnection line according to the input data at the second input point . The multi-chip package structure as claimed in claim 11, wherein the field programmable logic gate array IC further includes a second volatile memory unit for storing third data therein, wherein the configurable The interconnection circuit further includes a configurable selection circuit coupled to the configurable switch circuit via the first conductive interconnection, wherein the configurable selection circuit includes a third conductive interconnection and a fourth conductive interconnection , a third input point is coupled to the third conductive interconnection line, a fourth input point is coupled to the fourth conductive interconnection line, a second output point is coupled to the first conductive interconnection line, and a fifth an input point for inputting data associated with the third data, wherein the configurable selection circuit is configured to select among the third and fourth conductive interconnects according to the input data at the fifth input point One of them is coupled to the second output point, wherein the non-volatile memory circuit chip further includes a second non-volatile memory unit for storing a fourth data associated with the third data. As claimed in the multi-chip package structure of claim 9, the first volatile memory cell includes a static random access memory cell. The multi-chip package structure as claimed in claim 1, further comprising a polymer layer in the space and above the first interconnect structure, wherein the polymer layer is positioned on the field programmable The logic gate IC chip and the metal connection channel are on the same level, wherein the metal connection channel extends vertically through the polymer layer, wherein an upper surface of the polymer layer and an upper surface of the metal connection channel coplanar. The multi-chip package structure as claimed in claim 1, wherein the first interconnecting wire structure, the FPGA IC chip and the metal connection channel are formed by one of the multi-chip packaging structures The chip package structure is provided, wherein the chip package structure is located below the non-volatile memory circuit chip, wherein the multi-chip package structure further includes a metal bump located on a bottom of the chip package structure, wherein the metal bump The block is located at a bottom of the first interconnect structure and is coupled to the first interconnect metal layer. The multi-chip package structure as claimed in claim 15, wherein the metal bump includes a solder layer having a thickness between 20 and 100 microns. The multi-chip package structure as claimed in claim 1, wherein the metal connection via comprises a copper layer having a thickness between 10 and 100 microns. The multi-chip package structure as claimed in claim 1, wherein the non-volatile memory circuit (IC) chip is provided by a chip package structure in the multi-chip package structure, wherein the chip package structure is located in Above the first interconnecting wire structure, the FPGA IC chip and the metal connection channel, wherein the chip package structure is coupled to the FPGA IC chip via the metal connection channel . The multi-chip package structure as claimed in claim 18, wherein the multi-chip package structure further comprises a metal bump on a bottom of the chip package structure, wherein the chip package structure is coupled via the metal bump The metal connection channel. The multi-chip package structure as claimed in claim 19, wherein the chip package structure includes a polymer layer and a second interconnecting wire structure, the polymer layer is located on a side of the non-volatile memory circuit chip In a space outside the sidewall and extending in a horizontal direction, the second interconnecting line structure is located under the non-volatile memory circuit chip and the polymer layer, wherein the second interconnecting line structure includes a A third interconnect metal layer, a fourth interconnect metal layer and a second insulating dielectric layer, the third interconnect metal layer is located under the non-volatile memory bulk circuit chip and the polymer layer , the fourth interconnection wire metal layer is located under the third interconnection wire metal layer and the second insulating dielectric layer is located between the third interconnection wire metal layer and the fourth interconnection wire metal layer, Wherein the second interconnecting line structure includes a metal interconnecting line under the non-volatile memory circuit chip and across a boundary of the non-volatile memory circuit chip, wherein the metal bump is located on the first A bottom of the two interconnecting line structures is coupled to the fourth interconnecting line metal layer, wherein the non-volatile memory circuit chip passes through the third interconnecting line metal layer and the fourth interconnecting line metal layer in sequence , the metal bump, the metal connection channel and the second interconnection wire metal layer are coupled to the field programmable logic gate array integrated circuit chip. The multi-chip package structure as claimed in claim 1 of the claimed scope further comprises a second interconnecting wire structure located above the FPGA IC chip, the polymer layer and the metal connection channel, Wherein the second interconnecting wire structure includes a third interconnecting wire metal layer and a second insulating dielectric layer, the third interconnecting wire metal layer is located on the field programmable logic gate array integrated circuit chip, the polymer above the material layer and the metal connection channel, the second insulating dielectric layer is located above the third interconnection line metal layer, wherein the second interconnection line structure includes a metal interconnection line located in the field programmable logic over and across a boundary of the FPGA IC chip, wherein the non-volatile memory IC chip is positioned over the second interconnect structure and sequentially passed through The third interconnection wire metal layer, the metal connection channel and the second interconnection wire metal layer are coupled to the field programmable logic gate array integrated circuit chip. The multi-chip package structure as claimed in claim 1, wherein the non-volatile memory circuit chip is a NAND flash chip. The multi-chip package structure as claimed in claim 1, wherein the non-volatile memory circuit chip is a NOR flash chip. The multi-chip package structure as claimed in claim 1, wherein the FPGA IC chip is implemented with a semiconductor technology node advanced or equal to 10 nanometers. The multi-chip package structure as claimed in claim 24, wherein the field programmable logic gate array IC includes a transistor having a gate length less than or equal to 10 nm. The multi-chip package structure as claimed in claim 24, wherein the field programmable logic gate array IC includes a transistor having a gate oxide having a physical thickness of the gate oxide less than or equal to 4 nm. The multi-chip package structure as claimed in claim 24 is a standard commercial hardware, wherein the non-volatile memory IC chip includes a plurality of non-volatile memory cells for storing data therein , to configure the field programmable logic gate array IC for a specific application as a specific application device. The multi-chip package structure as claimed in claim 1, wherein the field programmable logic gate array IC is implemented with a semiconductor technology node advanced or equal to 10 nanometers, wherein the multi-chip The package structure provides a non-volatile reconfigurable device that enables a creator to implement his ideas under the semiconductor technology node.

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