CN109684653B - Programmable gate array package containing programmable computing units - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000003491 array Methods 0.000 description 4
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention provides a programmable gate array package, which comprises at least one programmable computing chip and one programmable logic chip. The programmable computing chip contains a plurality of programmable computing units, each containing a writable memory array that stores a look-up table (LUT) of a basis function. The programmable compute chip and the programmable logic chip are vertically stacked and electrically coupled by inter-chip connections.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to programmable gate arrays.
Background
The programmable gate array belongs to a semi-custom integrated circuit, namely, the customization of a logic circuit is realized through a back-end process or field programming. U.S. Pat. No. 4,870,302 discloses a programmable gate array. It contains a plurality of programmable logic units (configurable logic element, or configurable logic block) and programmable connections (configurable interconnect, or programmable interconnect). The programmable logic unit can selectively realize functions of shift, logical negation, AND (logical AND), OR (logical AND), NOR (AND), NAND (NAND), XOR (exclusive OR), plus (arithmetic addition), minus (arithmetic subtraction) AND the like under the control of a setting signal; the programmable connection can selectively realize the functions of connection, disconnection and the like between the two interconnection lines under the control of the setting signal.
Currently, many applications involve the computation of complex functions. Complex functions typically contain multiple arguments, which are a combination of basic functions. The basis functions contain one or a small number of arguments, examples of which include transcendental functions such as exponential (exp), logarithmic (log), trigonometric functions (sin, cos), etc. To guarantee execution speed, high performance applications require hardware to implement complex functions. In existing programmable gate arrays, complex functions are implemented by solidifying the computational cells. These cure computation units are part of a hard core (hard block) whose circuitry has been cured and cannot be reconfigured. It is clear that the curing calculation unit will limit further applications of the programmable gate array. To overcome this difficulty, the present invention generalizes the concept of programmable gates to make the solidification computation unit programmable. Specifically, the programmable gate circuit includes a programmable computing unit in addition to the programmable logic unit. The programmable computing unit may selectively implement any of a variety of functions.
Disclosure of Invention
The invention mainly aims to popularize the application of the programmable gate circuit in the field of complex mathematical computation.
It is a further object of the invention to provide a programmable gate whose logic functions can be customized as well as whose computing functions.
It is a further object of this invention to provide a programmable gate array that is more computationally flexible and powerful.
It is another object of the present invention to provide a programmable gate array with a smaller chip area and lower cost.
To achieve these and other objects, the present invention provides a programmable gate array package. It contains at least one programmable computing chip and one programmable logic chip. The programmable computing chip contains an array of programmable computing cells, and the programmable logic chip contains an array of programmable logic cells. The gate array package also contains a plurality of programmable connections distributed among the programmable compute chip and/or the programmable logic chip. Each programmable compute unit contains at least one writable memory array that stores a look-up table (LUT) of a function. The use of programmable computing units is divided into two phases: a setup phase and a calculation phase. In the setting stage, the LUT of the required function is loaded into a writable array according to the requirement of a user; in the calculation phase, the values of the basis functions are obtained by looking up the LUT. By using a writable array, different functions can be implemented even for the same lot of chips. Moreover, for a programmable gate array based on a multiple-time-to-multiple-program Memory (MTP) array, the programmable gate array can implement reconfigurable computation because the MTP array can be loaded with LUTs of different functions at different time periods.
In addition to the programmable compute units, the programmable gate array package also contains a plurality of programmable logic units and programmable connections. The programmable logic unit selectively realizes a logic operation from a logic operation library; the programmable connection may selectively implement one of a variety of connections. In the implementation of a complex function, the complex function is first decomposed into a plurality of basis functions. Then, a corresponding programmable computing unit is set for each basic function, so that the corresponding basic function is realized. Finally, by setting up programmable logic units and programmable connections, the required complex functions are realized.
Accordingly, the present invention proposes a programmable gate array package (400) characterized by comprising: a programmable computing chip (100W) comprising a plurality of programmable computing units (100 AA-100 AD), the programmable computing units (100 AA-100 AD) comprising at least one writable memory array (110), the writable memory array (110) storing at least part of a look-up table (LUT) of a basis function; a programmable logic chip (200W) comprising a plurality of programmable logic units (200 AA-200 AD), the programmable logic units (200 AA-200 AD) comprising at least one programmable logic unit (200), the programmable logic unit (200) selectively implementing a logic operation from a logic operation library; a plurality of programmable connections (300) selectively coupling the programmable computing units (100 AA-100 AD) and the programmable logic units (200 AA-200 AD); -implementing a complex function by programming the programmable computing unit (100 AA-100 AD), the programmable logic unit (200 AA-200 AD) and the programmable connection (300), the complex function being a combination of the basic functions; the programmable computing chip (100W) and the programmable logic chip (200W) are electrically coupled by an inter-chip connection (160).
Drawings
Fig. 1 is a symbol of a programmable computing unit.
Fig. 2 is a substrate circuit layout diagram of a programmable computing unit.
Fig. 3 is a layout diagram of a programmable gate array.
Fig. 4 shows two periods of use of a reconfigurable gate array.
FIG. 5A discloses a connection library for a programmable connection implementation; fig. 5B discloses a logic operation library of a programmable logic cell implementation.
Fig. 6 is a layout diagram of an implementation of such a programmable gate array.
Fig. 7 is a perspective view of a programmable gate array package.
Fig. 8A-8C are cross-sectional views of three programmable gate array packages.
It is noted that these figures are merely schematic and they are not drawn to scale. Some of the dimensions and structures in the figures may be exaggerated or reduced for clarity and convenience. The same reference numerals generally designate corresponding or similar structures in different embodiments.
Description of the embodiments
Fig. 1 is a symbol of a programmable computing unit 100. The input terminal IN thereof includes input data 115, the output terminal OUT includes output data 135, and the set terminal CFG includes a set signal 125. When the setting signal 125 is "write", the LUT of the required basic functions is written in the programmable computing unit 100. When the set signal 125 is "read", the values in the LUT are read out from the programmable computing unit 100. Fig. 2 is a circuit layout diagram of a programmable computing unit 100. In this embodiment, the LUT is stored in at least one writable storage array 110. The circuit also includes peripheral circuitry for the writable memory array 110: an X decoder 15 and a Y decoder (including a readout circuit) 17, and the like. The writable storage array 110 may be RAM or ROM. Examples of the RAM include SRAM, DRAM, and the like; examples of the ROM include OTP (one time programming), MTP (multiple time programming), and the like. Among them, MTP includes EPROM, EEPROM, flash memory, etc.
Fig. 3 shows a programmable gate array 400. It contains a regular arrangement of programmable modules 400A and 400B, etc. Each programmable module (e.g., 400A) contains a plurality of programmable computing units (e.g., 100AA-100 AD) and programmable logic units (e.g., 200AA-200 AD). A programmable channel 320, 340 is included between the programmable computational unit (e.g., 100AA-100 AD) and the programmable logic unit (e.g., 200AA-200 AD); between the programmable modules 400A and 400B, programmable channels 310, 330, 350 are also included. The programmable channels 310-350 contain a plurality of programmable connections 300. It will be apparent to those skilled in the art that a sea-of-gates design or the like may be used in addition to the programmable channels.
Fig. 4 shows two usage periods 620 and 660 of the reconfigurable gate array 400. The first usage period 620 is divided into two phases: a setup phase 610 and a calculation phase 630. In the setup phase 610, a lookup table associated with a basis function is loaded into the MTP array 110 according to user needs; in the calculation stage 630, the corresponding LUT is looked up in the MTP array 110 to obtain the value of the basis function. Similarly, the second usage period 660 also contains the same setup phase 650 and calculation phase 670. Reconfigurable computing is particularly suited for data processing in SIMD (single instruction multiple data stream). Once the LUT is loaded into the MTP array 110 at the setup stage 610, a large amount of data can be fed into the programmable computing unit 100 for processing and a higher processing speed is achieved. The SIMD has many applications such as the same operation or vector operation for a plurality of pixels in image processing, large-scale parallel computation used in scientific computation, and the like. In addition, the programmable gate array can streamline the computation in its programmable compute units to further increase throughput.
Fig. 5A discloses a connection library that can be implemented by the programmable connection 300. The programmable connection 300 is similar to the programmable connection disclosed in U.S. Pat. No. 4,870,302. It adopts a connection mode of the following connection library: a) Interconnect lines 302/304 are connected, interconnect lines 306/308 are connected, but 302/304 is disconnected from 306/308; b) Interconnect lines 302/304/306/308 are all connected; c) Interconnect lines 306/308 are connected, and interconnect lines 302, 304 are not connected nor are interconnect lines 306/308 connected; d) Interconnect lines 302/304 are connected, and interconnect lines 306, 306 are not connected nor are interconnect lines 302/304 connected; e) None of the interconnect lines 302, 304, 306 are connected. In this specification, a symbol "/" between two interconnect lines indicates that the two interconnect lines are connected, and a symbol "/" between two interconnect lines indicates that the two interconnect lines are disconnected.
Fig. 5B discloses a logic operation library that can be implemented by the programmable logic unit 200. Inputs a and B are input data 210, 220 and output C is output data 230. The programmable logic unit 200 is similar to the programmable logic unit disclosed in U.S. Pat. No. 4,870,302. It may implement at least one of the following logical operation libraries: c= A, A logical negation, a shift, AND (a, B), OR (a, B), NAND (a, B), NOR (a, B), XOR (a, B), arithmetic addition a+b, arithmetic subtraction a-B, AND the like. The programmable logic unit 200 may also contain circuit elements such as registers, flip-flops, etc. to implement pipeline operations.
Fig. 6 is a specific implementation of a programmable gate array 400 for implementing a complex function: e=a . sin(b)+c . cos (d). The programmable connection 300 in the programmable channels 310-350 takes the form represented in fig. 5A: a programmable connection with dots at the cross-point indicates that the cross-lines are connected, a programmable connection without dots at the cross-point indicates that the cross-lines are disconnected, and a broken programmable connection indicates that the broken interconnect line is divided into two interconnect segments that are disconnected from each other. In this embodiment, the programmable computing unit 100AA is set to log (), the result of which log (a) is sent to a first input of the programmable logic unit 200 AA. The programmable computing unit 100AB is set to log [ sin ()]The calculation result log [ sin (b) ]]Is provided to a second input of programmable logic unit 200 AA. The programmable logic unit 200AA is set to "arithmetic addition" and calculates the result log (a) +log [ sin (b) ]]Is sent to the programmable computing unit 100BA. The programmable computing unit 100BA is set to exp (), the result exp { log (a) +log [ sin (b)]}=a . sin (b) is supplied to a first input of programmable logic unit 200 BA. Similarly, with appropriate settings, programmable computing units 100AC, 100AD, programmable logic unit 200AC, result c of programmable computing unit 100BC . cos (d) is supplied to a second input of programmable logic unit 200 BA. The programmable logic unit 200BA is set to "arithmetic addition," a . sin (b) and c . cos (d) is added here and the final result is sent to output e. It is apparent that other complex functions can be implemented by the programmable gate array 400 by changing the settings.
Fig. 7 is a perspective view of a programmable gate array package 400. It contains a programmable computing chip 100W and a programmable logic chip 200W. The programmable computing chip 100W is formed in a computing chip substrate 100S, which contains a plurality of programmable computing units 100AA-100BB. Each programmable computing unit 100 contains a writable memory array 110 for storing a look-up table (LUT) of basis functions. The programmable logic chip 200W is formed in a logic chip substrate 200S and contains a plurality of programmable logic units 200AA-200BB, each programmable logic unit 200 selectively implementing a logic operation from a logic operation library. The programmable computing chip 100W is electrically coupled to the programmable logic chip 200W through a plurality of inter-chip connections 160. The inter-chip connection 160 may be a micro-bump (micro-bump) or a Through Silicon Via (TSV). The programmable gate array package 400 also contains a plurality of programmable connections, one part of which is located in the programmable computing chip 100W and another part of which is located in the programmable logic chip 200W.
Fig. 8A-8C are cross-sectional views of three programmable gate array packages 400, each of which is a multi-chip package (MCP). The programmable gate array package 400 of fig. 8A contains two separate chips: a programmable computing chip 100W and a programmable logic chip 200W. The chips 100W, 200W are stacked on the package substrate 110 and are located in the same package 130. Micro-pads 116 provide electrical coupling to them and function as inter-chip connections 160. In the present embodiment, the programmable computing chip 100W is stacked on the programmable logic chip 200W; meanwhile, the programmable computing chip 100W is flipped and stacked face-to-face with the programmable logic chip 200W. In other embodiments, the programmable computing chip 100W may not be flipped; alternatively, the programmable logic chip 200W is stacked on the programmable computing chip 100W.
The programmable gate array package 400 in fig. 8B contains a programmable compute chip 100W, a programmable logic chip 200W, and a silicon interposer (interposer) 120. The silicon interposer 120 contains a plurality of Through Silicon Vias (TSVs) 118 that facilitate electrical coupling between the programmable compute chip 100W and the programmable logic chip 200W, provide more freedom of design, and provide better heat dissipation. This embodiment also includes a plurality of micro-bond pads 116 that form inter-chip connections 160 with TSVs 118.
The programmable gate array package 400 of fig. 8C contains a programmable logic chip 200W and at least two programmable computing chips 100W, 100W'. These chips 200W, 100W and 100W' are separated and located in the same package 130. Wherein, the chip 100W' is stacked on the chip 100W, and the chip 100W is stacked on the chip 200W. Chips 200W, 100W, and 100W' are coupled to each other by TSV 118 and micro solder joint 116. It is apparent that fig. 8C has a larger storage capacity than fig. 8A. Similarly, in this embodiment, TSV 118 and micro solder joint 116 form an inter-chip connection 160.
The programmable gate array package 400 is beneficial from a manufacturing process perspective. Since the programmable computing chip 100W and the programmable logic chip 200W are different chips, the memory transistors constituting the programmable computing chip 100W and the logic transistors constituting the programmable logic chip 200W are respectively formed on different substrates (100S, 200S), and their manufacturing processes can be respectively optimized. The programmable computing chip 100W may employ any form of writable memory as a carrier of the LUT, such as SRAM, DRAM, MRAM, FRAM, OTP, NOR flash memory, NAND flash memory, etc.; the programmable logic chip 200W may contain any form of programmable logic circuit. Since the writable memory array in the programmable computing chip 100W is formed on the single crystal semiconductor substrate 100S, its speed is fast. In addition, the bandwidth between the programmable compute chip 100W and the programmable logic chip 200W is high due to the large number of micro-pads (or through-silicon vias) 160 and the short length.
The present description takes Field Programmable Gate Arrays (FPGAs) as examples. In an FPGA, the wafer will complete all the process steps (including all the programmable compute units, programmable logic units and programmable connections). In the programming field, the functions of the FPGA can be defined by setting programmable connections. The above examples of FPGAs can be easily generalized to conventional programmable gate arrays. In a conventional programmable gate array, the wafer is only semi-finished, i.e., the wafer production only completes the programmable compute units and programmable logic units, but does not complete the programmable connections. After the functionality of the chip is determined, the programmable channels 310-350 are customized by back-end processing.
It will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the invention should not be limited except as by the appended claims.
Claims (10)
1. A programmable gate array package (400), comprising:
a programmable compute chip (100W) comprising a plurality of programmable compute units (100 AA-100 AB), said programmable compute chip (100W) being formed in a compute chip substrate (100S), said compute chip substrate (100S) being a monocrystalline semiconductor substrate, each of said programmable compute units (100 AA-100 AB) comprising at least one writable memory array (110), said writable memory array (110) being formed on said compute chip substrate (100S) and being based on monocrystalline transistors and storing at least part of a look-up table (LUT) of a basis function;
a programmable logic chip (200W) comprising a plurality of programmable logic units (200 AA-200 AB), said programmable logic chip (200W) being formed in a logic chip substrate (200S), each of said programmable logic units (200 AA-200 AB) comprising at least one programmable logic unit (200), said programmable logic units (200) selectively implementing a logic operation from a logic operation library;
-a plurality of programmable connections (300) selectively coupling said programmable computing units (100 AA-100 AB) and said programmable logic units (200 AA-200 AB);
-implementing a complex function by programming said programmable computing unit (100 AA-100 AB), said programmable logic unit (200 AA-200 AB) and said programmable connection (300), said complex function being a combination of a plurality of said basis functions;
the programmable computing chip (100W) and the programmable logic chip (200W) are electrically coupled by an inter-chip connection (160).
2. The programmable gate array package (400) of claim 1, further characterized by: the writable storage array (110) is SRAM, DRAM, MRAM, FRAM, OTP, NOR flash or NAND flash.
3. The programmable gate array package (400) of claim 1, further characterized by: the programmable computing chip (100W) and the programmable logic chip (200W) are vertically stacked.
4. The programmable gate array package (400) of claim 1, further characterized in that its use comprises:
-a setup phase (610), in which setup phase (610) LUTs for a basis function are loaded into the writable storage array (110) according to user needs;
-a use phase (630), in which use phase (630) the corresponding LUT is looked up in the writable storage array (110) to obtain the value of the basis function.
5. The programmable gate array package (400) of claim 1, further characterized by: at least part of the programmable connection (300) is located in the programmable computing chip (100W) or the programmable logic chip (200W).
6. A programmable gate array package (400), comprising:
a programmable compute chip (100W) comprising a plurality of programmable compute units (100 AA-100 AB), said programmable compute chip (100W) being formed in a compute chip substrate (100S), said compute chip substrate (100S) being a single crystal semiconductor substrate, each of said programmable compute units (100 AA-100 AB) comprising at least one writable memory array (110), said writable memory array (110) being SRAM, DRAM, MRAM, FRAM, OTP, NOR flash memory or NAND flash memory and storing at least part of a look-up table (LUT) of a basis function;
a programmable logic chip (200W) comprising a plurality of programmable logic units (200 AA-200 AB), said programmable logic chip (200W) being formed in a logic chip substrate (200S), each of said programmable logic units (200 AA-200 AB) comprising at least one programmable logic unit (200), said programmable logic units (200) selectively implementing a logic operation from a logic operation library;
-a plurality of programmable connections (300) selectively coupling said programmable computing units (100 AA-100 AB) and said programmable logic units (200 AA-200 AB);
-implementing a complex function by programming said programmable computing unit (100 AA-100 AB), said programmable logic unit (200 AA-200 AB) and said programmable connection (300), said complex function being a combination of a plurality of said basis functions;
the programmable computing chip (100W) and the programmable logic chip (200W) are electrically coupled by an inter-chip connection (160).
7. The programmable gate array package (400) of claim 6, further characterized by: the SRAM, DRAM, MRAM, FRAM, OTP, NOR flash or NAND flash is formed on the compute chip substrate (100S) and is based on single crystal transistors.
8. The programmable gate array package (400) of claim 6, further characterized by: the programmable computing chip (100W) and the programmable logic chip (200W) are vertically stacked.
9. The programmable gate array package (400) of claim 6, further characterized in that its use comprises:
-a setup phase (610), in which setup phase (610) LUTs for a basis function are loaded into the writable storage array (110) according to user needs;
-a use phase (630), in which use phase (630) the corresponding LUT is looked up in the writable storage array (110) to obtain the value of the basis function.
10. The programmable gate array package (400) of claim 6, further characterized by: at least part of the programmable connection (300) is located in the programmable computing chip (100W) or the programmable logic chip (200W).
Priority Applications (7)
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| CN201710996864.7A CN109684653B (en) | 2017-10-19 | 2017-10-19 | Programmable gate array package containing programmable computing units |
| US15/793,968 US20180048317A1 (en) | 2016-03-05 | 2017-10-25 | Configurable Computing-Array Package |
| US16/059,023 US10312917B2 (en) | 2016-03-05 | 2018-08-08 | Configurable computing array for implementing complex math functions |
| US16/121,653 US10456800B2 (en) | 2016-03-05 | 2018-09-05 | Configurable computing array comprising configurable computing elements |
| US16/186,571 US10700686B2 (en) | 2016-03-05 | 2018-11-11 | Configurable computing array |
| US16/199,178 US20190115921A1 (en) | 2016-03-05 | 2018-11-24 | Configurable Computing-Array Package |
| US16/199,204 US20190115920A1 (en) | 2016-03-05 | 2018-11-25 | Configurable Computing-Array Package Implementing Complex Math Functions |
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