CN101924068A - Resistance storage and manufacturing method of integrated circuit comprising same - Google Patents
Resistance storage and manufacturing method of integrated circuit comprising same Download PDFInfo
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- CN101924068A CN101924068A CN2009100529423A CN200910052942A CN101924068A CN 101924068 A CN101924068 A CN 101924068A CN 2009100529423 A CN2009100529423 A CN 2009100529423A CN 200910052942 A CN200910052942 A CN 200910052942A CN 101924068 A CN101924068 A CN 101924068A
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- interconnection structure
- dielectric layer
- contact hole
- memister
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Abstract
The invention relates to a resistance storage and a manufacturing method of an integrated circuit comprising the same, wherein the resistance storage comprises a semiconductor substrate, a first interconnection structure, a dielectric layer, a resistance variable storage dielectric layer and an upper electrode, wherein, the first interconnection structure is arranged on the semiconductor substrate to serve as a lower electrode; the dielectric layer is arranged on the first interconnection layer and the semiconductor substrate; a first contact hole exposed out of the first interconnection structure is formed in the dielectric layer; the resistance variable storage dielectric layer is arranged in the first interconnection structure and corresponds to the position of the first contact hole; the material of the resistance variable storage dielectric layer is metal silicon oxide; and the upper electrode is arranged on the side wall of the first contact hole and the resistance variable storage dielectric layer. The dimension of the resistance storage can be regulated according to the demands, and the resistance storage can meet the demands on enhanced integrated level and has simple process.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to Memister and contain the manufacture method of the integrated circuit of Memister.
Background technology
Current, development cost is low, speed is fast, storage density is high, manufacturing is simple and be subjected to worldwide extensive concern with the compatible good novel memory technology of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) semiconductor integrated circuit technique.Memory techniques based on the resistive random access memory (RRAM) of the metal oxide with resistance switch characteristic is the emphasis that at present how tame device manufacturer is developed, because this technology can provide more high density, the more low-cost and Nonvolatile memory of low power consumption more.The memory cell of RRAM resistance value after applying pulse voltage can produce great changes, and this resistance value still can be kept down behind deenergization.In addition, RRAM has performances such as anti-irradiation, high-low temperature resistant, against violent vibration are moving, anti-electronic jamming.
Document " non-volatile resistive switching for advanced memory application " (An Chen, et, al., IEDM Technical Digest, Dec.2005, Page 746) provided a kind of Memister structure, with reference to the accompanying drawings shown in 1, have Semiconductor substrate 100, be formed with source electrode 110 in the described substrate and drain 120 and on Semiconductor substrate 100 source electrode 110 and the grid structure 130 between 120 of draining; Tungsten plug 140 and interconnection copper cash 150 are used for inter-level interconnects; The material of the bottom electrode 160 of Memister can be a tungsten, metallic copper etc., the resistance variable memory dielectric layer 170 that the described bottom electrode of oxidation forms, material such as tungsten oxide, cupric oxide for example, the top electrode 180 that forms on resistance variable memory dielectric layer 170 can be the double-decker of Ti/TiN; It is interconnected that interconnection copper cash or interconnection aluminum steel 190 are used for interlayer.
In the prior art, the area of Memister is big, the more and more higher trend of incompatibility integrated circuit integrated level; The storage medium material of resistance-variable is cupric oxide or tungsten oxide, adopts above-mentioned material can make the low-resistance value of Memister cross low and causes that device power consumption is big, electric current is big; For the integrated circuit that contains Memister, the interconnection structure of other memory carries out separately respectively in the formation technology of Memister and the integrated circuit, therefore, and complex manufacturing technology.
Summary of the invention
The problem that the present invention solves provides a kind of Memister and contains the manufacture method of the integrated circuit of Memister, the low-resistance value that prevents Memister is crossed low and is caused device power consumption big, prevent that the Memister area is excessive, integrated level is low and prevent complex manufacturing technology.
For addressing the above problem, a kind of manufacture method that contains the integrated circuit of Memister of the present invention, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure; On first interconnection structure, second interconnection structure and Semiconductor substrate, form dielectric layer; In dielectric layer, form first contact hole that exposes first interconnection structure; Along first contact hole first interconnection structure surface is handled, form the resistance variable memory dielectric layer, described resistance variable memory dielectric layer is the metallic silicon oxide; On the first contact hole sidewall and resistance variable memory dielectric layer, form top electrode, and in first contact hole filled conductive material; In dielectric layer, form second contact hole that exposes second interconnection structure; Form diffusion impervious layer at the second contact hole inwall, and the filled conductive material.
Optionally, described top electrode and diffusion impervious layer form simultaneously, while filled conductive material in first contact hole and second contact hole.
Optionally, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
Optionally, the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts.
Optionally, the technology of described formation resistance variable memory dielectric layer is that thermal oxidation method, plasma strengthen method or oxonium ion injection method.
Optionally, the material of described first interconnection structure and second interconnection structure is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
Optionally, the material of described top electrode, diffusion impervious layer is titanium, titanium nitride, tantalum or tantalum nitride.
Optionally, the thickness of described top electrode, diffusion impervious layer is 100 dusts～500 dusts.
The invention provides a kind of manufacture method that contains the integrated circuit of Memister, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure; On first interconnection structure, second interconnection structure and Semiconductor substrate, form dielectric layer; In dielectric layer, form first contact hole that exposes first interconnection structure and second contact hole that exposes second interconnection structure; Respectively first interconnection structure and the second interconnection structure surface are handled along first contact hole and second contact hole, formed the resistance variable memory dielectric layer, described resistance variable memory dielectric layer is the metallic silicon oxide; Remove the resistance variable memory dielectric layer on the second interconnection structure surface; On the first contact hole sidewall, resistance variable memory dielectric layer and the second contact hole inwall form diffusion impervious layer, the diffusion impervious layer in described first contact hole is as top electrode; Filled conductive material in first contact hole and second contact hole.
Optionally, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
Optionally, the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts.
Optionally, the technology of described formation resistance variable memory dielectric layer is that thermal oxidation method, plasma strengthen method or oxonium ion injection method.
Optionally, the material of described first interconnection structure and second interconnection structure is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
Optionally, the material of described top electrode, diffusion impervious layer is titanium, titanium nitride, tantalum or tantalum nitride.
Optionally, the thickness of described top electrode, diffusion impervious layer is 100 dusts～500 dusts.
The invention provides a kind of Memister, comprise, Semiconductor substrate; Be positioned on the Semiconductor substrate first interconnection structure as bottom electrode; Be positioned at the dielectric layer on first interconnection structure and the Semiconductor substrate, be formed with first contact hole that exposes first interconnection structure in the described dielectric layer; Be arranged in first interconnection structure resistance variable memory dielectric layer corresponding with the first contact hole position, the material of described resistance variable memory dielectric layer is the metallic silicon oxide; Be positioned at the top electrode on the first contact hole sidewall and the resistance variable memory dielectric layer.
Optionally, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
Optionally, the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts.
Optionally, the material of described first interconnection structure is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
Optionally, the material of described top electrode is titanium, titanium nitride, tantalum or tantalum nitride.
Optionally, the thickness of described top electrode is 100 dusts～500 dusts.
Compared with prior art, the present invention has the following advantages:
Directly the surface of first interconnection structure is handled and form variable storage medium layer, and in contact hole, form top electrode.Because Memister is arranged in the contact hole, size can be regulated as required, and can satisfy the needs that integrated level increases.
When forming Memister, can realize the inter-level interconnects structure of logic cells area, technology is simple.
Resistance variable memory dielectric layer material in the Memister is the metallic silicon oxide, and this kind material has very high low-resistance resistance value, reduces the program current from the low-resistance to the high resistant, thereby reduces the overall power of memory.In addition, metal silicide materials need not too big change and promptly can be used for industrial production line extensively adopting in the semiconductor industry now, and is easy to prepare.
Description of drawings
Fig. 1 is the structural representation for the prior art Memister;
Fig. 2 is the first embodiment flow chart that the present invention forms the integrated circuit that contains Memister;
Fig. 3, Fig. 4, Fig. 5 a, Fig. 5 b, Fig. 5 c are the first embodiment schematic diagrames that the present invention forms the integrated circuit that contains Memister;
Fig. 3, Fig. 4, Fig. 6 a, Fig. 6 b, Fig. 6 c are the second embodiment schematic diagrames that the present invention forms the integrated circuit that contains Memister;
Fig. 7 is the second embodiment flow chart that the present invention forms the integrated circuit that contains Memister;
Fig. 8 to Figure 12 is the 3rd embodiment schematic diagram that the present invention forms the integrated circuit that contains Memister.
Embodiment
The present invention form Memister first execution mode technological process as shown in Figure 2, execution in step S11, Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure; Execution in step S12 forms dielectric layer on first interconnection structure, second interconnection structure and Semiconductor substrate; Execution in step S13 forms first contact hole that exposes first interconnection structure in dielectric layer; Execution in step S14 handles the first interconnection structure surface along first contact hole, forms the resistance variable memory dielectric layer, and described resistance variable memory dielectric layer is the metallic silicon oxide; Execution in step S15 forms top electrode on the first contact hole sidewall and resistance variable memory dielectric layer, and in first contact hole filled conductive material; Execution in step S16 forms second contact hole that exposes second interconnection structure in dielectric layer; Execution in step S17 forms diffusion impervious layer at the second contact hole inwall, and the filled conductive material.
Below in conjunction with accompanying drawing first embodiment of the present invention is described in detail.
Embodiment 1
Fig. 3, Fig. 4, Fig. 5 a, Fig. 5 b, Fig. 5 c are the first embodiment schematic diagrames that the present invention forms Memister.
With reference to figure 3, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 comprises resistance memory cell district I and logical block district II.
Wherein, be formed with semiconductor device for example memory, transistor etc. in the Semiconductor substrate 200, can also be formed with other input or output circuit or line.
Continuation is forming the first interconnection structure 204a, forming the second interconnection structure 204b on the Semiconductor substrate 200 of logical block district II with reference to figure 3 on the Semiconductor substrate 200 of resistance memory cell district I.Concrete technology is: owing to be formed with MOS transistor on Semiconductor substrate 200, adopt chemical vapour deposition technique conductive metal deposition layer on the regions and source of MOS transistor or area of grid or other semiconductor substrate region, the material that the present embodiment conductive metal layer is selected for use is Ti, Ni or Co etc.; Then, conductive metal layer is carried out high-temperature process, form the first interconnection structure 204a and the second interconnection structure 204b, the electric conducting material of the described formation first interconnection structure 204a and the second interconnection structure 204b is the metal material that is suitable as Memister bottom electrode and integrated circuit interlayer line, and present embodiment is selected Ti for use
xSi
y, Ni
xSi
yOr Co
xSi
yDeng.
In the present embodiment, metal silicide materials need not too big change and promptly can be used for industrial production line extensively adopting in the semiconductor industry now, and is easy to prepare.
As shown in Figure 4, on the first interconnection structure 204a, the second interconnection structure 204b and Semiconductor substrate, form dielectric layer 206, in described dielectric layer 206, be formed with and run through first contact hole 207 that dielectric layer exposes the first interconnection structure 204a; First interconnection structure 204a surface in first contact hole 207 forms resistance variable memory dielectric layer 208.
Concrete processing step is as follows: adopting chemical vapour deposition technique to form thickness on the first interconnection structure 204a, the second interconnection structure 204b and Semiconductor substrate 200 is the dielectric layer 206 of 3000 dusts～10000 dusts, and the material of described dielectric layer 206 is silica, silicon oxynitride or tetraethoxysilane etc.; Then, spin coating first photoresist layer (not shown) on dielectric layer 206 through exposure imaging technology, defines and the first corresponding contact hole graph of the first interconnection structure 204a position; With first photoresist layer is mask, to exposing the first interconnection structure 204a, forms first contact hole 207 along the first contact hole graph etching dielectric layer 206.After adopting ashing method to remove first photoresist layer, oxidation processes is carried out on surface along 207 couples first interconnection structure 204a of first contact hole, forming thickness is the resistance variable memory dielectric layer 208 of 80 dusts～800 dusts, wherein the material of resistance variable memory dielectric layer 208 is the metallic silicon oxide, is specially Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
zDescribed oxidation processes can be directly thermal oxidation to be carried out on the first interconnection structure 204a surface, also can be that using plasma strengthens oxidizing process, can also carry out annealing process after oxonium ion is injected on first interconnection structure 204a surface along first contact hole 207.
In the present embodiment, resistance variable memory dielectric layer 208 material are the metallic silicon oxide, and this kind material has very high low-resistance resistance value, reduce the program current from the low-resistance to the high resistant, thereby reduce the overall power of memory.
Shown in Fig. 5 a, with chemical vapour deposition technique on the dielectric layer 206, to form thickness on first contact hole, 207 sidewalls and the resistance variable memory dielectric layer 208 be first diffusion impervious layer 210 of 100 dusts～500 dusts, the material of described first diffusion impervious layer 210 can be titanium, tantalum, tantalum nitride or titanium nitride etc.Then, adopt chemical vapour deposition technique on first diffusion impervious layer 210, to form first conductive layer 212 again, and full first contact hole 207 of first conductive layer, 212 fillings, the material of described first conductive layer 212 is a tungsten etc.
With reference to figure 5b, adopt chemical mechanical polishing method that first conductive layer 212, first diffusion impervious layer 210 are planarized to and expose dielectric layer 206, form the first conductive plunger 212a, the first diffusion impervious layer 210a after wherein smooth is as the top electrode of resistance variable memory.Then, on dielectric layer 206, the first diffusion impervious layer 210a after smooth and the first conductive plunger 212a, form second photoresist layer 214, after exposure imaging technology, define position second contact hole graph corresponding with the second interconnection structure 204b at logical block district II; With second photoresist layer 214 is mask, to exposing the second interconnection structure 204b, forms second contact hole 215 along the second contact hole graph etching dielectric layer 206.
Shown in Fig. 5 c, after the employing ashing method is removed second photoresist layer, form second diffusion impervious layer 216 at second contact hole, 215 inwalls; Then, in second contact hole 215, fill full conductive materials, form second conductive plunger 218.Concrete processing step is as follows: reaching second contact hole, 215 inwalls formation thickness with chemical vapour deposition technique on dielectric layer 206 is second diffusion impervious layer 216 of 100 dusts～500 dusts.Then, adopt chemical vapour deposition technique to form second conductive layer again on second diffusion impervious layer 216, the material of described second conductive layer is a tungsten etc.; Adopt chemical mechanical polishing method that second conductive layer, second diffusion impervious layer 216 are planarized to and expose dielectric layer 206, form second conductive plunger 218.
Present embodiment is directly handled the surface of the first interconnection structure 204a and is formed variable storage medium layer 208, and forms top electrode in first contact hole 207.Because the top electrode of Memister is arranged in first contact hole 207, size can be regulated as required, and can satisfy the needs that integrated level increases.
Comprise based on the Memister structure in the integrated circuit that contains Memister of the foregoing description formation: Semiconductor substrate 200; The first interconnection structure 204a is positioned on the Semiconductor substrate 200 of the source electrode of MOS transistor or drain region, as the bottom electrode of Memister; Dielectric layer 206 is positioned on the first interconnection structure 204a and the Semiconductor substrate 200; First contact hole 207 runs through dielectric layer 206 to exposing the first interconnection structure 204a; Resistance variable memory dielectric layer 208 is positioned at the first interconnection structure 204a surface of first contact hole 207, and the material of described resistance variable memory dielectric layer 208 is the metallic silicon oxide; Top electrode is positioned on first contact hole, 207 sidewalls and the resistance variable memory dielectric layer 208.
In the present embodiment, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
In the present embodiment, the thickness of described resistance variable memory dielectric layer 208 is 80 dusts～800 dusts.
In the present embodiment, the material of the described first interconnection structure 204a is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
In the present embodiment, the material of described top electrode is titanium, titanium nitride, tantalum or tantalum nitride, and thickness is 100 dusts～500 dusts.
Embodiment 2
Fig. 3, Fig. 4, Fig. 6 a, Fig. 6 b, Fig. 6 c are the second embodiment schematic diagrames that the present invention forms the integrated circuit that contains Memister.
Continuation provides Semiconductor substrate 200 with reference to figure 3, and described Semiconductor substrate 200 comprises resistance memory cell district I and logical block district II.
Wherein, be formed with semiconductor device for example memory, transistor etc. in the Semiconductor substrate 200, can also be formed with other input or output circuit or line.
With reference to figure 3, forming the first interconnection structure 204a on the Semiconductor substrate 200 of resistance memory cell district I, on the Semiconductor substrate 200 of logical block district II, forming the second interconnection structure 204b again.The concrete technology that forms does not repeat them here for to have described in detail in embodiment 1, and the material of the present embodiment first interconnection structure 204a and the second interconnection structure 204b is Ti
xSi
y, Ni
xSi
yOr Co
xSi
yDeng.
As shown in Figure 4, on the first interconnection structure 204a, the second interconnection structure 204b and Semiconductor substrate 200, form dielectric layer 206, in the described dielectric layer 206 of resistance memory cell district I, be formed with and run through first contact hole 207 that dielectric layer exposes the first interconnection structure 204a; The first interconnection structure 204a surface in first contact hole 207 is carried out oxidation processes and is formed resistance variable memory dielectric layer 208, and wherein the material of resistance variable memory dielectric layer 208 is the metallic silicon oxide, is specially Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
zConcrete resistance variable memory dielectric layer 208 oxidation processing technique that form do not repeat them here for to have described in detail in embodiment 1.
Shown in Fig. 6 a, on dielectric layer 206, form photoresist layer 300 with spin-coating method, after exposure imaging technology, define position second contact hole graph corresponding with the second interconnection structure 204b at logical block district II; With second photoresist layer 214 is mask, to exposing the second interconnection structure 204b, forms second contact hole 301 along the second contact hole graph etching dielectric layer 206.
With reference to figure 6b, after ashing method is removed photoresist layer 300, on first contact hole, 207 sidewalls, resistance variable memory dielectric layer 208 and second contact hole, 301 inwalls to form thickness be the diffusion impervious layer 302 of 100 dusts～500 dusts, the material of described diffusion impervious layer 302 can be titanium, tantalum, tantalum nitride or titanium nitride etc.Then, adopt chemical vapour deposition technique on diffusion impervious layer 302, to form conductive layer 304 again, and full first contact hole 207 of conductive layer 304 fillings and second contact hole 301, in the present embodiment, the material that described conductive layer 212 adopts is a tungsten etc.
With reference to figure 6c, adopt chemical mechanical polishing method that conductive layer 304, diffusion impervious layer 302 are planarized to and expose dielectric layer 206, form the first conductive plunger 304a and the second conductive plunger 304b.Wherein at resistance memory cell district I, the diffusion impervious layer 302 after smooth is as the top electrode of resistance variable memory.
Comprise based on the Memister structure in the integrated circuit that contains Memister of the foregoing description formation: Semiconductor substrate 200; The first interconnection structure 204a is positioned on the Semiconductor substrate 200 of the source electrode of MOS transistor or drain region, as the bottom electrode of Memister; Dielectric layer 206 is positioned on the first interconnection structure 204a and the Semiconductor substrate 200; First contact hole 207 runs through dielectric layer 206 to exposing the first interconnection structure 204a's; Resistance variable memory dielectric layer 208 is positioned at the first interconnection structure 204a surface of first contact hole 207, and the material of described resistance variable memory dielectric layer 208 is the metallic silicon oxide; Top electrode is positioned on first contact hole, 207 sidewalls and the resistance variable memory dielectric layer 208.
In the present embodiment, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
In the present embodiment, the thickness of described resistance variable memory dielectric layer 208 is 80 dusts～800 dusts.
In the present embodiment, the material of the described first interconnection structure 204a is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
In the present embodiment, the material of described top electrode is titanium, titanium nitride, tantalum or tantalum nitride, and thickness is 100 dusts～500 dusts.
Fig. 7 is the second embodiment flow chart that the present invention forms the integrated circuit that contains Memister.As shown in Figure 7, execution in step S21, Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure; Execution in step S22 forms dielectric layer on first interconnection structure, second interconnection structure and Semiconductor substrate; Execution in step S23 forms first contact hole that exposes first interconnection structure and second contact hole that exposes second interconnection structure in dielectric layer; Execution in step S24 handles first interconnection structure and the second interconnection structure surface respectively along first contact hole and second contact hole, forms the resistance variable memory dielectric layer, and described resistance variable memory dielectric layer is the metallic silicon oxide; Execution in step S25 removes the resistance variable memory dielectric layer on the second interconnection structure surface; Execution in step S26, on the first contact hole sidewall, resistance variable memory dielectric layer and the second contact hole inwall form diffusion impervious layer, the diffusion impervious layer in described first contact hole is as top electrode; Execution in step S27, filled conductive material in first contact hole and second contact hole.
Below in conjunction with accompanying drawing second embodiment of the present invention is described in detail.
Embodiment 3
Fig. 8 to Figure 12 is the 3rd embodiment schematic diagram that the present invention forms the integrated circuit that contains Memister.
With reference to figure 8, Semiconductor substrate 400 is provided, described Semiconductor substrate 400 comprises resistance memory cell district I and logical block district II.
Wherein, be formed with semiconductor device for example memory, transistor etc. in the Semiconductor substrate 400, can also be formed with other input or output circuit or line.
Continuation is forming the first interconnection structure 404a, forming the second interconnection structure 404b on the Semiconductor substrate 400 of logical block district II with reference to figure 8 on the Semiconductor substrate 400 of resistance memory cell district I.Concrete technology is: be formed with MOS transistor respectively on the Semiconductor substrate 400 of resistance memory cell district I and logical block district II; Then, adopt chemical vapour deposition technique conductive metal deposition layer on the regions and source of MOS transistor or area of grid or other semiconductor substrate region, the material that the present embodiment conductive metal layer is selected for use is Ti, Ni or Co etc.; Then, conductive metal layer is carried out high-temperature process, form the first interconnection structure 404a and the second interconnection structure 404b, the electric conducting material of the described formation first interconnection structure 404a and the second interconnection structure 404b is the metal material that is suitable as Memister bottom electrode and integrated circuit interlayer line, and present embodiment is selected Ti for use
xSi
y, Ni
xSi
yOr Co
xSi
yDeng.
In the present embodiment, metal silicide materials need not too big change and promptly can be used for industrial production line extensively adopting in the semiconductor industry now, and is easy to prepare.
As shown in Figure 9, on the first interconnection structure 404a, the second interconnection structure 404b and interlayer dielectric layer 402, form dielectric layer 406, in described dielectric layer 406, be formed with and run through dielectric layer 406 and expose the first contact hole 407a of the first interconnection structure 404a and run through the second contact hole 407b that dielectric layer 406 exposes the second interconnection structure 404b; First interconnection structure 404a surface in the first contact hole 407a and the second interconnection structure 404b surface in the second contact hole 407b form resistance variable memory dielectric layer 408.
Concrete processing step is as follows: adopting chemical vapour deposition technique to form thickness on the first interconnection structure 404a, the second interconnection structure 404b and interlayer dielectric layer 402 is the dielectric layer 406 of 3000 dusts～10000 dusts, and the material of described dielectric layer 406 is silica, silicon oxynitride or tetraethoxysilane etc.; Then, spin coating photoresist layer (not shown) on dielectric layer 406 through exposure imaging technology, defines and the first corresponding contact hole graph of the first interconnection structure 404a position, and with the second corresponding contact hole graph of the second interconnection structure 404b position; With first photoresist layer is mask, to exposing the first interconnection structure 404a and the second interconnection structure 404b respectively, forms the first contact hole 407a and the second contact hole 407b along first contact hole graph and the second contact hole graph etching dielectric layer 406.After adopting ashing method to remove first photoresist layer, respectively oxidation processes is carried out on the surface of the first interconnection structure 404a and the second interconnection structure 404b along the first contact hole 407a and the second contact hole 407b, forming thickness is resistance variable memory dielectric layer 408a, the 408b of 80 dusts～800 dusts, wherein the material of resistance variable memory dielectric layer 408a, 408b is the metallic silicon oxide, is specially Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
zDescribed oxidation processes can be directly the first interconnection structure 404a and the second interconnection structure 404b surface to be carried out thermal oxidation, also can be that using plasma strengthens oxidizing process, can also behind first interconnection structure 404a surface and second interconnection structure 404b surface injection oxonium ion, carry out annealing process along the first contact hole 407a and the second contact hole 407b.
In the present embodiment, resistance variable memory dielectric layer 408a, 408b material are the metallic silicon oxide, and this kind material has very high low-resistance resistance value, reduce the program current from the low-resistance to the high resistant, thereby reduce the overall power of memory.
With reference to Figure 10, in the dielectric layer 406 of resistance memory cell district I and the first contact hole 407a, form photoresist layer 410 with spin-coating method; With photoresist layer 410 is mask, removes the resistance variable memory dielectric floor 408b of logical block district II with dry etching method or wet etching method.
As shown in figure 11, ashing method is removed photoresist layer; On the first contact hole 407a sidewall, resistance variable memory dielectric layer 408a and the second contact hole 407b inwall to form thickness be the diffusion impervious layer 412 of 100 dusts～500 dusts, the material of described diffusion impervious layer 412 can be tantalum, tantalum nitride or titanium nitride etc.Then, adopt chemical vapour deposition technique on diffusion impervious layer 412, to form conductive layer 414 again, and the full first contact hole 407a of conductive layer 414 fillings and the second contact hole 407b, in the present embodiment, the material that described conductive layer 414 adopts is a tungsten etc.
With reference to Figure 12, adopt chemical mechanical polishing method that conductive layer 414, diffusion impervious layer 412 are planarized to and expose dielectric layer 406, form the first conductive plunger 414a and the second conductive plunger 414b.Wherein at resistance memory cell district I, the diffusion impervious layer 412 after smooth is as the top electrode of resistance variable memory.
Present embodiment is directly handled the surface of the first interconnection structure 404a and is formed variable storage medium layer 408a, and forms top electrode in the first contact hole 407a.Because Memister is arranged in the first contact hole 407a, size can be regulated as required, and can satisfy the needs that integrated level increases.
In addition, present embodiment can be realized the inter-level interconnects structure of logical block district II when forming Memister, and technology is simple.
Comprise based on the Memister structure in the integrated circuit that contains Memister of the foregoing description formation: Semiconductor substrate 400; The first interconnection structure 404a is positioned on the Semiconductor substrate 400 of the source electrode of MOS transistor or drain region, as the bottom electrode of Memister; Dielectric layer 406 is positioned on the first interconnection structure 404a and the Semiconductor substrate 400, is formed with the first contact hole 407a that exposes the first interconnection structure 404a in the described dielectric layer 406; Resistance variable memory dielectric layer 408a is positioned at the first interconnection structure 404a surface of the first contact hole 407a, and the material of described resistance variable memory dielectric layer 408a is the metallic silicon oxide; Top electrode is positioned on the first contact hole 407a sidewall and the resistance variable memory dielectric layer 408a.
In the present embodiment, described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
In the present embodiment, the thickness of described resistance variable memory dielectric layer 408 is 80 dusts～800 dusts.
In the present embodiment, the material of the described first interconnection structure 404a is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
In the present embodiment, the material of described top electrode is titanium, titanium nitride, tantalum or tantalum nitride, and thickness is 100 dusts～500 dusts.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (21)
1. a manufacture method that contains the integrated circuit of Memister is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure;
On first interconnection structure, second interconnection structure and Semiconductor substrate, form dielectric layer;
In dielectric layer, form first contact hole that exposes first interconnection structure;
Along first contact hole first interconnection structure surface is handled, form the resistance variable memory dielectric layer, described resistance variable memory dielectric layer is the metallic silicon oxide;
On the first contact hole sidewall and resistance variable memory dielectric layer, form top electrode, and in first contact hole filled conductive material;
In dielectric layer, form second contact hole that exposes second interconnection structure;
Form diffusion impervious layer at the second contact hole inwall, and the filled conductive material.
2. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that described top electrode and diffusion impervious layer form simultaneously, while filled conductive material in first contact hole and second contact hole.
3. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
4. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts.
5. according to claim 1 or the 4 described manufacture methods that contain the integrated circuit of Memister, it is characterized in that the technology of described formation resistance variable memory dielectric layer is that thermal oxidation method, plasma strengthen method or oxonium ion injection method.
6. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that the material of described first interconnection structure and second interconnection structure is Ti
xSi
y, Ni
xSi
yOr Co
xSi
y
7. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that the material of described top electrode, diffusion impervious layer is titanium, titanium nitride, tantalum or tantalum nitride.
8. according to the described manufacture method that contains the integrated circuit of Memister of claim 7, it is characterized in that the thickness of described top electrode, diffusion impervious layer is 100 dusts～500 dusts.
9. a manufacture method that contains the integrated circuit of Memister is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises resistive memory cell district and logical block district, wherein be formed with first interconnection structure on the Semiconductor substrate in resistive memory cell district as bottom electrode, on the Semiconductor substrate in logical block district, be formed with second interconnection structure;
On first interconnection structure, second interconnection structure and Semiconductor substrate, form dielectric layer;
In dielectric layer, form first contact hole that exposes first interconnection structure and second contact hole that exposes second interconnection structure;
Respectively first interconnection structure and the second interconnection structure surface are handled along first contact hole and second contact hole, formed the resistance variable memory dielectric layer, described resistance variable memory dielectric layer is the metallic silicon oxide;
Remove the resistance variable memory dielectric layer on the second interconnection structure surface;
On the first contact hole sidewall, resistance variable memory dielectric layer and the second contact hole inwall form diffusion impervious layer, the diffusion impervious layer in described first contact hole is as top electrode;
Filled conductive material in first contact hole and second contact hole.
10. according to the described manufacture method that contains the integrated circuit of Memister of claim 9, it is characterized in that described metallic silicon oxide is Ti
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
11., it is characterized in that the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts according to the described manufacture method that contains the integrated circuit of Memister of claim 9.
12., it is characterized in that the technology of described formation resistance variable memory dielectric layer is that thermal oxidation method, plasma strengthen method or oxonium ion injection method according to claim 9 or the 11 described manufacture methods that contain the integrated circuit of Memister.
13., it is characterized in that the material of described first interconnection structure and second interconnection structure is Ti according to the described manufacture method that contains the integrated circuit of Memister of claim 9
xSi
y, Ni
xSi
yOr Co
xSi
y
14., it is characterized in that the material of described top electrode, diffusion impervious layer is titanium, titanium nitride, tantalum or tantalum nitride according to the described manufacture method that contains the integrated circuit of Memister of claim 9.
15., it is characterized in that the thickness of described diffusion impervious layer is 100 dusts～500 dusts according to the described manufacture method that contains the integrated circuit of Memister of claim 14.
16. a Memister comprises Semiconductor substrate; Be positioned on the Semiconductor substrate first interconnection structure as bottom electrode; Be positioned at the dielectric layer on first interconnection structure and the Semiconductor substrate, be formed with first contact hole that exposes first interconnection structure in the described dielectric layer; Be arranged in first interconnection structure resistance variable memory dielectric layer corresponding with the first contact hole position, the material of described resistance variable memory dielectric layer is the metallic silicon oxide; Be positioned at the top electrode on the first contact hole sidewall and the resistance variable memory dielectric layer.
17., it is characterized in that described metallic silicon oxide is Ti according to the described Memister of claim 16
xSi
yO
z, Ni
xSi
yO
zOr Co
xSi
yO
z
18., it is characterized in that the thickness of described resistance variable memory dielectric layer is 80 dusts～800 dusts according to the described Memister of claim 16.
19., it is characterized in that the material of described first interconnection structure is Ti according to the described Memister of claim 16
xSi
y, Ni
xSi
yOr Co
xSi
y
20., it is characterized in that the material of described top electrode is titanium, titanium nitride, tantalum or tantalum nitride according to the described Memister of claim 16.
21., it is characterized in that the thickness of described top electrode is 100 dusts～500 dusts according to the described Memister of claim 20.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100529423A CN101924068B (en) | 2009-06-11 | 2009-06-11 | Resistance storage and manufacturing method of integrated circuit comprising same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100529423A CN101924068B (en) | 2009-06-11 | 2009-06-11 | Resistance storage and manufacturing method of integrated circuit comprising same |
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| Publication Number | Publication Date |
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| CN101924068A true CN101924068A (en) | 2010-12-22 |
| CN101924068B CN101924068B (en) | 2012-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009100529423A Expired - Fee Related CN101924068B (en) | 2009-06-11 | 2009-06-11 | Resistance storage and manufacturing method of integrated circuit comprising same |
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| CN (1) | CN101924068B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094301A (en) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | Metal oxide resistive random access memory (RRAM) and manufacturing method thereof |
| CN103904020A (en) * | 2012-12-24 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Method for optimizing morphology of metal silicide at the bottom of self-aligned contact hole |
| CN104752606A (en) * | 2013-12-26 | 2015-07-01 | 华邦电子股份有限公司 | Method for forming resistive memory |
| CN107732011A (en) * | 2017-09-29 | 2018-02-23 | 浙江师范大学 | A kind of new resistance-variable storing device and its manufacture method |
| CN109687864A (en) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | Programmable gate array containing programmable computing unit |
Family Cites Families (2)
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| CN1404118A (en) * | 2001-09-06 | 2003-03-19 | 旺宏电子股份有限公司 | Local forming process of metal silicide layer |
| KR100760926B1 (en) * | 2006-10-11 | 2007-09-21 | 동부일렉트로닉스 주식회사 | Nonvolatile semiconductor device to preparing multi bit cell and fabricating method thereof |
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2009
- 2009-06-11 CN CN2009100529423A patent/CN101924068B/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094301A (en) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | Metal oxide resistive random access memory (RRAM) and manufacturing method thereof |
| CN103094301B (en) * | 2011-11-04 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Metal oxide resistance-variable storing device and manufacture method |
| CN103904020A (en) * | 2012-12-24 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Method for optimizing morphology of metal silicide at the bottom of self-aligned contact hole |
| CN103904020B (en) * | 2012-12-24 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The method optimizing self-aligned contact hole bottom metal silicide pattern |
| CN104752606A (en) * | 2013-12-26 | 2015-07-01 | 华邦电子股份有限公司 | Method for forming resistive memory |
| CN104752606B (en) * | 2013-12-26 | 2018-06-22 | 华邦电子股份有限公司 | The forming method of resistance-type memory |
| CN107732011A (en) * | 2017-09-29 | 2018-02-23 | 浙江师范大学 | A kind of new resistance-variable storing device and its manufacture method |
| CN107732011B (en) * | 2017-09-29 | 2020-04-17 | 浙江师范大学 | Novel resistive random access memory and manufacturing method thereof |
| CN109687864A (en) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | Programmable gate array containing programmable computing unit |
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|---|---|
| CN101924068B (en) | 2012-08-22 |
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