CN109686673A - 一种大尺寸sop封装元器件耐振动点胶加固方法 - Google Patents

一种大尺寸sop封装元器件耐振动点胶加固方法 Download PDF

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CN109686673A
CN109686673A CN201811540570.4A CN201811540570A CN109686673A CN 109686673 A CN109686673 A CN 109686673A CN 201811540570 A CN201811540570 A CN 201811540570A CN 109686673 A CN109686673 A CN 109686673A
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colloid
large scale
sop
vibration resistance
reinforcement means
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醋强一
何燕春
姜红明
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Xian Aeronautics Computing Technique Research Institute of AVIC
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83024—Applying flux to the bonding area

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明属于电子设备机械结构技术领域，涉及一种大尺寸SOP封装元器件耐振动点胶加固方法，选用弹性模量大于2GPa的胶粘剂，在元器件两侧非引线边用胶粘剂将器件本体与印制板粘接，要求胶体高度需大于器件高度的80％，胶体斜面坡度范围在30°～60°之间，胶体长度必须超出器件引线长度，禁止胶体与器件引线粘连。此方法能够在不改变模块结构形式的条件下，有效降低大尺寸SOP封装元器件引线振动应力20％以上。

Description

一种大尺寸SOP封装元器件耐振动点胶加固方法
技术领域
本发明属于电子设备机械结构技术领域，涉及一种大尺寸SOP封装元器件耐振动点胶加固方法。
背景技术
目前存在一类大尺寸SOP陶瓷封装器件，外形尺寸大于15mm(长)x10mm(宽)。此类器件通过短边两侧飞翼引线与印制板跨接焊接，由于器件长边悬空，跨度大，陶瓷封装密度和刚性较大，并且引线细小，导致其振动受力脆弱，焊接后容易发生引线振动断裂。用胶粘剂将元器件与印制板粘接是一种通用的器件加固处理方式，但没有具体的操作标准规范。并且从实际使用过程中发现有的胶粘方式反倒起到负作用，使元器件更加不耐受振动，有的胶粘方式会导致后期维护困难等各种问题。
发明内容
本发明的目的：解决一种大尺寸SOP封装元器件耐振动的问题。
本发明的技术方案：一种大尺寸SOP封装元器件耐振动点胶加固方法，在元器件两侧非引线边用胶粘剂将器件本体与印制板粘接，胶粘剂固化后的胶体长度必须超出器件引线长度，所述胶粘剂弹性模量大于2GPa。
所述胶体与器件引线不粘连。
所述胶体高度需大于器件高度的80％。
所述胶体斜面坡度范围在30°～60°之间。
本发明具有的优点效果：本发明能够在不改变模块结构形式的条件下，有效降低大尺寸SOP封装元器件引线振动应力20％以上。并且本发明发现当胶体长度小于器件边长时，会对器件振动加固产生负作用，应禁止此种加固方式。
附图说明
图1：SOP封装器件的结构示意图，
图2：SOP封装器件的侧视图
图3：本发明实施效果俯视图，
图4：本发明实施效果胶体细节图。
具体实施方式
下面结合附图对本发明进一步说明：
如图1、图2所示，一种大尺寸SOP封装元器件的结构形式可看出，其长边悬空，跨度大，引线细小，器件振动受力脆弱。
如图2所示，在元器件两侧非引线边用胶粘剂将器件本体与印制板粘接，胶体长度必须超出器件引线长度，禁止胶体与器件引线粘连。
如图3所示，要求胶体高度需大于器件高度的80％，胶体斜面坡度范围在30°～60°之间。

Claims (4)

1.一种大尺寸SOP封装元器件耐振动点胶加固方法，其特征在于：在元器件两侧非引线边用胶粘剂将器件本体与印制板粘接，胶粘剂固化的胶体长度必须超出器件引线长度，所述胶粘剂弹性模量大于2GPa。
2.根据权利要求1所述的大尺寸SOP封装元器件耐振动点胶加固方法，其特征在于：所述胶体与器件引线不粘连。
3.根据权利要求1所述的大尺寸SOP封装元器件耐振动点胶加固方法，其特征在于：所述胶体高度需大于器件高度的80％。
4.根据权利要求1所述的大尺寸SOP封装元器件耐振动点胶加固方法，其特征在于：所述胶体斜面坡度范围在30°～60°之间。
CN201811540570.4A 2018-12-14 2018-12-14 一种大尺寸sop封装元器件耐振动点胶加固方法 Pending CN109686673A (zh)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN113873780A (zh) * 2021-10-19 2021-12-31 西安微电子技术研究所 一种径向片式电容的粘固方法
CN116113173A (zh) * 2022-10-26 2023-05-12 中国航空工业集团公司西安航空计算技术研究所 一种塑封叠层多晶硅结构器件的加固方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113873780A (zh) * 2021-10-19 2021-12-31 西安微电子技术研究所 一种径向片式电容的粘固方法
CN113873780B (zh) * 2021-10-19 2024-01-26 西安微电子技术研究所 一种径向片式电容的粘固方法
CN116113173A (zh) * 2022-10-26 2023-05-12 中国航空工业集团公司西安航空计算技术研究所 一种塑封叠层多晶硅结构器件的加固方法

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Application publication date: 20190426