CN109669073B - Self-adaptation soil conductivity check out test set - Google Patents

Self-adaptation soil conductivity check out test set Download PDF

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CN109669073B
CN109669073B CN201811518467.XA CN201811518467A CN109669073B CN 109669073 B CN109669073 B CN 109669073B CN 201811518467 A CN201811518467 A CN 201811518467A CN 109669073 B CN109669073 B CN 109669073B
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pin
capacitor
resistor
grounded
operational amplifier
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CN109669073A (en
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傅迎春
朱文越
张琳
张琪
黎玉晴
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

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Abstract

The invention discloses self-adaptive soil conductivity detection equipment. One side of hand push frame inlays and is equipped with the detector, the base member passes through the vice installation of sliding and detects ship base member both sides, the one end of spring is fixed on detecting the ship, the other end of spring is fixed on the hand push frame, the linear module of X-Y is fixed respectively in the both sides that detect the ship base member, two probes all link to each other with the detector, two probes pass through probe self-adaptation push down the device and install on the Y rail, the interior bottom surface of detecting the ship base member is passed through the laminating of probe self-adaptation push down the device to the lower bottom surface of two probes, detect the outer bottom surface and the soil contact of ship base member, two probes slide for two X rails with the Y rail jointly, two probes. One side of the detection ship base body is provided with a spiral wheel, the rotating direction of the spiral wheel is consistent with the back-and-forth moving direction of the hand-push frame, and the spiral wheel is connected to a driving motor through a belt wheel mechanism. The invention can adapt to different working conditions, and is convenient and fast to detect; the instrument has high sensitivity, stability and reliability.

Description

Self-adaptation soil conductivity check out test set
Technical Field
The invention belongs to the field of agricultural soil detection, and relates to self-adaptive soil conductivity detection equipment.
Background
With the development of science and technology, agricultural science is continuously advanced, in order to know the condition of farmland soil in advance and facilitate the adjustment of cultivated land planting varieties, various indexes of the soil need to be detected, water-soluble salt in the soil is an important index of the soil and an important factor for judging whether salt ions in the soil limit the growth of crops, and the dynamic measurement of the salt content in the soil can be realized by measuring the conductivity in the soil. Some existing instruments can realize non-contact measurement of soil conductivity. The instrument is generally pulled and pushed manually or pulled by a cultivator and the like, and has the following problems: firstly, the instrument is easily disturbed by uneven factors of the soil in the process of manual push-pull or traction of a cultivator, and then the detection result is influenced. And secondly, no mechanical structure which is suitable for manual push-pull and can be dragged by a cultivator exists at present. And the detection is inconvenient in different working conditions. And thirdly, the sensor is generally fixed in the detection ship, and the position cannot be timely adjusted according to actual conditions. Fourthly, the detection sensitivity is low, the detection efficiency is low, and the depth of the detected soil is small. Fifthly, the secondary development of the user is difficult, the excitation power of the instrument is insufficient, and the anti-interference performance is poor.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides the self-adaptive soil conductivity detection equipment for detecting various indexes of soil, and overcomes the defect that a soil detection instrument is easily interfered by uneven factors of the soil in the process of manual pushing and pulling or traction of a cultivator, so that the detection result is influenced and the adaptability of different working conditions is improved.
The technical scheme of the invention is as follows:
the invention comprises a hand-push frame, a spiral wheel, a detection boat and a detector, wherein the detector is embedded in one side of the hand-push frame, the detection boat and the spiral wheel are both arranged in the hand-push frame, and the bottom of the hand-push frame is provided with a roller for moving back and forth; the detection ship comprises a detection ship base body, two probes, a probe self-adaptive pressing device, an x-y linear module and a spring, wherein an installation through groove is formed in the middle of a hand-push frame, two sides of the detection ship base body are installed in the installation through groove of the hand-push frame in a sliding mode through a guide rail slider pair which is vertically arranged, one end of the spring is fixed to the lower bottom surface of a side flange of the detection ship base body, and the other end of the spring is fixed to the hand-push frame, so that the detection ship can do up-and-down floating motion on the hand-push frame along the.
An X-Y linear module is arranged in the detection ship base body and comprises an X rail and a Y rail which are perpendicular to each other, the two parallel X rails are connected through the Y rail to form an I-shaped X-Y linear module, and the two parallel X rails are respectively fixed on two sides of the detection ship base body.
The double probes are sequentially arranged on the Y rail through respective probe self-adaptive pressing devices, the lower bottom surfaces of the double probes are attached to the inner bottom surface of the detection ship base body through the probe self-adaptive pressing devices, the outer bottom surface of the detection ship base body 10 is in contact with soil, the double probes and the Y rail move together along the two X rails to serve as the X direction of the movement of the double probes, the double probes slide along the Y rail to serve as the Y direction of the movement of the double probes, and the double probes are connected with the detector.
The front portion of hand push frame is opened there is the rectangle to lead to the groove, install the helical wheel in the groove, the both ends of helical wheel place main shaft articulate in the both sides of hand push frame, the main shaft of helical wheel is on a parallel with the Y rail and arranges, the helical wheel is equipped with continuous distribution's spiral tooth along self main shaft, the both ends of helical wheel main shaft all are connected to driving motor through band pulley mechanism, driving motor installs in hand push frame rear portion, the equal coaxial coupling in both ends of driving motor output shaft has the motor band pulley, the motor band pulley at both ends corresponds the band pulley at both ends through hold-in range and helical wheel respectively and constitutes band.
Preferably, the front end of the hand pushing frame in the advancing direction is provided with a lifting lug for manual pushing and pulling or mechanical hooking.
Preferably, a device protective cover is arranged above the hand-push frame, and a belt wheel protective cover is sleeved outside the belt wheel mechanism.
Preferably, the hand push frame is made of an aluminum profile.
The detector comprises a CPU core circuit, a preceding stage processing circuit, a power amplification circuit, a receiving amplification circuit, a detection circuit, an alarm and level conversion circuit, a voltage reduction circuit and a power supply circuit, wherein the preceding stage processing circuit and the alarm and level conversion circuit are connected to the CPU core circuit, the preceding stage processing circuit inputs signals into the power amplification circuit, the power amplification circuit sends the signals to the receiving amplification circuit through an external exciting coil, the receiving amplification circuit receives the signals of the power amplification circuit through a receiving coil, the receiving amplification circuit inputs the signals to the detection circuit, and an input power PIN supplies power to each circuit through the voltage reduction circuit and the power supply circuit.
The CPU core circuit comprises a singlechip U1, an NRST pin and a VREF + pin of the singlechip U1 are respectively connected with a 3.3V power supply through a resistor R2 and a resistor R3, an OSC _ IN pin, an OSC _ OUT pin and an NRST pin of the singlechip U1 are respectively grounded through a capacitor C1, a capacitor C2 and a capacitor C3, a resistor R1 and a crystal oscillator X1 are connected between the capacitor C1 and the capacitor C2 IN parallel, the VREF + pin of the singlechip U1 is connected with one end of a voltage stabilizing diode D1, one end of the voltage stabilizing diode D1 is also connected with the 3.3V power supply through the resistor R3, the other end of the voltage stabilizing diode D1 is grounded, and a BOOT0 pin of the singlechip U1 is grounded through a resistor R4;
the pre-stage processing circuit comprises an operational amplifier U2 and an operational amplifier U3, an IN + pin of the operational amplifier U2 and an IN + pin of the operational amplifier U3 are respectively connected to a PA4 pin and a PA5 pin of the singlechip U1, the IN-pin of the operational amplifier U2 is grounded through a resistor R6, and the IN-pin of the operational amplifier U2 is respectively connected to an OUT pin of the operational amplifier U2 through a capacitor C4 and a resistor R5; an IN-pin of the operational amplifier U3 is grounded through a resistor R7, an IN-pin of the operational amplifier U3 is connected to an OUT-pin of the operational amplifier U3 through a capacitor C5 and a resistor R8 respectively, the OUT-pin of the operational amplifier U2 is connected to one end of a resistor R9, the OUT-pin of the operational amplifier U3 is connected to one end of the resistor R10, and a potentiometer R11 and a capacitor C6 are connected between the other ends of the resistor R9 and the resistor R10 IN parallel;
the power amplification circuit comprises a power amplification chip U4, an INPR pin of the power amplification chip U4 is connected to the other end of a resistor R9 through a blocking capacitor C7, an INNR pin of the power amplification chip U4 is connected to the other end of a resistor R10 through a blocking capacitor C8, a PLIMIT pin and a GVDD pin of the power amplification chip U4 are connected and grounded through a capacitor C9, a GVDD pin and a GND pin of the power amplification chip U4 are connected to a GAIN/SLV pin of the power amplification chip U4 through a resistor R12 and a resistor R13 respectively, a MUTE pin of the power amplification chip U4 is grounded through a resistor R14, a BSNR pin of the power amplification chip U4 is connected to one end of an inductor L1 through a capacitor C11, an OUTNR pin of the power amplification chip U4 is connected to one end of the inductor L1, the other end of the inductor L1 is externally connected with an; the BSPR pin of the power amplifier chip U4 is connected to one end of an inductor L2 through a capacitor C10, the OUTPR pin is connected to one end of an inductor L2, the other end of the inductor L2 is externally connected with an exciting coil through a 2 interface of a wiring terminal TX, and the other end of the inductor L2 is grounded through a capacitor C12;
the receiving amplifying circuit comprises an instrumentation amplifier U5, an operational amplifier U6, an operational amplifier U7 and an operational amplifier U8, wherein a V + pin of the instrumentation amplifier U5, a VS + pin of the operational amplifier U6, a VS + pin of the operational amplifier U7 and a VS + pin of the operational amplifier U8 are connected with a power supply AVCC; two RG pins of an instrument amplifier U5 are connected through a resistor R18, a ref pin of the instrument amplifier U5 is grounded, a resistor R17 and a capacitor C14 are connected IN parallel between an IN pin and an IN + pin of the instrument amplifier U5, the IN pin is connected with a receiving coil through an interface 1 of a wiring terminal RX, the IN pin is grounded through a resistor R16, the IN + pin of the instrument amplifier U5 is connected with the receiving coil through an interface 2 of the wiring terminal RX, an OUT pin of the instrument amplifier U5 is connected to the IN + pin of the operational amplifier U6 through a capacitor C15, a capacitor C16 and a capacitor C17 IN sequence, the capacitor C15 and the capacitor C16 are grounded through a resistor R20, and the capacitor C16 and the capacitor C17 are grounded through a resistor R21;
the IN-pin of the operational amplifier U6 is grounded through a resistor R19, the IN-pin of the operational amplifier U6 is connected to the OUT-pin of the operational amplifier U6 through a capacitor C18 and a resistor R22, the OUT-pin is connected to the IN + pin of the operational amplifier U7 through a capacitor C19, a capacitor C20 and a capacitor C21 IN sequence, the capacitor C19 and the capacitor C20 are grounded through a resistor R23, the capacitor C20 and the capacitor C21 are grounded through a resistor R24, the IN-pin of the operational amplifier U7 is grounded through a resistor R25, the IN-pin of the operational amplifier U7 is connected to the OUT-pin of the operational amplifier U7 through a capacitor C22 and a resistor R26,
an NC pin of the operational amplifier U7 is connected to an IN + pin of the operational amplifier U8 through a capacitor C23, a capacitor C24 and a capacitor C25 IN sequence, the capacitor C2 and the capacitor C24 are grounded through a resistor R27, and the capacitor C24 and the capacitor C25 are grounded through a resistor R28; the IN-pin of the operational amplifier U8 is grounded through a resistor R29, the IN-pin of the operational amplifier U8 is connected to the OUT-pin of the operational amplifier U8 through a capacitor C26 and a resistor R30, and the OUT-pin of the operational amplifier U8 is connected with a detector circuit;
the detector circuit comprises an instrument amplifier U9, a detector diode D2, a detector capacitor C27 and a detector capacitor C28, wherein the IN-pin of the instrument amplifier U9 is connected to the OUT pin of the operational amplifier U8 through a detector diode D2; an IN-pin of an instrumentation amplifier U9 is grounded through a capacitor C27 and a capacitor C28 respectively, an IN-pin of the instrumentation amplifier U9 is connected to a collector of a triode Q1, an emitter of the triode Q1 is grounded, a base of the triode Q1 is connected to a PE15 pin of a singlechip U1 through a resistor R31, an IN + pin of the instrumentation amplifier U9 is grounded through a filter capacitor C29, an IN + pin of the instrumentation amplifier U9 is connected to a potentiometer RW1, and two ends of the potentiometer RW1 are connected with a power supply AVCC and the ground respectively; a resistor R32 and a resistor R33 are connected in parallel between two RG pins of the instrumentation amplifier U9, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a capacitor C30 in sequence, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D3 in sequence to a 3.3V power supply, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D4 in sequence, and a ref pin of the instrumentation amplifier U9 is grounded;
the alarm and level conversion circuit comprises a conversion chip U10 and an LED diode, a 3.3V power supply is respectively connected with one ends of an LED diode DS2, an LED diode DS1 and an LED diode DS0 through a current-limiting resistor RD1, a current-limiting resistor RD2 and a current-limiting resistor RD3, and the other ends of the LED diode DS2, the LED diode DS1 and the LED diode DS0 are respectively connected with a PB12 pin, a PB13 pin and a PB14 pin of the singlechip U1; a DI pin of a conversion chip U10 is connected with a UART1_ RX/PA9 pin of a singlechip U1, an RO pin of the conversion chip U10 is connected with a UART1_ TX/PA10 pin, an RE pin and a DE pin of the conversion chip U10 are both connected with a PA8 pin of the singlechip U1, a VCC pin of the conversion chip U10 is connected with an interface 4 of a connecting terminal CONN, the connecting terminal CONN is used for data interaction with the outside, an interface 3 and an interface 2 of the connecting terminal CONN are respectively connected with a B pin of the conversion chip U10 and an A pin of the conversion chip U10 through a protection resistor R35 and a protection resistor R36, and an interface 1 of the connecting terminal CONN is connected with a GND pin of the conversion chip U10;
the voltage reduction circuit comprises a switching voltage regulator U11 and a voltage stabilization chip U12, an IN PIN of the switching voltage regulator U11 is connected with an input power PIN, an OUT PIN of the switching voltage regulator U11 is grounded through a freewheeling diode D5, and a GND PIN and an ON/OFF PIN of the switching voltage regulator U11 are both grounded; an OUT pin of the switching voltage regulator U11 is connected with an FB pin of the switching voltage regulator U11 through a freewheeling inductor L3 and then is commonly connected to one end of a decoupling filter capacitor C31 and one end of a decoupling filter capacitor C32, the other ends of the decoupling filter capacitor C31 and the decoupling filter capacitor C32 are grounded, the OUT pin and the FB pin of the switching voltage regulator U11 output 5V power, and the output 5V power is connected with an operational amplifier U2 and a VS + pin of an operational amplifier U3;
an IN pin of a voltage stabilizing chip U12 is connected with a 5V power supply output by a switching voltage regulator U11, the voltage stabilizing chip U12 stabilizes the input 5V voltage to 3.3V, two OUT pins of the voltage stabilizing chip U12 output the stabilized 3.3V power supply, the 3.3V power supply supplies power for a CPU core circuit, an instrumentation amplifier U9 and a conversion chip U10, two OUT pins of the voltage stabilizing chip U12 are grounded through a decoupling capacitor C33, and a GND pin of the voltage stabilizing chip U12 is grounded;
the power supply circuit comprises a power supply polarity converter U13, an adjustable voltage stabilizer U14 and an adjustable voltage stabilizer U15, a CAP + pin of the power supply polarity converter U13 is connected to a CAP-pin of the power supply polarity converter U13 through a starting capacitor C34, a GND pin and an LV pin of the power supply polarity converter U13 are both grounded, a VCC pin of the power supply polarity converter U13 is connected with a 5V power supply output by a switching voltage regulator U11, an OUT pin of the power supply polarity converter U13 is grounded through a decoupling filter capacitor C35 and a decoupling filter capacitor C36, and an OUT pin of the power supply polarity converter U13 outputs a-5V power supply; the output-5V power supply is respectively connected to VS-pins of the operational amplifier U2, the operational amplifier U3, the operational amplifier U6, the operational amplifier U7 and the operational amplifier U8, and the output-5V power supply is also connected to V-pins of the instrumentation amplifier U5 and the instrumentation amplifier U9;
the input power PIN is connected with an IN PIN of an adjustable voltage stabilizer U14 through an inductor L4, the adjustable voltage stabilizer U14 steps down and stabilizes the input power PIN into a power supply PVCC of the power amplifying circuit, and an OUT PIN of the adjustable voltage stabilizer U14 outputs the power supply PVCC; the two ends of the inductor L4 are grounded through a capacitor C37 and a capacitor C38 respectively, the capacitor C37, the inductor L4 and the capacitor C38 form a pi-type filter, an OUT pin of the adjustable voltage stabilizer U14 is connected with an ADJ pin of the adjustable voltage stabilizer U14 through a resistor R38, and the two ends of the resistor R38 are grounded through a resistor R37 and a capacitor C39 respectively;
an IN PIN of the adjustable voltage stabilizer U15 is connected with an input power PIN through an inductor L5, two ends of the inductor L5 are respectively grounded through a capacitor C40 and a capacitor C41, a pi-type filter is formed by a capacitor C40, an inductor L5 and a capacitor C41, the input power PIN is subjected to voltage reduction and voltage stabilization by the adjustable voltage stabilizer U15 to be a power supply AVCC of the receiving and amplifying circuit, an OUT PIN of the adjustable voltage stabilizer U15 outputs the power supply AVCC, the OUT PIN of the adjustable voltage stabilizer U15 is connected with an ADJ PIN of the adjustable voltage stabilizer U15 through a resistor R39, and two ends of a resistor R39 are respectively grounded through a resistor R40 and a capacitor C.
The invention has the following beneficial effects:
1) the spiral wheel arranged at the front end of the soil spade can be used for soil leveling, can provide a leveling detection condition for an instrument detection process, and avoids the interference of uneven soil factors in the manual push-pull or tillage machine traction process so as to influence the detection result.
2) The invention can adapt to different working conditions, can freely adjust the distance between the two sensors according to the actual working conditions, is suitable for manual push-pull, can depend on a mechanical structure drawn by a cultivator, and is convenient and fast to detect.
4) The invention utilizes the self-adaptive pressing device to realize that the detection ship can move up and down along with the height of the soil and keeps close contact with the soil, thereby improving the self-adaptability and the detection reliability and being suitable for popularization and application.
5) The invention has elegant and beautiful integral structure, can be assembled and disassembled in real time and is convenient to use.
6) The circuit design integration in the instrument breaks through the integration of the traditional instrument, can realize the detection and control functions, and has large excitation power and strong anti-interference capability through circuit optimization. The instrument has high sensitivity, stability and reliability.
Drawings
FIG. 1 is a schematic view of an apparatus of the present invention;
FIG. 2 is a schematic view of a test boat assembly;
FIG. 3 is a schematic diagram of a CPU core circuit of the detector;
FIG. 4 is a schematic diagram of a pre-processing circuit of the detector;
FIG. 5 is a schematic diagram of a power amplification circuit of the detector;
FIG. 6 is a schematic diagram of the receive amplifier circuit of the detector;
FIG. 7 is a schematic diagram of the detector circuit of the detector;
FIG. 8 is a schematic diagram of an alarm and level shift circuit of the detector;
FIG. 9 is a schematic diagram of a voltage reduction circuit of the detector;
FIG. 10 is a schematic diagram of the power supply circuitry of the detector.
In the figure: the device comprises a hand-push frame 1, a spiral wheel 2, detection ships 3 and 4, a vehicle body protective cover, a detector 5, lifting lugs 6 and 7, belt wheel protective covers, a belt wheel mechanism 8, a driving motor 9, a detection ship base body 10, a probe 11, a probe self-adaptive pressing device 12, an x-y linear module 13 and a spring 14.
Detailed Description
The invention is further described with reference to the accompanying drawings and the detailed description.
As shown in fig. 1 and 2, a detector 5 is embedded in one side of a hand-push frame 1, a detection boat 3 and a spiral wheel 2 are both arranged in the hand-push frame 1, and a roller for moving back and forth is arranged at the bottom of the hand-push frame 1. A device protective cover 4 for protecting equipment is arranged above the hand-push frame 1, and a belt wheel protective cover 7 is sleeved outside the belt wheel mechanism 8 to play a role in protection.
As shown in FIG. 2, the inspection boat 3 comprises an inspection boat base 10, a double probe 11, a probe adaptive pressing device 12, an x-y linear module 13 and a spring 14. An installation through groove is formed in the middle of the hand-push frame 1, two sides of the detection ship base body 10 are slidably installed in the installation through groove of the hand-push frame 1 through vertically-arranged guide rail slider pairs, one end of a spring 14 is fixed on the lower bottom surface of a flange on the side edge of the detection ship base body 10, the other end of the spring 14 is fixed on the hand-push frame 1, and the four guide rail slider pairs and the spring 14 jointly form a self-adaptive pressing device of the detection ship, so that the detection ship 3 can float up and down relative to the hand-push frame 1 along the guide rail slider pairs under the; when the soil is uneven, the detection boat 3 moves up and down relative to the trolley under the action of the spring 14 to avoid blocking, and the adaptability of the detection boat is improved.
An X-Y linear module 13 is arranged in the detection ship base body 10, the X-Y linear module 13 comprises an X rail and a Y rail which are vertical to each other, the two parallel X rails are connected through the Y rail to form an I-shaped X-Y linear module 13, the two parallel X rails are respectively fixed on the two sides of the detection ship base body 10,
the double probes 11 are sequentially arranged on a Y rail through respective probe self-adaptive pressing devices 12, the lower bottom surfaces of the double probes 11 are attached to the inner bottom surface of the detection ship base body 10 through the probe self-adaptive pressing devices 12, the outer bottom surface of the detection ship base body 10 is contacted with soil, the double probes 11 and the Y rail move together along the two X rails to serve as the X direction of the movement of the double probes 11, the double probes 11 slide along the Y rail to serve as the Y direction of the movement of the double probes 11, the movement direction of the Y rail relative to the two X rails is consistent with the front-back movement direction of the hand-push frame 1, the Y rail is perpendicular to the advancing direction of the hand-push frame 1, and the double probes 11 are connected with the detector; the x-y linear module 13 can adjust the position of the probe within the inspection boat 10 by moving in direction X, Y to adjust the optimal position of the probe.
The probe self-adaptive pressing device 12 is an elastic pressing device, one end of the elastic pressing device is connected with the double probe 11, and the double probe 11 is always tightly attached to the inner bottom surface of the detection ship base body 10 under the elastic action.
The front portion of hand push frame 1 is opened there is the rectangle to lead to the groove, install helical wheel 2 in the rectangle leads to the groove, make helical wheel 2 be located and detect 3 front sides of ship, the both ends of helical wheel 2 place main shaft articulate in hand push frame 1's both sides, helical wheel 2 is rotatory around the main shaft, helical wheel 2's main shaft is on a parallel with the Y rail and arranges, helical wheel 2 is equipped with the helical tooth of continuous distribution along self main shaft, the both ends of helical wheel 2 main shaft all are connected to driving motor 9 through band pulley mechanism 8, driving motor 9 installs in hand push frame 1 rear portion, the equal coaxial coupling in both ends of driving motor 9 output shaft has the motor band pulley, the motor band pulley at both ends constitutes band pulley mechanism 8 through the band pulley at hold-in.
In a specific implementation, the spiral wheel 2 is driven by a driving motor 9 through a belt wheel mechanism 8. Soil can be turned over and cut during rotation, the effect of softening and floating soil is reached, the follow-up 3 bottom plates of detecting ship are favorable to laminating with soil is fine, provide good detection environment.
In specific implementation, the hand push frame 1 is made of high-strength and light aluminum profiles, the front end of the hand push frame 1 in the advancing direction is provided with a lifting lug 6 for manual push-pull or mechanical hook, and the hand push frame can advance equipment by manually pulling the lifting lug 6 or by a mechanical hook. The equipment can realize manual push-pull and can also realize the hanging-pull of the device.
The detection boat 3 is the core part of the integral device, and can be assembled on a trolley through springs on two sides of the detection boat base body 10 and can be independently applied to soil detection. In specific implementation, the front and back surfaces of the detection ship base body 10 are cambered surfaces, so that forward and backward movement can be facilitated, and soil can be leveled. The bottom surface of the detection ship base body 10 is a plane, the lower part of the bottom surface is in contact with the soil surface, and the upper part of the bottom surface is tightly attached to the double probes 11 under the action of the probe self-adaptive pressing device 12.
The double probe 11 comprises a receiving probe and a transmitting probe, the double probe 11 can move relatively in the x-axis direction of the x-y linear module 13, and the position of the probe in the y-axis direction can be adjusted by using the linear module 13 according to the actual detection condition. The probe self-adaptive pressing device 12 is used for ensuring that the probe has a good contact surface with the bottom plate and clings to the bottom plate surface.
When the soil is uneven, the detection ship can move up and down relative to the trolley, so that blockage is avoided, and the self adaptability is improved. The device can select a hand-push type and a hanging type according to actual conditions, and can turn over, cut and soften soil. The sensor leads to the linear module of x-y and fixes in detecting the ship, can in time adjust the sensor position according to actual conditions. By utilizing the self-adaptive pressing device, the detection ship can move up and down along with the height of the soil and keep close contact with the soil.
The detector 5 is embedded in the trolley, and monitors signals fed back by the probe in real time, analyzes, displays and stores data. A preceding stage processing circuit and an alarm and level conversion circuit of the detector 5 are connected to a CPU core circuit, the preceding stage processing circuit inputs signals into a power amplification circuit, the power amplification circuit sends the signals to a receiving amplification circuit through an external excitation coil, the receiving amplification circuit receives the signals of the power amplification circuit through a receiving coil, the receiving amplification circuit inputs the signals into a detection circuit, and an input power PIN supplies power to each circuit through a voltage reduction circuit and a power supply circuit.
As shown IN fig. 3, the CPU core circuit includes a single chip microcomputer U1, an NRST pin and a VREF + pin of the single chip microcomputer U1 are respectively connected to a 3.3V power supply through a resistor R2 and a resistor R3, an OSC _ IN pin, an OSC _ OUT pin and an NRST pin of the single chip microcomputer U1 are respectively connected to ground through a capacitor C1, a capacitor C2 and a capacitor C3, a resistor R1 and a crystal oscillator X1 are connected IN parallel between the capacitor C1 and the capacitor C2, the VREF + pin of the single chip microcomputer U1 is connected to one end of a zener diode D1, one end of the zener diode D1 is further connected to the 3.3V power supply through a resistor R3, the other end of the zener diode D1 is connected to ground, and the D1 is a controllable precise voltage-stabilizing source, and the connection method can provide a precise reference voltage of 2.5V ± 4. The BOOT0 pin of the singlechip U1 is grounded through a resistor R4.
In specific implementation, the U1 adopts STM32F103VCT6 manufactured by seiko semiconductor corporation, which has abundant interface resources such as ROM with a space of 256KB, RAM with a space of 48KB, ADC with 16 channels and 12 bits, DAC with 2 channels and 12 bits, and 5 independent serial ports, and has a maximum dominant frequency of 72 MHz. C1, C2, R1 and X1 provide an oscillating circuit of a main frequency for the CPU, and the oscillating frequency is 8 MHz; C3R2 constitutes a reset circuit of the CPU; the R3D1 is a reference source voltage stabilizing circuit and is used for providing accurate 2.500V voltage reference for a DAC (digital-to-analog converter) and an ADC (analog-to-digital converter) of the CPU; r4 is the starting selection of the CPU, and the R4 grounded CPU starting entrance is the internal FLASH storage; SW is debugging interface of CPU.
As shown IN fig. 4, the pre-processing circuit includes an operational amplifier U2 and an operational amplifier U3, an IN + pin of the operational amplifier U2 is connected to a PA4 pin of the single chip microcomputer U1, an IN-pin of the operational amplifier U2 is grounded through a resistor R6, and an IN-pin of the operational amplifier U2 is connected to an OUT pin thereof through a capacitor C4 and a resistor R5, respectively; an IN + pin of the operational amplifier U3 is connected to an IN-pin of an operational amplifier U3 of a PA5 pin of the singlechip U1 and is grounded through a resistor R7, an IN-pin of the operational amplifier U3 is connected to an OUT pin of the operational amplifier U2 through a capacitor C5 and a resistor R8 respectively, the OUT pin of the operational amplifier U2 is connected to one end of a resistor R9, the OUT pin of the operational amplifier U3 is connected to one end of a resistor R10, and a potentiometer R11 and a capacitor C6 are connected between the other ends of the resistor R9 and the resistor R10 IN parallel.
In a specific implementation, the OP07 model can be used for the operational amplifier U2 and the operational amplifier U3. Because the power amplifier needs to input differential signals, two paths of sine waves with the phase difference of 180 degrees generated by a PA4 pin and a PA5 pin of the singlechip U1 are respectively input to input in-phase ends of the U2 and the U3, and the principle is as follows: the input voltage Ui of the 3 pin non-inverting terminal of U2, the output voltage Uo of 6 pins, the alternating current impedance Xc generated by C4, Uo ═ Ui (1+ R5/Xc), the low pass filtering frequency Fl ═ 1/2 pi × R5 × C4. The bandwidth at-3 db attenuation was tested to be about 15 kHz; u3 is the same. The two paths of output reverse signals are respectively connected with a potentiometer R11 through R9 and R10 for voltage division, and C6 is a filter capacitor for reducing high-frequency harmonic waves and waiting for differential signals WAVEP and WAVEN.
As shown in fig. 5, the power amplifier circuit includes a power amplifier chip U4, an INPR pin of the power amplifier chip U4 is connected to the other end of a resistor R9 through a dc blocking capacitor C7, an INNR pin is connected to the other end of a resistor R10 through a dc blocking capacitor C8, an SDZ pin and a futltz pin of the power amplifier chip U4 are both connected to a power supply PVCC through a resistor R15, wherein the futltz pin is an open-drain output, so that the resistor R15 needs to be pulled up to the power supply PVCC, when the chip fails due to overcurrent or over-temperature, the pin output is a low level, and when the chip normally operates, the pin output is a high level; SDZ is input, when the input is high level chip enable normal work, the chip stops working when low level is input; the connection method can protect the chip itself.
The PLIMIT pin and the GVDD pin of the power amplifier chip U4 are connected and grounded through a capacitor C9, the GVDD pin and the GND pin of the power amplifier chip U4 are connected to the GAIN/SLV pin of the power amplifier chip U4 through a resistor R12 and a resistor R13 respectively, and the MUTE pin of the power amplifier chip U4 is grounded through a resistor R14. The BSNR pin of the power amplifier chip U4 is connected to one end of an inductor L1 through a capacitor C11, the OUTNR pin is connected to one end of an inductor L1, the other end of the inductor L1 is externally connected with an exciting coil through a TX1 interface of a wiring terminal, TX is an interface connected with the exciting coil, and the other end of the inductor L1 is grounded through a capacitor; the BSPR pin is connected to one end of an inductor L2 through a capacitor C10, the OUTPR pin is connected to one end of an inductor L2, the other end of the inductor L2 is externally connected with an exciting coil through a TX2 interface of a wiring terminal, and the other end of the inductor L2 is grounded through a capacitor C12; TX is a wiring terminal and is externally connected with an exciting coil, and the effect of the TX is to radiate an electromagnetic field outwards, and the connection is BTL connection and differential output.
In specific implementation, the power amplifier chip U4 adopts TPA3118D2 produced by Texas instruments in America, which is a D-type power amplifier, the conversion efficiency is more than 90%, the heat generated by the operation of components can be greatly reduced, and the continuous operation in a small space is facilitated. Wherein C7 and C8 are blocking capacitors, and R14 and R15 are necessary configurations for normal operation of the chip; r12, R13 and C9 are used for adjusting the amplification gain of the chip, and the gain 30DB is designed in the design; c10 and C11 are feedback capacitors of the chip; l2, C12, L1 and C13 constitute LC filters, respectively, which greatly suppress higher harmonic components.
As shown in fig. 6, the receiving amplifying circuit includes an instrumentation amplifier U5, an operational amplifier U6, an operational amplifier U7 and an operational amplifier U8, and a V + pin of the instrumentation amplifier U5, a VS + pin of the operational amplifier U6, a VS + pin of the operational amplifier U7 and a VS + pin of the operational amplifier U8 are all connected to a 21.5V power supply AVCC.
Two RG pins of an instrument amplifier U5 are connected through a resistor R18, a ref pin of the instrument amplifier U5 is grounded, a resistor R17 and a capacitor C14 are connected IN parallel between an IN pin and an IN + pin of the instrument amplifier U5, an IN pin of an instrument amplifier U5 is connected with a receiving coil through an interface 1 of a connecting terminal RX, RX is a connecting terminal of the receiving coil, the IN pin of the instrument amplifier U5 is grounded through the resistor R16, the IN + pin of the instrument amplifier U5 is connected with the receiving coil through an interface 1 of the connecting terminal RX, an OUT pin of the instrument amplifier U5 is connected to an IN + pin of an operational amplifier U6 through a capacitor C15, a capacitor C16 and a capacitor C17 IN sequence, the capacitor C15 and a capacitor C16 are grounded through a resistor R20, and the capacitor C16 and a capacitor C17 are grounded through a resistor R21.
An IN-pin of an operational amplifier U6 is grounded through a resistor R19, an IN-pin of an operational amplifier U6 is connected to an OUT-pin of the operational amplifier U6 through a capacitor C18 and a resistor R22 respectively, the OUT-pin is connected to an IN + pin of the operational amplifier U20 through a capacitor C19, a capacitor C20 and a capacitor C20 IN sequence, the capacitor C20 and the capacitor C20 are grounded through a resistor R20, an IN-pin of the operational amplifier U20 is grounded through a resistor R20, the IN-pin of the operational amplifier U20 is connected to the OUT-pin of the operational amplifier U20 through a capacitor C20 and a resistor R20 respectively, an NC-pin of the operational amplifier U20 is connected to the IN + pin of the operational amplifier U20 through a capacitor C20, a capacitor C20 and a capacitor C20 are grounded through a resistor R20 respectively.
The IN pin of the operational amplifier U8 is grounded through a resistor R29, the IN pin of the operational amplifier U8 is connected to the OUT pin thereof through a capacitor C26 and a resistor R30, and the OUT pin of the operational amplifier U8 is connected to a detector circuit.
In a specific implementation, the model of the instrumentation amplifier U5 is AD620, and the models of the operational amplifiers U6, U7 and U8 are all OP 07. RX is a receiving coil interface, a receiving signal interface R16100 kR is used for enabling the whole coil to oscillate on the basis of 0V, R17 is a matching resistor, C14 is a matching capacitor, and the functions are to reduce noise of the receiving signal. U5 is an instrument amplifier, and the amplification gain Au: au ═ (49.5kR/R18) + 1. The magnification is about 100 times; the amplified signal enters U6 after passing through a C15R20 and C16R21 second-order high-pass filter; wherein each step of the high pass frequency Fh-Fl-1/2 pi-R15-C20 is about 1.6 kHz; r19, R20 and C18 form a low-pass feedback circuit and amplification factor. Au ═ 1+ (R22// Xc)/R19, where Xc is the capacitive reactance produced by C18. The low-pass frequency Fl is calculated to be about 16 kHz; the principle of U7 and U8 is the same as that of U6, and a signal U1 is obtained after three-stage amplification.
As shown IN FIG. 7, the detector circuit comprises an instrumentation amplifier U9, a detector diode D2, a detector capacitor C27 and a detector capacitor C28, wherein the IN-pin of the instrumentation amplifier U9 is connected to the OUT-pin of an operational amplifier U8 through a detector diode D2; the IN-pin of the instrumentation amplifier U9 is grounded through a capacitor C27 and a capacitor C28 respectively, the IN-pin of the instrumentation amplifier U9 is connected to the collector of a triode Q1, the emitter of the triode Q1 is grounded, and the base of the triode Q1 is connected to the PE15 pin of the singlechip U1 through a resistor R31.
The IN + pin of the instrumentation amplifier U9 is grounded through a filter capacitor C29, the IN + pin of the instrumentation amplifier U9 is connected to a potentiometer RW1, and two ends of the potentiometer RW1 are respectively connected with a power supply AVCC and the ground.
A resistor R32 and a resistor R33 are connected in parallel between two RG pins of the instrumentation amplifier U9, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a capacitor C30 in sequence, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D3 in sequence to a 3.3V power supply, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D4 in sequence, and a ref pin of the instrumentation amplifier U9 is grounded.
In specific implementation, the detector circuit mainly comprises an instrumentation amplifier U9, a detector diode D2 and detector capacitors C27 and C28, wherein the instrumentation amplifier U9 is AD 620. The signal U1 retains a positive half-axis signal after passing through a detection diode D2, and retains a positive half-axis envelope signal through C27 and C28; because the change of the conductivity can cause the change of a tiny peak value, a basic quantity signal is removed during detection, and an obtained signal can be amplified to provide an analog signal which can be collected by a CPU. Wherein Q1R31 is the release circuit, and the effect lies in: when the U1 peak is reduced, the charge of the capacitor cannot be discharged due to the unidirectional conductivity of the D2, and the output voltage signal remains unchanged, resulting in increased error in measurement. Therefore, the periodic discharge of the transistor Q18050 can effectively solve the problem.
Output signal Uo: uo { [49.5kR/(R32// R33) ] +1}, where Ui is the reverse terminal voltage of the input of U9, Ub is the analog signal regulated by the potentiometer RW1, and C29 is the filter capacitor, making Ub more stable. R34, D3, D4 and C30 form a protection circuit, D3 and D4 are clamping diodes, so that the amplitude of a signal entering a CPU is limited to-0.7-4.0 (the forward voltage drop of the diode is calculated to be 0.7V), and C30 is a filter capacitor, so that the signal measurement is stable.
As shown in fig. 8, the alarm and level shift circuit includes a shift chip U10 and an LED diode, the 3.3V power supply is connected to one end of an LED diode DS2, an LED diode DS1 and an LED diode DS0 through a current limiting resistor RD1, a current limiting resistor RD2 and a current limiting resistor RD3, and the other ends of the LED diode DS2, the LED diode DS1 and the LED diode DS0 are connected to a pin PB12, a pin PB13 and a pin PB14 of a single chip U1; the DI pin of the conversion chip U10 is connected with the UART1_ RX/PA9 pin of the singlechip U1, the RO pin of the conversion chip U10 is connected with the UART1_ TX/PA10 pin, the RE pin and the DE pin of the conversion chip U10 are both connected with the PA8 pin of the singlechip U1, the VCC pin of the conversion chip U10 is connected with the interface 4 of a connection terminal CONN, the connection terminal CONN is used for data interaction of RS485 signals with the outside, the interface 3 and the interface 2 of the connection terminal CONN are respectively connected with the B pin of the conversion chip U10 and the A pin of the conversion chip U10 through a protection resistor R35 and a protection resistor R36, and the interface 1 of the connection terminal CONN is connected with the GND pin of the conversion chip U10.
In specific implementation, the conversion chip U10 is a TTL-RS485 conversion chip, which is used for transmitting data acquired and processed by a CPU to an upper computer through a serial port, but TTL signals are easy to interfere and have short transmission distance, and the conversion chip is added for solving the problem, converting the TTL signals into RS485 signals, and the transmission distance can reach 1.2km at the rate of 9600 bps. TXD and RXD are a CPU serial port data transmitting end and a receiving end, and CTRL is half-duplex transceiving control; r35 and R36 are protection resistors. DS0, DS1 and DS2 are red LED indicators for indicating the operation status and data transmission/reception status. RD1, RD2, RD3 are current limiting resistors.
As shown IN fig. 9, the step-down circuit includes a switching voltage regulator U11 and a voltage regulation chip U12, an IN PIN of the switching voltage regulator U11 is connected to the input power PIN, an OUT PIN of the switching voltage regulator U11 is connected to the ground through a freewheeling diode D5, and a GND PIN and an ON/OFF PIN of the switching voltage regulator U11 are both connected to the ground.
An OUT pin of the switching voltage regulator U11 is connected with an FB pin of the switching voltage regulator U11 through a freewheeling inductor L3, and then is commonly connected to one end of a decoupling filter capacitor C31 and one end of a decoupling filter capacitor C32, the other ends of the decoupling filter capacitor C31 and the decoupling filter capacitor C32 are both grounded, and the OUT pin and the FB pin of the switching voltage regulator U11 output a 5V power supply.
The output 5V power supply is connected with the operational amplifier U2 and the VS + pin of the operational amplifier U3
An IN pin of the voltage stabilizing chip U12 is connected with a 5V power supply output by the switching voltage regulator U11, the voltage stabilizing chip U12 stabilizes an input 5V voltage to 3.3V, two OUT pins of the voltage stabilizing chip U12 output a stabilized 3.3V power supply, the 3.3V power supply supplies power for a CPU core circuit, an instrumentation amplifier U9 and a conversion chip U10, two OUT pins of the voltage stabilizing chip U12 are grounded through a decoupling capacitor C33, and a GND pin of the voltage stabilizing chip U12 is grounded.
In specific implementation, the switching voltage regulator U11 adopts a switching type voltage-stabilized power supply chip LM2596S-5.0, so that the conversion efficiency is high, and the generated heat is small. The model of the voltage stabilizing chip U12 is AMS 1117. L3 is a freewheeling inductor, D5 is a freewheeling diode, and C31C32 is a decoupling filter capacitor; the 3.3V power supply required by the CPU operation is generated by U12AMS1117-3.3, specifically, the input 5V voltage is stabilized to 3.3V, and C33 is a decoupling capacitor.
As shown in fig. 10, the power supply circuit includes a power polarity converter U13, an adjustable regulator U14 and an adjustable regulator U15, a CAP + pin of the power polarity converter U13 is connected to a CAP-pin of the power polarity converter U13 through a start-up capacitor C34, a GND pin and a LV pin of the power polarity converter U13 are both grounded, a VCC pin of the power polarity converter U13 is connected to a 5V power supply output by the switching voltage regulator U11, an OUT pin of the power polarity converter U13 is grounded through a decoupling filter capacitor C35 and a decoupling filter capacitor C36, and an OUT pin of the power polarity converter U13 outputs a-5V power supply.
The output-5V power supply is respectively connected to VS-pins of the operational amplifier U2, the operational amplifier U3, the operational amplifier U6, the operational amplifier U7 and the operational amplifier U8, and the output-5V power supply is also connected to VS-pins of the instrumentation amplifier U5 and the instrumentation amplifier U9.
The input power PIN is connected with an IN PIN of an adjustable voltage stabilizer U14 through an inductor L4, the adjustable voltage stabilizer U14 steps down and stabilizes the input power PIN into a power supply PVCC of the power amplifying circuit, and an OUT PIN of the adjustable voltage stabilizer U14 outputs the power supply PVCC; the two ends of the inductor L4 are grounded through a capacitor C37 and a capacitor C38 respectively, the capacitor C37, the inductor L4 and the capacitor C38 form a pi-type filter, an OUT pin of the adjustable voltage stabilizer U14 is connected with an ADJ pin of the adjustable voltage stabilizer U14 through a resistor R38, and the two ends of the resistor R38 are grounded through a resistor R37 and a capacitor C39 respectively.
An IN PIN of the adjustable voltage stabilizer U15 is connected with an input power PIN through an inductor L5, two ends of the inductor L5 are respectively grounded through a capacitor C40 and a capacitor C41, a pi-type filter is formed by a capacitor C40, an inductor L5 and a capacitor C41, the input power PIN is subjected to voltage reduction and voltage stabilization by the adjustable voltage stabilizer U15 to be a power supply AVCC of the receiving and amplifying circuit, an OUT PIN of the adjustable voltage stabilizer U15 outputs the power supply AVCC, the OUT PIN of the adjustable voltage stabilizer U15 is connected with an ADJ PIN of the adjustable voltage stabilizer U15 through a resistor R39, and two ends of a resistor R39 are respectively grounded through a resistor R40 and a capacitor C.
In specific implementation, the power polarity converter U13 is an ICL7660 type, and the adjustable voltage regulator U14 and the adjustable voltage regulator U15 are LM350 types. The negative pressure used by the system is generated by ICL7660, C34 is a vibration capacitor, the oscillation frequency of a voltage pump can be kept at about 10kHz, 5 pins can output a power supply of-5V under the condition that the power supply is 5V, and C35 and C36 are decoupling filter capacitors. U14, U15 are LM350 and are used for stepping down, in order to avoid the system work unstability that external power supply fluctuation arouses, have done step-down processing to input power PIN respectively, wherein C37, L4, C38 constitute pi type filter for the high frequency crosstalk of input power and output power carries out effective suppression, output voltage is that R37, R38 ratio determine, output voltage UO: uo ═ 1.25V ═ 1+ R37/R38) + Iadj R37. Iadj can be ignored, and the power supply PVCC is about 21.5V; u15 is the same.
Both PVCC and AVCC are generated by external power supply PIN inputs stepped down and regulated by adjustable regulator U14 and adjustable regulator U15, respectively. The PVCC is a power supply of the power amplification circuit, the AVCC is a power supply of the receiving amplification circuit, the voltage of each PVCC and the voltage of each AVCC are 21.5V, and the PVCC and the voltage of each AVCC are divided into two paths so as to prevent noise generated during power amplification from being coupled into the receiving signal amplification power supply to influence the signal-to-noise ratio of received signal amplification and supply power separately.
The entire circuit of the detector 5 can be divided into a power supply portion, a transmission portion, a reception portion, and a detection portion. The chips U11, U12, U13, U14, and U15 constitute a power supply portion of the meter 5. The power supply circuit provides stable power supply voltage for the instrument and the singlechip respectively. A plurality of high-frequency filtering and low-frequency filtering are additionally arranged in the circuit, so that the stable voltage is guaranteed.
The chips U2, U3 and U4 form an emitting part of the detector, and are used for exciting high-power sine waves, clutter signals are removed through a filter circuit, and the excited pure sine waves are applied to the self-made sensor. The receiving circuit is a multi-stage signal amplifying circuit composed of an operational amplifier OP07, and the amplification factor is automatically adjusted. Through the ingenious triode circuit design, the residual excitation signal can be released in real time through single-chip microcomputer control, and the continuous detection for multiple times is guaranteed.
The chips U5, U6, U7, U8 constitute the receiving portion of the detector. The instrument is used for exciting a stable sine wave through the ARM in cooperation with the high power amplifier chip to act on the self-made sensor, and the received signal is displayed after being processed by the instrument amplifier. U9 and U10 are used as sensor parts. The invention breaks through the integration of the traditional instrument through the circuit design integration, brings convenience for the secondary development of users, can realize the integration of the detection and control functions, solves the problem of insufficient excitation power of the traditional instrument through the circuit optimization and large excitation power, avoids the problem of external electromagnetic interference in the actual working condition through the optimization of the power supply circuit, and has strong interference resistance. The adaptability and the reliability are improved, and the method is suitable for popularization and application.

Claims (5)

1. A self-adaptation soil conductivity check out test set which characterized in that:
the device comprises a hand-push frame (1), a spiral wheel (2), a detection boat (3) and a detector (5), wherein the detector (5) is embedded in one side of the hand-push frame (1), the detection boat (3) and the spiral wheel (2) are both arranged in the hand-push frame (1), and the bottom of the hand-push frame (1) is provided with a roller for moving back and forth; the detection ship (3) comprises a detection ship base body (10), double probes (11), a probe self-adaptive pressing device (12), an x-y linear module (13) and a spring (14), wherein an installation through groove is formed in the middle of the hand-push frame (1), two sides of the detection ship base body (10) are arranged in the installation through groove of the hand-push frame (1) in a sliding mode through a vertically arranged guide rail slider pair, one end of the spring (14) is fixed to the lower bottom surface of a flange on the side edge of the detection ship base body (10), and the other end of the spring (14) is fixed to the hand-push frame (1), so that the detection ship (3) can float up and down along the guide rail slider pair under the action of the spring (14) relative to the hand; an X-Y linear module (13) is arranged in a detection ship base body (10), the X-Y linear module (13) comprises an X rail and a Y rail which are vertical to each other, the two X rails which are parallel to each other are connected through the Y rail to form an I-shaped X-Y linear module (13), the two X rails which are parallel to each other are respectively fixed on two sides of the detection ship base body (10), double probes (11) are respectively and sequentially arranged on the Y rail through respective probe self-adaptive pressing devices (12), the lower bottom surfaces of the double probes (11) are attached to the inner bottom surface of the detection ship base body (10) through the probe self-adaptive pressing devices (12), the outer bottom surface of the detection ship base body (10) is contacted with soil, the double probes (11) and the Y rail move together along the two X rails to serve as the X direction of the movement of the double probes (11), and the double probes (11) slide along the Y rail to serve as the Y direction of the movement of the double, the double probes (11) are connected with the detector (5); the front portion of hand push frame (1) is opened there is the rectangle to lead to the groove, install helical wheel (2) in the rectangle leads to the groove, the both ends of helical wheel (2) place main shaft articulate in the both sides of hand push frame (1), the main shaft of helical wheel (2) is on a parallel with the Y rail and arranges, helical wheel (2) are equipped with the helical tooth of continuous distribution along self main shaft, the both ends of helical wheel (2) main shaft all are connected to driving motor (9) through band pulley mechanism (8), driving motor (9) are installed in hand push frame (1) rear portion, the equal coaxial coupling in both ends of driving motor (9) output shaft has the motor band pulley, the motor band pulley at both ends corresponds the band pulley at both ends through hold-in range (7) and helical wheel (2) respectively and constitutes.
2. The adaptive soil conductivity detection device of claim 1, wherein: the front end of the hand-push frame (1) in the advancing direction is provided with a lifting lug (6) for manual push-pull or mechanical hook.
3. The adaptive soil conductivity detection device of claim 1, wherein: a device protective cover (4) is arranged above the hand-push frame (1), and a belt wheel protective cover (7) is sleeved outside the belt wheel mechanism (8).
4. The adaptive soil conductivity detection device of claim 1, wherein: the hand-push frame (1) is made of aluminum profiles.
5. The adaptive soil conductivity detection device of claim 1, wherein:
the detector (5) comprises a CPU core circuit, a preceding stage processing circuit, a power amplifying circuit, a receiving amplifying circuit, a detecting circuit, an alarm and level conversion circuit, a voltage reduction circuit and a power supply circuit,
the pre-stage processing circuit is connected with the detection circuit through the power amplification circuit and the receiving amplification circuit in sequence, the pre-stage processing circuit, the detection circuit and the alarm and level conversion circuit are all connected with the CPU core circuit, and the input power PIN is connected with the voltage reduction circuit and the power supply circuit;
the pre-stage processing circuit inputs signals into the power amplifying circuit, the power amplifying circuit sends the signals to the receiving amplifying circuit through the external exciting coil, the receiving amplifying circuit receives the signals of the power amplifying circuit through the receiving coil, the receiving amplifying circuit inputs the signals into the detection circuit, the detection circuit outputs the signals to the CPU core circuit, and the input power PIN supplies power to each circuit through the voltage reducing circuit and the power supply circuit;
the CPU core circuit comprises a singlechip U1, an NRST pin and a VREF + pin of the singlechip U1 are respectively connected with a 3.3V power supply through a resistor R2 and a resistor R3, an OSC _ IN pin, an OSC _ OUT pin and an NRST pin of the singlechip U1 are respectively grounded through a capacitor C1, a capacitor C2 and a capacitor C3, a resistor R1 and a crystal oscillator X1 are connected between the capacitor C1 and the capacitor C2 IN parallel, the VREF + pin of the singlechip U1 is connected with one end of a voltage stabilizing diode D1, one end of the voltage stabilizing diode D1 is also connected with the 3.3V power supply through the resistor R3, the other end of the voltage stabilizing diode D1 is grounded, and a BOOT0 pin of the singlechip U1 is grounded through a resistor R4;
the pre-stage processing circuit comprises an operational amplifier U2 and an operational amplifier U3, an IN + pin of the operational amplifier U2 and an IN + pin of the operational amplifier U3 are respectively connected to a PA4 pin and a PA5 pin of the singlechip U1, the IN-pin of the operational amplifier U2 is grounded through a resistor R6, and the IN-pin of the operational amplifier U2 is respectively connected to an OUT pin of the operational amplifier U2 through a capacitor C4 and a resistor R5; an IN-pin of the operational amplifier U3 is grounded through a resistor R7, an IN-pin of the operational amplifier U3 is connected to an OUT-pin of the operational amplifier U3 through a capacitor C5 and a resistor R8 respectively, the OUT-pin of the operational amplifier U2 is connected to one end of a resistor R9, the OUT-pin of the operational amplifier U3 is connected to one end of the resistor R10, and a potentiometer R11 and a capacitor C6 are connected between the other ends of the resistor R9 and the resistor R10 IN parallel;
the power amplification circuit comprises a power amplification chip U4, an INPR pin of the power amplification chip U4 is connected to the other end of a resistor R9 through a blocking capacitor C7, an INNR pin of the power amplification chip U4 is connected to the other end of a resistor R10 through a blocking capacitor C8, a PLIMIT pin and a GVDD pin of the power amplification chip U4 are connected and grounded through a capacitor C9, a GVDD pin and a GND pin of the power amplification chip U4 are connected to a GAIN/SLV pin of the power amplification chip U4 through a resistor R12 and a resistor R13 respectively, a MUTE pin of the power amplification chip U4 is grounded through a resistor R14, a BSNR pin of the power amplification chip U4 is connected to one end of an inductor L1 through a capacitor C11, an OUTNR pin of the power amplification chip U4 is connected to one end of the inductor L1, the other end of the inductor L1 is externally connected with an; the BSPR pin of the power amplifier chip U4 is connected to one end of an inductor L2 through a capacitor C10, the OUTPR pin is connected to one end of an inductor L2, the other end of the inductor L2 is externally connected with an exciting coil through a 2 interface of a wiring terminal TX, and the other end of the inductor L2 is grounded through a capacitor C12;
the receiving amplifying circuit comprises an instrumentation amplifier U5, an operational amplifier U6, an operational amplifier U7 and an operational amplifier U8, wherein a V + pin of the instrumentation amplifier U5, a VS + pin of the operational amplifier U6, a VS + pin of the operational amplifier U7 and a VS + pin of the operational amplifier U8 are connected with a power supply AVCC; two RG pins of an instrument amplifier U5 are connected through a resistor R18, a ref pin of the instrument amplifier U5 is grounded, a resistor R17 and a capacitor C14 are connected IN parallel between an IN pin and an IN + pin of the instrument amplifier U5, the IN pin is connected with a receiving coil through an interface 1 of a wiring terminal RX, the IN pin is grounded through a resistor R16, the IN + pin of the instrument amplifier U5 is connected with the receiving coil through an interface 2 of the wiring terminal RX, an OUT pin of the instrument amplifier U5 is connected to the IN + pin of the operational amplifier U6 through a capacitor C15, a capacitor C16 and a capacitor C17 IN sequence, the capacitor C15 and the capacitor C16 are grounded through a resistor R20, and the capacitor C16 and the capacitor C17 are grounded through a resistor R21;
the IN-pin of the operational amplifier U6 is grounded through a resistor R19, the IN-pin of the operational amplifier U6 is connected to the OUT-pin of the operational amplifier U6 through a capacitor C18 and a resistor R22, the OUT-pin is connected to the IN + pin of the operational amplifier U7 through a capacitor C19, a capacitor C20 and a capacitor C21 IN sequence, the capacitor C19 and the capacitor C20 are grounded through a resistor R23, the capacitor C20 and the capacitor C21 are grounded through a resistor R24, the IN-pin of the operational amplifier U7 is grounded through a resistor R25, the IN-pin of the operational amplifier U7 is connected to the OUT-pin of the operational amplifier U7 through a capacitor C22 and a resistor R26,
an NC pin of the operational amplifier U7 is connected to an IN + pin of the operational amplifier U8 through a capacitor C23, a capacitor C24 and a capacitor C25 IN sequence, the capacitor C23 and the capacitor C24 are grounded through a resistor R27, and the capacitor C24 and the capacitor C25 are grounded through a resistor R28; the IN-pin of the operational amplifier U8 is grounded through a resistor R29, the IN-pin of the operational amplifier U8 is connected to the OUT-pin of the operational amplifier U8 through a capacitor C26 and a resistor R30, and the OUT-pin of the operational amplifier U8 is connected with a detector circuit;
the detector circuit comprises an instrument amplifier U9, a detector diode D2, a detector capacitor C27 and a detector capacitor C28, wherein the IN-pin of the instrument amplifier U9 is connected to the OUT pin of the operational amplifier U8 through a detector diode D2; an IN-pin of an instrumentation amplifier U9 is grounded through a capacitor C27 and a capacitor C28 respectively, an IN-pin of the instrumentation amplifier U9 is connected to a collector of a triode Q1, an emitter of the triode Q1 is grounded, a base of the triode Q1 is connected to a PE15 pin of a singlechip U1 through a resistor R31, an IN + pin of the instrumentation amplifier U9 is grounded through a filter capacitor C29, an IN + pin of the instrumentation amplifier U9 is connected to a potentiometer RW1, and two ends of the potentiometer RW1 are connected with a power supply AVCC and the ground respectively; a resistor R32 and a resistor R33 are connected in parallel between two RG pins of the instrumentation amplifier U9, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a capacitor C30 in sequence, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D3 in sequence to a 3.3V power supply, an OUT pin of the instrumentation amplifier U9 is grounded through a resistor R34 and a clamping diode D4 in sequence, and a ref pin of the instrumentation amplifier U9 is grounded;
the alarm and level conversion circuit comprises a conversion chip U10 and an LED diode, a 3.3V power supply is respectively connected with one ends of an LED diode DS2, an LED diode DS1 and an LED diode DS0 through a current-limiting resistor RD1, a current-limiting resistor RD2 and a current-limiting resistor RD3, and the other ends of the LED diode DS2, the LED diode DS1 and the LED diode DS0 are respectively connected with a PB12 pin, a PB13 pin and a PB14 pin of the singlechip U1; a DI pin of a conversion chip U10 is connected with a UART1_ RX/PA9 pin of a singlechip U1, an RO pin of the conversion chip U10 is connected with a UART1_ TX/PA10 pin, an RE pin and a DE pin of the conversion chip U10 are both connected with a PA8 pin of the singlechip U1, a VCC pin of the conversion chip U10 is connected with an interface 4 of a connecting terminal CONN, the connecting terminal CONN is used for data interaction with the outside, an interface 3 and an interface 2 of the connecting terminal CONN are respectively connected with a B pin of the conversion chip U10 and an A pin of the conversion chip U10 through a protection resistor R35 and a protection resistor R36, and an interface 1 of the connecting terminal CONN is connected with a GND pin of the conversion chip U10;
the voltage reduction circuit comprises a switching voltage regulator U11 and a voltage stabilization chip U12, an IN PIN of the switching voltage regulator U11 is connected with an input power PIN, an OUT PIN of the switching voltage regulator U11 is grounded through a freewheeling diode D5, and a GND PIN and an ON/OFF PIN of the switching voltage regulator U11 are both grounded; an OUT pin of the switching voltage regulator U11 is connected with an FB pin of the switching voltage regulator U11 through a freewheeling inductor L3 and then is commonly connected to one end of a decoupling filter capacitor C31 and one end of a decoupling filter capacitor C32, the other ends of the decoupling filter capacitor C31 and the decoupling filter capacitor C32 are grounded, the OUT pin and the FB pin of the switching voltage regulator U11 output 5V power, and the output 5V power is connected with an operational amplifier U2 and a VS + pin of an operational amplifier U3;
an IN pin of a voltage stabilizing chip U12 is connected with a 5V power supply output by a switching voltage regulator U11, the voltage stabilizing chip U12 stabilizes the input 5V voltage to 3.3V, two OUT pins of the voltage stabilizing chip U12 output the stabilized 3.3V power supply, the 3.3V power supply supplies power for a CPU core circuit, an instrumentation amplifier U9 and a conversion chip U10, two OUT pins of the voltage stabilizing chip U12 are grounded through a decoupling capacitor C33, and a GND pin of the voltage stabilizing chip U12 is grounded;
the power supply circuit comprises a power supply polarity converter U13, an adjustable voltage stabilizer U14 and an adjustable voltage stabilizer U15, a CAP + pin of the power supply polarity converter U13 is connected to a CAP-pin of the power supply polarity converter U13 through a starting capacitor C34, a GND pin and an LV pin of the power supply polarity converter U13 are both grounded, a VCC pin of the power supply polarity converter U13 is connected with a 5V power supply output by a switching voltage regulator U11, an OUT pin of the power supply polarity converter U13 is grounded through a decoupling filter capacitor C35 and a decoupling filter capacitor C36, and an OUT pin of the power supply polarity converter U13 outputs a-5V power supply; the output-5V power supply is respectively connected to VS-pins of the operational amplifier U2, the operational amplifier U3, the operational amplifier U6, the operational amplifier U7 and the operational amplifier U8, and the output-5V power supply is also connected to V-pins of the instrumentation amplifier U5 and the instrumentation amplifier U9;
the input power PIN is connected with an IN PIN of an adjustable voltage stabilizer U14 through an inductor L4, the adjustable voltage stabilizer U14 steps down and stabilizes the input power PIN into a power supply PVCC of the power amplifying circuit, and an OUT PIN of the adjustable voltage stabilizer U14 outputs the power supply PVCC; the two ends of the inductor L4 are grounded through a capacitor C37 and a capacitor C38 respectively, the capacitor C37, the inductor L4 and the capacitor C38 form a pi-type filter, an OUT pin of the adjustable voltage stabilizer U14 is connected with an ADJ pin of the adjustable voltage stabilizer U14 through a resistor R38, and the two ends of the resistor R38 are grounded through a resistor R37 and a capacitor C39 respectively;
an IN PIN of the adjustable voltage stabilizer U15 is connected with an input power PIN through an inductor L5, two ends of the inductor L5 are respectively grounded through a capacitor C40 and a capacitor C41, a pi-type filter is formed by a capacitor C40, an inductor L5 and a capacitor C41, the input power PIN is subjected to voltage reduction and voltage stabilization by the adjustable voltage stabilizer U15 to be a power supply AVCC of the receiving and amplifying circuit, an OUT PIN of the adjustable voltage stabilizer U15 outputs the power supply AVCC, the OUT PIN of the adjustable voltage stabilizer U15 is connected with an ADJ PIN of the adjustable voltage stabilizer U15 through a resistor R39, and two ends of a resistor R39 are respectively grounded through a resistor R40 and a capacitor C.
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