CN109656855A - The method of data is read and write in network interface card, calculates storage network integration chip and network interface card - Google Patents
The method of data is read and write in network interface card, calculates storage network integration chip and network interface card Download PDFInfo
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- CN109656855A CN109656855A CN201810937150.3A CN201810937150A CN109656855A CN 109656855 A CN109656855 A CN 109656855A CN 201810937150 A CN201810937150 A CN 201810937150A CN 109656855 A CN109656855 A CN 109656855A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
It is a kind of in network interface card read and write data method include: to be decoded to the data packet received；If obtaining write order, then continue to data packet, the data demand for irrecoverable error occur is retransmitted, it is defined according to user and artificial intelligence is carried out to the data for not occurring above-mentioned mistake, compression calculates, Error Correction of Coding is carried out to data, according to storage chip agreement by the storage chip of Error Correction of Coding treated data write-in network interface card；If obtaining read command, data are then read from the storage chip of network interface card according to storage chip agreement, the data read are verified, it is defined according to user to correct data and carries out artificial intelligence reasoning and calculation, decompression calculations using the correct data that error correction algorithm obtains, the data after calculation processing are packaged and issued according to network protocol.The present invention can complete network protocol processing in network interface card, artificial intelligence calculates and storage control function, need not move through host CPU and memory, delay is very short, and realizes high-performance.
Description
Technical field
The present invention relates to field of computer technology, more specifically, particularly relate to it is a kind of in network interface card read and write data method,
Calculate storage network integration chip and network interface card.
Background technique
In traditional enterprise backend services device, network interface card handles network protocol, while network data transmission to host memory,
It is calculated by CPU and is handled, the data for needing to store are sent in storage array, are responsible for write-in storage by storage control and are situated between
Matter.
With the appearance of the high speeds storage medium such as full flash memory, storage performance growth rate is faster than the promotion of CPU processing capacity
Speed.Meanwhile in the data center, it has begun using 100G high speed network, CPU can no longer meet high speed network and high speed
Store bring supercomputing demand.
In the prior art, calculating, storage, network use three chips to realize respectively, and this technology has the disadvantage that:
1. reading and writing data will transmit between network interface card, memory and storage control, read-write postpones very long, period of reservation of number
It is very long；
2. the interface capability between network interface card, memory and storage control limits the promotion of overall performance；
3. the demand that universal cpu is unable to satisfy mass data calculating.
Therefore, promotion experience bottleneck etc. that this field is urgently required to solve reading and writing data delay length, system performance is asked
The technical solution of topic.
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is to propose a kind of method of read-write data in network interface card, calculates and deposit
Store up network integration chip and network interface card.The promotion that the present invention solves reading and writing data delay length, system performance meets with the skills such as bottleneck
Art problem specifically can complete network in a calculating storage network integration chip when reading and writing data in network interface card
Protocol processes, artificial intelligence calculate and storage control function, needs not move through host CPU and memory, is directly realized by data in net
Transmission between network port and storage array, delay is very short, and realizes high-performance.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of method that data are read and write in network interface card, packet
Include following steps:
The data packet received by network interface is decoded；
If obtaining write order, data packet is continued to, to there is irrecoverable error during continuing to
Data then require to retransmit, and are defined according to user and carry out artificial intelligence, compression calculating to the data for not occurring irrecoverable error,
Then Error Correction of Coding is carried out to data using error correction algorithm, finally according to storage chip agreement by Error Correction of Coding treated data
The storage chip of network interface card is written；
If obtaining read command, data are read from the storage chip of network interface card according to storage chip agreement, to what is read
Data are verified, and artificial intelligence reasoning and calculation, decompression calculations are carried out to correct data according to user's definition, to wrong data
Then using error correction algorithm obtain correct data and according to user define to obtained correct data carry out artificial intelligence reasoning and calculation,
Decompression calculations finally package to the data after calculation processing according to network protocol and are issued by network interface.
In some embodiments, this method further comprises: returning to write operation result after write operation completion
Issue the user of write order.
In some embodiments, this method further comprises: during read operation, if do not had using error correction algorithm
Correct data is obtained, then reading failure news is returned to the user for issuing read command.
The another aspect of the embodiment of the present invention, additionally provides a kind of calculating storage network integration chip, which is used for
In network interface card, and it is configured to execute above-mentioned method.
In some embodiments, which includes fpga chip, CPLD chip or asic chip.
The another aspect of the embodiment of the present invention additionally provides a kind of network interface card, comprising:
Network interface, the network interface are used to transmit data；
Storage chip array, the storage chip array are used to storing data；And
Above-mentioned calculating stores network integration chip, which stores network integration chip and the network interface and should
The connection of storage chip array.
In some embodiments, which further includes D/A converting circuit, which is used to simultaneously line number
Word signal is converted into high-speed serial signals.
The present invention has following advantageous effects: the method for the read-write data provided in an embodiment of the present invention in network interface card,
Storage network integration chip and network interface card are calculated, completes network by storing in network integration chip in a calculating of network interface card
Protocol processes, artificial intelligence calculate and the technical solution of storage control function, be able to use user data directly in the network port and
It is transmitted between storage chip, reduces the delay of 10 microseconds, period of reservation of number is reduced, in particular, this is in financial transaction, e-commerce
There is immense value in equal fields；Network card chip, storage control chip and artificial intelligence computing chip are integrated into a meter by the present invention
Storage network integration chip is calculated, reduces user cost to original one third；Network integration core is stored with a calculating
The turnover of piece little data, significantly improves system performance.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, embodiment will be described below
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the flow diagram according to the method for reading and writing data in network interface card of one embodiment of the invention；
Fig. 2 is the hardware structural diagram according to the network interface card of one embodiment of the invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention proposes a kind of side that data are read and write in network interface card
One embodiment of method.Shown in fig. 1 is the flow diagram of this method.
As shown in Figure 1, this method since step S101, in step S101, receives data by the network interface of network interface card
Packet.Next, calculating storage network integration chip (for example, fpga chip) of network interface card is in step S101 in step S102
The data packet received is decoded, and judgement is write order or read command (step S103) after decoding.If what is obtained is to write
Order, then continue to data packet (step S104).Next, calculating storage network integration chip judgement in step S105
Whether the data continued to there is irrecoverable error, then require to retransmit to the data for irrecoverable error occur
(step S106) carries out artificial intelligence, compression calculating to the data for not occurring irrecoverable error in addition, defining according to user
(step S107).Then, in step S108, storage network integration chip is calculated using error correction algorithm to by step S107
The data of reason carry out Error Correction of Coding, finally calculate storage network integration chip and are handled Error Correction of Coding according to storage chip agreement
The storage chip of the network interface card is written in data afterwards.In a preferred embodiment, this method may further include: write behaviour
Storage network integration chip is calculated after completing, and write operation result is returned to the user (step S109) for issuing write order.
On the other hand, if what is obtained is read command, storage network integration chip is calculated according to storage chip agreement from network interface card
Storage chip reads user data (step S110), is verified (step S111) to the data read, is defined according to user
Artificial intelligence reasoning and calculation, decompression calculations are carried out to correct data, then positive exact figures are obtained using error correction algorithm to wrong data
It is defined according to and according to user and artificial intelligence reasoning and calculation, decompression calculations (step S113) is carried out to obtained correct data, most
It is packaged afterwards according to network protocol to the data after calculation processing and (step S114) is issued by network interface.It is excellent at one
It selects in embodiment, this method further comprises: during read operation, if not obtaining correct data using error correction algorithm,
Reading failure news is then returned to the user (step S112) for issuing the read command.
Based on above-mentioned purpose, the second aspect of the embodiment of the present invention proposes a kind of calculating storage network integration core
One embodiment of piece, the calculating store network integration chip and are used in network interface card, and are configured to execute the method for the present invention reality
Apply the method in example.
In a preferred embodiment, which may include fpga chip, CPLD chip or asic chip.With FPGA
For chip, FPGA is a kind of chip with reconfigurable function, and the difference of general special chip is that special chip is patrolled
Solidification is collected, can not just be changed after production, and the calculating logic inside fpga chip can be reconfigured by user.Using FPGA core
Piece at least provides following three functions: 1. network protocols coding and decoding in the present invention；2. providing computing resource to do to user
Data processing, artificial intelligence etc. calculate；3. controlling storage chip array.
Based on above-mentioned purpose, the third aspect of the embodiment of the present invention proposes a kind of one embodiment of network interface card.Fig. 2
Show the hardware structural diagram of the network interface card.As shown in Fig. 2, the network interface card may include: network interface 201, it is used to transmit
Data, for example, network interface 201 is used to transmit data between front-end server and back-end server；Storage chip array
202, it is used to storing data；And storage network integration chip 203 is calculated, with network interface 201 and storage chip battle array
Column 202 connect, for handling network protocol, data being carried out with artificial intelligence calculating, and control storage chip array, specifically
Ground calculates storage network integration chip 203 and is configured to execute the method in embodiment of the present invention method.It is preferably implemented at one
In example, calculating storage network integration chip 203 may include fpga chip, CPLD chip or asic chip.
In a preferred embodiment, which can also include D/A converting circuit (not shown), D/A converting circuit
For parallel digital signal is converted into high-speed serial signals.In addition to this, it will be understood by those skilled in the art that it is of the invention
Network interface card can also include other elements.
Finally, it should be noted that the embodiment of the present invention, which discloses the network interface card, can be used for various electric terminal equipments, example
Such as, personal computer (PC), tablet computer (PAD), smart television etc., can be used for large-scale terminal device, such as server,
Therefore protection scope disclosed by the embodiments of the present invention should not limit as certain certain types of system, equipment.
Various illustrative logical blocks, module and circuit, which can use, in conjunction with described in disclosure herein is designed to
The following component of function described here is executed to realize or execute: specific integrated circuit (ASIC), field programmable gate array
(FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component or these components are appointed
What is combined.
It is exemplary embodiment disclosed by the invention above, the disclosed sequence of the embodiments of the present invention is just to retouching
It states, does not represent the advantages or disadvantages of the embodiments.It should be noted that the discussion of any of the above embodiment is exemplary only, it is not intended that
Imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples, what is limited without departing substantially from claim
Under the premise of range, it may be many modifications and modify.According to the claim to a method of open embodiment described herein
Function, step and/or movement are not required to the execution of any particular order.In addition, although element disclosed by the embodiments of the present invention can be with
It is described or is required in the form of individual, but be unless explicitly limited odd number, it is understood that be multiple.
Claims (7)
1. a kind of method for reading and writing data in network interface card, which is characterized in that the described method comprises the following steps:
The data packet received by network interface is decoded；
If obtaining write order, data packet is continued to, to there are the data of irrecoverable error during continuing to
It then requires to retransmit, is defined according to user and artificial intelligence, compression calculating are carried out to the data for not occurring irrecoverable error, then
Error Correction of Coding is carried out to data using error correction algorithm, finally Error Correction of Coding treated data are written according to storage chip agreement
The storage chip of the network interface card；
If obtaining read command, data are read from the storage chip of the network interface card according to storage chip agreement, to reading
To data verified, according to user definition to correct data carry out artificial intelligence reasoning and calculation, decompression calculations, to mistake
Data are then obtained correct data and are defined according to user to carry out artificial intelligence reasoning to obtained correct data using error correction algorithm
It calculates, decompression calculations, finally packaged according to network protocol to the data after calculation processing and is issued by network interface.
2. the method according to claim 1, wherein the method further includes: write operation completion after
Write operation result is returned to the user for issuing the write order.
3. the method according to claim 1, wherein the method further includes: during read operation, such as
Fruit does not obtain correct data using error correction algorithm, then reading failure news is returned to the user for issuing the read command.
4. a kind of calculating stores network integration chip, which is characterized in that the chip is used in network interface card, and is configured to execute
Method as described in any one of claim 1-3.
5. chip according to claim 4, which is characterized in that the chip include fpga chip, CPLD chip or
Asic chip.
6. a kind of network interface card, which is characterized in that the network interface card includes:
Network interface, the network interface are used to transmit data；
Storage chip array, the storage chip array are used to storing data；And
Calculating described in claim 4 or 5 stores network integration chip, calculatings store network integration chip with it is described
Network interface is connected with the storage chip array.
7. network interface card according to claim 6, which is characterized in that the network interface card further includes D/A converting circuit, the digital-to-analogue
Conversion circuit is used to parallel digital signal being converted into high-speed serial signals.
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| CN201810937150.3A CN109656855A (en) | 2018-08-16 | 2018-08-16 | The method of data is read and write in network interface card, calculates storage network integration chip and network interface card |
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| CN201810937150.3A CN109656855A (en) | 2018-08-16 | 2018-08-16 | The method of data is read and write in network interface card, calculates storage network integration chip and network interface card |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112948300A (en) * | 2021-01-19 | 2021-06-11 | 浙江大华技术股份有限公司 | Server, integrated storage and calculation device, and server system |
| US11082410B2 (en) | 2019-04-26 | 2021-08-03 | Advanced New Technologies Co., Ltd. | Data transceiving operations and devices |
| CN113438219A (en) * | 2020-07-08 | 2021-09-24 | 支付宝(杭州)信息技术有限公司 | Replay transaction identification method and device based on block chain all-in-one machine |
| TWI743651B (en) * | 2019-04-26 | 2021-10-21 | 開曼群島商創新先進技術有限公司 | Network card, data sending/receiving method and equipment |
| CN113778320A (en) * | 2020-06-09 | 2021-12-10 | 华为技术有限公司 | Network card and method for processing data by network card |
| WO2022073399A1 (en) * | 2020-10-10 | 2022-04-14 | 华为技术有限公司 | Storage node, storage device and network chip |
| US11444783B2 (en) | 2020-07-08 | 2022-09-13 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for processing transactions based on blockchain integrated station |
| US11463553B2 (en) | 2020-07-08 | 2022-10-04 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying to-be-filtered transaction based on blockchain integrated station |
| US11665234B2 (en) | 2020-07-08 | 2023-05-30 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for synchronizing data based on blockchain integrated station |
| US11783339B2 (en) | 2020-07-08 | 2023-10-10 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for transferring transaction based on blockchain integrated station |
| US12014173B2 (en) | 2020-06-09 | 2024-06-18 | Huawei Technologies Co., Ltd. | Data processing method for network adapter and network adapter |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434413A (en) * | 2003-02-27 | 2003-08-06 | 上海交通大学 | Error-correction coder/decoder for long distance medical system data transmission |
| CN101140809A (en) * | 2007-09-07 | 2008-03-12 | 炬力集成电路设计有限公司 | Flash controller supporting pipelined error-correcting code and configurable operations and control method thereof |
| CN101562052A (en) * | 2008-04-14 | 2009-10-21 | 深圳市朗科科技股份有限公司 | Storage equipment screening device and method |
| CN102751995A (en) * | 2012-07-20 | 2012-10-24 | 天津工大瑞工光电技术有限公司 | FPGA (field programmable gate array)-based multiple bit upset resisting RS code error detection and correction system |
| CN103441948A (en) * | 2013-07-03 | 2013-12-11 | 华为技术有限公司 | Data access method, network card and storage system |
| CN105872849A (en) * | 2016-03-30 | 2016-08-17 | 成都凯腾四方数字广播电视设备有限公司 | Network transmission real-time audio-video error correction method and system based on FPGA |
-
2018
- 2018-08-16 CN CN201810937150.3A patent/CN109656855A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434413A (en) * | 2003-02-27 | 2003-08-06 | 上海交通大学 | Error-correction coder/decoder for long distance medical system data transmission |
| CN101140809A (en) * | 2007-09-07 | 2008-03-12 | 炬力集成电路设计有限公司 | Flash controller supporting pipelined error-correcting code and configurable operations and control method thereof |
| CN101562052A (en) * | 2008-04-14 | 2009-10-21 | 深圳市朗科科技股份有限公司 | Storage equipment screening device and method |
| CN102751995A (en) * | 2012-07-20 | 2012-10-24 | 天津工大瑞工光电技术有限公司 | FPGA (field programmable gate array)-based multiple bit upset resisting RS code error detection and correction system |
| CN103441948A (en) * | 2013-07-03 | 2013-12-11 | 华为技术有限公司 | Data access method, network card and storage system |
| CN105872849A (en) * | 2016-03-30 | 2016-08-17 | 成都凯腾四方数字广播电视设备有限公司 | Network transmission real-time audio-video error correction method and system based on FPGA |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11082410B2 (en) | 2019-04-26 | 2021-08-03 | Advanced New Technologies Co., Ltd. | Data transceiving operations and devices |
| TWI743651B (en) * | 2019-04-26 | 2021-10-21 | 開曼群島商創新先進技術有限公司 | Network card, data sending/receiving method and equipment |
| CN113778320A (en) * | 2020-06-09 | 2021-12-10 | 华为技术有限公司 | Network card and method for processing data by network card |
| US12014173B2 (en) | 2020-06-09 | 2024-06-18 | Huawei Technologies Co., Ltd. | Data processing method for network adapter and network adapter |
| CN113438219A (en) * | 2020-07-08 | 2021-09-24 | 支付宝(杭州)信息技术有限公司 | Replay transaction identification method and device based on block chain all-in-one machine |
| US11336660B2 (en) | 2020-07-08 | 2022-05-17 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying replay transaction based on blockchain integrated station |
| US11444783B2 (en) | 2020-07-08 | 2022-09-13 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for processing transactions based on blockchain integrated station |
| US11463553B2 (en) | 2020-07-08 | 2022-10-04 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying to-be-filtered transaction based on blockchain integrated station |
| US11665234B2 (en) | 2020-07-08 | 2023-05-30 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for synchronizing data based on blockchain integrated station |
| US11783339B2 (en) | 2020-07-08 | 2023-10-10 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for transferring transaction based on blockchain integrated station |
| WO2022073399A1 (en) * | 2020-10-10 | 2022-04-14 | 华为技术有限公司 | Storage node, storage device and network chip |
| CN112948300A (en) * | 2021-01-19 | 2021-06-11 | 浙江大华技术股份有限公司 | Server, integrated storage and calculation device, and server system |
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Application publication date: 20190419 |