CN109655736A

CN109655736A - A kind of quick pinpoint method of chip solder failure

Info

Publication number: CN109655736A
Application number: CN201811568442.0A
Authority: CN
Inventors: 喻波; 陈建; 韦双; 蔺江鹏
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2018-12-21
Filing date: 2018-12-21
Publication date: 2019-04-19

Abstract

The present invention relates to a kind of quick pinpoint methods of chip solder failure, Boundary-scan test technology principle based on IEEE1149.1 standard, using walking algorithm basic ideas, a kind of general test program thinking is provided, achievees the purpose that Rapid transplant is tested in various boards.It can sweep between device on different sides, be tested while sweeping Rapid transplant between device and memory.This method is mainly used in integrated circuit testing field, and when being mainly used for solving chip welding spot failure on high density circuit board, the failure as caused by the complexity and chip testability of circuit theory is difficult to the problem being accurately positioned.

Description

A kind of quick pinpoint method of chip solder failure

Technical field

The invention belongs to integrated circuit testing, it is related to a kind of chip solder failure quickly pinpoint method.

Background technique

With the rapid development of electronic technology and the continuous improvement of PCB production technology level, digital circuit integrated level is got over Come that higher, size is smaller and smaller, especially the appearance of surface note dress technology SMT (Surface Mounted Technology), It implement traditional measuring technology can not to the test method of internal system node visit, bring unprecedented Test problem.Traditional needle bed test obtains test point information by probe and test point contact, not only costly, time-consuming It is long, and be difficult to meet current testing requirement.

To solve this problem, JTAG tissue and IEEE tissue be proposed jointly a kind of standard boundary-scan architecture and its Test interface, i.e. IEEE1149.1 boundary scan standard.Its main thought is: by chip pin and chip interior logic Increase boundary scan cell (BSC) between circuit, serial setting and reading to chip pin state is realized, to provide core Chip level, plate grade, system-level standard testing frame.Fault test can be rapidly completed using boundary scan emulator to position.

Summary of the invention

Technical problems to be solved

In order to avoid the shortcomings of the prior art, the present invention proposes a kind of chip solder failure quickly pinpoint side Method, the actual techniques problem of solution is can quick positioning failure when PCBA breaks down.

Technical solution

A kind of quick pinpoint method of chip solder failure, it is characterised in that steps are as follows:

Step 1: utilizing JTAG pinboard, the JTAG device on circuit-under-test plate is accessed into circuit board arrangement link；

Step 2: the BSDL file of inquiry test link coboundary scanning device determines that the defeated of device interconnection pin is swept on side Enter output relation, the pin type that boundary scan emulator can control includes tri- kinds of input, output and bidir；

Step 3: generate test and excitation using walking algorithm, the initial serial test vector of 1 algorithm of walking be " 1,0, 0 ..., N " then allow " 1 " sequential shifts, constitute the combination of N number of serially test vector, corresponding with 1 algorithm of walking is walking 0 Algorithm, the initial testing vector of 0 algorithm of walking are that " 0,1,1 ..., N " then allow " 0 " sequential shifts；The benefit in test code Required test vector is generated with shift instruction；

Step 4: utilizing shift instruction, modification cycle-index N generates the test vector of N group；The N, which is equal to, to be needed to test Number of pin；

Step 5: sweeping the output pin of device to one of side using boundary scan emulator one group of test and excitation of transmission On；It is acquired and is responded from the pin of another device by emulator, it is whether consistent by comparison input stimulus and acquisition response, It is judged as failure pin when non_uniform response.

It is swept on different interconnection sides and sends excitation and acquisition response between device pin, need to only modified transmission and acquisition pin is fixed Justice can Rapid transplant.

Test is written and read to memory using boundary scan emulator, by comparison write-in data and whether reads data It unanimously can determine whether failure pin.

For same memory, in use, need to only modify the control pin that corresponding sides sweep device on other circuit boards ?.

Beneficial effect

A kind of quick pinpoint method of chip solder failure proposed by the present invention, the side based on IEEE1149.1 standard Boundary's scan testing techniques principle using walking algorithm basic ideas, provides a kind of general test program thinking, reaches The purpose that Rapid transplant is tested in various boards.It can be swept between device on different sides, while sweeping between device and memory quickly Transplanting test.This method is mainly used in integrated circuit testing field, is mainly used for solving chip welding spot on high density circuit board When failure, the failure as caused by the complexity and chip testability of circuit theory is difficult to the problem being accurately positioned.

The present invention has the advantages that

1, device is swept for sides different on circuit board, only need to modify test interface can transplant test module, carry out fast Speed test.

2, for the test of memory, the type of memory need to only be established to different test code libraries.In follow-up test In directly modify interface and can quickly test.

Detailed description of the invention

Fig. 1: while sweeping interconnection test and memory test figure；

A kind of Fig. 2: boundary scan testing universal adapter plate suitable for JTAG.

Specific embodiment

Now in conjunction with embodiment, attached drawing, the invention will be further described:

1, using JTAG pinboard, the JTAG device on circuit-under-test plate is accessed into circuit board arrangement link；

2, inquiry test link coboundary scanning device BSDL file, determine side sweep device interconnection pin input it is defeated Relationship out, the pin type that boundary scan emulator can control include tri- kinds of input, output and bidir；

3, test and excitation is generated using walking algorithm, the initial serial test vector of 1 algorithm of walking is " 1,0,0 ..., N " Then it allows " 1 " sequential shifts, constitutes the combination of N number of serially test vector, corresponding with 1 algorithm of walking is 0 algorithm of walking, is walked The initial testing vector for walking 0 algorithm is that " 0,1,1 ..., N " then allow " 0 " sequential shifts.Based on principles above, in test generation Required test vector is generated using shift instruction in code；

4, using shift instruction, it can produce the test vector of (N) group by modifying cycle-index (N), N also represents needs The number of pin of test；

5, it is sent using boundary scan emulator on the output pin that one group of test and excitation sweeps device to one of side. It is acquired and is responded from the pin of another device by emulator.It is responded by comparison input stimulus and acquisition and whether is unanimously sentenced Disconnected failure pin；

6, the above method can be swept on different interconnection sides and send excitation and acquisition response between device pin, need to only modify hair Sending can Rapid transplant with acquisition pin definitions；

7, the method for generating test and excitation according to 3, is written and read test to memory using boundary scan emulator, leads to It crosses comparison write-in data and reads whether data unanimously can determine whether failure pin；

8, for same memory, in use, need to only modify the control pipe that corresponding sides sweep device on other circuit boards Foot.

Claims

1. a kind of quick pinpoint method of chip solder failure, it is characterised in that steps are as follows:

Step 2: the BSDL file of inquiry test link coboundary scanning device determines that the input and output of device interconnection pin are swept on side Relationship, the pin type that boundary scan emulator can control include tri- kinds of input, output and bidir；

Step 3: generating test and excitation using walking algorithm, the initial serial test vector of 1 algorithm of walking is " 1,0,0 ..., N " Then it allows " 1 " sequential shifts, constitutes the combination of N number of serially test vector, corresponding with 1 algorithm of walking is 0 algorithm of walking, walking The initial testing vector of 0 algorithm is that " 0,1,1 ..., N " then allow " 0 " sequential shifts；Shift instruction is utilized in test code To generate required test vector；

Step 4: utilizing shift instruction, modification cycle-index N generates the test vector of N group；The N, which is equal to, needs pin to be tested Quantity；

Step 5: being sent using boundary scan emulator on the output pin that one group of test and excitation sweeps device to one of side；It is logical It crosses emulator and acquires response from the pin of another device, it is whether consistent by comparison input stimulus and acquisition response, work as response It is judged as failure pin when inconsistent.