CN109599431A - 一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 - Google Patents
一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 Download PDFInfo
- Publication number
- CN109599431A CN109599431A CN201811202453.7A CN201811202453A CN109599431A CN 109599431 A CN109599431 A CN 109599431A CN 201811202453 A CN201811202453 A CN 201811202453A CN 109599431 A CN109599431 A CN 109599431A
- Authority
- CN
- China
- Prior art keywords
- power device
- ion
- terminal
- active area
- production method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910002601 GaN Inorganic materials 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 13
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical group [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 11
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910017083 AlN Inorganic materials 0.000 claims description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- 238000010348 incorporation Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 3
- 238000003763 carbonization Methods 0.000 claims 1
- 238000005259 measurement Methods 0.000 claims 1
- 229910052594 sapphire Inorganic materials 0.000 claims 1
- 239000010980 sapphire Substances 0.000 claims 1
- 230000009471 action Effects 0.000 abstract description 13
- 238000002347 injection Methods 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 230000004913 activation Effects 0.000 abstract description 2
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000009776 industrial production Methods 0.000 abstract 1
- 229910001425 magnesium ion Inorganic materials 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical compound Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种用于III‑V族氮化物功率器件有源区与终端结构的制作方法。该方法可以用于制作III‑V族氮化物材料结势垒肖特基二极管结构。本结构中，外延层包括低掺杂浓度的N型漂移层以及高掺杂浓度的P型外延层。在P区中通过注入氢离子或其他具有相似作用的离子以钝化P区中镁离子的激活，降低P型导电率。通过以上方法可以局部钝化P区并与阳极形成肖特基接触，进而制成GaN结势垒肖特基结势垒二极管。通过以上方法也可以得到不同有效掺杂的区域，从而在器件结边缘制作终端，提高器件耐压。这种工艺在实验室和工业生产的条件下可行性较高。能够在P型III‑V族氮化物中降低P型导电率，从而制成结势垒肖特基、各型终端、IGBT、MOSFET等半导体器件或相关结构。
Description
技术领域
本发明涉及半导体技术领域，特别涉及一种用于III-V族氮化物功率器件有源区与终端结构的制作方法。
背景技术
相较于以硅为代表的第一代半导体和以砷化镓为代表的第二代半导体，以碳化硅和III-V族氮化物为代表的第三代半导体，因其禁带宽度大、临界击穿场强高、电子饱和速率高等特点，在电力电子应用中具有显著优势。
目前以结势垒肖特基二极管为代表的结势垒结构已经用于硅和碳化硅器件，但由于工艺原因，在III-V族氮化物器件中，难以形成选择性P性掺杂结构。
肖特基二极管的正向导通电压较低，但是导通后呈现阻性并且反向耐压与方向漏电难以达到较高要求。传统PiN二极管反向击穿电压较高，但是正向导通压降较高，存在较大损耗。引入氢离子或其他具有相似作用的离子后制作得到的结势垒肖特基二极管之后可以有效结合上述两种结构优点，得到正向导通压降较低，击穿电压较高的特性。
在器件阻断特性方面，尽管高压功率器件的阻断特性最终由漂移区的掺杂浓度和厚度决定，但通常会因结附近电场聚集出现提前击穿，因此终端保护技术对于提高器件耐压和可靠性有着重要作用。。
在硅和碳化硅体系中，常用的功率器件终端结构包括场限环(FLR)，结终端延伸(JTE)等终端结构，往往涉及到局部P型掺杂。由于局部P型离子注入和激活效率的根本限制，通过热扩散和离子注入实现氮化镓局部P型掺杂极其困难，使得氮化镓高效稳足终端结构的实现颇具挑战。
发明内容
本发明首先所要解决的技术问题是提供一种用于III-V族氮化物功率器件有源区与终端结构的制作方法，该方法针对现有的结制作技术的难点与不足，适用于III-V族氮化物体系，工艺相对简单，可以降低P型掺杂区域导电率，进而得到结势垒肖特基二极管的有源区结构，或基于结的终端结构。
为此，本发明所述方法采用以下技术方案：一种III-V族氮化物功率器件的有源区制作方法，该方法包括对有源区的P型掺杂区中的部分区域进行钝化，钝化的区域与功率器件的终端不连通。
进一步地，钝化后的区域通过或不通过额外注入Si形成目标浓度的N型区域，并与未钝化的P区形成PN结，且钝化后的区域将与金属形成肖特基接触。
进一步地，所述功率器件包括结势垒肖特基二极管(JBS)、混合PiN/Schottky二极管(MPS)。
一种III-V族氮化物功率器件的终端结构制作方法，所述功率器件中包含有源区，且所述有源区外围具有P型掺杂区，该方法包括：对有源区外围的P型掺杂区进行钝化，获得所述终端结构。
进一步地，所述的终端结构包括结终端扩展、场限环等终端结构。
进一步地，终端结构与功率器件的电极、有源区中的任意一个重叠，不重叠或边缘对齐；其深度与主结深度相同，或者不同。
进一步地，终端结构单独作为功率器件的终端，或者，与场板或沟槽结构共同构成功率器件的终端，其中所述沟槽的数量为任意个，沟槽的形状是：倒梯形、U型、v型、方形或阶梯型中任一种。
进一步地，所述功率器件包括PiN二极管、肖特基二极管、结势垒肖特基二极管(JBS)、混合PiN/Schottky二极管(MPS)、MOSFET、电流孔径垂直电子晶体管(CAVET)。
上述有源区和终端结构的制作方法中，所述钝化是通过引入离子来实现的，所述离子包括但不限于氢离子。
上述有源区和终端结构的制作方法中，离子的引入方式包括但不限于：离子注入、等离子体工艺、在含相应元素的气体氛围中经退火、在含相应元素的液体中浸泡。
进一步地，离子的引入是采用相应的等离子体通过反应离子刻蚀、感应耦合等离子体-反应离子刻蚀、等离子体增强原子层沉积、等离子体增强化学气相沉积中任一种或多种工艺引入。
上述有源区和终端结构的制作方法中，功率器件的衬底为氮化镓、碳化硅、硅、蓝宝石、绝缘体上硅(SOI)、氮化铝、金刚石中任一种。
上述有源区和终端结构的制作方法中，功率器件的介质层为二氧化硅、氮化硅、氧化铝、氮化铝、氧化铪、聚合物中任一种或多种介质层组合。
上述有源区和终端结构的制作方法中，在钝化之前对需要钝化的目标半导体区域进行刻蚀或不刻蚀处理。
上述有源区和终端结构的制作方法中，以界面电荷衡量在1×1011～1×1016cm-2，体电荷衡量在1×1015～1×1020cm-3引入离子。
优选的，所述的氢离子或其他具有相似作用的离子，以界面电荷衡量在1×1012～1×1015cm-2，以体电荷衡量在1×1016～1×1019cm-3引入。
更优选的，所述的氢离子或其他具有相似作用的离子，以界面电荷衡量在1×1013～1×1015cm-2，以体电荷衡量在1×1017～1×1019cm-3引入。
上述有源区和终端结构的制作方法中，钝化区域，深度在0.1～3μm。
上述终端结构的制作方法中，包含多个钝化区域，多个区域深度相同或不同，多个区域浓度相同或不同，多个区域间距相同或不同。
本发明的有益效果为：通过引入适用于III-V族氮化物体系的氢离子或其他具有相似作用的离子，降低P区导电率，可以得到结势垒肖特基二极管的有源区结构，以及基于结的终端结构。工艺相对可行简单，结势垒肖特基二极管可以有效保证较低的正向导通电压和较高的反向击穿电压，终端结构则可以简单有效地提高器件的阻断水平。
具体的，对于采用这种方法的结势垒肖特基二极管，正向导通时，引入氢离子或其他具有相似作用的离子得到的肖特基接触部分将在较低电压下导通，电压继续升高后，PN结部分也将导通。因此在正向情况下，这种结的结构可以保证较低的导通电压并承受较大的电流。反向时，PN结部分将会承受大部分电压，如果比例设置合适，PN结可以扩展并相连，形成阻断区，提高了反向耐压。对于采用这种方法的终端结构，引入氢离子或其他具有相似作用的离子降低P区导电率，进而形成结终端扩展、场限环等基于结的终端结构，有效减少边缘电场聚集，提高器件耐压。
附图说明
图1是本发明的一种实施结构示意图，在P型外延层中，使用氢离子或其他具有相似作用的离子注入技术制作结。得到氮化镓器件的结势垒肖特基结构。
图2是本发明的一种实施结构示意图，在P型外延层中，使用氢离子或其他具有相似作用的离子注入技术制作结。与图1相比，离子注入的深度更大。
图3是本发明的一种实施结构示意图，在P型外延层中，使用氢离子或其他具有相似作用的离子注入技术制作结。与图1相比，离子注入区的宽度改变，改变宽度比例可以调整结势垒肖特基二极管器件的反向耐压特性。
图4是本发明的一种实施结构示意图，按照不同的浓度梯度引入氢离子或其他具有相似作用的离子，得到结终端扩展的终端结构。
图5是本发明的一种实施结构示意图，对于GaN器件通过氢离子钝化原P区，并结合Si注入等方法制成N沟道区域，进而制成GaN材料的VDMOSFET。
图6为本发明的一种实施结构示意图，使用引入氢离子钝化P区，钝化后的P区可通过或不通过额外注入Si进一步降低P区导电率，制成结势垒肖特基二极管。
图7是通过仿真得到的PN结与离子注入区宽度比为1：1的结势垒肖特基二极管结构的PN结边缘的电场场强曲线，供本发明的结构优化和电场分布对比。
图8是通过仿真得到的PN结与离子注入区宽度比为1：1的结势垒肖特基二极管结构的电场分布图。
图9是通过仿真得到的PN结与离子注入区宽度比为1：1的结势垒肖特基二极管结构的PN结边缘的电场分布图。
图10为结势垒肖特基二极管和传统肖特基二极管的正向导通电流电压关系曲线对比，其趋势可用作设计及优化的参考。
图11为结势垒肖特基二极管和传统肖特基二极管的反向电场强度随反向电压关系曲线对比，其趋势可用作设计及优化的参考。
具体实施方式
下面结合附图及具体实施例对本发明作进一步详细说明。
本发明通过引入适用于III-V族氮化物体系的氢离子或其他具有相似作用的离子，构建钝化区域，降低P区导电率，可以得到结势垒肖特基二极管的有源区结构，以及基于结的终端结构。
所引入的氢离子或其他具有相似作用的离子可以通过多种来源应用多种工艺引入器件终端。以氢离子为例，来源可以是含氢等离子体；来源可以是含氢的气体；来源可以是含氢的液体；可以通过任何其他含氢的氛围引入。工艺可以是反应离子刻蚀(RIE)、感应耦合等离子体-反应离子刻蚀(ICP-RIE)、等离子体增强原子层沉积(PEALD)、等离子体增强化学气相沉积法(PECVD)等包含等离子体的工艺；工艺可以是在相应的气体氛围中经退火或其他工艺而引入的；工艺可以是在相应的液体环境中经浸泡或其他工艺而引入的；可以引入氢离子的工艺均可能成为本发明使用的工艺。
下面结合实施例对本发明进行进一步说明
实施例1
本公开实例提供了一种结势垒肖特基二极管的PN结的结构及其引入氢离子或其他具有相似作用的离子的制成方法，如图1所示，包括离子注入区1，P型GaN区域2，阳极3，N型GaN漂移区4，N型GaN衬底5，阴极6。
在实施实例中，所述P区和引入离子的区域厚度为0.5μm，漂移区厚度为9.5μm，PN结宽度为3μm，肖特基接触区宽度为3μm。
在实施实例中，离子注入区1中，界面电荷衡量在1×1011～1×1016cm-2，体电荷衡量在1×1015～1×1020cm-3。所述的P区有效掺杂浓度为1×1018～5×1018cm-3，氢离子引入区(N区)的掺杂浓度为1×1015～5×1017cm-3。
在实施实例中，正向导通时，引入离子的肖特基接触区首先导通，保证了较低的导通电压，电压进一步升高之后，PN结接触区也相继导通。
在实施实例中，在承受反向高压时，PN结部分将承担较大压降，耗尽区将会向肖特基接触区域扩展，当两区宽度比例恰当(如PN结区域与肖特基接触区宽度比为5：1时)，肖特基接触区将被夹断，从而形成对电场屏蔽，耐受高电压。
作为优选的方案，离子注入区1还通过或不通过额外注入离子(硅粒子)形成目标浓度的N型区域，且钝化后的区域将与金属电极(阳极3)形成肖特基接触。
在实施实例中，由此制成的结势垒肖特基二极管，反向击穿电压在1700V左右，正向导通压降在1V左右。
如图7所示为PN结边缘的电场强度曲线，如图8所示为结势垒肖特基二极管的电场分布图，如图9所示为PN主结下沿横向切向所得附近的电场分布图。上述数值仿真结果可用于对引入氢离子制成的结势垒肖特基二极管的耐压进行优化。
如图10所示为传统肖特基二极管和结势垒肖特基二极管的正向导通电流电压关系曲线对比，如图11所示为传统肖特基二极管和结势垒肖特基二极管的反向电场强度随反向电压关系曲线对比。上述数值仿真结果可较好地说明引入氢离子制成的结势垒肖特基二极管其导通电压与传统肖特基二极管相接近，而反向耐压远好于传统肖特基二极管的特点。
实施例2：
本发明实例提供了一种氮化镓肖特基二极管的终端结构及引入氢离子或其他具有相似作用的离子的制成方法，如图4，P型GaN区域2和7，阳极3，N型GaN漂移区4，N型GaN衬底5，阴极6。
在实施实例中，所述结终端区域由在P型GaN区域中的部分区域7引入氢离子或其他具有相似作用的离子制作而成。
在实施实例中，所述PN结区域由外延生长的N型漂移区和P区形成，不引入氢离子。
在实施实例中，区域7中，界面电荷衡量在1×1011～1×1016cm-2，体电荷衡量在1×1015～1×1020cm-3。低掺杂N区的掺杂浓度约为8×1015cm-3，P区的有效掺杂浓度为1×1018cm-3，结终端的掺杂浓度为5×1015～1×1018cm-3。
具体的，所述的终端结构，或者单独使用，或者结合场板、结终端扩展等其他终端结构。
具体的，所述的终端结构，适用于PIN二极管，肖特基二极管，结势垒肖特基器件(JBS)，MOSFET，电流孔径垂直电子晶体管(CAVET)等所有垂直型氮化镓器件。
在实施实例中，所述的终端区域与PN结区域起到耐压保护的作用。在承受反向高压时，所述的结终端区使得阳极边缘的电场尖峰减小，结终端外侧区域的电场增大，电势线向外推移，起到保护结边缘的作用。
实施例3：
本实例提供了一种通过引入氢离子制成氮化镓材料VDMOSFET的方法，如图5，包括氢离子注入区(N沟道)1，P型GaN区域(基区)2，N型GaN漂移区4，N型GaN衬底5，漏极8，栅极9，门极电介质10，源极11，N+GaN区域12。
在实施实例中，所述N沟道区可由引入氢离子或其他具有相似作用的离子的方法制成。
在实施实例中，通过外延生长得到低掺杂N型漂移层，P型外延层与高掺杂N型外延层。
在实施实例中，离子注入区(N沟道)1中，界面电荷衡量在1×1011～1×1016cm-2，体电荷衡量在1×1015～1×1020cm-3。离子引入区(N区)的掺杂浓度为5×1015～5×1017cm-3，N+区的掺杂浓度约为3×1018cm-3，P基区的有效掺杂浓度约为5×1016cm-3，漂移区的掺杂浓度约为8×1015cm-3。
在实施实例中，由离子注入生成的氮化镓材料MOSFET在正向导通时，P基区被夹断，形成电流通路，在反向关断时，N沟道区被夹断，PN结承担电压降。
以上所述，为本发明内容的较佳实施例，并非对本发明内容做任何限制，凡根据本发明内容技术实质对以上实施例所作的任何简单修改、变更以及等效结构变化，均属于本发明内容技术方案的保护范围内。
Claims (15)
1.一种III-V族氮化物功率器件的有源区制作方法，其特征在于，该方法包括对有源区的P型掺杂区中的部分区域进行钝化。
2.根据权利要求1所述的制作方法，其特征在于，钝化后的区域通过或不通过额外注入离子形成目标浓度的N型区域，且钝化后的区域将与金属电极形成肖特基接触。
3.根据权利要求1所述的制作方法，其特征在于，所述功率器件包括结势垒肖特基二极管(JBS)、混合PiN/Schottky二极管(MPS)。
4.一种III-V族氮化物功率器件的终端结构制作方法，所述功率器件中包含有源区，且所述有源区外围具有P型掺杂区，其特征在于，该方法包括：对有源区外围的P型掺杂区进行局部钝化，获得所述终端结构。
5.根据权利要求4所述的方法，其特征在于，所述的终端结构包括结终端扩展、场限环等终端结构。
6.根据权利要求4所述的方法，其特征在于，终端结构与功率器件的电极、有源区中的任意一个重叠，不重叠或边缘对齐；其深度与主结深度相同，或者不同。
7.根据权利要求4所述的方法，其特征在于，终端结构单独作为功率器件的终端，或者，与场板或沟槽结构共同构成功率器件的终端，其中所述沟槽的数量为任意个，沟槽的形状是：倒梯形、U型、V型、方形或阶梯型中任一种。
8.根据权利要求4所述的制作方法，其特征在于，所述功率器件包括PiN二极管、肖特基二极管、结势垒肖特基二极管(JBS)、混合PiN/Schottky二极管(MPS)、MOSFET、电流孔径垂直电子晶体管(CAVET)。
9.根据权利要求1～8任一项所述的制作方法，其特征在于，所述钝化是通过引入离子来实现的，所述离子包括但不限于氢离子。
10.根据权利要求1～8所述的制作方法，其特征在于，离子的引入方式包括但不限于：离子注入、等离子体工艺、在含相应元素的气体氛围中经退火、在含相应元素的液体中浸泡。
11.根据权利要求10所述的制作方法，其特征在于，离子的引入是采用相应的等离子体通过反应离子刻蚀、感应耦合等离子体-反应离子刻蚀、等离子体增强原子层沉积、等离子体增强化学气相沉积中任一种或多种工艺引入。
12.根据权利要求1～8所述的制作方法，其特征在于，功率器件的衬底为氮化镓、碳化硅、硅、蓝宝石、绝缘体上硅(SOI)、氮化铝、金刚石中任一种。
13.根据权利要求1～8所述的制作方法，其特征在于，功率器件的介质层为二氧化硅、氮化硅、氧化铝、氮化铝、氧化铪、聚合物中任一种或多种介质层组合。
14.根据权利要求1～8所述的制作方法，其特征在于，在钝化之前对需要钝化的目标半导体区域进行刻蚀或不刻蚀处理。
15.根据权利要求1～8所述的制作方法，其特征在于，钝化后的区域中，界面电荷衡量在1×1011～1×1016cm-2，体电荷衡量在1×1015～1×1020cm-3。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811202453.7A CN109599431A (zh) | 2018-10-16 | 2018-10-16 | 一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811202453.7A CN109599431A (zh) | 2018-10-16 | 2018-10-16 | 一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109599431A true CN109599431A (zh) | 2019-04-09 |
Family
ID=65956995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811202453.7A Pending CN109599431A (zh) | 2018-10-16 | 2018-10-16 | 一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109599431A (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112186031A (zh) * | 2020-09-25 | 2021-01-05 | 浙江大学杭州国际科创中心 | 一种等离子体的处理方法及其应用 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104094417A (zh) * | 2011-12-22 | 2014-10-08 | 阿沃吉有限公司 | 利用注入制造氮化镓p-i-n二极管的方法 |
| US20150048421A1 (en) * | 2013-08-14 | 2015-02-19 | Samsung Electronics Co., Ltd. | High electron mobility transistors, methods of manufacturing the same, and electronic devices including the same |
| CN106920833A (zh) * | 2015-12-25 | 2017-07-04 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
| CN109285774A (zh) * | 2018-09-12 | 2019-01-29 | 江苏能华微电子科技发展有限公司 | 一种基于氮化镓的结势垒肖特基二极管及其形成方法 |
-
2018
- 2018-10-16 CN CN201811202453.7A patent/CN109599431A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104094417A (zh) * | 2011-12-22 | 2014-10-08 | 阿沃吉有限公司 | 利用注入制造氮化镓p-i-n二极管的方法 |
| US20150048421A1 (en) * | 2013-08-14 | 2015-02-19 | Samsung Electronics Co., Ltd. | High electron mobility transistors, methods of manufacturing the same, and electronic devices including the same |
| CN106920833A (zh) * | 2015-12-25 | 2017-07-04 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
| CN109285774A (zh) * | 2018-09-12 | 2019-01-29 | 江苏能华微电子科技发展有限公司 | 一种基于氮化镓的结势垒肖特基二极管及其形成方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112186031A (zh) * | 2020-09-25 | 2021-01-05 | 浙江大学杭州国际科创中心 | 一种等离子体的处理方法及其应用 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105793991B (zh) | 半导体装置 | |
| US8912623B2 (en) | Fast recovery diode | |
| CN103413824B (zh) | 一种rc-ligbt器件及其制作方法 | |
| US20180166530A1 (en) | Power semiconductor devices having gate trenches and buried edge terminations and related methods | |
| CN104779278B (zh) | 双极半导体器件及其制造方法 | |
| JP7215898B2 (ja) | ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 | |
| CN108538717A (zh) | 在GaN材料中制造浮置保护环的方法及系统 | |
| CN102403357A (zh) | 半导体装置及其制造方法 | |
| WO2020149354A1 (ja) | 半導体装置および半導体装置の製造方法 | |
| CN103985746B (zh) | 沟槽型igbt器件及其制造方法 | |
| KR20160012879A (ko) | 반도체 장치 | |
| CN107731898A (zh) | 一种cstbt器件及其制造方法 | |
| CN107104135A (zh) | 垂直型iii‑v族氮化物功率器件终端结构及制作方法 | |
| CN106129110B (zh) | 一种双通道rc-igbt器件及其制备方法 | |
| CN109841676A (zh) | 辅助掺杂实现常关型GaN HEMT器件及其制备方法 | |
| CN111048580A (zh) | 一种碳化硅绝缘栅双极晶体管及其制作方法 | |
| CN106067481B (zh) | 一种双通道rc-igbt器件及其制备方法 | |
| CN105845718B (zh) | 一种4H-SiC沟槽型绝缘栅双极型晶体管 | |
| CN106158631A (zh) | 带埋层沟槽功率器件及其制作方法 | |
| CN110137267A (zh) | 一种垂直型氮化镓肖特基二极管器件及其制备方法 | |
| CN109599431A (zh) | 一种用于iii-v族氮化物功率器件有源区与终端结构的制作方法 | |
| CN104253152A (zh) | 一种igbt及其制造方法 | |
| CN104517837B (zh) | 一种绝缘栅双极型晶体管的制造方法 | |
| CN112366227A (zh) | 一种绝缘栅双极晶体管及其制备方法 | |
| Wang et al. | Comprehensive design and numerical study of GaN vertical MPS diodes towards alleviated electric field crowding and efficient carrier injection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190409 |
|
| RJ01 | Rejection of invention patent application after publication |