CN109586892A - A kind of fractional order memristor chaos circuit - Google Patents
A kind of fractional order memristor chaos circuit Download PDFInfo
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- CN109586892A CN109586892A CN201710904219.8A CN201710904219A CN109586892A CN 109586892 A CN109586892 A CN 109586892A CN 201710904219 A CN201710904219 A CN 201710904219A CN 109586892 A CN109586892 A CN 109586892A
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- 239000003990 capacitor Substances 0.000 claims abstract description 107
- 230000036581 peripheral resistance Effects 0.000 claims abstract description 4
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 230000000739 chaotic effect Effects 0.000 abstract description 4
- 238000013486 operation strategy Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 2
- -1 C1=1nF Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
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Abstract
The invention discloses a kind of fractional order memristor chaos circuits, it is made of capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, high-speed switch K1 and its peripheral resistance, can produce complicated chaotic dynamics behavior by adjusting resistance R.Circuit of the present invention is free of inductance, is easy to hardware realization, has widened the operation strategies of fractional order memristor chaos circuit, enriches fractional order memristor chaos circuit library.
Description
Technical field
The invention patent relates to field of electronic circuitry, more particularly to a kind of fractional order memristor chaos circuit.
Background technique
Chaos system is with a wide range of applications in scientific domains such as bioengineering, mechanics, physics and information.Compared to
Integer rank chaos system, chaotic systems with fractional order can more accurately reflect practical nonlinear system characteristic, therefore in recent years, score
Rank chaos system becomes the hot spot of research.Memristor is the 4th kind of element after resistance capacitor and inductor, has non-linear spy
Property, being employed for chaotic systems with fractional order can produce more abundant chaotic dynamics behavior, at present fractional order memristor chaos
Circuit number is rare, and circuit is complex, includes inductance, is unfavorable for integrating.
Summary of the invention
To solve the problems in the background art, the invention proposes a kind of fractional order memristor chaos circuits, by capacitor
C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0,
Amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, high speed
Switch K1 and its peripheral resistance composition；
Wherein, the normal phase input end of amplifier U0 is connected with the normal phase input end of amplifier U5；The inverting input terminal of amplifier U0
It is connected with amplifier U0 output end；The output end of amplifier U0 is connected by resistance Rf7 with the inverting input terminal of amplifier U2；
Resistance Rf9 is connected between the inverting input terminal of amplifier U2 and the output end of amplifier U2；Capacitor Cf1 is connected to amplification
Between the normal phase input end of device U2 and the output end of amplifier U2；The normal phase input end of amplifier U2 is grounded by resistance Rf1；
The normal phase input end of amplifier U3 is connect with the inverting input terminal of amplifier U4；The inverting input terminal connection-of amplifier U3
The DC voltage source of 1V；The DC voltage source of the normal phase input end connection 1V of amplifier U4；The output end of amplifier U3 passes through two
Pole pipe D1 is connected with the port IN1 of high-speed switch K1；The output end of amplifier U4 passes through the IN1 of diode D2 and high-speed switch K1
Port is connected；The cathode of diode D2 is grounded by resistance Rf8；
The port D1 of high-speed switch K1 is grounded by resistance Rf10；The port GND of high-speed switch K1 is grounded；The S1 of high-speed switch K1
Port is connected with the normal phase input end of amplifier U6；
Resistance Rf6 is connected between the normal phase input end of amplifier U6 and amplifier U6 output end；Resistance Rf5 is connected to amplifier
Between the inverting input terminal and amplifier U6 output end of U6；The inverting input terminal energization resistance Rf4 of amplifier U6 is connected to the ground；
Resistance Rf3 is connected between the normal phase input end of amplifier U5 and amplifier U5 output end；Resistance Rf2 is connected to amplifier
Between the inverting input terminal and amplifier U5 output end of U5；The port the D1 phase of the inverting input terminal of amplifier U5 and high-speed switch
Even；
The normal phase input end of amplifier U0 is connected with one end of resistance R；
One end after capacitor C1 is in parallel with resistance R1 is connected with one end of resistance R；One end after capacitor C2 is in parallel with resistance R2 with
The other end after capacitor C1 is in parallel with resistance R1 is connected；One end and capacitor C2 and resistance R2 after capacitor C3 is in parallel with resistance R3 are simultaneously
The other end after connection is connected；Other end ground connection after capacitor C3 is in parallel with resistance R3；
One end after the other end of resistance R is in parallel with resistance R7 with capacitor C7 is connected；One end after capacitor C8 is in parallel with resistance R8
The other end after in parallel with resistance R7 with capacitor C7 is connected；One end and capacitor C8 and resistance R8 after capacitor C9 is in parallel with resistance R9
The other end after parallel connection is connected；Other end ground connection after capacitor C9 is in parallel with resistance R9；
One end after the other end of resistance R is in parallel with resistance R6 with capacitor C6 is connected；One end after capacitor C5 is in parallel with resistance R5
The other end after in parallel with resistance R6 with capacitor C6 is connected；One end and capacitor C5 and resistance R5 after capacitor C4 is in parallel with resistance R4
The other end after parallel connection is connected；The other end after capacitor C4 is in parallel with resistance R4 is connected by R10 with the output end of amplifier U1；
Resistance R13 is connected between the inverting input terminal of amplifier U1 and the output end of amplifier U1；The reverse phase of amplifier U1 is defeated
Enter end to be connected to the ground by resistance R11；The just opposite input terminal of amplifier U1 is grounded by resistance R12；The positive of amplifier U1
Input terminal is connected with the other end of resistance R.
The method have the benefit that: circuit of the present invention is free of inductance, is easy to hardware realization, has widened fractional order and recalled
The operation strategies for hindering chaos circuit, enrich fractional order memristor chaos circuit library.
Detailed description of the invention
A kind of fractional order memristor chaos circuit figure of Fig. 1.
Fig. 2 Vc1-Vc6Phasor.
Specific embodiment
The following further describes the specific embodiments of the present invention with reference to the drawings.
As shown in Figure 1, the present invention is by capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, electricity
Hold C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, put
Big device U6, diode D1, diode D2, high-speed switch K1 and its peripheral resistance composition；
Wherein, the normal phase input end of amplifier U0 is connected with the normal phase input end of amplifier U5；The inverting input terminal of amplifier U0
It is connected with amplifier U0 output end；The output end of amplifier U0 is connected by resistance Rf7 with the inverting input terminal of amplifier U2；
Resistance Rf9 is connected between the inverting input terminal of amplifier U2 and the output end of amplifier U2；Capacitor Cf1 is connected to amplification
Between the normal phase input end of device U2 and the output end of amplifier U2；The normal phase input end of amplifier U2 is grounded by resistance Rf1；
The normal phase input end of amplifier U3 is connect with the inverting input terminal of amplifier U4；The inverting input terminal connection-of amplifier U3
The DC voltage source of 1V；The DC voltage source of the normal phase input end connection 1V of amplifier U4；The output end of amplifier U3 passes through two
Pole pipe D1 is connected with the port IN1 of high-speed switch K1；The output end of amplifier U4 passes through the IN1 of diode D2 and high-speed switch K1
Port is connected；The cathode of diode D2 is grounded by resistance Rf8；
The port D1 of high-speed switch K1 is grounded by resistance Rf10；The port GND of high-speed switch K1 is grounded；The S1 of high-speed switch K1
Port is connected with the normal phase input end of amplifier U6；
Resistance Rf6 is connected between the normal phase input end of amplifier U6 and amplifier U6 output end；Resistance Rf5 is connected to amplifier
Between the inverting input terminal and amplifier U6 output end of U6；The inverting input terminal energization resistance Rf4 of amplifier U6 is connected to the ground；
Resistance Rf3 is connected between the normal phase input end of amplifier U5 and amplifier U5 output end；Resistance Rf2 is connected to amplifier
Between the inverting input terminal and amplifier U5 output end of U5；The port the D1 phase of the inverting input terminal of amplifier U5 and high-speed switch
Even；
The normal phase input end of amplifier U0 is connected with one end of resistance R；
One end after capacitor C1 is in parallel with resistance R1 is connected with one end of resistance R；One end after capacitor C2 is in parallel with resistance R2 with
The other end after capacitor C1 is in parallel with resistance R1 is connected；One end and capacitor C2 and resistance R2 after capacitor C3 is in parallel with resistance R3 are simultaneously
The other end after connection is connected；Other end ground connection after capacitor C3 is in parallel with resistance R3；
One end after the other end of resistance R is in parallel with resistance R7 with capacitor C7 is connected；One end after capacitor C8 is in parallel with resistance R8
The other end after in parallel with resistance R7 with capacitor C7 is connected；One end and capacitor C8 and resistance R8 after capacitor C9 is in parallel with resistance R9
The other end after parallel connection is connected；Other end ground connection after capacitor C9 is in parallel with resistance R9；
One end after the other end of resistance R is in parallel with resistance R6 with capacitor C6 is connected；One end after capacitor C5 is in parallel with resistance R5
The other end after in parallel with resistance R6 with capacitor C6 is connected；One end and capacitor C5 and resistance R5 after capacitor C4 is in parallel with resistance R4
The other end after parallel connection is connected；The other end after capacitor C4 is in parallel with resistance R4 is connected by R10 with the output end of amplifier U1；
Resistance R13 is connected between the inverting input terminal of amplifier U1 and the output end of amplifier U1；The reverse phase of amplifier U1 is defeated
Enter end to be connected to the ground by resistance R11；The just opposite input terminal of amplifier U1 is grounded by resistance R12；The positive of amplifier U1
Input terminal is connected with the other end of resistance R.
In the present embodiment, amplifier U0, amplifier U1, amplifier U2, amplifier U3, the amplifier U4, amplifier of selection
U5, amplifier U6 are AD711, and the supply voltage of amplifier is positive and negative 12V；
Resistance Rf1=10k Ω, resistance Rf2=100k Ω, resistance Rf3=100k Ω, resistance Rf4=2.5k Ω, the Ω of resistance Rf5=220,
The Ω of resistance Rf6=220, the Ω of resistance Rf7=220, resistance Rf8=4k Ω, resistance Rf9=48k Ω, resistance Rf10=1.47k Ω, resistance
R1=1.2k Ω, resistance R2=100k Ω, resistance R3=1.2M Ω, resistance R4=1.5k Ω, resistance R5=220k Ω, resistance R6=2M
Ω, resistance R7=1k Ω, resistance R8=135k Ω, resistance R9=0.9M Ω, resistance R10=2k Ω, resistance R11=10k Ω, resistance R12
=6kΩ；
Capacitor Cf1=1nF capacitor, C1=1nF, capacitor C2=47nF, capacitor C3=1.2uF, capacitor C4=5nF, capacitor C5=470nF,
Capacitor C6=1.7uF, capacitor C7=1.5nF, capacitor C8=500nF, capacitor C9=10uF;
Diode D1 and diode D2 selects 1N4148.
Fig. 2 shows Vc1-Vc6Phasor, it can be seen that a kind of fractional order memristor chaos circuit disclosed by the invention will produce
Raw complicated dynamic behavior.
What has been described above is only a preferred embodiment of the present invention, and present invention is not limited to the above embodiments.It is appreciated that this
The other improvements and change that field technical staff directly exports or associates without departing from the spirit and concept in the present invention
Change, is considered as being included within protection scope of the present invention.
Claims (1)
1. a kind of fractional order memristor chaos circuit, which is characterized in that by capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5,
Capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, amplifier U2, amplifier U3, amplification
Device U4, amplifier U5, amplifier U6, diode D1, diode D2, high-speed switch K1 and its peripheral resistance composition；
Wherein, the normal phase input end of amplifier U0 is connected with the normal phase input end of amplifier U5；The inverting input terminal of amplifier U0
It is connected with amplifier U0 output end；The output end of amplifier U0 is connected by resistance Rf7 with the inverting input terminal of amplifier U2；
Resistance Rf9 is connected between the inverting input terminal of amplifier U2 and the output end of amplifier U2；Capacitor Cf1 is connected to amplification
Between the normal phase input end of device U2 and the output end of amplifier U2；The normal phase input end of amplifier U2 is grounded by resistance Rf1；
The normal phase input end of amplifier U3 is connect with the inverting input terminal of amplifier U4；The inverting input terminal connection-of amplifier U3
The DC voltage source of 1V；The DC voltage source of the normal phase input end connection 1V of amplifier U4；The output end of amplifier U3 passes through two
Pole pipe D1 is connected with the port IN1 of high-speed switch K1；The output end of amplifier U4 passes through the IN1 of diode D2 and high-speed switch K1
Port is connected；The cathode of diode D2 is grounded by resistance Rf8；
The port D1 of high-speed switch K1 is grounded by resistance Rf10；The port GND of high-speed switch K1 is grounded；The S1 of high-speed switch K1
Port is connected with the normal phase input end of amplifier U6；
Resistance Rf6 is connected between the normal phase input end of amplifier U6 and amplifier U6 output end；Resistance Rf5 is connected to amplifier
Between the inverting input terminal and amplifier U6 output end of U6；The inverting input terminal energization resistance Rf4 of amplifier U6 is connected to the ground；
Resistance Rf3 is connected between the normal phase input end of amplifier U5 and amplifier U5 output end；Resistance Rf2 is connected to amplifier
Between the inverting input terminal and amplifier U5 output end of U5；The port the D1 phase of the inverting input terminal of amplifier U5 and high-speed switch
Even；
The normal phase input end of amplifier U0 is connected with one end of resistance R；
One end after capacitor C1 is in parallel with resistance R1 is connected with one end of resistance R；One end after capacitor C2 is in parallel with resistance R2 with
The other end after capacitor C1 is in parallel with resistance R1 is connected；One end and capacitor C2 and resistance R2 after capacitor C3 is in parallel with resistance R3 are simultaneously
The other end after connection is connected；Other end ground connection after capacitor C3 is in parallel with resistance R3；
One end after the other end of resistance R is in parallel with resistance R7 with capacitor C7 is connected；One end after capacitor C8 is in parallel with resistance R8
The other end after in parallel with resistance R7 with capacitor C7 is connected；One end and capacitor C8 and resistance R8 after capacitor C9 is in parallel with resistance R9
The other end after parallel connection is connected；Other end ground connection after capacitor C9 is in parallel with resistance R9；
One end after the other end of resistance R is in parallel with resistance R6 with capacitor C6 is connected；One end after capacitor C5 is in parallel with resistance R5
The other end after in parallel with resistance R6 with capacitor C6 is connected；One end and capacitor C5 and resistance R5 after capacitor C4 is in parallel with resistance R4
The other end after parallel connection is connected；The other end after capacitor C4 is in parallel with resistance R4 is connected by R10 with the output end of amplifier U1；
Resistance R13 is connected between the inverting input terminal of amplifier U1 and the output end of amplifier U1；The reverse phase of amplifier U1 is defeated
Enter end to be connected to the ground by resistance R11；The just opposite input terminal of amplifier U1 is grounded by resistance R12；The positive of amplifier U1
Input terminal is connected with the other end of resistance R.
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| CN201710904219.8A CN109586892A (en) | 2017-09-29 | 2017-09-29 | A kind of fractional order memristor chaos circuit |
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| CN201710904219.8A CN109586892A (en) | 2017-09-29 | 2017-09-29 | A kind of fractional order memristor chaos circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110209111A (en) * | 2019-06-10 | 2019-09-06 | 华北电力大学（保定） | Adjustable fractional order passive inductor based on field programmable gate array |
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| CN110209111A (en) * | 2019-06-10 | 2019-09-06 | 华北电力大学（保定） | Adjustable fractional order passive inductor based on field programmable gate array |
| CN110209111B (en) * | 2019-06-10 | 2022-05-13 | 华北电力大学（保定） | Adjustable fractional order passive inductor based on field programmable gate array |
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