CN109586892A - A kind of fractional order memristor chaos circuit - Google Patents

A kind of fractional order memristor chaos circuit Download PDF

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CN109586892A
CN109586892A CN201710904219.8A CN201710904219A CN109586892A CN 109586892 A CN109586892 A CN 109586892A CN 201710904219 A CN201710904219 A CN 201710904219A CN 109586892 A CN109586892 A CN 109586892A
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capacitor
resistance
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王波
邹富成
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Xihua University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices

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Abstract

本发明公布了一种分数阶忆阻混沌电路，由电容C1、电容C2、电容C3、电容C4、电容C5、电容C6、电容C7、电容C8、电容C9、电容Cf1、放大器U0、放大器U1、放大器U2、放大器U3、放大器U4、放大器U5、放大器U6、二极管D1、二极管D2、高速开关K1以及其外围电阻组成，通过调节电阻R可以产生复杂的混沌动力学行为。本发明电路不含电感，易于硬件实现，拓宽了分数阶忆阻混沌电路的运用范围，丰富了分数阶忆阻混沌电路库。

The invention discloses a fractional-order memristive chaotic circuit, which consists of capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, The amplifier U2, the amplifier U3, the amplifier U4, the amplifier U5, the amplifier U6, the diode D1, the diode D2, the high-speed switch K1 and its peripheral resistance are composed. By adjusting the resistance R, the complex chaotic dynamic behavior can be generated. The circuit of the invention does not contain inductance, is easy to implement in hardware, widens the application range of the fractional-order memristive chaotic circuit, and enriches the fractional-order memristive chaotic circuit library.

Description

A kind of fractional order memristor chaos circuit
Technical field
The invention patent relates to field of electronic circuitry, more particularly to a kind of fractional order memristor chaos circuit.
Background technique
Chaos system is with a wide range of applications in scientific domains such as bioengineering, mechanics, physics and information.Compared to Integer rank chaos system, chaotic systems with fractional order can more accurately reflect practical nonlinear system characteristic, therefore in recent years, score Rank chaos system becomes the hot spot of research.Memristor is the 4th kind of element after resistance capacitor and inductor, has non-linear spy Property, being employed for chaotic systems with fractional order can produce more abundant chaotic dynamics behavior, at present fractional order memristor chaos Circuit number is rare, and circuit is complex, includes inductance, is unfavorable for integrating.
Summary of the invention
To solve the problems in the background art, the invention proposes a kind of fractional order memristor chaos circuits, by capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0, Amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, high speed Switch K1 and its peripheral resistance composition；
Wherein, the normal phase input end of amplifier U0 is connected with the normal phase input end of amplifier U5；The inverting input terminal of amplifier U0 It is connected with amplifier U0 output end；The output end of amplifier U0 is connected by resistance Rf7 with the inverting input terminal of amplifier U2；
Resistance Rf9 is connected between the inverting input terminal of amplifier U2 and the output end of amplifier U2；Capacitor Cf1 is connected to amplification Between the normal phase input end of device U2 and the output end of amplifier U2；The normal phase input end of amplifier U2 is grounded by resistance Rf1；
The normal phase input end of amplifier U3 is connect with the inverting input terminal of amplifier U4；The inverting input terminal connection-of amplifier U3 The DC voltage source of 1V；The DC voltage source of the normal phase input end connection 1V of amplifier U4；The output end of amplifier U3 passes through two Pole pipe D1 is connected with the port IN1 of high-speed switch K1；The output end of amplifier U4 passes through the IN1 of diode D2 and high-speed switch K1 Port is connected；The cathode of diode D2 is grounded by resistance Rf8；
The port D1 of high-speed switch K1 is grounded by resistance Rf10；The port GND of high-speed switch K1 is grounded；The S1 of high-speed switch K1 Port is connected with the normal phase input end of amplifier U6；
Resistance Rf6 is connected between the normal phase input end of amplifier U6 and amplifier U6 output end；Resistance Rf5 is connected to amplifier Between the inverting input terminal and amplifier U6 output end of U6；The inverting input terminal energization resistance Rf4 of amplifier U6 is connected to the ground；
Resistance Rf3 is connected between the normal phase input end of amplifier U5 and amplifier U5 output end；Resistance Rf2 is connected to amplifier Between the inverting input terminal and amplifier U5 output end of U5；The port the D1 phase of the inverting input terminal of amplifier U5 and high-speed switch Even；
The normal phase input end of amplifier U0 is connected with one end of resistance R；
One end after capacitor C1 is in parallel with resistance R1 is connected with one end of resistance R；One end after capacitor C2 is in parallel with resistance R2 with The other end after capacitor C1 is in parallel with resistance R1 is connected；One end and capacitor C2 and resistance R2 after capacitor C3 is in parallel with resistance R3 are simultaneously The other end after connection is connected；Other end ground connection after capacitor C3 is in parallel with resistance R3；
One end after the other end of resistance R is in parallel with resistance R7 with capacitor C7 is connected；One end after capacitor C8 is in parallel with resistance R8 The other end after in parallel with resistance R7 with capacitor C7 is connected；One end and capacitor C8 and resistance R8 after capacitor C9 is in parallel with resistance R9 The other end after parallel connection is connected；Other end ground connection after capacitor C9 is in parallel with resistance R9；
One end after the other end of resistance R is in parallel with resistance R6 with capacitor C6 is connected；One end after capacitor C5 is in parallel with resistance R5 The other end after in parallel with resistance R6 with capacitor C6 is connected；One end and capacitor C5 and resistance R5 after capacitor C4 is in parallel with resistance R4 The other end after parallel connection is connected；The other end after capacitor C4 is in parallel with resistance R4 is connected by R10 with the output end of amplifier U1；
Resistance R13 is connected between the inverting input terminal of amplifier U1 and the output end of amplifier U1；The reverse phase of amplifier U1 is defeated Enter end to be connected to the ground by resistance R11；The just opposite input terminal of amplifier U1 is grounded by resistance R12；The positive of amplifier U1 Input terminal is connected with the other end of resistance R.
The method have the benefit that: circuit of the present invention is free of inductance, is easy to hardware realization, has widened fractional order and recalled The operation strategies for hindering chaos circuit, enrich fractional order memristor chaos circuit library.
Detailed description of the invention
A kind of fractional order memristor chaos circuit figure of Fig. 1.
Fig. 2 Vc1-Vc6Phasor.
Specific embodiment
The following further describes the specific embodiments of the present invention with reference to the drawings.
As shown in Figure 1, the present invention is by capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, electricity Hold C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, put Big device U6, diode D1, diode D2, high-speed switch K1 and its peripheral resistance composition；
Wherein, the normal phase input end of amplifier U0 is connected with the normal phase input end of amplifier U5；The inverting input terminal of amplifier U0 It is connected with amplifier U0 output end；The output end of amplifier U0 is connected by resistance Rf7 with the inverting input terminal of amplifier U2；
Resistance Rf9 is connected between the inverting input terminal of amplifier U2 and the output end of amplifier U2；Capacitor Cf1 is connected to amplification Between the normal phase input end of device U2 and the output end of amplifier U2；The normal phase input end of amplifier U2 is grounded by resistance Rf1；
The normal phase input end of amplifier U3 is connect with the inverting input terminal of amplifier U4；The inverting input terminal connection-of amplifier U3 The DC voltage source of 1V；The DC voltage source of the normal phase input end connection 1V of amplifier U4；The output end of amplifier U3 passes through two Pole pipe D1 is connected with the port IN1 of high-speed switch K1；The output end of amplifier U4 passes through the IN1 of diode D2 and high-speed switch K1 Port is connected；The cathode of diode D2 is grounded by resistance Rf8；
The port D1 of high-speed switch K1 is grounded by resistance Rf10；The port GND of high-speed switch K1 is grounded；The S1 of high-speed switch K1 Port is connected with the normal phase input end of amplifier U6；
Resistance Rf6 is connected between the normal phase input end of amplifier U6 and amplifier U6 output end；Resistance Rf5 is connected to amplifier Between the inverting input terminal and amplifier U6 output end of U6；The inverting input terminal energization resistance Rf4 of amplifier U6 is connected to the ground；
Resistance Rf3 is connected between the normal phase input end of amplifier U5 and amplifier U5 output end；Resistance Rf2 is connected to amplifier Between the inverting input terminal and amplifier U5 output end of U5；The port the D1 phase of the inverting input terminal of amplifier U5 and high-speed switch Even；
The normal phase input end of amplifier U0 is connected with one end of resistance R；
One end after capacitor C1 is in parallel with resistance R1 is connected with one end of resistance R；One end after capacitor C2 is in parallel with resistance R2 with The other end after capacitor C1 is in parallel with resistance R1 is connected；One end and capacitor C2 and resistance R2 after capacitor C3 is in parallel with resistance R3 are simultaneously The other end after connection is connected；Other end ground connection after capacitor C3 is in parallel with resistance R3；
One end after the other end of resistance R is in parallel with resistance R7 with capacitor C7 is connected；One end after capacitor C8 is in parallel with resistance R8 The other end after in parallel with resistance R7 with capacitor C7 is connected；One end and capacitor C8 and resistance R8 after capacitor C9 is in parallel with resistance R9 The other end after parallel connection is connected；Other end ground connection after capacitor C9 is in parallel with resistance R9；
One end after the other end of resistance R is in parallel with resistance R6 with capacitor C6 is connected；One end after capacitor C5 is in parallel with resistance R5 The other end after in parallel with resistance R6 with capacitor C6 is connected；One end and capacitor C5 and resistance R5 after capacitor C4 is in parallel with resistance R4 The other end after parallel connection is connected；The other end after capacitor C4 is in parallel with resistance R4 is connected by R10 with the output end of amplifier U1；
Resistance R13 is connected between the inverting input terminal of amplifier U1 and the output end of amplifier U1；The reverse phase of amplifier U1 is defeated Enter end to be connected to the ground by resistance R11；The just opposite input terminal of amplifier U1 is grounded by resistance R12；The positive of amplifier U1 Input terminal is connected with the other end of resistance R.
In the present embodiment, amplifier U0, amplifier U1, amplifier U2, amplifier U3, the amplifier U4, amplifier of selection U5, amplifier U6 are AD711, and the supply voltage of amplifier is positive and negative 12V；
Resistance Rf1=10k Ω, resistance Rf2=100k Ω, resistance Rf3=100k Ω, resistance Rf4=2.5k Ω, the Ω of resistance Rf5=220, The Ω of resistance Rf6=220, the Ω of resistance Rf7=220, resistance Rf8=4k Ω, resistance Rf9=48k Ω, resistance Rf10=1.47k Ω, resistance R1=1.2k Ω, resistance R2=100k Ω, resistance R3=1.2M Ω, resistance R4=1.5k Ω, resistance R5=220k Ω, resistance R6=2M Ω, resistance R7=1k Ω, resistance R8=135k Ω, resistance R9=0.9M Ω, resistance R10=2k Ω, resistance R11=10k Ω, resistance R12 =6kΩ；
Capacitor Cf1=1nF capacitor, C1=1nF, capacitor C2=47nF, capacitor C3=1.2uF, capacitor C4=5nF, capacitor C5=470nF, Capacitor C6=1.7uF, capacitor C7=1.5nF, capacitor C8=500nF, capacitor C9=10uF;
Diode D1 and diode D2 selects 1N4148.
Fig. 2 shows Vc1-Vc6Phasor, it can be seen that a kind of fractional order memristor chaos circuit disclosed by the invention will produce Raw complicated dynamic behavior.
What has been described above is only a preferred embodiment of the present invention, and present invention is not limited to the above embodiments.It is appreciated that this The other improvements and change that field technical staff directly exports or associates without departing from the spirit and concept in the present invention Change, is considered as being included within protection scope of the present invention.

Claims (1)

1.一种分数阶忆阻混沌电路，其特征在于，由电容C1、电容C2、电容C3、电容C4、电容C5、电容C6、电容C7、电容C8、电容C9、电容Cf1、放大器U0、放大器U1、放大器U2、放大器U3、放大器U4、放大器U5、放大器U6、二极管D1、二极管D2、高速开关K1以及其外围电阻组成；1. a fractional-order memristive chaotic circuit is characterized in that, by capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor Cf1, amplifier U0, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, high-speed switch K1 and its peripheral resistance; 其中，放大器U0的正相输入端与放大器U5的正相输入端相连；放大器U0的反相输入端与放大器U0输出端相连；放大器U0的输出端经过电阻Rf7与放大器U2的反相输入端相连；Among them, the non-inverting input terminal of amplifier U0 is connected to the non-inverting input terminal of amplifier U5; the inverting input terminal of amplifier U0 is connected to the output terminal of amplifier U0; the output terminal of amplifier U0 is connected to the inverting input terminal of amplifier U2 through resistor Rf7 ; 电阻Rf9连接于放大器U2的反相输入端与放大器U2的输出端之间；电容Cf1连接于放大器U2的正相输入端与放大器U2的输出端之间；放大器U2的正相输入端通过电阻Rf1接地；The resistor Rf9 is connected between the inverting input end of the amplifier U2 and the output end of the amplifier U2; the capacitor Cf1 is connected between the non-inverting input end of the amplifier U2 and the output end of the amplifier U2; the non-inverting input end of the amplifier U2 passes through the resistor Rf1 ground; 放大器U3的正相输入端与放大器U4的反相输入端连接；放大器U3的反相输入端连接-1V的直流电压源；放大器U4的正相输入端连接1V的直流电压源；放大器U3的输出端通过二极管D1与高速开关K1的IN1端口相连；放大器U4的输出端通过二极管D2与高速开关K1的IN1端口相连；二极管D2的阴极通过电阻Rf8接地；The non-inverting input terminal of amplifier U3 is connected to the inverting input terminal of amplifier U4; the inverting input terminal of amplifier U3 is connected to a DC voltage source of -1V; the non-inverting input terminal of amplifier U4 is connected to a DC voltage source of 1V; the output of amplifier U3 The terminal is connected to the IN1 port of the high-speed switch K1 through the diode D1; the output end of the amplifier U4 is connected to the IN1 port of the high-speed switch K1 through the diode D2; the cathode of the diode D2 is grounded through the resistor Rf8; 高速开关K1的D1端口通过电阻Rf10接地；高速开关K1的GND端口接地；高速开关K1的S1端口与放大器U6的正相输入端相连；The D1 port of the high-speed switch K1 is grounded through the resistor Rf10; the GND port of the high-speed switch K1 is grounded; the S1 port of the high-speed switch K1 is connected to the non-inverting input terminal of the amplifier U6; 电阻Rf6连接于放大器U6的正相输入端与放大器U6输出端之间；电阻Rf5连接于放大器U6的反相输入端与放大器U6输出端之间；放大器U6的反相输入端通电阻Rf4与地相连；The resistor Rf6 is connected between the non-inverting input end of the amplifier U6 and the output end of the amplifier U6; the resistor Rf5 is connected between the inverting input end of the amplifier U6 and the output end of the amplifier U6; the inverting input end of the amplifier U6 is connected to the ground through the resistor Rf4 connected; 电阻Rf3连接于放大器U5的正相输入端与放大器U5输出端之间；电阻Rf2连接于放大器U5的反相输入端与放大器U5输出端之间；放大器U5的反相输入端与高速开关的D1端口相连；The resistor Rf3 is connected between the non-inverting input terminal of the amplifier U5 and the output terminal of the amplifier U5; the resistor Rf2 is connected between the inverting input terminal of the amplifier U5 and the output terminal of the amplifier U5; the inverting input terminal of the amplifier U5 and the D1 of the high-speed switch port is connected; 放大器U0的正相输入端与电阻R的一端相连；The non-inverting input terminal of the amplifier U0 is connected to one end of the resistor R; 电容C1与电阻R1并联后的一端与电阻R的一端相连；电容C2与电阻R2并联后的一端与电容C1与电阻R1并联后的另一端相连；电容C3与电阻R3并联后的一端与电容C2与电阻R2并联后的另一端相连；电容C3与电阻R3并联后的另一端接地；One end of capacitor C1 and resistor R1 in parallel is connected to one end of resistor R; one end of capacitor C2 and resistor R2 is connected in parallel to the other end of capacitor C1 and resistor R1 in parallel; one end of capacitor C3 and resistor R3 is connected in parallel to capacitor C2 Connected to the other end of the resistor R2 in parallel; the other end of the capacitor C3 connected to the resistor R3 in parallel is grounded; 电阻R的另一端与电容C7与电阻R7并联后的一端相连；电容C8与电阻R8并联后的一端与电容C7与电阻R7并联后的另一端相连；电容C9与电阻R9并联后的一端与电容C8与电阻R8并联后的另一端相连；电容C9与电阻R9并联后的另一端接地；The other end of the resistor R is connected to the one end of the capacitor C7 and the resistor R7 in parallel; the one end of the capacitor C8 and the resistor R8 in parallel is connected to the other end of the capacitor C7 and the resistor R7 in parallel; the one end of the capacitor C9 and the resistor R9 in parallel is connected to the capacitor C8 is connected to the other end of the resistor R8 in parallel; the other end of the capacitor C9 and the resistor R9 is connected to the ground; 电阻R的另一端与电容C6与电阻R6并联后的一端相连；电容C5与电阻R5并联后的一端与电容C6与电阻R6并联后的另一端相连；电容C4与电阻R4并联后的一端与电容C5与电阻R5并联后的另一端相连；电容C4与电阻R4并联后的另一端通过R10与放大器U1的输出端相连；The other end of the resistor R is connected to the one end of the capacitor C6 and the resistor R6 in parallel; the one end of the capacitor C5 and the resistor R5 in parallel is connected to the other end of the capacitor C6 and the resistor R6 in parallel; the one end of the capacitor C4 and the resistor R4 in parallel is connected to the capacitor C5 is connected to the other end of the resistor R5 in parallel; the other end of the capacitor C4 is connected to the output of the amplifier U1 through R10; 电阻R13连接于放大器U1的反相输入端和放大器U1的输出端之间；放大器U1的反相输入端通过电阻R11与地相连；放大器U1的正相向输入端通过电阻R12接地；放大器U1的正相输入端与电阻R的另一端相连。The resistor R13 is connected between the inverting input terminal of the amplifier U1 and the output terminal of the amplifier U1; the inverting input terminal of the amplifier U1 is connected to the ground through the resistor R11; the non-inverting input terminal of the amplifier U1 is grounded through the resistor R12; The phase input is connected to the other end of the resistor R.
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Publication number Priority date Publication date Assignee Title
CN110209111A (en) * 2019-06-10 2019-09-06 华北电力大学（保定） A Adjustable Fractional-Order Passive Inductor Based on Field Programmable Gate Array
CN110209111B (en) * 2019-06-10 2022-05-13 华北电力大学（保定） Adjustable fractional order passive inductor based on field programmable gate array

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Application publication date: 20190405