CN207166505U - A kind of time-lag chaos circuit - Google Patents
A kind of time-lag chaos circuit Download PDFInfo
- Publication number
- CN207166505U CN207166505U CN201721264949.8U CN201721264949U CN207166505U CN 207166505 U CN207166505 U CN 207166505U CN 201721264949 U CN201721264949 U CN 201721264949U CN 207166505 U CN207166505 U CN 207166505U
- Authority
- CN
- China
- Prior art keywords
- inductance
- amplifier
- electric capacity
- resistance
- normal phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Microwave Amplifiers (AREA)
Abstract
The utility model discloses a kind of time-lag chaos circuit, including amplifier UW1, amplifier UW2, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, speed-sensitive switch K1, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity CW1, electric capacity CW2, electric capacity CW3, electric capacity Cf1, inductance L, inductance L1, inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6, inductance L7, inductance L8, inductance L9, inductance L10, inductance L11, inductance L12 and its peripheral resistance；The utility model discloses a kind of time-lag chaos circuit, time lag and chaos circuit interaction, the dynamic behavior of complexity is generated, there is physical realizability.
Description
Technical field
The utility model patent is related to field of electronic circuitry, more particularly to a kind of time-lag chaos circuit.
Background technology
Time delay is found to be present among numerous systems such as physics, biological and chemical；The dynamic characteristic of time lag system
It is not only relevant with current state, but also influenceed by past state；Finite dimension time lag system, Differential Delay Equation can be passed through
Mathematics is described.Although the research on time-delayed chaotic system has been carried out, be limited to theory greatly, presently, there are when
Stagnant chaos circuit negligible amounts.
Utility model content
The problem of being related to for background technology, the utility model discloses a kind of time-lag chaos circuit, it is characterised in that：Bag
Include amplifier UW1, amplifier UW2, amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, two
Pole pipe D1, diode D2, speed-sensitive switch K1, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity CW1、
Electric capacity CW2, electric capacity CW3, electric capacity Cf1, inductance L, inductance L1, inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6,
Inductance L7, inductance L8, inductance L9, inductance L10, inductance L11, inductance L12 and its peripheral resistance.
Wherein, inductance L one end is grounded, another termination capacitor CW3Positive terminal；Electric capacity CW3Negative pole end pass through resistance RW1Connect
Ground；Electric capacity CW3Negative pole end passes through electric capacity CW2Ground connection；Electric capacity CW3Negative pole end pass through resistance R and electric capacity CW1Positive terminal be connected；Electricity
Hold CW1Negative pole end ground connection；
Electric capacity CW3Negative pole end be connected by resistance R with amplifier U1 normal phase input end；Amplifier U1 positive input
End is connected with amplifier U5 normal phase input end；Amplifier U1 inverting input is connected with amplifier U1 output ends；Amplifier
U1 output end is connected by resistance Rf7 with amplifier U2 inverting input；
Resistance Rf9 is connected between amplifier U2 inverting input and amplifier U2 output end；Electric capacity Cf1 is connected to
Between amplifier U2 normal phase input end and amplifier U2 output end；Amplifier U2 normal phase input end is connect by resistance Rf1
Ground；
Amplifier U3 normal phase input end is connected with amplifier U4 inverting input；Amplifier U3 inverting input connects
Connect -1V direct voltage source；Amplifier U4 normal phase input end connection 1V direct voltage source；Amplifier U3 output end passes through
Diode D1 is connected with speed-sensitive switch K1 IN1 ports；Amplifier U4 output end passes through diode D2's and speed-sensitive switch K1
IN1 ports are connected；Diode D2 negative electrode is grounded by resistance Rf8；
Speed-sensitive switch K1 D1 ports are grounded by resistance Rf10；Speed-sensitive switch K1 GND ports ground connection；Speed-sensitive switch K1
S1 ports be connected with amplifier U6 normal phase input end；
Resistance Rf6 is connected between amplifier U6 normal phase input end and amplifier U6 output ends；Resistance Rf5, which is connected to, to be put
Between big device U6 inverting input and amplifier U6 output ends；Amplifier U6 inverting input energization resistance Rf4 is connected to the ground；
Resistance Rf3 is connected between amplifier U5 normal phase input end and amplifier U5 output ends；Resistance Rf2, which is connected to, to be put
Between big device U5 inverting input and amplifier U5 output ends；Amplifier U5 inverting input and the D1 ports of speed-sensitive switch
It is connected；
Electric capacity CW3Negative pole end pass through resistance R1With amplifier UW1Inverting input be connected；Resistance R1It is connected to amplifier
UW1Inverting input and output end between；Amplifier UW1Output end be connected by resistance R3 with inductance L1 one end；Amplification
Device UW1Output end be connected by electric capacity C1 with the inductance L1 other end；Amplifier U1 output end passes through electric capacity C1 and inductance L2
One end be connected；
The inductance L2 other end is grounded by electric capacity C2；The inductance L2 other end is connected with inductance L3 one end；Inductance L3
The other end be connected with inductance L4 one end；
The inductance L4 other end is grounded by electric capacity C3；The inductance L4 other end is connected with inductance L5 one end；Inductance L5
The other end be connected with inductance L6 one end；
The inductance L6 other end is grounded by electric capacity C4；The inductance L6 other end is connected with inductance L7 one end；Inductance L7
The other end be connected with inductance L8 one end；
The inductance L8 other end is grounded by electric capacity C5；The inductance L8 other end is connected with inductance L9 one end；Inductance L9
The other end be connected with inductance L10 one end；
The inductance L10 other end is grounded by electric capacity C6；The inductance L10 other end is connected with inductance L11 one end；Inductance
The L11 other end is connected with inductance L12 one end；
The inductance L11 other end passes through resistance R5 and amplifier UW2End of oppisite phase be connected；The inductance L12 other end passes through electricity
Hinder R6 ground connection；Resistance R4 is connected to amplifier UW2End of oppisite phase and output end between；
Amplifier UW2Output end be connected with amplifier U1 normal phase input end；
Advantageous effects of the present utility model are：The utility model discloses a kind of time-lag chaos circuit, time lag and mixed
Ignorant circuit interaction, generates the dynamic behavior of complexity, has physical realizability.
Brief description of the drawings
A kind of time-lag chaos circuit diagrams of Fig. 1.
Fig. 2 VcW1-VcW2Phasor.
Embodiment
The embodiment of the utility model circuit is described further below in conjunction with the accompanying drawings.
As shown in figure 1, the utility model discloses a kind of time-lag chaos circuit, including amplifier UW1, amplifier UW2, put
Big device U1, amplifier U2, amplifier U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, open at a high speed
Close K1, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity CW1, electric capacity CW2, electric capacity CW3, electric capacity Cf1、
Inductance L, inductance L1, inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6, inductance L7, inductance L8, inductance L9,
Inductance L10, inductance L11, inductance L12 and its peripheral resistance.
Wherein, inductance L one end is grounded, another termination capacitor CW3Positive terminal；Electric capacity CW3Negative pole end pass through resistance RW1Connect
Ground；Electric capacity CW3Negative pole end passes through electric capacity CW2Ground connection；Electric capacity CW3Negative pole end pass through resistance R and electric capacity CW1Positive terminal be connected；Electricity
Hold CW1Negative pole end ground connection；
Electric capacity CW3Negative pole end be connected by resistance R with amplifier U1 normal phase input end；Amplifier U1 positive input
End is connected with amplifier U5 normal phase input end；Amplifier U1 inverting input is connected with amplifier U1 output ends；Amplifier
U1 output end is connected by resistance Rf7 with amplifier U2 inverting input；
Resistance Rf9 is connected between amplifier U2 inverting input and amplifier U2 output end；Electric capacity Cf1 is connected to
Between amplifier U2 normal phase input end and amplifier U2 output end；Amplifier U2 normal phase input end is connect by resistance Rf1
Ground；
Amplifier U3 normal phase input end is connected with amplifier U4 inverting input；Amplifier U3 inverting input connects
Connect -1V direct voltage source；Amplifier U4 normal phase input end connection 1V direct voltage source；Amplifier U3 output end passes through
Diode D1 is connected with speed-sensitive switch K1 IN1 ports；Amplifier U4 output end passes through diode D2's and speed-sensitive switch K1
IN1 ports are connected；Diode D2 negative electrode is grounded by resistance Rf8；
Speed-sensitive switch K1 D1 ports are grounded by resistance Rf10；Speed-sensitive switch K1 GND ports ground connection；Speed-sensitive switch K1
S1 ports be connected with amplifier U6 normal phase input end；
Resistance Rf6 is connected between amplifier U6 normal phase input end and amplifier U6 output ends；Resistance Rf5, which is connected to, to be put
Between big device U6 inverting input and amplifier U6 output ends；Amplifier U6 inverting input energization resistance Rf4 is connected to the ground；
Resistance Rf3 is connected between amplifier U5 normal phase input end and amplifier U5 output ends；Resistance Rf2, which is connected to, to be put
Between big device U5 inverting input and amplifier U5 output ends；Amplifier U5 inverting input and the D1 ports of speed-sensitive switch
It is connected；
Electric capacity CW3Negative pole end pass through resistance R1With amplifier UW1Inverting input be connected；Resistance R1It is connected to amplifier
UW1Inverting input and output end between；Amplifier UW1Output end be connected by resistance R3 with inductance L1 one end；Amplification
Device UW1Output end be connected by electric capacity C1 with the inductance L1 other end；Amplifier U1 output end passes through electric capacity C1 and inductance L2
One end be connected；
The inductance L2 other end is grounded by electric capacity C2；The inductance L2 other end is connected with inductance L3 one end；Inductance L3
The other end be connected with inductance L4 one end；
The inductance L4 other end is grounded by electric capacity C3；The inductance L4 other end is connected with inductance L5 one end；Inductance L5
The other end be connected with inductance L6 one end；
The inductance L6 other end is grounded by electric capacity C4；The inductance L6 other end is connected with inductance L7 one end；Inductance L7
The other end be connected with inductance L8 one end；
The inductance L8 other end is grounded by electric capacity C5；The inductance L8 other end is connected with inductance L9 one end；Inductance L9
The other end be connected with inductance L10 one end；
The inductance L10 other end is grounded by electric capacity C6；The inductance L10 other end is connected with inductance L11 one end；Inductance
The L11 other end is connected with inductance L12 one end；
The inductance L11 other end passes through resistance R5 and amplifier UW2End of oppisite phase be connected；The inductance L12 other end passes through electricity
Hinder R6 ground connection；Resistance R4 is connected to amplifier UW2End of oppisite phase and output end between；
Amplifier UW2Output end be connected with amplifier U1 normal phase input end；
In the present embodiment,
Selection electric capacity C1=1nF, electric capacity C2=1nF, electric capacity C3=1nF, electric capacity C4=1nF, electric capacity C5=1nF, electric capacity C6=
1nF;Electric capacity Cf1=1nF, electric capacity CW1=1nF, electric capacity CW2=100nF, electric capacity CW3=100nF；
Amplifier UW1With amplifier UW2From LM324；Amplifier U1, amplifier U2, amplifier U3, amplifier U4, amplification
Device U5, amplifier U6 select AD711, and the supply voltage of amplifier is positive and negative 12V；
K Ω of k Ω of k Ω of k Ω of resistance R=1.2k Ω, resistance R1=1, resistance R2=10, resistance R3=1, resistance R4=22, electricity
Hinder the k Ω of k Ω of k Ω of k Ω of R5=1, resistance R6=10, resistance Rf1=10 k Ω, resistance Rf2=100, resistance Rf3=100, resistance
The Ω of the Ω of Rf4=2.5k Ω, resistance Rf5=220, resistance Rf6=220, resistance Rf7=220 Ω, resistance Rf8=4k Ω, resistance Rf9=
48k Ω, resistance Rf10=1.47k Ω；
Inductance L=68mH, inductance L1=1mH, inductance L2=1mH, inductance L3=1mH, inductance L4=1mH, inductance L5=1mH, electricity
Sense L6=1mH, inductance L7=1mH, inductance L8=1mH, inductance L9=1mH, inductance L10=1mH, inductance L11=1mH, inductance L12=
1mH；
Diode D1 and diode D2 selections 1N4148;
Fig. 2 shows VcW1-VcW2Phasor, it can be seen that a kind of time-lag chaos circuit disclosed in the utility model has multiple
Miscellaneous dynamic behavior.
Above-described is only preferred embodiment of the present utility model, and the utility model is not limited to above example.Can
To understand, what those skilled in the art directly exported or associated on the premise of spirit of the present utility model and design is not departed from
Oher improvements and changes, it is considered as being included within the scope of protection of the utility model.
Claims (1)
- A kind of 1. time-lag chaos circuit, it is characterised in that：Including amplifier UW1, amplifier UW2, amplifier U1, amplifier U2, put Big device U3, amplifier U4, amplifier U5, amplifier U6, diode D1, diode D2, speed-sensitive switch K1, electric capacity C1, electric capacity C2, Electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity CW1, electric capacity CW2, electric capacity CW3, electric capacity Cf1, inductance L, inductance L1, inductance L2, Inductance L3, inductance L4, inductance L5, inductance L6, inductance L7, inductance L8, inductance L9, inductance L10, inductance L11, inductance L12 and Its peripheral resistance；Wherein, inductance L one end is grounded, another termination capacitor CW3Positive terminal；Electric capacity CW3Negative pole end pass through resistance RW1Ground connection； Electric capacity CW3Negative pole end passes through electric capacity CW2Ground connection；Electric capacity CW3Negative pole end pass through resistance R and electric capacity CW1Positive terminal be connected；Electric capacity CW1Negative pole end ground connection；Electric capacity CW3Negative pole end be connected by resistance R with amplifier U1 normal phase input end；Amplifier U1 normal phase input end with Amplifier U5 normal phase input end is connected；Amplifier U1 inverting input is connected with amplifier U1 output ends；Amplifier U1's Output end is connected by resistance Rf7 with amplifier U2 inverting input；Resistance Rf9 is connected between amplifier U2 inverting input and amplifier U2 output end；Electric capacity Cf1 is connected to amplification Between device U2 normal phase input end and amplifier U2 output end；Amplifier U2 normal phase input end is grounded by resistance Rf1；Amplifier U3 normal phase input end is connected with amplifier U4 inverting input；Amplifier U3 inverting input connection- 1V direct voltage source；Amplifier U4 normal phase input end connection 1V direct voltage source；Amplifier U3 output end passes through two Pole pipe D1 is connected with speed-sensitive switch K1 IN1 ports；The IN1 that amplifier U4 output end passes through diode D2 and speed-sensitive switch K1 Port is connected；Diode D2 negative electrode is grounded by resistance Rf8；Speed-sensitive switch K1 D1 ports are grounded by resistance Rf10；Speed-sensitive switch K1 GND ports ground connection；Speed-sensitive switch K1 S1 Port is connected with amplifier U6 normal phase input end；Resistance Rf6 is connected between amplifier U6 normal phase input end and amplifier U6 output ends；Resistance Rf5 is connected to amplifier Between U6 inverting input and amplifier U6 output ends；Amplifier U6 inverting input energization resistance Rf4 is connected to the ground；Resistance Rf3 is connected between amplifier U5 normal phase input end and amplifier U5 output ends；Resistance Rf2 is connected to amplifier Between U5 inverting input and amplifier U5 output ends；The D1 ports phase of amplifier U5 inverting input and speed-sensitive switch Even；Electric capacity CW3Negative pole end pass through resistance R1With amplifier UW1Inverting input be connected；Resistance R1It is connected to amplifier UW1's Between inverting input and output end；Amplifier UW1Output end be connected by resistance R3 with inductance L1 one end；Amplifier UW1 Output end be connected by electric capacity C1 with the inductance L1 other end；Amplifier U1 output end passes through the one of electric capacity C1 and inductance L2 End is connected；The inductance L2 other end is grounded by electric capacity C2；The inductance L2 other end is connected with inductance L3 one end；Inductance L3's is another One end is connected with inductance L4 one end；The inductance L4 other end is grounded by electric capacity C3；The inductance L4 other end is connected with inductance L5 one end；Inductance L5's is another One end is connected with inductance L6 one end；The inductance L6 other end is grounded by electric capacity C4；The inductance L6 other end is connected with inductance L7 one end；Inductance L7's is another One end is connected with inductance L8 one end；The inductance L8 other end is grounded by electric capacity C5；The inductance L8 other end is connected with inductance L9 one end；Inductance L9's is another One end is connected with inductance L10 one end；The inductance L10 other end is grounded by electric capacity C6；The inductance L10 other end is connected with inductance L11 one end；Inductance L11 The other end be connected with inductance L12 one end；The inductance L11 other end passes through resistance R5 and amplifier UW2End of oppisite phase be connected；The inductance L12 other end passes through resistance R6 Ground connection；Resistance R4 is connected to amplifier UW2End of oppisite phase and output end between；Amplifier UW2Output end be connected with amplifier U1 normal phase input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721264949.8U CN207166505U (en) | 2017-09-29 | 2017-09-29 | A kind of time-lag chaos circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721264949.8U CN207166505U (en) | 2017-09-29 | 2017-09-29 | A kind of time-lag chaos circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207166505U true CN207166505U (en) | 2018-03-30 |
Family
ID=61724257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721264949.8U Expired - Fee Related CN207166505U (en) | 2017-09-29 | 2017-09-29 | A kind of time-lag chaos circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207166505U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109586891A (en) * | 2017-09-29 | 2019-04-05 | 西华大学 | A kind of time-lag chaos circuit |
-
2017
- 2017-09-29 CN CN201721264949.8U patent/CN207166505U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109586891A (en) * | 2017-09-29 | 2019-04-05 | 西华大学 | A kind of time-lag chaos circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207352398U (en) | General digital input/output multiplexing circuit and input/output control device | |
| CN208479470U (en) | Adjustable voltage output circuit | |
| CN103227614A (en) | Power amplifying apparatus and audio system | |
| CN103401219A (en) | Phase-shifted full-bridge drive signal control circuit and control method thereof | |
| CN207166505U (en) | A kind of time-lag chaos circuit | |
| CN206283237U (en) | A kind of overvoltage crowbar | |
| CN208835727U (en) | Current limiting circuit and current limiting device | |
| CN207677708U (en) | There is source crystal oscillator filter circuit module | |
| CN113900030A (en) | Battery detection system and method with high adaptability | |
| CN107980206A (en) | Multi-channel time-delay control device and control power supply | |
| CN206743149U (en) | Make the high-low double-speed control circuit on the garden instrument of driving power with battery bag | |
| CN209559957U (en) | Steering wheel current detection circuit and system | |
| CN207166504U (en) | A kind of fractional order memristor chaos circuit | |
| CN207150552U (en) | Analog switch circuit | |
| CN207215278U (en) | A kind of rotation formula vibration acquisition system and its rotation formula censor key | |
| CN206164505U (en) | Analog signal modulate circuit of optimizing | |
| CN206075263U (en) | Multiplexing reception device based on single-chip microcomputer GPIO pins | |
| CN109586891A (en) | A kind of time-lag chaos circuit | |
| CN205955847U (en) | Gas engine rotational speed control system | |
| CN204965086U (en) | Be applied to thing networking monitored control system's general extension module | |
| CN209728909U (en) | Control circuit is sold in a kind of water purification based on Internet of Things | |
| CN206611183U (en) | Low-voltage reactive compensator | |
| CN206490664U (en) | Analog quantity modulate circuit | |
| CN206818783U (en) | A kind of three-phase current maximum selecting device | |
| CN203101896U (en) | Anti-failure drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180330 Termination date: 20180929 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |