CN109585552A - 差异层形成工艺和由此形成的结构 - Google Patents

差异层形成工艺和由此形成的结构 Download PDF

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CN109585552A
CN109585552A CN201810521121.9A CN201810521121A CN109585552A CN 109585552 A CN109585552 A CN 109585552A CN 201810521121 A CN201810521121 A CN 201810521121A CN 109585552 A CN109585552 A CN 109585552A
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drain regions
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CN109585552B (zh
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柯忠廷
李志鸿
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本文描述了形成半导体器件中的诸如接触蚀刻停止层(CESL)的差异层的方法以及通过该方法形成的结构。在实施例中，结构包括位于衬底上的有源区，位于有源区上的栅极结构和沿着栅极结构的侧壁的栅极间隔件以及差异蚀刻停止层。差异蚀刻停止层具有沿着栅极间隔件的侧壁的第一部分并且具有位于源极/漏极区的上表面上的第二部分。第一部分的第一厚度在垂直于栅极间隔件的侧壁的方向上，并且第二部分的第二厚度在垂直于源极/漏极区的上表面的方向上。第二厚度大于第一厚度。本发明实施例涉及差异层形成工艺和由此形成的结构。

Description

差异层形成工艺和由此形成的结构
技术领域
本发明实施例涉及差异层形成工艺和由此形成的结构。
背景技术
随着半导体产业已步入到了纳米技术工艺节点以追求更大的器件密度、更卓越的性能以及更低的成本方面，来自制造和设计问题的挑战已经引起诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET器件通常包括具有高高宽比的鳍，并且在鳍中形成沟道和源极/漏极区。利用沟道的增加的表面面积的优势沿着鳍结构的侧壁(例如，包裹)并且在鳍结构的上方形成栅极以产生更快、更可靠和更好地控制的半导体晶体管器件。然而，随着尺寸的减小，出现新的挑战。
发明内容
根据本发明的一些实施例，提供了一种半导体结构，包括：有源区，位于衬底上，所述有源区包括源极/漏极区；栅极结构，位于所述有源区上方，所述源极/漏极区邻近所述栅极结构；栅极间隔件，沿着所述栅极结构的侧壁；以及差异蚀刻停止层，具有沿着所述栅极间隔件的侧壁的第一部分并且具有位于所述源极/漏极区的上表面上方的第二部分，所述第一部分的第一厚度在垂直于所述栅极间隔件的侧壁的方向上，所述第二部分的第二厚度在垂直于所述源极/漏极区的上表面的方向上，所述第二厚度大于所述第一厚度。
根据本发明的另一些实施例，还提供了一种处理半导体的方法，包括：在衬底上的器件结构上方形成差异层，形成所述差异层包括：在第一暴露中，将所述器件结构暴露于一种或多种第一前体；在所述第一暴露之后，使用定向等离子体活化激活所述器件结构上的上表面；和在激活所述器件结构上的上表面之后，在第二暴露中，将所述器件结构暴露于一种或多种第二前体，其中，当将所述器件结构暴露于所述一种或多种第二前体时，与所述器件结构上的未激活表面相比，在所述器件结构上的激活的上表面处发生更多的反应。
根据本发明的又一些实施例，还提供了一种处理半导体的方法，包括：形成差异蚀刻停止层，所述差异蚀刻停止层具有位于源极/漏极区的上表面上的第一部分和沿着栅极间隔件的侧壁的第二部分，所述源极/漏极区位于有源区中，所述栅极间隔件位于所述有源区上方并且邻近所述源极/漏极区，所述第一部分的厚度大于所述第二部分的厚度，形成所述差异蚀刻停止层包括实施定向活化；在所述差异蚀刻停止层上方沉积层间电介质(ILD)；以及穿过所述层间电介质和所述差异蚀刻停止层形成接触所述源极/漏极区的导电部件。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的示例性简化的鳍式场效应晶体管(FinFET)的三维图。
图2A-B，图3A-B，图4A-B，图5A-B，图6A-B，图7A-B，图8A-B，图9A-B，图10A-B，图11A-B，和图12A-B是根据一些实施例的在形成半导体器件的示例性工艺中的中间阶段处的相应的中间结构的截面图。
图13A-B，14A-B，15A-B和图16A-B是根据一些实施例的在形成半导体器件的另一示例性工艺中的中间阶段处的相应的中间结构的截面图。
图17，图18，图19和图20是根据一些实施例的在形成半导体器件中的差异接触蚀刻停止层(CESL)的示例性等离子体增强原子层沉积(PEALD)工艺中的中间阶段处的相应的中间结构的截面图。
图21是根据一些实施例的图17至图20的示例性PEALD工艺的流程图。
图22是根据一些实施例的利用原位等离子体活化的示例性化学气相沉积(CVD)工艺的流程图。
图23是根据一些实施例的半导体器件中的差异CESL的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的元件或部件与另(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文描述了在诸如包括鳍式场效应晶体管(FinFET)的半导体器件中，形成诸如接触蚀刻停止层(CESL)的差异层的方法，以及由此方法形成的结构。通常，实施定向等离子体活化工艺，其允许差异层的一些部分(例如，在具有水平分量的上表面上)以比其他部分(例如，在没有明显水平分量的垂直表面上)更大的速率沉积。因此，差异层的一些部分可以比差异层的其他部分具有更大的厚度。差异层可以允许源极/漏极区的更大的保护和/或除了其他可能的优势之外，可增加用于形成其他组件或部件的工艺窗口。
本文在FinFET上形成CESL的上下文中描述了示例性实施例。本发明的一些方面的实施方式可被用来形成不是蚀刻停止层的层。本发明的一些方面的实施方式可用于其他工艺、其他器件和/或其他层。例如，其他示例性器件可以包括平面FET、水平全环栅(HGAA)FET、垂直全环栅(VGAA)FET和其他器件。本文介绍了示例性方法和结构的一些变化。本领域普通技术人员可以很容易地理解，可以预期在其他实施例的范围内可以进行的其他修改。虽然方法实施例可以按照特定的顺序进行描述，但是各种其他方法实施例可以按任何逻辑顺序执行，并且可以包含比本文描述的步骤更少或更多的步骤。
图1示出了三维图中的简化的FinFET 40的实例。相对于图1没有说明或描述的其他方面可以从下列附图和描述中变得显而易见。图1中的结构可以通过电连接或耦接的方式来操作，例如，电连接或耦接至一个晶体管或多个晶体管，诸如四个晶体管。
FinFET 40位于衬底42上的鳍46a和46b。衬底42包括隔离区44，以及鳍46a和46b各自从相邻隔离区44之间向上突出。栅极电介质48a和48b沿着鳍46a和46b的侧壁并且位于鳍46a和46b的顶面上方，并且栅电极50a和50b分别位于栅极电介质48a和48b上方。源极/漏极区52a-f设置在鳍46a和46b的相应区域中。源极/漏极区52a和52b设置在鳍46a的相对于栅极电介质48a和栅电极50a的相对区域中。源极/漏极区52b和52c设置在鳍46a的相对于栅极电介质48b和栅电极50b的相对区域中。源极/漏极区52d和52e设置在鳍46b的相对于栅极电介质48a和栅电极50a的相对区域中。源极/漏极区52e和52f设置在鳍46b的相对于栅极电介质48b和栅电极50b的相对区域中。
在一些实例中，四个晶体管可以通过以下方式实现:(1)源极/漏极区52a和52b，栅极电介质48a，栅电极50a；(2)源极/漏极区52b和52c，栅极电介质48b，栅电极50b；(3)源极/漏极区52d和52e，栅极电介质48a，栅电极50a；和(4)源极/漏极区52e和52f，栅极电介质48b，栅电极50b。如所示出的，例如，一些源极/漏极区可在不同的晶体管之间共享，并且其他没有被示出共享的源极/漏极区可与没有示出的邻近晶体管共享。在一些实例中，各个源极/漏极区可以连接或耦接在一起，从而使得FinFET被实现为两个功能晶体管。例如，如果相邻的(例如，与相对相反)源极/漏极区52a-f是电连接的，诸如通过外延生长来合并该区域(例如，源极/漏极区52a和52d合并，源极/漏极区52b和52e合并等)，可以实现两个功能晶体管。其他实例中的其他配置可以实现其他数量的功能晶体管。
图1进一步示出了用于后续附图的参考截面。截面A-A位于沿着例如相对的源极/漏极区52a-f之间的鳍46a中的沟道截取的平面中。截面B-B位于垂直于截面A-A，并且穿过鳍46a中的源极/漏极区52a和穿过鳍46b中的源极/漏极区52d的平面中。为了清楚起见，后面的图代表这些参考截面。以“A”标号结尾的以下附图示出了对应于截面A-A的处于各个处理实例的截面图，并且以“B”标号结尾的以下附图示出了对应于截面B-B的处于各个处理实例的截面图。在一些附图中，可以省略其中示出的一些组件或部件的参考标号以避免混淆其他组件或特征；这是为了便于描述附图。
图2A-B至图12A-B是根据一些实施例的在形成半导体器件的示例性工艺中的中间阶段处的相应的中间结构的截面图。图2A-B至图10A-B的方面可应用于本文中描述的先栅极工艺和替换栅极工艺。图11A-B和图12A-B进一步示出了本文所述的先栅极工艺的方面。
图2A和2B示出了半导体衬底70。半导体衬底70可以是或包括块状半导体衬底，绝缘体上半导体(SOI)衬底等，其可以被掺杂(例如，具有p型或n型掺杂剂)或不被掺杂。一般来说，SOI衬底包括在绝缘层上形成的半导体材料层。例如，绝缘层可以是埋氧(BOX)层，氧化硅层等。绝缘层提供在通常是硅或玻璃衬底的衬底上。也可以使用诸如多层或梯度衬底的其他衬底。在一些实施例中，半导体衬底的半导体材料可以包括硅(Si)或锗(Ge)的元素半导体；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟或锑化铟；合金半导体，包括SiGe，GaAsP，AlInAs，AlGaAs，GaInAs，GaInP，或GaInAsP；或者它们的组合。
图3A和3B示出了半导体衬底70中鳍74的形成。在一些实例中，在形成鳍74中使用掩模72(例如，硬掩模)。例如，在半导体衬底70上沉积一个或多个掩模层，然后将一个或多个掩模层图案化成掩模72。在一些实例中，一个或多个掩模层可以包括或可以是氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并可通过化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)或另一种沉积技术沉积。可以采用光刻技术图案化一个或多个掩模层。例如，诸如通过使用旋涂可以在一个或多个掩模层上形成光刻胶，并利用适当的光掩模将光刻胶暴露于光来图案化光刻胶。取决于所使用的光刻胶是正性光刻胶或者负性光刻胶，可以然后去除光刻胶的曝光部分或者未曝光部分。然后，可以诸如通过使用合适的蚀刻工艺，将光刻胶的图案转印到一个或多个掩模层，这形成了掩模72。蚀刻工艺可以包括反应离子蚀刻(RIE)，中性束蚀刻(NBE)，电感耦合等离子体(ICP)蚀刻等或其组合。蚀刻可以是各向异性的。随后，例如，在灰化或湿剥离工艺中去除光刻胶。
使用掩模72，可以蚀刻半导体衬底70，从而在相邻的一对鳍74之间形成沟槽76，并且使得鳍74从半导体衬底70突出。蚀刻工艺可以包括RIE、NBE、ICP蚀刻等，或它们的组合。蚀刻可以是各向异性的。
图4A和4B示出了隔离区78的形成，各个隔离区78形成在相应的沟槽76中。隔离区78可以包括或可以为诸如氧化物(诸如氧化硅)、氮化物等或它们的组合的绝缘材料，并且绝缘材料可以由高密度等离子体CVD(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的CVD基材料沉积和后固化以将其转化为诸如氧化物的另一种材料)等或它们的组合形成。可以使用通过任何可接受的工艺所形成的其他绝缘材料。在图示的实施例中，隔离区78包括由FCVD工艺形成的氧化硅。诸如化学机械抛光(CMP)的平坦化工艺可以去除任何多余的绝缘材料和任何剩余的掩模(例如，用于蚀刻沟槽76和形成鳍74)以形成将共面的绝缘材料的顶面和鳍74的顶面。然后，可以凹进绝缘材料来形成隔离区78。绝缘材料被凹进，从而使得鳍74从相邻的隔离区78之间突出，这可以至少部分地将鳍74限定为半导体衬底70上的有源区。可以使用可接受的蚀刻工艺对绝缘材料进行凹进，诸如对绝缘材料的材料具有选择性的蚀刻工艺。例如，可以使用化学氧化物去除，其中，化学氧化物去除使用蚀刻或应用材料SICONI工具或稀氢氟酸(dHF)。此外，隔离区78的顶面可以具有如图所示的平坦表面、凸面、凹面(如凹陷)或其组合，这可以是蚀刻工艺的结果。
本领域普通技术人员将容易理解，参照图2A-B至图4A-B所描述的工艺仅仅是如何形成鳍74的实例。在其他实施例中，可以在半导体衬底70的顶面上方形成介电层；可以穿过介电层蚀刻沟槽；可以在沟槽中外延生长同质外延结构；并且可以凹进介电层，使得同质外延结构从介电层突出以形成鳍。在其他实施例中，异质外延结构可用于鳍。例如，鳍74可以被凹进(例如，在平坦化隔离区78的绝缘材料之后和在凹进绝缘材料之前)，可以在它们的位置上外延生长与鳍不同的材料。在进一步的实施例中，可以在半导体衬底70的顶面上方形成介电层；可以穿过介电层蚀刻沟槽；可以使用与半导体衬底70的材料不同的材料在沟槽中外延生长异质外延结构；并且可以凹进介电层，使得异质外延结构从介电层突出以形成鳍。在外延生长同质外延或异质外延结构的一些实施例中，可以在生长期间原位掺杂生长的材料，这可以避免鳍的之前注入，但是原位掺杂和注入掺杂可以一起使用。此外，对于与p型器件的材料不同的n型器件而言，外延生长材料可以是有利的。
图5A和5B示出了在鳍74上形成栅极堆叠件。栅极堆叠件位于鳍74上方，并且垂直于鳍74横向延伸。每个栅极堆叠件包括介电层80、栅极层82和掩模84。在先栅极工艺中，栅极堆叠件可以是可操作栅极堆叠件，或者在替换栅极工艺中可以是伪栅极堆叠件。
在先栅极工艺中，介电层80可以是栅极电介质，并且栅极层82可以是栅电极。用于栅极堆叠件的栅极电介质、栅电极和掩模84可以通过依次形成相应的层，和然后将这些层图案化成栅极堆叠件来形成。例如，栅极电介质的层可以包括或为氧化硅、氮化硅、高k介电材料等或它们的多层。高k介电材料的k值可以大于约7.0，可以包括Hf，Al，Zr，La，Mg，Ba，Ti，Pb的金属氧化物或硅酸盐，或者它们的组合。用于栅极电介质的层可以在鳍74上热生长和/或化学生长，或者诸如通过等离子体增强CVD(PECVD)、ALD、分子束沉积(MBD)或另一种沉积技术来共形地沉积。用于栅电极的层可以包括或可以为硅(例如，多晶硅，可以掺杂或未掺杂)、含金属的材料(诸如钛、钨、铝、钌等)，或它们的组合(诸如其硅化物或其多层)。栅电极的层可由CVD、PVD或其他沉积技术沉积。掩模84的层可以包括或可以为由CVD、PVD、ALD或另一种沉积技术沉积的氮化硅、氮氧化硅、碳氮化硅等或它们的组合。例如，然后可以使用如上所述的光刻和一个或多个蚀刻工艺来图案化掩模84、栅电极和栅极电介质的层以形成每个栅极堆叠件的掩模84、栅极层82以及介电层80。
在替换栅极工艺中，介电层80可以是界面电介质，而栅极层82可以是伪栅极。用于栅极堆叠件的界面电介质、伪栅极和掩模84可以通过依次形成相应的层，和然后将这些层图案化成栅极堆叠件来形成。例如，用于界面电介质的层可以包括或为氧化硅、氮化硅等或它们的多层，并且可以在鳍74上热生长和/或化学生长或诸如通过PECVD、ALD或另一沉积技术来共形沉积。用于伪栅极的层可以包括或可以为硅(例如，多晶硅)或由CVD、PVD或另一种沉积技术沉积的另一种材料。用于掩模84的层可以包括或可以为由CVD、PVD、ALD或另一种沉积技术沉积的氮化硅、氧氮化硅、碳氮化硅等或它们的组合。例如，可以使用如上所述的光刻和一个或多个蚀刻工艺来图案化用于掩模84、伪栅极和界面电介质的层以形成用于每个栅极堆叠件的掩模84、栅极层82以及介电层80。
在一些实施例中，在形成栅极堆叠件之后，可以在有源区域内形成轻掺杂漏极(LDD)区(没有具体示出)。例如，可以使用栅极堆叠件作为掩模，将掺杂剂注入到有源区内。例如，示例性掺杂剂可以包括或者可以为用于p型器件的硼和用于n型器件的磷或砷，但是，可以使用其他掺杂剂。LDD区的掺杂剂浓度可以在约1015cm-3到约1017cm-3的范围内。
图6A和6B示出了栅极间隔件86的形成。栅极间隔件86形成为沿着栅极堆叠件的侧壁(例如，介电层80、栅极层82和掩模84的侧壁)和位于鳍74上方。剩余的栅极间隔件86也可以沿着鳍74的侧壁形成，这取决于在隔离区78上方的鳍74的高度。例如，可以通过共形沉积用于栅极间隔件86的一层或多层，并且各向异性蚀刻该一层或多层来形成栅极间隔件86。用于栅极间隔件86的一层或多层可以包括或可以为碳氧化硅、氮化硅、氮氧化硅、碳氮化硅等、它们的多层或它们的组合，并可由CVD、ALD或其他沉积技术沉积。蚀刻工艺可以包括RIE、NBE或其他蚀刻工艺。
图7A和7B示出了形成用于源极/漏极区的凹槽90。如图所示，在栅极堆叠件的相对两侧上的鳍74中形成凹槽90。可以通过蚀刻工艺进行凹进。蚀刻工艺可以是各向同性或各向异性的，或者进一步地，可以相对于半导体衬底70的一个或多个晶面具有选择性。因此，根据实施的蚀刻工艺，凹槽90可以具有各种截面轮廓。蚀刻工艺可以是诸如RIE、NBE等的干蚀刻，或诸如使用四甲基氢氧化铵(TMAH)、氢氧化铵(NH4OH)或其他蚀刻剂的湿蚀刻。
图8A和8B示出了在凹槽90中形成外延源极/漏极区92。外延源极/漏极区92可以包括或者是硅锗(SixGe1-x，其中x可以在约0到1之间)、碳化硅、硅磷、纯或基本上纯的锗、III-V族化合物半导体、II-VI族化合物半导体等。例如，用于形成III-V族化合物半导体的材料包括:InAs，AlAs，GaAs，InP，GaN，InGaAs，InAlAs，GaSb，AlSb，AlP，GaP等。可以诸如通过金属有机CVD(MOCVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)、选择性外延生长(SEG)等或者它们的组合在凹槽中外延生长材料而在凹槽90中形成外延源极/漏极区92。如图8A和8B所示，由于被隔离区78阻挡，外延源极/漏极区92首先在凹槽90中垂直生长，在此期间，外延源极/漏极区92不水平生长。当凹槽90被完全填满后，外延源极/漏极区92同时在垂直和水平方向上生长以形成可以对应于半导体衬底70的晶面的切面。在一些实例中，对于p型器件和n型器件的外延源/漏极区，使用不同的材料。在凹进或外延生长期间的适当的掩蔽可以允许不同的材料在不同的器件中使用。
本领域普通技术人员将容易理解，可以省略图7A-B和图8A-B的凹进和外延生长，并且可以通过使用栅极堆叠件和栅极间隔件86作为掩模，将掺杂剂注入到鳍74中而形成源极/漏极区。在实现外延源极/漏极区92的一些实例中，可以通过诸如外延生长期间的原位掺杂和/或在外延生长之后将掺杂剂注入到外延源极/漏极区92内来掺杂外延源极/漏极区92。例如，示例性掺杂剂可以包括或者可以为用于p型器件的硼和用于n型器件的磷或砷，但是，可以使用其他掺杂剂。外延源极/漏极区92(或其他源极/漏极区)的掺杂剂浓度可以在约1019cm-3到约1021cm-3的范围内。因此，可以通过掺杂(例如，如果合适的话，在外延生长工艺中注入和/或原位掺杂)和/或外延生长(如果合适的话)来描述源极/漏极区，这可以进一步限定有源区，其中，源极/漏极区限定在有源区中。
图9A和9B示出了差异接触蚀刻停止层(CESL)96的形成。通常，蚀刻停止层可以提供一种机制以停止蚀刻工艺，例如，当形成接触件或通孔时。蚀刻停止层可以由与相邻层或组件具有不同的蚀刻选择性的介电材料形成。在外延源极/漏极区92的表面上、栅极间隔件86的侧壁和顶面上、掩模84的顶面上和隔离区78的顶面上形成差异CESL 96。差异CESL 96具有水平部分96h和垂直部分96v。水平部分96h形成在具有相应的水平分量的支撑表面上。如下文中进一步描述的，在形成差异CESL 96期间，可以通过定向等离子体活化来激活具有水平分量的支撑表面。垂直部分96v形成在不具有明显水平分量的支撑表面上(例如，使得这些表面不被定向等离子体活化激活)。水平部分96h的厚度(例如，在垂直于相应的支撑表面的方向上)大于垂直部分96v(例如，在垂直于相应的支撑表面的方向上)的厚度。差异CESL 96可以包括或可以是氮化硅、碳氮化硅、碳氮化物等或它们的组合。可以通过包括诸如等离子体增强ALD(PEALD)、CVD的定向等离子体活化的沉积工艺、或另一种沉积技术的沉积工艺沉积差异CESL 96。在下文中，诸如相对于图17至图23描述示例性沉积工艺和差异CESL 96的额外的细节。
图10A和10B示出了在差异CESL 96上方形成第一层间电介质(ILD)100。第一ILD100可以包括或者可以是二氧化硅、诸如氮氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、有机硅酸盐玻璃(OSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的组合物等或它们的组合的低k介电材料(例如，具有低于二氧化硅的介电常数的材料)。可以通过旋涂、CVD、FCVD、PECVD、PVD或另一沉积技术来沉积层间电介质。
可以在沉积后诸如通过CMP来平坦化第一ILD100。在先栅极工艺中，第一ILD100的顶面可以位于差异CESL 96和栅极堆叠件的上部之上。因此，差异CESL 96的上部可以保留在栅极堆叠件上方。
图11A和11B示出了形成穿过第一ILD100和差异CESL 96至外延源极/漏极区92的开口102以暴露例如外延源极/漏极区92的至少部分。例如，可以使用光刻和一个或多个蚀刻工艺将第一ILD100和差异CESL 96图案化为具有开口102。
图12A和12B示出了在开口102中形成至外延源极/漏极区92的导电部件104。例如，导电部件104可以包括粘附和/或阻挡层和位于粘附和/或阻挡层上的导电材料。在一些实例中，导电部件104可以包括如图所示的位于外延源极/漏极区92上的硅化区106。可以在开口102中并且在第一ILD100上方共形地沉积粘附和/或阻挡层。粘附和/或阻挡层可以是或包括钛、氮化钛、氧化钛、钽、氮化钽、氧化钽等或它们的组合并且可以通过ALD、CVD或其他沉积技术沉积。可以通过使外延源极/漏极区92的上部与粘附和/或阻挡层反应在外延源极/漏极区92的上部上形成硅化区106。可以实施退火来促进外延源极/漏极区92与粘附和/或阻挡层的反应。
导电材料可沉积在粘附和/或阻挡层上并填充开口102。导电材料可以是或可以包括钨、铜、铝、金、银、它们的合金等或它们的组合，并且可以通过CVD、ALD、PVD或其他沉积技术沉积。在沉积导电部件104的材料之后，例如，可以通过使用诸如CMP的平坦化工艺去除多余的材料。平坦化工艺可以从第一ILD100的顶面之上去除导电部件104的多余材料。因此，导电部件104和第一ILD100的顶面可以是共面的。导电部件104可以是或可以称为接触件、插塞等。
图13A-B至图16A-B是根据一些实施例的在形成半导体器件的另一示例性工艺中的中间阶段处的相应的中间结构的截面图。图13A-B至图16A-B示出了如本文中所述的替换栅极工艺的其他方面。首先实施参照图2A-2B至图10A-10B所述的处理。
图13A和13B示出了用替换栅极结构来替换栅极堆叠件。第一ILD100和差异CESL96形成为具有与栅极层82的顶面共面的顶面。可以实施诸如CMP的平坦化工艺以使第一ILD100和差异CESL 96的顶面与栅极层82的顶面平齐。CMP也可以去除位于栅极层82上方的掩模84(并且，在一些情况下，栅极间隔件86的上部)。因此，栅极层82的顶面通过第一ILD100和差异CESL 96暴露。
在通过第一ILD100和差异CESL 96暴露栅极层82的情况下，诸如通过一个或多个蚀刻工艺去除栅极层82和介电层80。可以通过对栅极层82具有选择性的蚀刻工艺去除栅极层82，其中介电层80作为蚀刻停止层，随后，通过对介电层80具有选择性的不同的蚀刻工艺去除介电层80。例如，蚀刻工艺可以是RIE、NBE、湿蚀刻或其他蚀刻工艺。在栅极间隔件86之间的栅极堆叠件被去除的位置形成凹槽，并且通过该凹槽暴露出鳍74的沟道区。
在其中通过去除栅极堆叠件而形成的凹槽中形成替换栅极结构。每个替换栅极结构均包括一个或多个共形层120和栅电极122。一个或多个共形层120包括栅极介电层，并且可以包括一个或多个功函调整层。可以在其中去除了栅极堆叠件的凹槽中(例如，在隔离区78的顶面上、沿着沟道区的鳍74的侧壁和表面上和在栅极间隔件86的侧壁上)以及在第一ILD100、差异CESL 96和栅极间隔件86的顶面上共形沉积栅极介电层。栅极介电层可以是或可以包括氧化硅、氮化硅、高k介电材料、它们的多层或其他介电材料。高k介电材料的k值可以大于约7.0，并且可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或金属硅酸盐或者它们的组合。可由ALD、PECVD、MBD或其他沉积技术沉积栅极介电层。
然后，如果已经实施，则可以在栅极介电层上共形沉积功函调整层。功函调整层可以包括或者可以是钽、氮化钽、钛、氮化钛等或它们的组合，并可由ALD、PECVD、MBD或其他沉积技术沉积。可以按顺序沉积类似于该第一功函调整层的任何额外的功函调整层。
在一个或多个共形层120上形成用于栅电极122的层。用于栅电极122的层可以填充去除了栅极堆叠件的剩余的凹槽。用于栅电极122的层可以是或包括诸如Co、Ru、Al、W、Cu的含金属材料，它们的多层或它们的组合。栅电极122的层可由ALD、PECVD、MBD、PVD或其他沉积技术沉积。
去除在在第一ILD100、差异CESL 96和栅极间隔件86的顶面之上的栅电极122的层和一个或多个共形层120的部分。例如，诸如CMP的平坦化的工艺可以去除位于第一ILD100、差异CESL 96和栅极间隔件86的顶面之上的栅电极122的层和一个或多个共形层120的部分。因此，可以形成如图13A所示的包括栅电极122和一个或多个共形层120的替换栅极结构。
图14A和14B示出了在第一ILD100、替换栅极结构、栅极间隔件86和差异CESL 96上方形成第二ILD130。虽然没有说明，在一些实例中，蚀刻停止层(ESL)可以沉积在第一ILD100等上方，并且第二ILD130可以沉积在ESL上方。如果实施，蚀刻停止层可以包括或可以为氮化硅、碳氮化硅、碳氧化硅、碳氮化物等或它们的组合，并可由CVD、PECVD、ALD或其他沉积技术沉积。第二ILD130可以包括或者可以为二氧化硅、诸如氮氧化硅、PSG、BSG、BPSG、USG、FSG、OSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物或它们的组合等的低k介电材料。可以通过旋涂、CVD、FCVD、PECVD、PVD或另一沉积技术来沉积第二ILD130。
图15A和15B示出了形成穿过第二ILD130、第一ILD100、和差异CESL 96至外延源极/漏极区是92的开口132以暴露例如外延源极/漏极区92的至少一部分。例如，使用光刻和一个或多个蚀刻工艺将第二ILD130、第一ILD100、和差异CESL 96图案化为具有开口132。
图16A和16B示出了在开口132中形成至外延源极/漏极区92的导电部件134。例如，导电部件134可以包括粘附和/或阻挡层和位于粘附和/或阻挡层上的导电材料。在一些实例中，导电部件134可以包括如图所示的位于外延源极/漏极区92上的硅化区136。可以在开口132中并且在第二ILD130上方共形地沉积粘附和/或阻挡层。粘附和/或阻挡层可以是或包括钛、氮化钛、氧化钛、钽、氮化钽、氧化钽等或它们的组合并且可以通过ALD、CVD或其他沉积技术沉积。可以通过使外延源极/漏极区92的上部与粘附和/或阻挡层反应在外延源极/漏极区92的上部上形成硅化区136。可以实施退火来促进外延源极/漏极区92与粘附和/或阻挡层的反应。
导电材料可沉积在粘附和/或阻挡层上并填充开口132。导电材料可以是或可以包括钨、铜、铝、金、银、它们的合金等或它们的组合，并且可以通过CVD、ALD、PVD或其他沉积技术沉积。在沉积导电部件134的材料之后，例如，可以通过使用诸如CMP的平坦化工艺去除多余的材料。平坦化工艺可以从第二ILD130的顶面之上去除导电部件134的多余材料。因此，导电部件134和第二ILD130的顶面可以是共面的。导电部件134可以是或可以称为接触件、插塞等。
图17至图20是是根据一些实施例的在形成半导体器件中的差异CESL的示例性等离子体增强ALD(PEALD)工艺中的中间阶段处的相应的中间结构的截面图。图21是根据一些实施例的图17至图20的示例性PEALD工艺的流程图。虽然在差异CESL的上下文中描述，但是PEALD工艺的实例可以用于形成任意层，诸如非ESL的层。
图17示出了通过以上参考图2A-B至图8A-B描述的处理形成的中间结构的部分。中间结构包括具有鳍74的半导体衬底，位于鳍74中且横向位于栅极间隔件86之间的外延源极/漏极区92以及包括沿着栅极间隔件86的掩模84的栅极堆叠件。
图18示出了通过在PEALD工艺中暴露于第一前体(诸如在图21的操作202中)在中间结构上形成的单层。例如，将图17的中间结构暴露于诸如二氯硅烷SiH2Cl(DCS)的第一前体或另一前体，这取决于要沉积的材料。在示出的实例中，使用DCS前体，并且DCS前体沿着暴露于DCS前体的中间结构的外表面形成SiH3单层。外表面包括掩模84的顶面、栅极间隔件86的顶面和侧壁、外延源极/漏极区92的上表面和隔离区78的顶面(例如，见8B和图9B)。在其他的实例中，可以使用不同的前体，其可以形成不同材料的单层。在暴露于第一前体之后，可以从工具室中清除第一前体，其中，工具室用于将中间结构暴露于第一前体。
图19示出了对该单层实施的定向等离子体活化200，诸如在图21的操作204中。定向的或各向异性的等离子体活化激活了部分单层，以增加与随后的前体的反应。位于中间结构的具有水平分量的相应上表面上的部分单层被定向等离子活化200激活，而位于不具有水平分量的相应表面上的部分单层可以不被定向等离子活化200激活。表面的激活可以随着表面的水平分量的增加而增加。例如，不具有或具有较小水平分量的表面可以不被激活或者很少被激活，而具有更大水平分量的表面可以具有更多的激活。
在图示的实例中，例如，外延源极/漏极区92的上表面具有切面，从而使得外延源极/漏极区92的上表面具有水平分量和垂直分量，如图8B所示。位于外延源极/漏极区92的上表面上的单层被定向等离子体活化200激活。由如图所示，栅极间隔件86的侧壁是垂直的，没有明显的水平分量，因此，没有被定向等离子体活化200激活。
如图19所示，氩(Ar)定向等离子体激活位于中间结构的具有水平分量的上表面上的部分单层以将这些部分中的SiH3修改成激活的SiH2*。在一些实例中，实施为用于激活单层的等离子体工艺可以是微波远程等离子体，但是也可以实施诸如定向等离子体的其他等离子体源。用于等离子体的氩(Ar)气体的流速可以在大约1000sccm到约9000sccm之间的范围内。等离子体工艺的压力可以在从约0.5托到约50托之间的范围内。等离子体工艺的温度可以在范围从约200℃到约650℃的范围内。等离子体工艺的等离子体发生器的功率可以在从约50W到约4000W之间的范围内。等离子发生器的频率可以在从约13.56MHz到约2.45GHz之间范围内。等离子体工艺的衬底保持器可以是无偏置的。将中间结构暴露于等离子体工艺的时间范围在从0.1秒到120秒的范围内。在其他的实例中，诸如不同的等离子体工艺、条件和/或气体(如惰性气体、氮气等)的不同等离子体可以用来激活部分单层。通过利用定向等离子体活化200激活部分单层，可以在单层的激活部分上创建更多的反应位点以在PEALD工艺中与随后的前体反应。可以在用于将中间结构暴露于第一前体和随后第二前体的相同的工具室中原位实施定向等离子体活化200。
图20示出了通过将中间结构暴露于PEALD工艺中的第二前体而在中间结构上形成的层，诸如在图21的操作204中。例如，将图19所示的中间结构暴露于诸如氨(NH3)等离子体的第二前体或另一前体，这取决于要沉积的材料。相比于单层的未被激活的部分，第二前体更多地与单层的激活部分反应。例如，由于通过定向等离子体活化200形成在单层的激活部分上的增加的反应位点，相比于单层的未激活部分和第二前体之间的反应，在单层的激活部分和第二前体之间发生更多的反应。这使得与通常不发生激活的不具有明显水平分量的垂直表面相比，在发生激活的具有水平分量的上表面上以更大的速率沉积差异CESL 96。
在图20所示的实例中，使用氨(NH3)等离子体前体并且氨(NH3)等离子体前体与大部分SiH2*，或者在一些情况下与所有的SiH2*以及一些未激活的SiH3(例如，少于激活的SiH2*)发生反应，从而形成氮化硅(例如，SiNH2)。例如，氨(NH3)等离子体前体气体可以在等离子体工艺中以约50sccm到约1000sccm范围内的流速流动。因此，在示出的实例中，与不具有明显水平分量的垂直表面相比，在具有水平分量的上表面上沉积更多的SiNH2。在其他的实例中，可以使用不同的前体，它可以形成不同的材料层。在暴露于第二前体之后，可以将第二前体从用于将中间结构暴露于第二前体的工具室清除。
图18至图20，以及图21的操作202、204和206示出了PEALD工艺的循环。参考图18至图20描述的处理以及图21的操作202、204和206可以重复任意次数，例如，可以实施任意数目的PEALD工艺的循环，诸如通过图21的流程中的回路所示出的，以获得具有期望厚度的差异CESL96。
在其他实例中，根据一些实施例，利用原位等离子体活化的CVD工艺可以用于形成半导体器件中的差异CESL96。图22是根据一些实施例的利用原位等离子体活化的示例性CVD工艺的流程图。虽然在差异CESL的上下文中描述，但是CVD工艺可以用于形成任意层，诸如非ESL的层。
例如，如在图22的操作222中，可以将图17的中间结构转移到CVD工具的室内，并且在CVD工具的室内提供一种或多种前体(例如，包括至少两种前体的混合物)。通过将结构暴露于室中的一种或多种前体，层可以开始沉积。可以将该结构暴露于一种或多种前体并持续一些时间，该持续时间小于用于沉积具有完成的厚度的层的持续时间。可以从CVD工具的室中清除一种或多种前体。
在清除一种或多种前体之后，如图22的操作224中所示，对位于CVD工具的室中的中间结构实施定向等离子体活化。定向的或各向异性的等离子体活化激活沉积为具有水平分量的部分层的上表面以增加与一种或多种前体(例如，两种或更多种前体)的反应物的反应。具有水平分量的部分层的相应上表面被定向等离子体活化激活，而不具有水平分量的相应的表面可以不被定向等离子体活化激活，类似于图19所描述的。例如，位于外延源极/漏极区92上的部分层的上表面被定向等离子体活化激活，而位于栅极间隔件86的侧壁上的部分层的表面是垂直的且不具有明显的水平分量，并且不被定向等离子体活化激活。通过利用定向等离子体活化激活具有水平分量的上表面，可以在激活的上表面上创建更多的反应位点以与CVD工艺中的一种或多种随后的前体的反应物反应。
在定向等离子体活化后，如在图22的操作226中所示，在CVD工具的室中，提供一种或多种前体(例如，包括至少两种前体的混合物)。可以发生为中间结构的表面提供反应物的气相反应。与未激活的表面相比，激活的上表面提供更多的反应位点以吸附反应物和与反应物反应。这导致与通常不发生活化的不具有明显水平分量的垂直表面相比，差异CESL96以更高的速率沉积在激活发生的具有水平分量的上表面上。
在一些实例中，一种或多种前体可以周期性地从CVD工具的室中清除，并且可以在CVD工具的室中原位实施定向等离子体活化。之后，可以在CVD工具的室中提供一种或多种前体。通过以这种方式重复定向等离子体活化，诸如通过图22中的流程中的回路所示出的，水平表面和垂直表面上的沉积速率可以保持更成比例。实施定向等离子体活化、提供一种或多种前体和清除一种或多种前体的处理可以重复任意次数。
图23示出了使用图18至图20的PEALD工艺、利用原位定向等离子体活化的CVD工艺或另一差异沉积工艺形成的差异CESL 96的各个方面。差异CESL 96包括位于下面的具有水平分量的上表面上的水平部分96h和包括位于不具有明显的水平分量的垂直支撑表面上的垂直部分96v。水平部分96h在与其上形成有相应的水平部分的支撑表面垂直的方向上具有厚度Th。垂直部分96v在与其上形成有相应的垂直部分的支撑表面垂直的方向上具有厚度Tv。水平部分96h的厚度Th大于垂直部分96v的厚度Tv。在一些实例中，水平部分96h的厚度Th至少比垂直部分96v的Tv多2nm。例如，水平部分96h的厚度Th可以是4nm，并且垂直部分96v的厚度Tv可以是2nm。在一些实例中，水平部分96h的厚度Th与垂直部分96v的厚度Tv的比率可以等于或大于2。
第一尺寸D1被示出为介于栅极间隔件86的相对的侧壁表面之间，其中，差异CESL96的相应的垂直部分96v形成在栅极间隔件86的相对的侧壁表面上。第二尺寸D2示出为介于差异CESL96的垂直部分96v的相对表面之间。通常，第一尺寸D1等于第二尺寸D2加上2倍的垂直部分96v的厚度Tv。
一些实施例可以获得优势。在一些实施方式中，用于形成导电部件(例如，图12A和图16A中的导电部件104或134)的工艺窗口可以增大，这是因为与自始至终均具有均匀厚度的CESL相比，通过减小垂直部分96v的厚度Tv可以增大第二尺寸D2。在其他实施方式中，对于用于形成导电部件的给定的工艺窗口(其可以确定最小第二尺寸D2)，当与自始至终均具有均匀厚度的CESL相比时，差异CESL96可以允许水平部分96h的增大的厚度Th，栅极间隔件86增加的宽度(例如，在第二尺寸D2的方向上)和/或增加的栅极堆叠件宽度。如果栅极间隔件86的宽度相对较小，例如，垂直部分96v的厚度Tv可以相对较大，其可以允许水平部分96h的厚度成比例地更大。例如，这可以允许在形成用于导电部件的开口(例如，在图11A-B和图15A-B中的开口102或132)的蚀刻工艺期间，对外延源极/漏极区92的更大的保护和/或更大的蚀刻停止能力。这也可以允许外延源极/漏极区92免受氧化的更大的保护。如果垂直部分96v的厚度Tv相对较小，例如，栅极间隔件86的宽度可以相对较大，这可以允许用于栅极间隔件86的更多的间隔件材料(例如低k材料)，从而通过减小阻容(RC)延迟来提高器件性能。如果栅极间隔件86的宽度和水平部分96h的厚度Th相比于均匀CESL工艺中的相应的结构保持相同，则可以减小垂直部分96v的厚度Tv，这可以允许栅极堆叠件的增加的宽度(例如，平行于相应的外延源极/漏极区92之间的沟道长度方向)。可以实现各种变换和尺寸和厚度的组合以允许实现各种优势。
一个实施例是一种结构。该结构包括：位于衬底上的有源区，位于有源区上方的栅极结构和差异蚀刻停止层。有源区包括源极/漏极区，并且源极/漏极区邻近栅极结构。差异蚀刻停止层具有沿着栅极间隔件的侧壁的第一部分并且具有位于源极/漏极区的上表面上方的第二部分。第一部分的第一厚度在垂直于栅极间隔件的侧壁的方向上，第二部分的第二厚度在垂直于源极/漏极区的上表面的方向上。第二厚度大于第一厚度。
另一实施例是一种半导体处理的方法。在衬底上的器件结构上方形成差异层。在第一暴露中，将器件结构暴露于一种或多种第一前体。在第一暴露之后，使用定向等离子体活化激活器件结构上的上表面。在激活器件结构上的上表面之后，在第二暴露中，将器件结构暴露于一种或多种第二前体。其中，当将器件结构暴露于一种或多种第二前体时，与器件结构上的未激活表面相比，在器件结构上的激活的上表面处发生更多的反应。
进一步的实施例是一种半导体处理的方法。形成差异蚀刻停止层，差异蚀刻停止层具有位于源极/漏极区的上表面上的第一部分和沿着栅极间隔件的侧壁的第二部分。源极/漏极区位于有源区中，栅极间隔件位于有源区上方并且邻近源极/漏极区。第一部分的厚度大于第二部分的厚度。形成差异蚀刻停止层包括实施定向活化。在差异蚀刻停止层上方沉积层间电介质(ILD)。穿过层间电介质和差异蚀刻停止层形成接触源极/漏极区的导电部件。
根据本发明的一些实施例，提供了一种半导体结构，包括：有源区，位于衬底上，所述有源区包括源极/漏极区；栅极结构，位于所述有源区上方，所述源极/漏极区邻近所述栅极结构；栅极间隔件，沿着所述栅极结构的侧壁；以及差异蚀刻停止层，具有沿着所述栅极间隔件的侧壁的第一部分并且具有位于所述源极/漏极区的上表面上方的第二部分，所述第一部分的第一厚度在垂直于所述栅极间隔件的侧壁的方向上，所述第二部分的第二厚度在垂直于所述源极/漏极区的上表面的方向上，所述第二厚度大于所述第一厚度。
在上述半导体结构中，所述源极/漏极区是外延源极/漏极区。
在上述半导体结构中，所述差异蚀刻停止层包括氮化硅。
在上述半导体结构中，所述第二厚度比所述第一厚度大至少2纳米(nm)。
在上述半导体结构中，还包括：层间电介质(ILD)，位于所述差异蚀刻停止层上方；以及导电部件，穿过所述层间电介质和所述差异蚀刻停止层的第二部分并且接触所述源极/漏极区。
根据本发明的另一些实施例，还提供了一种处理半导体的方法，包括：在衬底上的器件结构上方形成差异层，形成所述差异层包括：在第一暴露中，将所述器件结构暴露于一种或多种第一前体；在所述第一暴露之后，使用定向等离子体活化激活所述器件结构上的上表面；和在激活所述器件结构上的上表面之后，在第二暴露中，将所述器件结构暴露于一种或多种第二前体，其中，当将所述器件结构暴露于所述一种或多种第二前体时，与所述器件结构上的未激活表面相比，在所述器件结构上的激活的上表面处发生更多的反应。
在上述方法中，所述一种或多种第一前体包括不包含在所述一种或多种第二前体中的第一前体；在所述第一暴露期间，所述第一前体与所述器件结构的上表面和侧壁表面反应，所述器件结构的上表面具有水平分量；被激活的所述器件结构上的上表面是所述器件结构的反应的上表面；以及所述一种或多种第二前体包括不包含在所述一种或多种第一前体中的第二前体。
在上述方法中，所述第一前体是二氯甲硅烷(SiH2Cl,DCS)；以及所述第二前体是氨气(NH3)，并且所述第二暴露包括等离子体。
在上述方法中，形成所述差异层包括使用原子层沉积(ALD)工艺。
在上述方法中，所述一种或多种第一前体包括至少两种前体；在所述第一暴露期间，所述至少两种前体反应以在所述器件结构的侧壁表面和上表面上形成所述差异层的部分，所述器件结构的上表面具有水平分量；被激活的所述器件结构上的所述上表面是所述差异层的位于所述器件结构的上表面上的部分的上表面；以及所述一种或多种第二前体包括至少两种前体。
在上述方法中，形成所述差异层包括使用化学气相沉积(CVD)工艺，其中，利用所述化学气相沉积工艺原位实施所述定向等离子体活化。
在上述方法中，形成所述差异层沿着所述器件结构上的上表面形成所述差异层的第一部分和沿着所述器件结构的未激活表面形成所述差异层的第二部分，所述差异层的所述第一部分在垂直于所述器件结构上的上表面的方向上具有第一厚度，所述差异层的第二部分在垂直于所述器件结构上的未激活表面的方向上具有第二厚度，所述第一厚度大于所述第二厚度。
在上述方法中，所述器件结构包括：有源区，位于所述衬底上，所述有源区包括源极/漏极区；以及栅极间隔件，位于所述有源区上并且邻接所述源极/漏极区，所述器件结构上的上表面沿着所述源极/漏极区的上表面，所述器件结构上的未激活表面沿着所述栅极间隔件的侧壁表面。
在上述方法中，所述有源区位于所述衬底上的鳍中，并且所述源极/漏极区是外延源极/漏极区。
根据本发明的另一些实施例，还提供了一种处理半导体的方法，包括：形成差异蚀刻停止层，所述差异蚀刻停止层具有位于源极/漏极区的上表面上的第一部分和沿着栅极间隔件的侧壁的第二部分，所述源极/漏极区位于有源区中，所述栅极间隔件位于所述有源区上方并且邻近所述源极/漏极区，所述第一部分的厚度大于所述第二部分的厚度，形成所述差异蚀刻停止层包括实施定向活化；在所述差异蚀刻停止层上方沉积层间电介质(ILD)；以及穿过所述层间电介质和所述差异蚀刻停止层形成接触所述源极/漏极区的导电部件。
在上述方法中，所述定向活化是等离子体定向活化。
在上述方法中，形成所述差异蚀刻停止层包括：在第一暴露的第一工具室中，将所述源极/漏极区的上表面和所述栅极间隔件的侧壁暴露于所述第一前体以沿着所述源极/漏极区的上表面和所述栅极间隔件的侧壁形成相应的反应表面；在所述第一暴露之后，从所述工具室清除所述第一前体；在清除所述第一前体之后，在所述工具室中，实施所述定向活化以沿着所述源极/漏极区的上表面激活所述反应表面；以及在实施所述定向活化之后，在第二暴露的工具室中，将沿着所述源极/漏极区的上表面的激活的反应表面和沿着所述栅极间隔件的侧壁的反应表面暴露于第二前体，所述第二前体不包括在所述第一暴露中，所述第一前体不包括在所述第二暴露中。
在上述方法中，形成所述差异蚀刻停止层包括使用原子层沉积(ALD)工艺。
在上述方法中，形成所述差异蚀刻停止层包括：在第一暴露的工具室中，将所述源极/漏极区的上表面和所述栅极间隔件的侧壁暴露于至少两种前体以形成所述差异蚀刻停止层的沿着所述源极/漏极区的上表面和所述栅极间隔件的侧壁的部分；在所述第一暴露之后，在所述工具室中实施所述定向活化以激活所述差异蚀刻停止层的沿着所述源极/漏极区的上表面的部分；以及在实施所述定向活化之后，在所述工具室中，将所述差异蚀刻停止层的沿着所述源极/漏极区的上表面的激活部分和所述差异蚀刻停止层的沿着所述栅极间隔件的侧壁的部分暴露于所述至少两种前体。
在上述方法中，形成所述差异蚀刻停止层包括使用利用定向活化的化学气相沉积(CVD)工艺，在所述化学气相沉积工艺中原位实施所述定向活化。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
有源区，位于衬底上，所述有源区包括源极/漏极区；
栅极结构，位于所述有源区上方，所述源极/漏极区邻近所述栅极结构；
栅极间隔件，沿着所述栅极结构的侧壁；以及
差异蚀刻停止层，具有沿着所述栅极间隔件的侧壁的第一部分并且具有位于所述源极/漏极区的上表面上方的第二部分，所述第一部分的第一厚度在垂直于所述栅极间隔件的侧壁的方向上，所述第二部分的第二厚度在垂直于所述源极/漏极区的上表面的方向上，所述第二厚度大于所述第一厚度。
2.根据权利要求1所述的半导体结构，其中，所述源极/漏极区是外延源极/漏极区。
3.根据权利要求1所述的半导体结构，其中，所述差异蚀刻停止层包括氮化硅。
4.根据权利要求1所述的半导体结构，其中，所述第二厚度比所述第一厚度大至少2纳米(nm)。
5.根据权利要求1所述的半导体结构，还包括：
层间电介质(ILD)，位于所述差异蚀刻停止层上方；以及
导电部件，穿过所述层间电介质和所述差异蚀刻停止层的第二部分并且接触所述源极/漏极区。
6.一种处理半导体的方法，包括：
在衬底上的器件结构上方形成差异层，形成所述差异层包括：
在第一暴露中，将所述器件结构暴露于一种或多种第一前体；
在所述第一暴露之后，使用定向等离子体活化激活所述器件结构上的上表面；和
在激活所述器件结构上的上表面之后，在第二暴露中，将所述器件结构暴露于一种或多种第二前体，其中，当将所述器件结构暴露于所述一种或多种第二前体时，与所述器件结构上的未激活表面相比，在所述器件结构上的激活的上表面处发生更多的反应。
7.根据权利要求6所述的方法，其中：
所述一种或多种第一前体包括不包含在所述一种或多种第二前体中的第一前体；
在所述第一暴露期间，所述第一前体与所述器件结构的上表面和侧壁表面反应，所述器件结构的上表面具有水平分量；
被激活的所述器件结构上的上表面是所述器件结构的反应的上表面；以及
所述一种或多种第二前体包括不包含在所述一种或多种第一前体中的第二前体。
8.根据权利要求7所述的方法，其中：
所述第一前体是二氯甲硅烷(SiH2Cl,DCS)；以及
所述第二前体是氨气(NH3)，并且所述第二暴露包括等离子体。
9.根据权利要求6所述的方法，其中，形成所述差异层包括使用原子层沉积(ALD)工艺。
10.一种处理半导体的方法，包括：
形成差异蚀刻停止层，所述差异蚀刻停止层具有位于源极/漏极区的上表面上的第一部分和沿着栅极间隔件的侧壁的第二部分，所述源极/漏极区位于有源区中，所述栅极间隔件位于所述有源区上方并且邻近所述源极/漏极区，所述第一部分的厚度大于所述第二部分的厚度，形成所述差异蚀刻停止层包括实施定向活化；
在所述差异蚀刻停止层上方沉积层间电介质(ILD)；以及
穿过所述层间电介质和所述差异蚀刻停止层形成接触所述源极/漏极区的导电部件。
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