CN109545768B - 具有采用改善引线设计的引线框架的封装体及其制造 - Google Patents

具有采用改善引线设计的引线框架的封装体及其制造 Download PDF

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CN109545768B
CN109545768B CN201811110608.4A CN201811110608A CN109545768B CN 109545768 B CN109545768 B CN 109545768B CN 201811110608 A CN201811110608 A CN 201811110608A CN 109545768 B CN109545768 B CN 109545768B
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China
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die
semiconductor package
discrete electronic
lead
leads
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CN109545768A (zh
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R·罗德里奎兹
B·C·巴奎安
M·G·马明
D·加尼
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STMicroelectronics SA
STMicroelectronics lnc USA
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STMicroelectronics SA
STMicroelectronics lnc USA
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Abstract

本申请涉及具有采用改善引线设计的引线框架的封装体及其制造。半导体封装体包括引线框架、裸片、分立电子组件和电连接件。引线框架包括引线和裸片焊盘。一些引线包括其中具有凹部的刻印区域，并且裸片焊盘可包括刻印区域或多个刻印区域。每个刻印区域形成为容纳并限制导电粘合剂流过刻印引线或裸片焊盘的边缘。当被放置在刻印区域上时，边界将导电粘合剂限制在刻印引线或刻印裸片焊盘上的适当位置。通过利用具有刻印区域的引线框架，可以容纳导电粘合剂的流动或导电粘合剂的润湿性并将其限制在刻印引线或刻印裸片焊盘的适当区域，使得导电粘合剂不会引起半导体封装体内的电子组件之间的串扰或半导体封装体内的短路。

Description

具有采用改善引线设计的引线框架的封装体及其制造
技术领域
本公开涉及半导体封装体和制造所述半导体封装体的方法，所述半导体封装体具有引线框架，所述引线框架包括具有刻印(engrave)的裸片焊盘和引线，用于在半导体封装体内安装分立电子组件。
背景技术
随着半导体封装体的消费需求增加，制造商面临零缺陷地制造和形成包括几个裸片和分立电子组件的封装体的重大挑战。当形成包括多个分立电子组件的半导体封装体或系统级封装体(SiP)时，在半导体封装体或系统级封装体(SiP)内可能产生各种缺陷。例如，诸如短路或非预期的电连接的缺陷可能是由于导电粘合剂暴露在封装体的底部而导致。导电粘合剂的这种暴露可能是由导电粘合剂错位、在半导体封装体内耦合分立电子组件时涂覆太多导电粘合剂或具有高润湿性的导电粘合剂造成的。另外，当导电粘合剂不在适当位置或暴露在半导体封装体的表面上时，半导体封装体可能超出规范并且不能用于其预期目的。此外，半导体封装体内的裸片、引线、裸片焊盘或电子组件的任何组合之间的非预期的电连接或串扰可能导致有故障或有缺陷的半导体封装体。另外，在各种电连接件、半导体封装体的多个组件、电子器件内的多个电子组件或半导体封装体内的多个分立电子组件之间的这些缺陷(例如短路和串扰)可能导致半导体封装体或电子器件效率低、有故障和超出规范。
形成半导体封装体的一种方法是使用由导电材料制成的引线框架。引线框架包括裸片焊盘和多个引线。首先，将导电粘合剂放置在多个引线的一些引线上。在放置导电粘合剂之后，通过在引线对之间的导电粘合剂由导电粘合剂耦合分立电子组件。一旦分立电子组件已经耦合到引线对，就通过导电粘合剂将裸片耦合到引线框架的裸片焊盘。一旦裸片耦合到裸片焊盘，就在多个引线的各个引线和裸片之间形成电连接件。这些电连接件可以由多个导线形成。在裸片和多个引线的相应引线之间形成电连接件之后，放置模制化合物以包封引线框架、分立电子组件和电连接件。
利用上述形成工艺在单个制造批次中形成多个半导体封装体。遗憾的是，当利用上述形成工艺时，将分立电子组件耦合到引线的导电粘合剂可能错位或移位，导致不希望的或非预期的电连接。然后，这些不需要的电连接可能导致半导体封装体以非预期的方式工作、效率低下或出现故障。例如，由于半导体封装体内的导电粘合剂的溢出、不适当的位移或错位，在半导体封装体中的多个引线和裸片焊盘之间可能造成短路和串扰。类似地，由于导致导电粘合剂暴露在半导体封装体的外表面上的导电粘合剂的溢出，所以可能与半导体封装体外部的组件形成不希望的或非预期的电连接。还存在其他困难。首先，如果使用太少的导电粘合剂将分立电子组件耦合到引线，则电连接可能在物理上很弱。类似地，如果没有使用足够的导电粘合剂将分立电子组件耦合到引线，则可能形成引线和分立电子组件之间的不良电连接。第三，由于在分立电子组件、导电粘合剂和引线的边缘之间或在半导体封装体内的诸如裸片、裸片焊盘、电连接件或其他电子和导电组件的各种组件之间，期望紧密空间间隙，所以利用具有高润湿性的导电粘合剂可能导致被拒绝或超出规格的封装体。
发明内容
本公开提供了通过利用引线和裸片焊盘形成的半导体封装体，所述引线和裸片焊盘具有刻印区域以在半导体封装体内形成电连接件时控制导电粘合剂的流动。在用于形成这些半导体封装体的方法中，引线框架的第二侧上的选定位置被覆盖在导电材料中。导电材料可以是选择性化学抗蚀的导电材料。覆盖在导电材料中的一些选定位置将用于形成引线框架的裸片焊盘，并且由导电材料覆盖的一些选定位置将用于形成引线框架的引线。在选定位置被覆盖在导电材料中之后，分立电子组件耦合到引线框架的引线和裸片焊盘的刻印区域。引线框架的引线和裸片焊盘的刻印区域包括低区域和高区域。更具体地，低区域围绕高区域并与高区域相邻。换句话说，低区域是凹凹部、谷或槽，其围绕并限定高区域，该高区域是脊或丘。高区域包括顶表面，以将半导体封装体内的分立电子组件耦合至引线框架的相应引线或相应裸片焊盘的相应刻印区域。刻印区域的凹部被配置成：在分立电子组件通过导电粘合剂耦合到引线框架的各种引线和裸片焊盘时，收集过量的导电粘合剂以控制导电粘合剂的流动或润湿。分立电子组件耦合到引线框架的引线和裸片焊盘的刻印区域的高区域的顶表面。一旦分立电子组件耦合到引线框架的引线和裸片焊盘的相应刻印区域，裸片也耦合到引线框架的裸片焊盘。然而，在备选方法中，可以在分立电子组件耦合到引线或裸片焊盘之前，将裸片耦合到裸片焊盘。裸片通过粘合剂材料耦合到裸片焊盘。例如，该粘合剂材料可以是裸片附接膜、胶或一些其他粘合剂材料。另外，该粘合剂材料可以是导电的。一旦裸片耦合到引线框架的裸片焊盘，就在半导体封装体的裸片和相应引线之间形成电连接件。半导体封装体的这些引线可以包括具有耦合到分立电子组件的刻印区域的引线以及不具有刻印区域的引线。在裸片和各种引线之间形成电连接件之后，放置模制化合物以包封引线框架、裸片、分立电子组件和电连接件。在放置并固化模制化合物之后，去除引线框架的第二侧的部分以物理分离且电分离半导体封装体的裸片焊盘和引线。在去除引线框架的第二侧的部分之后，将半导体封装体分割为单独的半导体封装体。
根据一个实施例，形成具有多个引线、裸片焊盘、裸片、多个导线和模制化合物的封装体。裸片焊盘和一些引线具有包括高区域和低区域的刻印区域。当在分立电子组件、裸片焊盘或引线之间形成电连接件时，刻印区域的低区域用作槽或凹部以收集过量的导电材料。多个引线中的一些引线是刻印引线，并且多个引线中的其他引线未被刻印。而且，在其他引线和裸片之间形成电连接件。尽管这些组件被包封在模制化合物中以形成半导体封装体，但是引线和裸片焊盘的表面保持暴露，因此半导体封装体可以被安装在电子设备内或安装到电子设备。
通过利用具有刻印区域的引线和裸片焊盘，可以更容易地控制用于将分立电子组件耦合到引线和裸片焊盘的导电粘合剂。换句话说，刻印区域的刻印可以收集可能原本溢出到不需要导电粘合剂的区域的导电粘合剂。另外，这显著降低了在半导体封装体内或与半导体封装体外部的其他电子组件形成不需要的电连接或串扰的机会。同样地，通过利用少量额外的导电粘合剂，使得导电粘合剂在将分立电子组件耦合到引线和裸片焊盘刻印区域时填充或部分填充刻印区域，将在半导体封装体内在分立电子组件和引线或裸片焊盘之间形成强的物理连接和更好的电连接。另外，通过在引线和裸片焊盘上具有刻印区域，显著降低了半导体封装体内的短路和串扰的可能性。另外，可以以高一致性形成具有高容差规格的半导体封装体。
附图说明
在附图中，除非上下文另有说明，否则相同的数字标识相似的元件或动作。附图中元件的尺寸和相对位置不一定按比例绘制。
图1A是半导体封装体的横截面图，示出了现有技术的问题；
图1B是半导体封装体的横截面图，示出了现有技术的问题；
图2A是通过利用具有刻印的引线框架的公开方法形成的本发明完成的半导体封装体的顶视平面图；
图2B是在本发明完成的半导体封装体中耦合到引线框架的刻印区域的分立电子组件的放大顶视平面图，如图2A中的虚线矩形2B所示；
图2C是在本发明完成的半导体封装体中耦合到引线框架的刻印区域的分立电子组件的放大顶视平面图，如图2A中的虚线矩形2C所示；
图2D是耦合到引线框架的刻印区域的分立电子组件的沿图2B中的2D-2D截取的横截面图；
图2E是本发明完成的半导体封装体的实施例的横截面图；
图3是本发明完成的半导体封装体的备选实施例的横截面图；
图4至图10是利用刻印的引线框架形成本发明完成的半导体封装体的实施例的方法的连续步骤的横截面图，该半导体封装体具有耦合到引线框架的刻印区域的分立电子组件；
图11是利用刻印的引线框架形成本发明完成的半导体封装体的实施例的方法的备选实施例的横截面图，该半导体封装体具有耦合到引线框架的刻印区域的分立电子组件；
图12是根据图4至图10的利用具有刻印区域的引线框架的半导体封装体形成工艺的连续步骤的流程图；和
图13是根据图11的利用具有刻印区域的引线框架的备选半导体封装体形成工艺的连续步骤的流程图。
具体实施方式
在以下描述中，阐述了某些具体细节以便提供对本公开的各种实施例的透彻理解。然而，本领域技术人员将理解，可以在没有这些具体细节的情况下实践本公开。在其他情况下，没有详细描述与电子组件和制造技术相关联的公知结构，以避免不必要地模糊本公开的实施例的描述。
除非上下文另有要求，否则在整个说明书和随后的权利要求中，词语“包括”及其变体，例如“含”和“包含”，应以开放的、包含性的意义解释，即“包括但不限于”。
诸如第一、第二和第三之类的序数的使用不一定意味着排序的秩序感，而是可以仅区分动作或结构的多个实例。
贯穿本说明书对“一个实施例”或“实施例”的引用意味着结合该实施例描述的特定特征、结构或特性包括在至少一个实施例中。因此，贯穿本说明书在各个地方出现的短语“在一个实施例中”或“在实施例中”不一定都指的是同一实施例。此外，特定特征、结构或特性可以在一个或多个实施例中以任何合适的方式组合。
如在本说明书和所附权利要求中所使用的，除非内容另有明确说明，单数形式“一”、“一个”和“该”包括复数指示物。还应注意，术语“或”通常以包括“和/或”的含义使用，除非内容另有明确说明。
图1A示出了通过半导体封装体形成工艺形成的半导体封装体100。封装体100包括多个引线102、裸片焊盘104、裸片108、分立电子组件114、多个电连接件110和模制化合物118。
在该封装体100中，分立电子组件114电耦合且物理耦合到多个引线102中的一个引线对。分立电子组件114通过导电粘合剂112耦合到该引线对102。导电粘合剂112可以是导电胶或一些其他导电粘合剂材料。此外，裸片108通过粘合剂106耦合到裸片焊盘104。粘合剂106可以是裸片附接膜、导电粘合剂材料或一些其他粘合剂材料。另外，裸片108耦合到与分立电子组件114耦合的引线对102中的一个相应引线。裸片108通过电连接件110耦合到引线对102中的所述一个相应的引线。电连接件可以由导线110形成。同样地，裸片108耦合到多个引线102的没有耦合到分立电子组件114的引线。裸片108可以耦合到多个引线102中的没有通过电连接件110耦合到分立电子组件的引线。该电连接件110可以是导线110的形式。另外，模制化合物118包封多个引线102、裸片焊盘104、裸片108、分立电子组件114和多个电连接件110。然而，另外，模制化合物118留下裸片焊盘104和多个引线102的暴露表面，因此封装体可以被安装在电子设备内。例如，电子设备可以是计算器、笔记本电脑、平板电脑、手机或一些其他电子设备。
为了形成该半导体封装体100，使用半导体封装体形成工艺。在该形成工艺中，利用引线框架来形成半导体封装体100。
在该形成工艺中，分立电子组件直接耦合到多个引线102中的一个引线对102。分立电子组件通过导电胶112物理耦合且电耦合到该引线对102。此外，耦合到分立电子组件114的引线对102中的每个引线彼此相邻。在分立电子组件114耦合到引线框架的引线对102之后，裸片108通过裸片附接膜106耦合到裸片焊盘104。一旦裸片108通过裸片附接膜106耦合到裸片焊盘104，就形成多个电连接件110。多个电连接件110由多个导线110形成。所述多个导线110中的一些导线具有耦合到所述裸片108的相应第一端和与没有耦合到分立电子组件114的引线耦合的相应第二端。类似地，多个导线110中的相应导线具有耦合到裸片108的相应第一端以及与耦合到分立电部件114的引线对102中的至少一个引线耦合的相应第二端。在形成电连接件110之后，放置模制化合物118以包封多个引线102、裸片焊盘104、裸片108、电连接件110和分立电子组件114。在放置模制化合物118之后，使模制化合物118固化。在模制化合物118固化后，将半导体封装体100分割为单独的半导体封装体100。
除了一个步骤之外，备选的半导体形成工艺与上述半导体形成工艺相同。在使模制化合物118固化之后，多个引线102和裸片焊盘104仍然物理连接且电连接在引线框架的暴露表面处。此时，通过刻蚀步骤在暴露表面上使多个引线102和裸片焊盘104物理分离且电分离。该刻蚀步骤从引线框架的暴露表面去除部分，以物理分离且电分离多个引线102和裸片焊盘104。在图1B中示出通过该备选形成工艺形成的完整的备选半导体封装体200。
在图1A和图1B的上述两种半导体封装体中，存在以下区域：导电胶112已被推出位置，并且在半导体封装体100、200的表面上暴露出导电胶116。当安装在电子器件内时，图1A中的这种移位的导电胶116会导致不希望的电连接。同样地，如果移位的导电胶116朝向半导体封装体200内的其他电子组件移动，如图1B所示，移位的导电胶116可能导致半导体封装体200内的多个引线、多个电子组件之间或引线102与裸片焊盘104之间的串扰。该串扰将导致错误或低效的半导体封装体200。另外，如果对于导电胶112可以布置在引线102上的地方具有高容差规格并且导电胶112的润湿性高，则非常难以保持导电胶112不流动或移入半导体封装体100、200内的不希望的或非期望的位置。换句话说，如果导电胶112具有高润湿性，则当具有高润湿性的导电胶112放置在相应的引线102上时，非常难以控制粘性导电胶112将在哪里停止。类似地，当使用具有高润湿性的导电胶112将分立电子组件114耦合到半导体封装体100、200内的引线102时，具有高润湿性的导电胶112在放置分立电子组件114时可以移位到半导体封装体100、200的不希望的位置116中。
该示例说明了应该在半导体封装体100、200中解决的发明人意识到的缺点，该半导体封装体利用包括将分立电子组件耦合到半导体封装体100、200内的引线的形成工艺。
本公开描述了一种半导体封装体和形成工艺，其克服了上述半导体封装体100、200的许多缺点。本公开描述了通过利用具有刻印的引线框架形成的半导体封装体的各种实施例，以显著提高半导体封装体的效率并减少由于包括分立电子组件的半导体封装体内的粘合剂材料的移位引起的缺陷数量。
图2A至2E示出了本公开的一个实施例，用于提供具有引线框架152的半导体封装体300，引线框架152包括引线122、刻印引线124和刻印裸片焊盘138。此外，半导体封装体300包括模制化合物120、分立电子组件130、132、裸片134和电连接件136。
图2A是半导体封装体300的顶视图。引线框架152的刻印引线124包括刻印区域。每个刻印区域包括高区域126和低区域128，高区域126是丘126，低区域128是凹部128。该凹部128邻近于丘126并且包围丘126。类似于刻印引线124，在该实施例中，裸片焊盘138也具有刻印区域。然而，在备选实施例中，裸片焊盘可以不具有刻印区域。裸片焊盘138的刻印区域包括丘和凹部，类似于刻印引线124。凹部邻近丘并围绕丘。引线框架152的刻印区域可以是任何形状或尺寸，例如圆形、椭圆形、矩形、方形或任何其他形状或尺寸、或形状或尺寸的组合。此外，分立电子组件130、132耦合到裸片焊盘138的刻印区域、刻印引线124或两者。更具体地，每个分立电子组件130、132具有耦合到第一相应刻印区域的第一端和耦合到第二相应刻印区域的第二端。第一相应刻印区域和第二相应刻印区域可以是两个相邻的刻印引线124之间的刻印区域对，或者可以是裸片焊盘138的刻印区域和刻印引线124的刻印区域。另外，分立电子组件130、132通过粘合剂材料140耦合到刻印区域。粘合剂材料140是导电粘合剂材料。分立电子组件130、132可以是电阻器、电感器、电容器、半导体或一些其他分立电子组件或分立电子组件的组合。而且，电连接件136可以形成在裸片和一些刻印引线124之间、裸片和一些引线122之间、或这两者。另外，裸片134在裸片附接区域139处耦合到裸片焊盘138。裸片134通过裸片附接区域139处的粘合剂材料148耦合到裸片焊盘138。粘合剂材料148可以是导电粘合剂材料、裸片附接膜或一些其他粘合剂材料或粘合剂材料的组合。因此，模制化合物120包封引线122、刻印引线124、裸片134、电连接件136和裸片焊盘138。然而，模制化合物使每个引线122、每个刻印引线124和裸片焊盘138的表面暴露，因此半导体封装体300可以安装在电子设备内或电子设备上。例如，电子设备可以是手机、平板电脑、计算机、笔记本电脑、计算器或一些其他电子设备。
图2B和图2C是耦合到相邻刻印引线对124的分立电子组件130、132的放大视图。如图2B和图2C的这些放大视图所示，每个凹部128形成围绕刻印引线124的刻印区域的相应丘126的周边。
图2D是沿图2B中的2D-2D的横截面图。如图2D所示，分立电子组件130的一端耦合到刻印引线124的刻印区域的丘126。分立电子组件130通过导电粘合剂材料140耦合到刻印引线的丘126。此外，在该实施例中，如果导电粘合剂材料140朝向刻印引线124的边缘移位或向外推，则凹部128将用作槽并收集向外移位的过量导电粘合剂材料140。换句话说，凹部128形成围绕刻印引线的丘的周边或边界，以显著降低导电粘合剂材料140到达刻印引线124的边缘的机会。在备选实施例中，每个刻印引线124可具有第一凹部和第二凹部。第一凹部可以定位在刻印引线的丘的一侧上，并且第二凹部可以在刻印引线的丘的相对侧上与第一凹部相对地定位。换句话说，刻印引线的凹部128可以形成围绕每个刻印引线124的丘126的周边，可以是多个不同的凹部，或者可以是不形成围绕丘126的完整周边或边界的凹部128。更具体地，凹部128可具有任何形状或尺寸，以减少导电粘合剂材料140到达刻印引线124的边缘的机会。备选地，在备选实施例中，每个刻印引线124和刻印裸片焊盘138可仅包括凹部128而不包括丘126。该备选实施例如图3所示。而且，刻印引线124和裸片焊盘138的刻印区域的任何上述实施例可以以任何组合来使用。
凹部128可以通过任何可接受的技术形成，包括湿法刻蚀、激光刻蚀、丝网图案和刻蚀、机械加工或其他可接受的方法。它们可以由制造引线框架的一方或由放置裸片和模制最终封装体的一方来形成，这些部件彼此等同并且形成的位置和定时是等同的。
图2E示出了本公开完成的半导体封装体300的实施例的横截面图。然而，在该完成的半导体封装体300中，当将一个分立电子组件132耦合到刻印引线124和裸片焊盘138的刻印区域时，导电粘合剂材料140已经被移位到一个刻印引线124的凹部128中。因此，凹部128用作被移位或接近刻印引线124的边缘的导电粘合剂140的边界。换句话说，凹部124阻止导电粘合剂140到达引线的边缘，进而阻止导电粘合剂140移位到半导体封装体300内的不期望的位置。
图3示出了本公开完成的半导体封装体400的备选实施例的横截面侧视图。类似于图2E中完成的半导体封装体300的实施例，在完成的半导体封装体400的该备选实施例中，完成的半导体封装体400包括引线框架152、分立电子组件130、132、裸片134和模制化合物120。引线框架152包括刻印裸片焊盘138和刻印引线124。然而，与其中刻印引线124具有高区域126和低区域128的完成的半导体封装体300不同，在完成的半导体封装体400的本备选实施例中，刻印引线124具有低区域150如凹部形式的刻印区域。刻印引线124上的凹部150的壁用作阻止导电粘合剂140朝向刻印引线124的边缘移位的边界。因此，类似于完成的半导体封装体300中的刻印引线124，在完成的半导体封装体400的本备选实施例中，凹部150的壁以与图2E中完成的半导体封装体300的实施例中的丘126和槽128的组合相同的方式起作用。
图4至图10示出了形成具有刻印引线124的完成的半导体封装体300的实施例的方法。图4示出了引线框架152的横截面侧视图。引线框架152包括多个引线122、124和多个裸片焊盘138。多个引线包括引线122和刻印引线124。刻印引线124具有包括高区域126和低区域128的刻印区域。换句话说，高区域126是丘或脊，并且低区域128是槽、谷或凹部，其用作容纳导电粘合剂140的边界以防止在形成期间流入半导体封装体300、400内的不希望的位置。例如，这些不希望的位置可以是与裸片焊盘相邻的引线的边缘、与另一引线相邻的引线的边缘或半导体封装体的外表面。然而，在备选实施例中，刻印引线124可以是具有壁的凹部150，所述壁充当容纳导电粘合剂140的边界。此外，引线框架152由导电材料制成。该导电材料可以是银、金、铜或任何其他导电材料或导电材料的组合。
在本实施例中，刻印引线124的每个低区域128与刻印引线的相应高区域126相邻。此外，每个低区域128位于刻印引线124的相应的高区域126和相应边缘之间。此外，引线框架152具有第一侧和第二侧。第一侧包括刻印引线124的刻印区域。类似地，第一侧包括裸片焊盘138的刻印区域。裸片焊盘138的刻印区域可以是高区域126和低区域128，可以是具有壁的凹部150，或者可以是一些其他刻印。然而，在该实施例中，类似于刻印引线124，裸片焊盘138的刻印区域包括高区域126和低区域128。引线框架152的第二侧包括被覆盖在导电材料中的选定位置142、144。导电材料可以是选择性化学抗蚀的导电材料。导电材料的一些选定位置142覆盖引线122的第二侧和刻印引线124，并且导电材料的一些选定位置144覆盖裸片焊盘138的第二侧。然而，在备选实施例中，引线框架152的第二侧的选定位置142、144可以根本不被覆盖。另外，引线框架152包括在引线框架152的引线122、刻印引线128和裸片焊盘138之间的凹部154。
图5示出了将导电粘合剂140放置在刻印引线124的刻印区域的高区域126上。导电粘合剂140可以是导电胶、具有高润湿性的导电材料或任何其他导电粘合剂材料。例如，导电粘合剂可以是导电胶，例如汉高粘合剂(Henkel Adhesives)的ICP 3535M1或汉高粘合剂的9507-2C2。然而，在备选实施例中，它可以是导电胶、导电粘合剂或导电粘合剂的组合。
在导电粘合剂140已经放置在引线框架152的高区域126上之后，分立电子组件130、132和裸片134耦合到引线框架152。图6示出了通过粘合剂148将裸片134耦合到裸片焊盘138的裸片附接区域139。粘合剂148可以是导电粘合剂、裸片附接膜、胶或一些其他粘合剂材料或粘合剂材料的组合。此外，分立电子组件130、132包括耦合到引线框架152的刻印区域的第一分立电子组件130和第二分立电子组件132。第一分立电子组件130耦合到相邻刻印引线124的高区域126。类似地，第二分立电子组件132被耦合到相应刻印引线124的高区域126和裸片焊盘138的高区域。裸片焊盘138可以具有一个刻印区域、多个刻印区域或者没有刻印区域。分立电子组件130、132可以是电阻器、电感器、电容器、半导体或一些其他分立电子组件或分立电子组件的组合。
此外，如图6所示，一些导电胶140已溅入一个刻印引线124的低区域128中。因此，如果导电粘合剂润湿性高或者如果是高度粘稠，通过具有高区域126和与高区域126相邻并形成围绕高区域126的周边的低区域128，形成边界以容纳导电粘合剂140的流动。另外，高区域126和低区域128的组合将导电粘合剂140限制在完成的半导体封装体300的适当位置，并且显著地减少了当将分立电子组件130、132耦合到引线框架152时由于导电粘合剂的移位引起的缺陷。
附加地，如果使用比所需略多的导电粘合剂140，使得导电粘合剂140在将分立电子组件130、132耦合到引线框架152时部分地流入刻印引线124的低区域128，在引线框架152和每个分立电子组件130、132之间形成更强的物理连接和电连接。因为导电粘合剂140互锁并覆盖刻印引线124的高区域126的更大部分，所以形成更强的物理连接。类似地，因为导电粘合剂140覆盖刻印引线124的刻印区域的更大表面区域，所以形成更强的电连接。
在分立电子组件130、132和裸片134耦合到引线框架152之后，形成电连接件136。电连接件136可以通过导线、焊料或一些其他电连接技术形成。在该实施例中，电导线形成电连接件136。电导线136可以由铜、银、金或一些其他导电材料或导电材料的组合制成。电连接件136可以形成在裸片134和相应的刻印引线124之间、裸片134和相应的引线122之间或者可以形成在半导体封装体300、400内的电连接件136的任何其他组合。
在形成电连接件136之后，将模制化合物156放置在引线框架152的第一侧上，其覆盖裸片134、分立电子组件130、132和电连接件136。模制化合物156还填充引线框架152的凹部154。图8示出了模制化合物156放置在引线框架152的第一侧上。放置模制化合物156后，使模制化合物156固化。此时，裸片焊盘138、刻印引线124和引线122仍然通过引线框架152的第二侧物理连接和电连接。
在放置并固化模制化合物之后，去除引线框架152的第二侧的部分。可以通过化学刻蚀、激光刻蚀或一些其他刻蚀技术去除这些部分。但是，在该方法中，进行化学刻蚀步骤。更具体地，覆盖引线框架152的第二侧的选定位置的导电材料142、144是选择性化学抗蚀的导电材料，其保护引线122、124和裸片焊盘138的部分免受化学刻蚀。这允许去除选择性化学抗蚀导电材料142、144之间的部分。另外，这种从引线框架152第二侧的部分的去除电分离且物理分离引线122、刻印引线124和裸片焊盘138。然而，如果刻蚀步骤不是化学刻蚀步骤，则引线框架152的第二侧不具有由选择性化学抗蚀的导电材料覆盖的选定位置142、144。
在通过刻蚀步骤去除引线框架152的第二侧的部分之后，将各种组件分割成单独的半导体封装体300。在图10中示出了将各种组件分割成单独的半导体封装体300。可以通过锯切分割、激光分割或一些其他分割技术将半导体封装体300分割成单独的半导体封装体。然而，在该方法中，使用诸如锯的切割设备162来分割各个半导体封装体300。切割设备162在分割位置158处将半导体封装体分割为单独的半导体封装体300，切割设备162可以是锯、激光器或一些其他切割设备。
在上述形成具有刻印引线124的半导体封装体300的方法的备选实施例中，在导电粘合剂140耦合到引线框架152的高区域126之前，支撑件164耦合到引线框架152。支撑件164允许引线框架152具有更大的刚性，以减少在上述形成工艺期间半导体封装体中的缺陷。在图11中示出了形成具有刻印引线124的半导体封装体300的上述方法的备选实施例中的步骤。支撑件164可以是引线框架带、可去除支撑材料或一些其他支撑技术。
图12涉及图4至图10中所示方法的流程图500。更具体地，图12示出了总结利用包括引线122、124和裸片焊盘138的引线框架一次以大阵列制造数百、数千或任何数量的半导体封装体300、400的方法的流程图500。在该方法中，引线122、124包括引线122和刻印引线124，刻印引线124具有包括高区域126和低区域128的刻印区域。另外，裸片焊盘138可以具有类似于刻印引线124的刻印区域。
第一步骤502是将粘合剂140沉积到刻印引线124的刻印区域和裸片焊盘138的刻印区域的高区域126上。粘合剂140是导电粘合剂140。该步骤502在图5中示出。稍后将在该方法中将使用导电粘合剂140，以在刻印引线124和裸片焊盘138的高区域与分立电子组件130、132之间形成电连接和物理连接。此外，可以通过将导电粘合剂140分配到高区域126上来将导电粘合剂140沉积到高区域126上。更具体地，导电粘合剂140可以是导电胶，其是被分配到引线框架152的刻印区域的高区域126上的转移胶。例如，这种转移胶分配可以由Datacon 2200Evo进行。
在将导电粘合剂140沉积到刻印引线124和裸片焊盘138的高区域126上之后，执行第二步骤504。在第二步骤504中，裸片134和分立电子组件130、132附接到引线框架152。该步骤504在图6中示出。更具体地，裸片134附接到引线框架152的裸片焊盘138的相应裸片附接区域139。通过诸如裸片附接膜的粘合剂148将裸片附接到相应的裸片附接区域139。另外，通过将分立电子组件130、132放置在引线框架152上的导电粘合剂140上，将分立电子组件130、132耦合到刻印引线124和裸片焊盘138的相应刻印区域。例如，裸片134和分立电子组件130、132的这种放置可以由西门子Siplace D2机器执行。
在裸片134耦合到裸片附接区域139并且分立电子组件130、132耦合到引线框架152的相应刻印区域之后，执行第三步骤506。在第三步骤506中，形成电连接件136。这些电连接件136可以是导线、焊料或一些其他电连接技术。电连接件136可以形成在裸片134和相应的刻印引线124之间、裸片134和相应的引线122之间、裸片焊盘138和相应的刻印引线124之间、以及裸片134和相应的引线122之间。
在形成电连接件136之后，执行第四步骤508。在第四步骤508中，引线框架152、裸片134、分立电子组件130、132和电连接件136被包封在模制化合物156中。模制化合物156是非导电材料。此外，模制化合物156可以是环氧树脂、密封剂或用于包封半导体封装体的组件的任何其他材料。尽管模制化合物156包封引线框架152、裸片134、分立电子组件130、132和电连接件，但可以使引线框架152的表面暴露，使得半导体封装体300、400可以安装在电子设备内或者安装到电子设备。更具体地，使引线122、刻印引线124和裸片焊盘134的表面暴露。一旦放置模制化合物，则使其固化。例如，模制化合物可以在静态烘箱中在180℃下固化1小时、在150℃下固化1小时、或者在任何时间或任何温度下固化模制化合物。
在放置并固化模制化合物156后，进行第五步骤510。在第五步骤510中，将半导体封装体300、400分割为单独且不同的半导体封装体300、400。半导体封装体的组件可以通过锯切分割、激光分割或一些其他分割技术来分割。每个单独且不同的半导体封装体300、400包括引线122、124、裸片焊盘138、裸片134、分立电子组件130、132、电连接件136和模制化合物120。
图13涉及图11中所示的备选方法的流程图500。更具体地，图13具有与图12相同的步骤，然而图13还包括将支撑件附接到引线框架的步骤602和移除支撑件的步骤612。在将支撑件附接到引线框架的步骤602中，在该备选方法的开始处将支撑件164耦合到引线框架的第二侧。支撑件164可以是稍后可以在该备选方法中去除的引线框架带、可移除支撑材料或者一些其他支撑件。
在图12中的流程图中不存在的、在图13中的备选方法中包括的另一步骤是移除支撑件的步骤612。该步骤发生在步骤610中放置并固化包封半导体封装体的各种组件的模制化合物之后。在该步骤中，从引线框架152去除支撑件164，使得可以在步骤614中刻蚀引线框架152，并且可以在步骤616中将半导体封装体300、400分割为单独且不同的半导体封装体，如在图12中的流程图中那样。
通过利用上述方法和具有刻印区域的引线框架，可以根据需要制造数百、数千或任何数量的单个半导体封装体。而且，通过利用具有拥有高区域和低区域的刻印区域的引线框架，显著减少了由于移位或错位的导电粘合剂导致的半导体封装体内的电子组件之间的串扰。例如，如果放置太多导电粘合剂或导电粘合剂具有高润湿性，当通过导电粘合剂将分立电子组件耦合到引线框架的刻印区域时，移位或错位的导电粘合剂填充作为容纳导电粘合剂的边界的低区域。另外，刻印区域的低区域控制导电粘合剂在半导体封装体内的位置。同样，通过利用上面公开的方法，分立电子组件和引线框架的刻印区域之间的物理连接和电连接更强。由于导电粘合剂将与引线框架的刻印部分的高区域互锁，因此连接在物理上更强。类似地，由于高区域和低区域的组合，导电粘合剂将具有与每个刻印部分更大的接触表面区域，因此连接在电方面是更强的。当刻印区域仅是具有壁的凹部时也是如此。因此，使用上述公开的方法制造的封装体将具有显著更低的、由于导电粘合剂错位或移位到每个半导体封装体内的不希望的位置而导致缺陷的机会。另外，每个半导体封装体将在分立电子组件和引线框架的刻印区域之间具有更强的电连接和物理连接。
此外，通过利用具有刻印区域的裸片焊盘和具有刻印区域的引线来限制和容纳导电粘合剂，半导体封装体可以制造得更小，因为需要更少的引线和电连接以在半导体封装体内形成适当的电连接。
可以组合上述各种实施例以提供进一步的实施例。本说明书中提及和/或在申请数据表中列出的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利出版物，其全部通过引用并入本文。如果需要，可以修改实施例的各方面以采用各种专利、申请和公开的构思来提供其他实施例。
根据以上详细描述，可以对实施例进行这些和其他改变。通常，在以下权利要求中，所使用的术语不应被解释为将权利要求限制于说明书和权利要求中公开的特定实施例，而是应该被解释为包括所有可能的实施例以及这样的等同物的全部范围。因此，权利要求不受本公开的限制。

Claims (20)

1.一种半导体封装体，包括：
引线框架，具有第一侧和第二侧，所述引线框架包括：
刻印引线，具有在所述引线框架的所述第一侧的第一刻印区域，所述第一刻印区域包括：第一凹部，所述第一凹部朝向所述刻印引线的第二侧延伸进入所述刻印引线的第一侧，所述第一凹部具有位于所述刻印引线内的第一端；第一高区域，被所述第一凹部围绕，所述第一高区域的表面与所述第一凹部的第一端具有间隔；
裸片焊盘，具有在所述第一侧的第二刻印区域，所述第二刻印区域包括：第二凹部，所述第二凹部朝向所述裸片焊盘的第二侧延伸进入所述裸片焊盘的第一侧，第二凹部具有位于所述裸片焊盘内的第二端；第二高区域，被所述第二凹部围绕，所述第二高区域的表面与所述第二凹部的第二端具有间隔；
分立电子组件，具有电耦合并物理耦合到所述第一高区域的第一端和电耦合并物理耦合到所述第二高区域的第二端；
裸片，电耦合并物理耦合到所述裸片焊盘的第一端，所述裸片与所述分立电子组件具有间隔；和
模制化合物，包封所述引线框架、所述裸片和所述分立电子组件。
2.根据权利要求1所述的半导体封装体，其中导电粘合剂将所述分立电子组件耦合到所述第一刻印区域和所述第二刻印区域。
3.根据权利要求2所述的半导体封装体，其中所述导电粘合剂将所述分立电子组件的第一端耦合到所述刻印引线的第一高区域。
4.根据权利要求2所述的半导体封装体，其中所述第一凹部被配置为容纳将所述分立电子组件耦合到所述第一刻印区域的导电粘合剂的溢出。
5.根据权利要求2所述的半导体封装体，其中所述导电粘合剂将所述分立电子组件的第二端耦合到所述裸片焊盘的第二高区域。
6.根据权利要求2所述的半导体封装体，其中所述第二凹部被配置为容纳将所述分立电子组件耦合到所述第二刻印区域的导电粘合剂的溢出。
7.根据权利要求1所述的半导体封装体，其中粘合剂将所述裸片耦合到所述裸片焊盘，并且所述裸片与所述裸片焊盘的第二刻印区域相邻。
8.根据权利要求1所述的半导体封装体，其中所述刻印引线和所述裸片焊盘具有在所述引线框架的第二侧上的、被第一导电材料覆盖的表面，所述第一导电材料是选择性化学抗蚀的导电材料。
9.一种半导体封装体，包括：
引线框架，具有第一表面和第二表面，所述第一表面与所述第二表面相对，所述引线框架包括：
多个刻印引线，每个刻印引线具有第一刻印区域和位于所述第一表面和所述第二表面之间的第一高度，所述第一刻印区域包括丘和槽，所述槽与所述丘相邻并且围绕所述丘，所述槽朝向所述第二表面延伸进入所述第一表面第二高度，所述第二高度小于所述第一高度；
裸片焊盘，具有第二刻印区域和所述第一高度，所述第二刻印区域包括丘和槽，所述槽与所述丘相邻并且围绕所述丘，所述槽朝向所述引线框架的第二表面延伸进入所述引线框架的第一表面第三高度，所述第三高度小于所述第一高度；
第一分立电子组件，电耦合并物理耦合到所述多个刻印引线的第一丘和第二丘之间；
第二分立电子组件，电耦合并物理耦合到所述多个刻印引线的第三丘和所述裸片焊盘的所述第二刻印区域的第四丘之间；
裸片，电耦合并物理耦合到所述裸片焊盘的第一表面，所述裸片与所述第一分立电子组件和所述第二分立电子组件具有间隔；和
模制化合物，包封所述引线框架、所述第一分立电子组件、所述第二分立电子组件和所述裸片。
10.根据权利要求9所述的半导体封装体，还包括：
多个引线；
第一电连接件，电耦合并物理耦合在所述多个刻印引线中的至少一个刻印引线与所述裸片之间；和
第二电连接件，电耦合并物理耦合在所述多个引线中的一个引线与所述裸片之间，所述第一电连接件和所述第二电连接件是导线。
11.根据权利要求9所述的半导体封装体，还包括：
第一导电粘合剂，将所述第一分立电子组件的第一端耦合到所述第一丘；和
第二导电粘合剂，将所述第一分立电子组件的第二端耦合到所述第二丘。
12.根据权利要求11所述的半导体封装体，还包括：
第三导电粘合剂，将所述第二分立电子组件的第三端耦合到所述第三丘；和
第四导电粘合剂，将所述第二分立电子组件的第四端耦合到所述第四丘。
13.根据权利要求12所述的半导体封装体，其中与每个丘相邻的每个槽被配置为容纳所述第一导电粘合剂、所述第二导电粘合剂、所述第三导电粘合剂和所述第四导电粘合剂中的一个的相应部分。
14.根据权利要求9所述的半导体封装体，其中粘合剂将所述裸片耦合到所述裸片焊盘，并且所述裸片与所述裸片焊盘的第二刻印区域相邻。
15.一种半导体封装体，包括：
引线框架，具有第一表面和第二表面，所述第二表面背离所述第一表面，所述引线框架包括：
第一引线，所述第一引线具有第一凹部，所述第一凹部在所述第一引线的第一表面中朝向所述第一引线的第二表面延伸，所述第一引线包括被所述第一凹部围绕的第一高区域；
第二引线，所述第二引线具有第二凹部，所述第二凹部在所述第二引线的第一表面中朝向所述第二引线的第二表面延伸，所述第二凹部终止于所述第二引线内，所述第二引线包括被所述第二凹部围绕的第二高区域；
裸片焊盘，与所述第一引线和所述第二引线具有间隔；
裸片，电耦合并物理耦合到所述裸片焊盘；以及
第一分立电子组件，具有电耦合并物理耦合到所述第一高区域的第一端和电耦合并物理耦合到所述第二高区域的第二端，所述第一分立电子组件与所述裸片具有间隔。
16.根据权利要求15所述的半导体封装体，其中所述引线框架还包括：第三引线，所述第三引线具有第三凹部，所述第三凹部在所述第三引线的第一表面中延伸，所述第三凹部终止于所述第三引线内。
17.根据权利要求16所述的半导体封装体，还包括：裸片焊盘，所述裸片焊盘包括第四凹部，所述第四凹部在所述裸片焊盘的第一表面中延伸，所述第四凹部与裸片相邻，所述第四凹部终止于所述裸片焊盘内。
18.根据权利要求17所述的半导体封装体，还包括：第二分立电子组件，电耦合并物理耦合至被所述第三引线的第三凹部围绕的第三高区域和被所述裸片焊盘的第四凹部围绕的第四高区域。
19.根据权利要求18所述的半导体封装体，其中所述第三凹部和所述第四凹部由导电粘合剂填充，所述导电粘合剂将所述第二分立电子组件耦合至所述第三凹部和所述第四凹部。
20.根据权利要求15所述的半导体封装体，还包括：填充所述第一凹部和所述第二凹部的导电粘合剂，所述导电粘合剂将所述第一分立电子组件耦合至所述第一凹部和所述第二凹部。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763194B2 (en) * 2017-09-22 2020-09-01 Stmicroelectronics, Inc. Package with lead frame with improved lead design for discrete electrical components and manufacturing the same
US10892212B2 (en) * 2017-11-09 2021-01-12 Stmicroelectronics, Inc. Flat no-lead package with surface mounted structure
US11562947B2 (en) * 2020-07-06 2023-01-24 Panjit International Inc. Semiconductor package having a conductive pad with an anchor flange

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486535B2 (en) * 2001-03-20 2002-11-26 Advanced Semiconductor Engineering, Inc. Electronic package with surface-mountable device built therein
US6750546B1 (en) * 2001-11-05 2004-06-15 Skyworks Solutions, Inc. Flip-chip leadframe package
US7768131B1 (en) * 2009-06-27 2010-08-03 Kinsus Interconnect Technology Corp. Package structure preventing solder overflow on substrate solder pads
CN208848898U (zh) * 2017-09-22 2019-05-10 意法半导体有限公司 半导体封装体

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6828661B2 (en) * 2001-06-27 2004-12-07 Matsushita Electric Industrial Co., Ltd. Lead frame and a resin-sealed semiconductor device exhibiting improved resin balance, and a method for manufacturing the same
US6903447B2 (en) * 2002-05-09 2005-06-07 M/A-Com, Inc. Apparatus, methods and articles of manufacture for packaging an integrated circuit with internal matching
JP4359110B2 (ja) * 2003-09-24 2009-11-04 三洋電機株式会社 回路装置
US7005325B2 (en) * 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration
ATE445232T1 (de) * 2004-07-13 2009-10-15 Nxp Bv Elektronische vorrichtung mit integrierter schaltung
US20070093000A1 (en) * 2005-10-21 2007-04-26 Stats Chippac Ltd. Pre-molded leadframe and method therefor
US8174127B2 (en) * 2007-06-21 2012-05-08 Stats Chippac Ltd. Integrated circuit package system employing device stacking
US8481368B2 (en) * 2008-03-31 2013-07-09 Alpha & Omega Semiconductor, Inc. Semiconductor package of a flipped MOSFET and its manufacturing method
US8241965B2 (en) * 2009-10-01 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
US8519518B2 (en) * 2010-09-24 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with lead encapsulation and method of manufacture thereof
US8698291B2 (en) * 2011-12-15 2014-04-15 Freescale Semiconductor, Inc. Packaged leadless semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486535B2 (en) * 2001-03-20 2002-11-26 Advanced Semiconductor Engineering, Inc. Electronic package with surface-mountable device built therein
US6750546B1 (en) * 2001-11-05 2004-06-15 Skyworks Solutions, Inc. Flip-chip leadframe package
US7768131B1 (en) * 2009-06-27 2010-08-03 Kinsus Interconnect Technology Corp. Package structure preventing solder overflow on substrate solder pads
CN208848898U (zh) * 2017-09-22 2019-05-10 意法半导体有限公司 半导体封装体

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