CN109542811B - Data communication processing method - Google Patents
Data communication processing method Download PDFInfo
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- CN109542811B CN109542811B CN201811193759.0A CN201811193759A CN109542811B CN 109542811 B CN109542811 B CN 109542811B CN 201811193759 A CN201811193759 A CN 201811193759A CN 109542811 B CN109542811 B CN 109542811B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/285—Halt processor DMA
Abstract
The technical scheme of the invention comprises a data communication processing method, which realizes a large amount of real-time data communication based on DMA double buffering combined with soft interrupt, in a DMA interrupt program, only the operation of switching a destination address of a DMA channel and triggering the soft interrupt is executed, and the data carrying operation is carried out in the soft interrupt program, but the DMA interrupt can cause CPU interrupt, and the soft interrupt can not cause CPU interrupt, so that the DMA interrupt cost is low, less CPU resources can be occupied when the CPU transaction is busy as much as possible, and the method has strong advantages in a system with resource shortage and busy transactions.
Description
Technical Field
The invention relates to a data communication processing method, and belongs to the technical field of data communication.
Background
In the existing embedded system, the MCU has more and more tasks, and the speed of the communication data interface is faster and faster, so the burden of communication is heavier and heavier. Under the condition of full load communication, a communication interface of the MCU occupies more resources of the processor and is easy to cause communication data loss.
Although the traditional DMA double-buffer data can solve the problem of data loss, when the data volume is large, the time consumption for carrying data is high when the DMA is interrupted, and more resources of a processor are occupied, so that the data communication requirements of system resources shortage and various tasks are difficult to meet.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a data communication processing method, which implements a large amount of real-time data communication based on DMA double-buffer combined with soft interrupt, in a DMA interrupt program, only switching a destination address of a DMA channel and triggering soft interrupt, and then carrying data in the soft interrupt program, where the DMA interrupt will cause CPU interrupt, and the soft interrupt will not cause CPU interrupt, so that the DMA interrupt overhead is small, and the method can occupy a small CPU resource when the CPU transaction is busy as much as possible, and has a strong advantage in a system with resource shortage and busy transaction.
The technical scheme adopted by the invention for solving the problems is as follows: a data communication processing method is based on DMA double buffering combined with soft interruption to realize data communication between an MCU and an external device, wherein the MCU comprises a serial port, an FIFO memory, a DMA controller, an internal memory and a CPU; the method comprises the following steps:
s1, starting a serial port DMA receiving mode, configuring a FIFO memory and setting a receiving threshold value of the FIFO memory;
s2, opening up two receiving buffer areas in the memory, namely a first buffer area and a second buffer area;
s3, initializing the DMA controller, configuring a DMA channel between the peripheral and the memory, and setting the source address of the DMA channel as the data storage address of the peripheral;
s4, setting the destination address of the DMA channel as the address of the first buffer area, and enabling the DMA channel to receive data;
s5, when the data capacity received by the first buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the second buffer, enabling the DMA channel to receive data, and triggering the first soft interruption;
s6, in the first soft interrupt program, after transferring the data of the first buffer area to the FIFO memory, the DMA controller quits the first soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s7, when the data capacity received by the second buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the first buffer, enabling the DMA channel to receive data, and triggering a second soft interruption;
s8, in the second soft interrupt program, after transferring the data of the second buffer area to the FIFO memory, the DMA controller quits the second soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s9, executing steps S5-S8 in a circulating way until the communication is finished.
Further, the buffer capacity thresholds of the first buffer and the second buffer are equal.
Further, the DMA interrupt is a hard interrupt generated by the peripheral, and the first soft interrupt and the second soft interrupt are soft interrupts generated by the MCU process.
Further, the DMA interrupt has a higher priority than the first soft interrupt and the second soft interrupt.
Further, the FIFO memory includes a FIFO controller having a read pointer and a write pointer, and when the DMA controller performs a read or write operation on the FIFO memory, the FIFO controller changes the value of the read pointer or the write pointer accordingly.
Further, the FIFO controller reads or writes a FIFO memory reception threshold of data at a time.
The invention has the beneficial effects that: the data communication processing method adopted by the invention realizes a large amount of real-time data communication based on the combination of DMA double buffering and soft interruption, in a DMA interruption program, only the operation of switching the destination address of a DMA channel and triggering the soft interruption is executed, the data carrying operation is carried out in the soft interruption program, the CPU interruption can be caused by the DMA interruption, and the CPU interruption can not be caused by the soft interruption, so the DMA interruption cost is lower, the smaller CPU resource can be occupied when the CPU transaction is busy as much as possible, and the method has stronger advantages in a system with resource shortage and busy transactions.
Drawings
FIG. 1 is a data flow block diagram of an embodiment of the present disclosure;
FIG. 2 is a flow chart of the basic steps of an embodiment of the present disclosure;
fig. 3 is a block diagram of a specific implementation of an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The data communication processing method is suitable for real-time data communication of a system with resource shortage and busy affairs.
Referring to fig. 1-3, a data communication processing method of the present invention, based on DMA double buffering combined with soft interrupt, implements data communication between an MCU and an external device, where the MCU includes a serial port, an FIFO memory, a DMA controller, a memory, and a CPU, and the data flow direction is as shown in fig. 1, and data is transmitted between the memory of the MCU and the external device through a data bus; as shown in fig. 2, the method comprises the following steps:
s1, starting a serial port DMA receiving mode, configuring a FIFO memory and setting a receiving threshold value of the FIFO memory;
s2, opening up two receiving buffer areas in the memory, namely a first buffer area and a second buffer area;
s3, initializing the DMA controller, configuring a DMA channel between the peripheral and the memory, and setting the source address of the DMA channel as the data storage address of the peripheral;
s4, setting the destination address of the DMA channel as the address of the first buffer area, and enabling the DMA channel to receive data;
s5, when the data capacity received by the first buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the second buffer, enabling the DMA channel to receive data, and triggering the first soft interruption;
s6, in the first soft interrupt program, after transferring the data of the first buffer area to the FIFO memory, the DMA controller quits the first soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s7, when the data capacity received by the second buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the first buffer, enabling the DMA channel to receive data, and triggering a second soft interruption;
s8, in the second soft interrupt program, after transferring the data of the second buffer area to the FIFO memory, the DMA controller quits the second soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s9, executing steps S5-S8 in a circulating way until the communication is finished.
Further, the buffer capacity threshold of the first buffer and the second buffer are equal.
Further, the DMA interrupt is a hard interrupt generated by the peripheral, and the first soft interrupt and the second soft interrupt are soft interrupts generated by the MCU process.
Further, the DMA interrupt has a higher priority than the first soft interrupt and the second soft interrupt. The first soft interrupt and the second soft interrupt may be interrupted by other DMA interrupts to allow the system to process in time when a transaction request with a higher real-time requirement is received.
Further, the FIFO memory includes a FIFO controller, wherein the FIFO controller has a read pointer and a write pointer, and when the DMA controller performs a read or write operation on the FIFO memory, the FIFO controller changes the value of the read pointer or the write pointer accordingly.
Further, the FIFO controller therein reads or writes the data of the FIFO memory reception threshold value at a time.
When the received data of the FIFO memory does not reach the receiving threshold and new data is not received within a preset time period, the FIFO controller reads or writes all the existing data.
As shown in fig. 3, taking an STM32F103RCT6 chip as an example, a serial port is configured in a DMA reception mode, the first buffer and the second buffer are set to have capacity thresholds of 512 bytes, a DMA interrupt program executes switching of a destination address of a DMA channel and triggering of a soft interrupt, and the soft interrupt program executes transferring data from the first buffer or the second buffer to a FIFO memory.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and the present invention shall fall within the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.
Claims (6)
1. A data communication processing method is based on DMA double buffering combined with soft interruption to realize data communication between an MCU and an external device, wherein the MCU comprises a serial port, an FIFO memory, a DMA controller, an internal memory and a CPU; the method is characterized by comprising the following steps:
s1, starting a serial port DMA receiving mode, configuring a FIFO memory and setting a receiving threshold value of the FIFO memory;
s2, opening up two receiving buffer areas in the memory, namely a first buffer area and a second buffer area;
s3, initializing the DMA controller, configuring a DMA channel between the peripheral and the memory, and setting the source address of the DMA channel as the data storage address of the peripheral;
s4, setting the destination address of the DMA channel as the address of the first buffer area, and enabling the DMA channel to receive data;
s5, when the data capacity received by the first buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the second buffer, enabling the DMA channel to receive data, and triggering the first soft interruption;
s6, in the first soft interrupt program, after transferring the data of the first buffer area to the FIFO memory, the DMA controller quits the first soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s7, when the data capacity received by the second buffer reaches the buffer capacity threshold, generating DMA interruption, the CPU executing the DMA interruption program, switching the destination address of the DMA channel to the address of the first buffer, enabling the DMA channel to receive data, and triggering a second soft interruption;
s8, in the second soft interrupt program, after transferring the data of the second buffer area to the FIFO memory, the DMA controller quits the second soft interrupt program and returns to the main program, and the data in the FIFO memory is processed by the CPU;
s9, executing steps S5-S8 in a circulating way until the communication is finished.
2. The data communication processing method according to claim 1, wherein: the buffer capacity thresholds of the first buffer and the second buffer are equal.
3. The data communication processing method according to claim 1, wherein: the DMA interrupt is a hard interrupt generated by a peripheral, and the first soft interrupt and the second soft interrupt are soft interrupts generated by an MCU process.
4. The data communication processing method according to claim 1, wherein: the DMA interrupt has a higher priority than the first soft interrupt and the second soft interrupt.
5. The data communication processing method according to claim 1, wherein: the FIFO memory comprises a FIFO controller, the FIFO controller is provided with a reading pointer and a writing pointer, and when the DMA controller reads or writes the FIFO memory, the FIFO controller correspondingly changes the value of the reading pointer or the writing pointer.
6. The data communication processing method according to claim 5, wherein: the FIFO controller reads or writes a FIFO memory receive threshold of data at a time.
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