CN1095290C - Single board test apparatus for conference TV system - Google Patents

Abstract

The present invention relates to a single board test device for conference television systems, which is composed of a PC, a microprocessing unit, a conversion board, a back plate and a digital signal processing unit. A tested plate insertion slot is arranged on the back plate, and plates to be tested can be directly inserted into the test device for being tested. Excitation signals are added on the tested single plate, response signals of the tested plate are measured, and the device can judge whether the functions of the single plate are normal and whether the quality of a corresponding chip on the single plate is good according to whether the tested response signals are in a standard range.

Description

Single board test apparatus for conference TV system

The present invention relates to Image Communication, test more specifically to TV conference system.

Comprise veneers such as image coding and decoding plate, communication process plate, cradle head control box, network interface board, network exchange plate in the TV conference system.Veneer in the TV conference system has used many very lagre scale integrated circuit (VLSIC) special chips, digital signal processor, random asccess memory, programmable logic device etc.The production process complexity of veneer, the quality problems of the device that uses on each veneer itself or the error in the veneer production process all may cause the veneer cisco unity malfunction.In order to judge the veneer quality, need detect veneer.

In existing testing equipment, on-line testing view can only testing single-board on 74 * * path and the short circuit of family chip and veneer, can not detect other chips, can not detect the function of veneer.With on the online tester testing single-board 74 * * need special fixture during family chip, and the location hole of using to anchor clamps to be set on veneer.The quality of each veneer can only just can judge in machine debugging.Judge that in machine debugging the defective in quality general employing of which piece veneer substitutes exclusive method, efficient is very low, and efficient is lower when having several veneers to have quality problems.

The object of the present invention is to provide a kind of can testing session the tester of television system veneer function, can this tester can test out the veneer of TV conference system operate as normal, judges on the veneer quality with the function related chip.

Single board test apparatus for conference TV system among the present invention, by personal computer, keyset, postnotum is formed, described keyset is by the industrial standard architectures (ISA of switch, industrialstandard architecture) bus circuit, bus is isolated and long line transmission drive circuit, power on-off control circuit constitutes, wherein bus isolate and the defeated drive circuit of long line with the isa bus Signal Spacing of removing power supply signal in the personal computer and after driving the isa bus circuit by switch pass to postnotum, power on-off control circuit passes to postnotum with the power supply signal of the isa bus of the personal computer isa bus circuit by switch; Described postnotum is distributed by electric source filter circuit, clock generation circuit, HW (highway) line and constitutes from loop circuit, Board Under Test slot, wherein electric source filter circuit provides power supply signal for the postnotum slot, clock generation circuit provides clock signal for the postnotum slot, the HW line distributes and is used for controlling and switches HW signal in the postnotum slot from loop circuit, and the postnotum slot is used for providing slot for Board Under Test.

Single board test apparatus for conference TV system among the present invention, it is characterized in that: it also has a microprocessing unit and peripheral circuit thereof, and described microprocessing unit is made up of a CPU (CPU), a RAM (random asccess memory), an EPROM (erasable read-only memory), double port memory, bus driver and address decoding circuitry; Isa bus in the PC is undertaken behind bus driver and the address decoding by double port memory and CPU conversation test order and test data information by bus driver and address decoding circuitry, RAM links to each other by address, data and the control line of CPU with CPU, program and data storage areas as CPU, EPROM and CPU also be by CPU address, data and control line link to each other, as the storage area of sintering program; Described peripheral circuit can be a clock measuring circuit, and the clock signal after will changing by data, address, the control line of CPU is delivered among the CPU and counted; Described peripheral circuit also can be an audio signal generator, audio signal real effective change-over circuit and A/D (analog-to-digital conversion) circuit, the audio signal that described audio signal generator produces is delivered to Board Under Test, output to audio signal real effective change-over circuit and A/D (analog-to-digital conversion) circuit from Board Under Test again, the signal after the conversion is delivered to CPU detect; Described peripheral circuit can also be a serial line interface, a camera lens signaling conversion circuit, a The Cloud Terrace signaling conversion circuit, an infrared encoded signal generator, a programmable parallel interface chip, CPU produces infrared encoded signal by programmable parallel interface chip and infrared encoded signal generator and delivers to Board Under Test, delivering to CPU from the serial ports of Board Under Test by serial line interface again measures, CPU delivers to Board Under Test by the control signal that serial ports sends The Cloud Terrace and camera lens respectively, carry out level conversion by The Cloud Terrace signaling conversion circuit and camera lens signaling conversion circuit respectively from the signal of Board Under Test output The Cloud Terrace and camera lens, deliver to CPU by the programmable parallel interface chip again and detect.

Single board test apparatus for conference TV system among the present invention, it is characterized in that: it also has a digital signal processing unit, described digital signal processing unit is by a digital signal processor, a RAM, an EPROM, a serial/parallel change-over circuit, a HW (highway) line transmission circuit, a digital repeat circuit, a clock generation circuit, a double port memory, bus driver and address decoding circuitry are formed, the isa bus signal of PC carries out bus driver and address decoding through bus driver and address decoding circuitry, again by twoport memory circuit and digital signal processor conversation test order and test data information, RAM is by the data of digital signal processor, the address links to each other with digital signal processor with control line, EPROM is by the data of digital signal processor, the address links to each other with digital signal processor with control line, PC provides control signal for HW receipts/Power Generation Road, clock generation circuit provides clock signal for HW receipts/Power Generation Road, and the data-signal that sends from digital signal processor is converted to serial signal by serial/parallel change-over circuit with parallel signal and by HW receipts/Power Generation Road and digital junction chip the HW signal is received on the Board Under Test slot of postnotum.

Can also be provided with monitor jack, flying-spot video generator jack, microphone jack on the single board test apparatus for conference TV system postnotum in the present invention.

The present invention adopts the method for analog veneer operational environment, add pumping signal to tested single board, survey the response signal of tested single board again, whether judge within the limits prescribed according to the response signal that is recorded whether the function of veneer normally reaches the quality of relevant chip on the veneer.Because the tester among the present invention is provided with the tested single board slot, tested single board can directly be inserted tester and test, and location hole need be set on veneer, does not also need special fixture, and method of testing is simple.Can test each veneer before the TV conference system machine debugging with the tester among the present invention, and can directly judge the function of tested single board and the quality of relevant chip, efficient is higher.

The present invention will be described in detail below in conjunction with drawings and Examples.

Fig. 1 is the single board test apparatus for conference TV system The general frame.

Fig. 2 is microprocessing unit and peripheral circuit structured flowchart thereof.

Fig. 3 is the postnotum structured flowchart.

Fig. 4 is the keyset structured flowchart.

Fig. 5 is the digital signal processing unit structured flowchart.

Fig. 6 is image coding and decoding plate (VPB) test philosophy figure.

Fig. 7 is network exchange plate (NSB) test philosophy figure.

Fig. 8 is communication process plate (CPE1) test philosophy figure.

Fig. 9 is network interface board (NIE1) test philosophy figure.

Figure 10 is cradle head control box (CCTL) test philosophy figure.

Fig. 1 is the The general frame of single board test apparatus for conference TV system most preferred embodiment.In most preferred embodiment of the present invention, single board test apparatus for conference TV system has comprised PC 101, microprocessing unit 102, keyset 103, postnotum 104, digital signal processing unit 105.

Fig. 2 has provided the microprocessing unit in the tester and the details of peripheral circuit thereof.Microprocessing unit and peripheral circuit thereof be divided into CPU201, audio signal generator 208 and audio test signal circuit 207, infrared coding circuit 206, The Cloud Terrace signaling conversion circuit 205, camera lens signaling conversion circuit 204,, several parts such as serial line interface 203, double port memory 213, bus driver and address decoding circuitry 212.In the present embodiment, CPU adopts Intel 8031, and its peripheral circuit comprises that the RAM210 of system, EPROM211, system clock circuit 202, programmable parallel interface circuit 209 adopt 8255 chips.Common 8031 Single Chip Microcomputer (SCM) system of forming of CPU and its peripheral circuit are finished corresponding test job.Audio signal generator adopts waveform generation chip MAX038.This chip periphery circuit is few, control is simple, precision is high, and frequency band range is wide, can produce multiple waveforms such as sine wave, triangular wave, square wave.Audio signal real effective change-over circuit adopts AD536, and A/D adopts AD574, and both form the audio test signal circuit.Earlier convert direct voltage to from the audio signal of Board Under Test CPE1 plate output, be sent to AD574 again and be converted into digital signal by AD536.Infrared encoded signal is by emulation Infrared remote controller output on 8031, and The Cloud Terrace and camera lens corresponding action are detected by The Cloud Terrace and camera lens control signal test circuit, are sent to 8031 single-chip microcomputers after light-coupled isolation.The twoport memory circuit adopts two fifo chips.A slice is that PC writes data, 8031 system's reading of data.A slice is that 8031 systems write data, the PC reading of data.Two exchanges of finishing information between PC and the microprocessing unit jointly.PC bus driver and address decoding circuitry are finished the unidirectional drive of PC isa bus address signal A9～A0, address valid signal AEN, I/O port reads signal/IOR, I/O port write signal/IOW, reset signal RESPC, the bi-directional drive of data-signal D7～D0, functions such as I/O port address decoding.In the microprocessing unit voltage reference circuit can also be arranged, realize self-checking function.The peripheral circuit of microprocessor can also comprise watchdog circuit, and when stronger interference was arranged, it can make the Automatic Program of microprocessor reset.

Fig. 3 is the detailed composition diagram of tester postnotum.Postnotum is distributed by the isa bus circuit 401 of switch, clock generation circuit 302, electric source filter circuit 301, HW line and forms from loop circuit 303, also is provided with Board Under Test slot, microphone jack, flying-spot video generator jack, monitor jack on postnotum.In the present embodiment, clock generation circuit adopts digital phase-locked chip MT8941.This chip can produce the clock signal of 4M, 2M, 8K, can be operated in master-slave mode.When master mode was worked, this chip free oscillation produced 4M, 2M, 8K clock, and external circuit is synchronous with it.When mode is worked, need outside 8K frame synchronizing signal.4M, 2M, 8K clock that this chip produces are all synchronous with it.When tester was Auto-Sensing Mode, clock signal was delivered to microprocessing unit, was used to test the clock measuring circuit of microprocessing unit.When tester is test pattern, can provide the clock signal of 4M, 2M, 8K for tested NIE1 plate.Electric source filter circuit to from keyset+5V ,+12V ,-5V ,-the 12V power supply carries out the filtering of π type.Also have protective tube and power supply indicator in electric source filter circuit, protective tube is used to prevent power supply short circuit, the on off state of power supply indicator circuit indication power supply.When power supply disconnection and bus isolation, indicator light does not work.When power supply closure and the non-isolation of bus, indicator light is bright.Have long line transmission drive circuit in the isa bus of switch, finish the damping driving of output signal and input signal on socket receipts, prevent that reflected wave was to the interference of high-frequency signal when long line from transmitting.The HW line distributes and realizes that from loop circuit a road of HW line is assigned to eight road and eight tunnel functions from ring, is mainly used in the output HW line and the input HW line of test NIE1 plate.

Fig. 4 is the detailed composition diagram of keyset.Keyset is a circuit board that is inserted on the PC isa bus, is divided into PC isa bus 401, bus isolation and several parts such as long line transmission driving 402, mains switch control 403.Finish functions such as the isolation of the required isa bus signal of veneers such as TV conference system CPE1 plate, NIE1 plate, NSB plate, VPB plate, long line transmission driving, mains switch control.These signals are delivered to postnotum by the flat cable of two 50 cores.The isolation of signal is controlled by PC, during the plug Board Under Test, and Signal Spacing, during the test Board Under Test, signal communication.In the present embodiment, the PC isa bus is isolated and drive circuit, adopts 7,4HC,245 eight tunnel bi-directional drive chips, realizes that the three-state of isa bus signal is isolated and driving.When the plug Board Under Test, the isa bus signal is isolated.During Board Under Test, isa bus is non-isolation in test, damages Board Under Test when avoiding charged plug.Isa bus Chief Signal Boatswain line (1 meter) after long line transmission drive circuit is realized isolating is when being transferred to postnotum, the damping of signal drive and on socket receipts, eliminates the influence of reflected wave that long line transmits to high-frequency signal.Power on-off control circuit finishes+5V ,-5V ,+12V ,-the closed and disconnected control of 12V power supply, control signal is produced by PC.

Fig. 5 is the detailed composition diagram of digital signal processing unit.Digital signal processing unit is a test board that is inserted on the PC isa bus, and digital signal processing unit is divided into seven parts such as digital signal processor 503, digital junction circuit 504, HW line receipts/Power Generation Road 505, serial/parallel change-over circuit 506, twoport memory circuit 507, clock generation circuit 508, bus driver and address decoding circuitry 509.Finish the Board Functional Test, Board Function Test and the test of MCU overall performance of circuit boards such as TV conference system CPE1 plate, NIE1 plate, NSB plate.In the present embodiment, digital signal processor adopts high-speed dsp chip TMS320C50, and its peripheral circuit comprises high-speed RAM 501, EPROM502.The digital signal processing unit software systems are mainly finished unpacking and packing H.221, and H.221 code stream links to each other with CPE1 plate, NIE1 plate by the digital junction circuit, finishes the test of Board Under Test E1 interface circuit.HW line transmission circuit 505 adopts exchange chip MT8985 chip, finishes the test of NIE1 plate and NSB plate I/O HW line.Serial/parallel change-over circuit 506 adopts MT8920 chip, twoport memory circuit 507 to adopt twoport FIFO.Digital signal processing unit links to each other by the E1 interface of MT8920, digital junction circuit and Board Under Test, by information such as twoport FIFO and PC conversation test order and test datas.The digital junction circuit adopts thick film digital junction chip MH89790B.This chip periphery circuit is few, control simple, have AMI and HDB3 transfer encoding, transmission rate is 2048kbit/s, function such as CRC check is arranged.This chip links to each other with PC by MT8985, links to each other with digital signal processor with MT8920 by MT8985.The initialization of E1 interface is finished by PC.

Test philosophy and method from each veneer illustrates how the tester the present invention works below.1, method of testing Fig. 6 of image coding and decoding (VPB) plate is the test philosophy figure of image coding and decoding (VPB) plate.1, the control register of the chip of test pattern encoding and decoding (VPB) plate of 1 chip is the I/O mouth of PC, and read-write.Call over after writing with the software control order, identical as data, then specification interface circuit and chip operation are normal again.1,2 self-looped testings

Need a flying-spot video generator and a monitor during self-looped testing.Give the Board Under Test incoming video signal with flying-spot video generator, one, two, three encircles certainly with software control, observes the image of monitor output.If output is identical with the image of input, then the fourth stage is set from ring (promptly X.21 interface from ring) with wire jumper, observe output image.If output is identical with input picture, illustrate that then this plate is working properly.2, the method for testing of network exchange (NSB) plate

Fig. 7 is the test philosophy figure of network exchange (NSB) plate.2, the measurement of 1 clock frequency

The clock signal of the 4M of Board Under Test, 2M and 8K is delivered to the INT0 and the INT1 end of 8031 single-chip microcomputers respectively through behind the frequency division, calculates clock frequency by measuring pulse duration.If clock frequency is correct, illustrate that then 16.384M crystal oscillator and MT8941 are working properly.2, the test of 2 MT8985

Control register, data storage, the memory that continues by PC read-write MT8985 if read-write is normal, illustrate that then tested MT8985 is working properly.2, the test of 3 M34116

If control register, data register read-write by PC read-write M34116 are normal, illustrate that then tested M34116 is working properly.2,4 TMS320C50 H.221 frame structure locate, unpack, the software packaging test

Connect the E1 interface, plug the NIE1 plate, the operation TMS320C50 H.221 frame structure unpack, software packaging, to MCU transmission code stream H.221, MCU can correctly carry out frame alignment, unpack, packs, and guarantee that Board Under Test do not receive error code, like this with regard to integrated testability the stable row and the reliability of hardware and software of MCU.3, the method for testing of communication process (CPE1) plate

Fig. 8 is the test philosophy figure of communication process (CPE1) plate.3,1 self-looped testing, 3,1,1 X.21 interface self-looped testing

With pin 2 and 8,3 and 7, the 4 and 6 difference short circuits of socket X14 on the Board Under Test, every 8K interrupts writing earlier to the 51H of TMS320C50 mouth the data of 30Bits, reads then, if readout is identical with the value of writing, then test is passed through.3,1,2 E1 interface self-looped testings

Socket X5 on the Board Under Test and X6 short circuit are got up.Initialization MT8985 makes its HW1 HW2 that continues, the HW2 HW1 that continues, and the MH89790B that reinitializes makes it be operated in the outer shroud mode.TMS320C50 writes frame data to MT8920 continuously, reads back after the time-delay slightly again.Except that TSO and TS16, if read with write identical, then the test pass through.3, the test of 2 audio signals

The TMS320C50 serial port is initialized as the 16Bit burst mode, and AD55 is operated in the electrification reset state, from the audio signal of X8 input 2KHZ 1V.TMS320C50 the DRR register read to data write direct in the DXX register.The output signal of test X7, if amplitude is about 1V, then test is passed through.3, the test of 3 RAM and dual port RAM

The address ram of TMS320C50 is 8000H～FFFFH, and respectively to this address random writing and sense data, if identical, then test is passed through.The address realm of the dual port RAM of TMS320C50 is 6000H～7FFFH.The address realm of the dual port RAM of PC is determined by wire jumper X2.3,4 TMS320C50 H.221 frame structure locate, unpack, the software packaging test

Plug the VPB plate, the E1 interface connects the X.21 interface of CPE1 plate and VPB plate from ring,

Operation TMS320C50 H.221 frame structure unpack, software packaging, send H.221 to the E1 interface

Code stream, the CPE1 plate can correctly carry out frame alignment, unpack, packs, and guarantees not receive

To error code, like this with regard to integrated testability the stable row and the reliability of CPE1 plate hardware and software.

4, the method for testing of network interface (NIE1) plate

Fig. 9 is the test philosophy figure of network interface (NIE1) plate.4, the test of 1 dsp interface (Bt8510 and Bt8071A)

The E1 interface (MH89790B) of digital signal processor and the E1 interface of Board Under Test link to each other, and the clock of Board Under Test is produced by the MT8941 of test board.MT8985 sends the 2M code stream, and MT8985 receives the HW line data of Bt8510 output simultaneously, and whether comparing data is identical.MT8985 sends the 2M code stream to Bt8510, links to each other with MT8985 by the E1 interface, and whether comparing data is identical.MT8985 sends the PCM data to Bt8071A, and Bt8071A in dual port RAM, reads this data by TMS320C50 with storage, if identical with the PCM data that send, then Bt8071A is normal.

4, the test of 2 MT8920 and MT8985

The MT8985 of postnotum links to each other with the MT8920 of Board Under Test, MT8985, and MT8985 sends data to the HW line of MT8920, MT8985 input, receives the data on the output HW line simultaneously, and whether comparing data is identical.

4, the test of 3 RAM and dual port RAM

By TMS320C50 its RAM and dual port RAM are read and write, relatively read whether identical with the data that write.

4,4 TMS320C50 H.221 frame structure locate, unpack, the software packaging test

Connect the E1 interface, plug the NSB plate, the operation TMS320C50 H.221 frame structure unpack, software packaging, to MCU transmission code stream H.221, MCU can correctly carry out frame alignment, unpack, packs, and guarantee that Board Under Test do not receive error code, like this with regard to integrated testability the stable row and the reliability of hardware and software of MCU.

5, the method for testing of cradle head control (CCTL)

Figure 10 is test philosophy Fig. 5 of cradle head control (CCTL), the test of 1 infrared receiving circuit

Send corresponding infrared encoded signal to Board Under Test, receive the distant control function sign indicating number,, illustrate that then the chip operation of this plate control infrared signal is normal if be setting by the RS232 interface.5, the test of 2 The Cloud Terraces, camera lens signal circuit

Send the distant control function sign indicating number by the RS232 interface, detect The Cloud Terrace signal and camera lens signal,, illustrate that then The Cloud Terrace, camera lens signal circuit are working properly if corresponding signal is arranged.

Claims (4)

1, a kind of single board test apparatus for conference TV system is characterized in that: be made up of personal computer (101), keyset (103), postnotum (104); Wherein keyset (103) is industrial standard architectures (ISA) module, is inserted in any industrial standard architectures slot of personal computer (101), and keyset (103) links to each other with postnotum (104) by the isa bus of switch; Described keyset (103) is by the isa bus circuit (401) of switch, bus is isolated and defeated drive circuit (402) of long line and power on-off control circuit (403) formation, wherein bus isolate and the defeated drive circuit (402) of long line with the isa bus Signal Spacing of removing power supply signal in the personal computer (101) and after driving the isa bus circuit (401) by switch pass to postnotum (104), power on-off control circuit (403) passes to postnotum (104) with the power supply signal of the isa bus of personal computer (101) the isa bus circuit (401) by switch; Described postnotum is distributed by electric source filter circuit (301), clock generation circuit (302), HW line and constitutes from loop circuit (303), Board Under Test slot (304), wherein electric source filter circuit (301) provides power supply signal for postnotum slot (304), clock generation circuit (302) provides clock signal for postnotum slot (304), the HW line distributes and the HW signal in loop circuit (303) is used for control and switching postnotum slot (304), and postnotum slot (304) is used for providing slot for Board Under Test.

2, single board test apparatus for conference TV system according to claim 1, it is characterized in that: it also has a microprocessing unit and peripheral circuit thereof, and described microprocessing unit is formed (212) by a CPU (201), a random asccess memory (210), an erasable read-only memory (211), a double port memory (213), bus driver and address decoding circuitry; Isa bus in the personal computer (101) is undertaken passing through double port memory (213) and CPU (201) conversation test order and test data information behind bus driver and the address decoding by bus driver and address decoding circuitry (212), random asccess memory (210) and the address of CPU (201) by CPU (201), data link to each other with control line, program and data storage areas as CPU (201), erasable read-only memory (211) and CPU (201) be the address by CPU (201) also, data link to each other with control line, as the storage area of sintering program; Described peripheral circuit can be a clock measuring circuit (202), and the clock signal after will changing by data, address, the control line of CPU (201) is delivered in the CPU and counted; Described peripheral circuit also can be an audio signal generator (208), audio signal real effective change-over circuit and A/D (analog-to-digital conversion) circuit (207), the audio signal that described audio signal generator (208) produces is delivered to Board Under Test, output to audio signal real effective change-over circuit and A/D (analog-to-digital conversion) circuit (207) from Board Under Test again, the signal after the conversion is delivered to CPU detect; Described peripheral circuit can also be a serial line interface (203), a camera lens signaling conversion circuit (204), a The Cloud Terrace signaling conversion circuit (205), an infrared encoded signal generator (206), a programmable parallel interface chip (209), CPU (201) produces infrared encoded signal by programmable parallel interface chip (209) and infrared encoded signal generator (206) and delivers to Board Under Test, delivering to CPU from the serial ports of Board Under Test by serial line interface (203) again measures, CPU is delivered to Board Under Test by the control signal that serial ports sends The Cloud Terrace and camera lens respectively, carry out level conversion by The Cloud Terrace signaling conversion circuit (205) and camera lens signaling conversion circuit (204) respectively from the signal of Board Under Test output The Cloud Terrace and camera lens, deliver to CPU by programmable parallel interface chip (209) again and detect.

3, single board test apparatus for conference TV system according to claim 1 and 2, it is characterized in that: it also has a digital signal processing unit, described digital signal processing unit is by a digital signal processor (503), a random asccess memory (501), an erasable read-only memory (502), a serial/parallel change-over circuit (506), a HW line transmission circuit (505), a digital repeat circuit (504), a clock generation circuit (508), a double port memory (507), bus driver and address decoding circuitry (509) are formed, the isa bus signal of personal computer (101) carries out bus driver and address decoding through bus driver and address decoding circuitry (509), again by twoport memory circuit (507) and digital signal processor (503) conversation test order and test data information, random asccess memory (501) is by the data of digital signal processor (503), the address links to each other with digital signal processor (503) with control line, erasable read-only memory (502) is by the data of digital signal processor (503), the address links to each other with digital signal processor (503) with control line, personal computer (101) provides control signal for HW receipts/Power Generation Road (505), clock generation circuit (508) provides clock signal for HW receipts/Power Generation Road (505), and the data-signal that sends from digital signal processor (503) is converted to serial signal by serial/parallel change-over circuit (506) with parallel signal and by HW receipts/Power Generation Road (505) and digital junction chip (504) the HW signal is received on the Board Under Test slot of postnotum.

4, single board test apparatus for conference TV system according to claim 3 is characterized in that: also be provided with monitor jack, flying-spot video generator jack, microphone jack on the postnotum.

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