CN216956938U - Communication interface circuit of 40Gbps high-speed communication system based on FPGA - Google Patents

Abstract

The utility model discloses a communication interface circuit of a 40Gbps high-speed communication system based on an FPGA (field programmable gate array). A data adapter plate comprises a PCIE (peripheral component interface express) interface and a DDR4 multi-frame buffer; the high-speed baseband board comprises an AD _ RAM logic module, a DA _ RAM logic module and a JESD204B protocol module, the data transfer board and the high-speed baseband board both comprise optical fiber transceiving logic modules, the data transfer board and the high-speed baseband board are communicated through the optical fiber transceiving logic modules, a PCIE interface is communicated with an upper computer, a DDR4 multi-frame buffer is connected with the PCIE interface, data exchange is carried out between the PCIE interface and the upper computer, and the AD _ RAM logic module and the DA _ RAM logic module are subjected to data exchange with an AD daughter card and a DA daughter card through the JESD204B protocol module. The utility model constructs a complete high-speed communication system with 40Gbps in two directions from a transmitting end to a receiving end.

Description

Communication interface circuit of 40Gbps high-speed communication system based on FPGA

Technical Field

The utility model belongs to the field of high-speed data acquisition, and particularly relates to a communication interface circuit of a 40Gbps high-speed communication system based on an FPGA.

Background

With the rapid development of the internet industry, more and more terminal devices are incorporated into the internet, and the amount of data is explosively increased, and it is difficult for the existing communication network to support communication of such a large amount of data. It becomes extremely important to study communication modes with higher transmission rates.

Because of the advantages of large communication capacity, long transmission distance, small signal interference, good transmission quality and the like of the optical fiber, the optical fiber plays an increasingly important role in the field of communication. As the demand for hardware speed in industrial systems increases, the data communication rate between hardware also increases. Optical fibers are widely used for data exchange between hardware.

The field programmable gate array, namely the FPGA, is a product developed by a mature programmable device after PAL, GAL and CPLD, and has the characteristics of low delay, high connectivity and parallel transmission, so that the FPGA becomes one of the best platforms for realizing high-speed data transmission.

SUMMERY OF THE UTILITY MODEL

In order to achieve the purpose, the technical scheme of the utility model is as follows: a communication interface circuit of a 40Gbps high-speed communication system based on an FPGA (field programmable gate array) comprises a data adapter plate and a high-speed baseband plate, wherein the data adapter plate is connected with an upper computer and the high-speed baseband plate and used for realizing data transmission between the upper computer and the FPGA;

the data adapter board comprises a PCIE interface and a DDR4 multi-frame buffer; the high-speed baseband board comprises an AD _ RAM logic module, a DA _ RAM logic module and a JESD204B protocol module, the data transfer board and the high-speed baseband board both comprise optical fiber transceiving logic modules, the data transfer board and the high-speed baseband board are communicated through the optical fiber transceiving logic modules, a PCIE interface is communicated with an upper computer, a DDR4 multi-frame buffer is connected with the PCIE interface, data exchange is carried out between the PCIE interface and the upper computer, and the AD _ RAM logic module and the DA _ RAM logic module are subjected to data exchange with an AD daughter card and a DA daughter card through the JESD204B protocol module.

Preferably, the PCIE interface communicates with the upper computer by reading and writing an AXI bus.

Preferably, the DDR4 multi-frame buffer is directly connected to the PCIE interface through AXI Interconnect.

Preferably, the optical fiber transceiver logic module completes communication between the data patch panel and the high-speed baseband board through a four-channel SFP interface.

Preferably, the data exchange between the data patch board and the high-speed baseband board adopts an Aurora64b/66b high-speed serial protocol.

The beneficial effects of the utility model at least comprise:

1. the utility model has relatively complete functions, has QSFP, PCIE and DDR4 memory space and AD/DA daughter card, and constructs a complete high-speed communication system with 40Gbps in two directions from a transmitting end to a receiving end.

2. The data exchange between the upper computer and the data adapter plate adopts a PCI Express 3.0X 8 standard protocol, the communication rate theory is 8GT/s, the transmission speed is higher than that of USB 3.0, the data is not easy to lose, and the safety is higher;

3. the data exchange between the data adapter board and the high-speed baseband board adopts an Aurora64b/66b high-speed serial protocol. The data signal and the SFP optical fiber signal are mutually converted through an Aurora64b/66b high-speed serial protocol; the effective code rate of the Aurora64b/66b protocol can reach 96.97%, and the single-path bandwidth can reach 16.375Gbps at most. Under 156.25M clock, each path of data point is represented by 64 bits, 4 paths of data points are represented by 256 bits, 256 bits 156.25M can reach 40Gbps data transmission rate, and single-path SFP between the data transfer board and the high-speed baseband board can reach 10 Gbps;

4. the data exchange between the high-speed baseband board and the AD/DA daughter card adopts a JESD204B high-speed serial protocol, and the JESD204B high-speed serial protocol can convert optical fiber signals and stream data streams mutually.

Drawings

FIG. 1 is a block diagram of the overall architecture of a 40Gbps high-speed communication system based on FPGA according to the present invention;

FIG. 2 is a specific structure block diagram of the 40Gbps high-speed communication system based on FPGA;

FIG. 3 is a system interface diagram of an upper computer of the 40Gbps high-speed communication system based on the FPGA;

FIG. 4 is a waveform diagram of the fiber logic access of the 40Gbps high-speed communication system based on FPGA according to the present invention;

FIG. 5 is a waveform diagram of the fiber logic and RAM logic interaction of the FPGA-based 40Gbps high-speed communication system of the present invention;

FIG. 6 is an AD/DA signal transceiving diagram of a 40Gbps high-speed communication system based on FPGA according to the present invention;

FIG. 7 is a waveform diagram of the fiber logic recycled data of the 40Gbps high-speed communication system based on FPGA according to the present invention;

FIG. 8 is a data constellation diagram for transmitting and receiving 40Gbps high-speed communication system based on FPGA;

FIG. 9 is a DLL internal data format conversion diagram of the 40Gbps high-speed communication system based on the FPGA.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to fig. 1 and 2, a 40Gbps high-speed communication system based on FPGA includes an upper computer 10 and an FPGA portion, the FPGA portion includes a data adapter board 20, a high-speed baseband board 30, a DA daughter card 41 and an AD daughter card 42, wherein,

the upper computer 10 is connected with the data adapter board 20, the upper computer 10 comprises a parameter setting module 11 and a data drawing module 12, the parameter setting module 11 selects proper parameters to generate frame data, sends the data to the data adapter board 20, and receives control instructions and data transmitted by the FPGA part; the data drawing module 12 performs algorithm analysis on the recycled frame data, compares the data with the sent data, draws a corresponding constellation diagram, and completes the verification of the communication link;

the data adapter board 20 comprises a PCIE interface 21 and a DDR4 multiframe buffer 22, and further comprises an FPGA chip and a minimum system circuit thereof, which are not the distinguishing technical features of the present invention and are not described in detail; the high-speed baseband board 30 includes an AD _ RAM logic module 32, a DA _ RAM logic module 31, and a JESD204B protocol module 33, the data adaptor board 20 and the high-speed baseband board 30 also include an optical fiber transceiving logic module 23, the data adaptor board 20 communicates with the high-speed baseband board 30 through the optical fiber transceiving logic module 23, the PCIE interface 21 communicates with the upper computer 10, the DDR4 multi-frame buffer 22 is connected to the PCIE interface 21, and exchanges data with the upper computer 10 through the PCIE interface 21, and the AD _ RAM logic module 32 and the DA _ RAM logic module 31 exchange data with the AD daughter card 42 and the DA daughter card 41 through the JESD204B protocol module 33.

In one embodiment, the data adapter board 20 may be an XCKu040 card, and the high-speed baseband board 30 may be an XCVu11p card.

The PCIE interface 21 communicates with the upper computer 10 by reading and writing the AXI bus. The DDR4 multi-frame buffer 22 is directly connected to the PCIE interface 21 through the AXI Interconnect. The optical fiber transceiving logic module 23 completes the communication between the data patch panel 20 and the high-speed baseband panel 30 through a four-channel SFP interface. The data exchange between the data patch panel 20 and the high-speed baseband board 30 adopts an Aurora64b/66b high-speed serial protocol.

In the system, the FPGA part is divided into two parts:

one is the data patch panel 20 portion: the data transfer board 20 includes an XCKu040 board, and the part has two data paths, one is a memory mapping of the AXI bus, and the other is a register mapping interface of the AXI _ Lite. Through the former, PCIE data exchanged between the upper computer 10 and the XCKu040 board card can be directly mapped to the memory space of the DDR4 multi-frame buffer 22; through the latter, the control command exchanged between the upper computer 10 and the XCKu040 board card is mapped to the AXI _ Lite interface, so that the transmission of large data can be realized through the AXI bus interface, and the transmission of the control command can be realized through the AXI _ Lite interface. In addition, 4 AXI _ GPIOs are added for transmitting a write control command, a write completion control command of the upper computer 10, a read control command and a read completion control command, respectively. The upper computer 10 can monitor these control registers in real time and exchange lightweight data with them, which does not affect normal PCIE large data stream transmission.

Second, the high-speed base band plate 30 part: the high-speed baseband board 30 includes XCVu11p boards, and carries an AD daughter card 42 and a DA daughter card 41. The data adapter board 20 and the high-speed baseband board 30 are connected through a quad-channel optical fiber pluggable transceiver QSFP, data exchange follows an Aurora64b/66b protocol to convert data signals into optical fiber signals, the transmitted optical fiber signals are stored in a DA _ RAM logic module 31, high-speed data are transmitted to a DA daughter card 41 through a high-speed serial port through a JESD204B protocol, the DA daughter card 41 converts digital signals into analog signals, transmits the analog signals to an AD daughter card 42 through FIFO, converts the analog signals into digital signals through the high-speed AD daughter card 42 and transmits the digital signals back to an XCVu11p board card, and a JESD204B protocol converts high-speed serial data streams into stream data streams to be stored in the AD _ RAM logic module 32; then, the received stream data stream is converted into an optical fiber signal and sent to the optical fiber transceiving logic module 23, and the XCKu040 board converts the optical fiber signal into frame data through the optical fiber transceiving logic module 23 and stores the frame data in the memory space of the DDR4 multiframe buffer 22.

In the system, the upper computer 10 part is mainly divided into two parts: firstly, drawing an interface of the upper computer 10, and secondly, writing a DLL program to enable the MATLAB program to call PCIE drive to issue and receive data. The interface of the upper computer 10 includes various parameters and graphic drawing areas required for generating frame data. The MATLAB algorithm generates different frame data according to the parameters, and each bit of data is represented by 16 bits. After the MATLAB calls the DLL program, the DLL program firstly splits each bit of the frame data into a high 8 bit and a low 8 bit, then sends a write control instruction, and the PCIE interface 21 stores the data into the DDR4 memory space according to the write control instruction. And after the data is sent, the DLL program sends a write completion control instruction again to inform the XCKu040 board card that the data is sent completely. When the upper computer 10 receives data, the XCKu040 board transmits a read control instruction to the upper computer 10 through the PCIE interface 21, and after receiving the read control instruction, the DLL program starts to read data from the memory space of the DDR4 multi-frame buffer 22. After the reading is finished, the DLL program sends a reading finishing control instruction to the XCKu040 board card to notify the hardware upper computer 10 that the reading is finished. And performing data splicing on the read data according to a splitting rule, returning the spliced data to the upper computer 10, and completing link loop verification after verifying that the data is correct.

The communication method of the 40Gbps high-speed communication system based on the FPGA comprises the following steps:

s1, the upper computer 10 sends the frame data and the write control command to be issued to the DLL program;

s2, the DLL program calls the PCIE driver to send the data and the control instruction to the PCIE interface 21 of the data transfer board 20;

s3, the PCIE interface 21 stores the received data to the memory space of the corresponding DDR4 multi-frame buffer 22 according to the control instruction;

s4, after the upper computer 10 sends out a writing-finished control instruction, the data adapter board 20 converts the frame data into SFP optical fiber signals, and the optical fiber signals are internally transmitted by an Aurora64b/66b protocol;

s5, sending the SFP optical fiber signals to the high-speed baseband board 30, and storing the received optical fiber signals into the DA _ RAM logic module by the high-speed baseband board 30;

s6, converting the protocol into stream data stream, converting the stream data stream from JESD204B high-speed serial protocol into high-speed serial data and transmitting the high-speed serial data to the DA daughter card 41;

s7, the DA daughter card 41 converts the digital signal into an analog signal, sends the analog signal to the AD daughter card 42 through the FIFO, and converts the analog signal into a digital signal through the high-speed AD daughter card 42 and sends the digital signal back to the high-speed baseband board 30;

s8, converting the high-speed serial data stream into stream data stream by JESD204B protocol and storing the stream data stream into the AD _ RAM logic module 32;

s9, converting the received stream data stream into optical fiber signals and sending the optical fiber signals to the optical fiber transceiving logic module 23;

s10, converting the optical fiber signal into frame data through the optical fiber transceiving logic module 23 and storing the frame data in the memory space of the DDR4 multi-frame buffer 22;

s11, the data adapter board 20 transmits a read control command to the upper computer 10 through the PCIE interface 21;

s12, after the DLL program receives the read control instruction, the upper computer 10 reads the frame data buffered in the memory space of the DDR4 multi-frame buffer 22 to the upper computer 10 through the PCIE interface 21;

and S13, the upper computer 10 compares the received and transmitted data to verify whether the data link is opened.

The interface of the upper computer 10 is shown in fig. 3, a complete high-speed communication system platform with 40Gbps in two directions from a transmitting end to a receiving end is established, appropriate parameters are set on the interface of the upper computer 10 to generate transmitting data, appropriate AXI bus addresses and GPIO control instructions are selected, the transmitting data are clicked, then data are transmitted to an XCKu040 board card through a DLL program calling PCIE drive, the XCKu040 board card stores the data in a memory space of a DDR4 multiframe buffer 22, and an optical fiber reads the data from the memory space of the DDR4 multiframe buffer 22 through the FIFO, which is shown in fig. 4. Then, the data signal is converted into an SFP optical fiber signal through an Aurora64b/66b protocol, the optical fiber signal is transmitted to an XCVu11p board card, i.e., the high-speed baseband board 30, through a quad optical fiber pluggable transceiver QSFP, and after the optical fiber transceiving logic module 23 acquires data, data interaction with the AD _ RAM logic module 32 and the DA _ RAM logic module 31 is required, as shown in fig. 5. The XCVu11p board stores the received optical fiber signals into a DA _ RAM logic module, converts the optical fiber signals into stream data streams according to a protocol, converts the stream data streams from a JESD204B high-speed serial protocol into high-speed serial data and transmits the high-speed serial data to the DA daughter card 41, the DA daughter card 41 sends the data signals to the AD daughter card 42 through FIFO, converts the data into digital signals through the high-speed AD daughter card 42 and returns the digital signals to the XCVu11p board, and the data exchange between the high-speed baseband board 30 and the carried AD daughter card 42 and DA daughter card 41 is shown in FIG. 6. The JESD204B protocol module 33 converts the high-speed serial data stream into a stream data stream, stores the stream data stream into the AD _ RAM logic module 32, and then converts the received stream data stream into an optical fiber signal to be sent to the optical fiber transceiving logic module 23. The XCKu040 board receives the received data through the optical fiber processing logic module and temporarily stores the data in the memory space of the DDR4 multiframe buffer 22, and the optical fiber retrieves the data as shown in fig. 7. An XCKu040 board card, namely a data transfer board 20 transmits a read control instruction to an upper computer 10 through a PCIE interface 21, after a DLL program receives the read control instruction, the upper computer 10 reads frame data cached in a memory space of a DDR4 multi-frame buffer 22 to the MATLAB upper computer 10 through the PCIE interface 21, a data drawing module 12 of the upper computer 10 draws a constellation diagram of the received and sent data, and the drawing result is shown in FIG. 8. Due to the influence of the external environment and the error of the hardware of the AD daughter card 42 and the DA daughter card 41, the transmitted and received data may not be completely consistent. But the dotting conditions on the constellation diagram tend to be consistent, and the data can be considered to complete more accurate loop in the high-speed communication link.

The data transmission of the upper computer 10 is completed through a DLL (delay locked loop) program, a drive lays a foundation for constructing the DLL program, the DLL program which can be called by MATLAB (matrix laboratory) is generated according to the communication process of the PCIE (peripheral component interface express) reading and writing DDR4 multi-frame buffer 22 memory space, and the actual change can be well combined with an MATLAB algorithm. There are two main functions in the DLL program: respectively, a write function and a read function: the function completed by the write function is to read data and control instructions written into the DDR4 multi-frame buffer 22 provided in the MATLAB algorithm, and because 16 bits of signed data read from the MATLAB are used, and 8 bits of unsigned data are used in PCIE communication, negative number conversion and splitting are required in the write function; the read function is the inverse of the write function, and referring to fig. 9, MATLAB data is transferred from the host computer 10 to the memory space of the DDR4 multi-frame buffer 22 by calling the DLL program.

In practice, when the DLL program is used to receive the read control command, the upper computer 10 may not receive the control command in time, so that the setting of the read control command during programming is performed until the corresponding control command is received, and the program is not exited. If the hardware cannot feed back a control instruction to the upper computer 10 all the time, the DLL program can carry out program detection all the time, so that the program of the upper computer 10 is crashed, overtime detection is added into the control instruction detection program, and if the set detection time of 5 seconds is exceeded, the DLL program automatically exits and returns an error message to the MATLAB.

Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the utility model, and that, although the utility model has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the utility model as defined by the appended claims.

Claims (5)

1. A communication interface circuit of a 40Gbps high-speed communication system based on an FPGA (field programmable gate array) is characterized by comprising a data adapter plate and a high-speed base band plate, wherein the data adapter plate is connected with an upper computer and the high-speed base band plate and is used for realizing data transmission between the upper computer and the FPGA;

the data adapter board comprises a PCIE interface and a DDR4 multi-frame buffer; the high-speed baseband board comprises an AD _ RAM logic module, a DA _ RAM logic module and a JESD204B protocol module, the data switching board and the high-speed baseband board both comprise an optical fiber transceiving logic module, the data switching board and the high-speed baseband board are communicated through the optical fiber transceiving logic module, a PCIE interface is communicated with an upper computer, a DDR4 multi-frame buffer is connected with the PCIE interface, data exchange is carried out between the PCIE interface and the upper computer, and the AD _ RAM logic module and the DA _ RAM logic module are in data exchange with an AD daughter card and a DA daughter card through the JESD204B protocol module.

2. The communication interface circuit of 40Gbps high-speed communication system based on FPGA of claim 1, wherein said PCIE interface realizes communication with an upper computer through an AXI bus.

3. The communication interface circuit of the FPGA-based 40Gbps high-speed communication system of claim 1, wherein the DDR4 multi-frame buffer is directly connected to the PCIE interface through AXI Interconnect.

4. The communication interface circuit of 40Gbps high-speed communication system based on FPGA of claim 1, wherein the optical fiber transceiving logic module completes communication between the data patch panel and the high-speed baseband board through a four-channel SFP interface.

5. The communication interface circuit of 40Gbps high-speed communication system based on FPGA of claim 1, wherein the data exchange between the data patch board and the high-speed baseband board adopts Aurora64b/66b high-speed serial protocol.

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