CN109524385A - 具有绝缘分离体的半导体管芯接合焊盘 - Google Patents

具有绝缘分离体的半导体管芯接合焊盘 Download PDF

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Publication number
CN109524385A
CN109524385A CN201811093826.1A CN201811093826A CN109524385A CN 109524385 A CN109524385 A CN 109524385A CN 201811093826 A CN201811093826 A CN 201811093826A CN 109524385 A CN109524385 A CN 109524385A
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landing pad
contact zone
layer
metalization layer
semiconductor element
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CN109524385B (zh
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C.布雷特豪尔
B.劳梅尔
H.珀勒
M.施特夫雷夫
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

具有绝缘分离体的半导体管芯接合焊盘。一种半导体管芯包括在半导体衬底上方的最后金属化层;在最后金属化层上方的接合焊盘;保护层,其覆盖接合焊盘的部分并且具有限定接合焊盘的接触区的开口;绝缘区域,其至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离;以及导电互连结构,其在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层。还提供了相应的制造方法。

Description

具有绝缘分离体的半导体管芯接合焊盘
技术领域
本申请涉及半导体管芯,特别地涉及具有稳健的接合焊盘结构的半导体管芯。
背景技术
接合焊盘为半导体管芯提供外部电连接/探测(probing)的点。与4N(99.99%纯度)Au接合线组合的诸如NiP焊盘之类的硬的和化学稳定的无电镀(electroless-plated)接合焊盘已经被用于在半导体管芯的主动区(active areas)之上的探测和接合。然而,用于形成这种硬的接合焊盘的无电镀工艺是复杂且昂贵的。此外,无电镀接合焊盘易于在半导体管芯的最后金属化层中产生铜空洞(copper void)。这样,设计规则通常禁止在最上面的金属化层中的直接布线(direct routing)。否则,在无电镀接合焊盘侧的弱界面允许到接合焊盘的表面的铜迁移,这可以导致不期望的金属间相生长。
AlCu接合焊盘已经被用于汽车技术。然而,AlCu接合焊盘很容易产生势垒破裂(barrier cracks)并且因此具有低稳健性。取决于产品的类型,由探测引起的破裂可以是重大的可靠性风险。对于这些产品,通常提供附加的探测焊盘以适应晶圆探测,这增加了管芯大小并且因此增加了每个管芯的成本。
因此,存在对于可以以低成本方式生产的稳健的接合焊盘的需要。
发明内容
根据半导体管芯的实施例,所述管芯包括在半导体衬底上方的最后金属化层;在最后金属化层上方的接合焊盘;保护层,其覆盖接合焊盘的部分并且具有限定接合焊盘的接触区的开口;绝缘区域,其至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离;以及导电互连结构,其在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层。
根据制造半导体管芯的方法的实施例,所述方法包括:在半导体衬底上方形成最后金属化层;在最后金属化层上方形成接合焊盘;利用保护层覆盖接合焊盘的部分,所述保护层具有限定接合焊盘的接触区的开口;形成用于至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离的绝缘区域;以及形成在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层的导电互连结构。
在阅读下文的具体实施方式时并且在查看附图时,本领域中的技术人员将认识到附加的特征和优势。
附图说明
附图的元素不一定相对于彼此是按比例的。相同的附图标记指定相应的类似部分。可以将各种图示的实施例的特征组合,除非它们排除彼此。实施例在附图中被描绘并且在以下的描述中被详述。
图1图示了半导体管芯的实施例的局部截面图,所述半导体管芯具有接合焊盘、至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离的绝缘区域以及在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层的导电互连结构。
图2到图5图示了根据不同实施例的导电互连结构的各个平面图。
图6图示了在接合焊盘的探测期间的半导体管芯。
图7图示了在将引线接合到接合焊盘期间的半导体管芯。
图8A到图8F图示了制造半导体管芯的方法的实施例。
具体实施方式
本文中描述的实施例为半导体管芯提供了稳健和成本有效的接合焊盘。可以将本文中描述的接合焊盘用于在管芯的主动区之上的探测和在主动区之上的接合两者。绝缘区域至少在与接合焊盘的接触区相对应的区中将接合焊盘与管芯的最后(最上面的)金属化层分离,接触区是被探测和接合的接合焊盘的区。绝缘区域确保了高机械稳健性,并且在限定的技术限制内经受过度探测(over-probing)。在接合焊盘的限定的接触区的外部实现管芯的接合焊盘和最后金属化层之间的电连接。即使绝缘分离区域受损,例如,由于接合设备的误用,分离区域也使在附接到接合焊盘的接合线和在下面的管芯金属化层之间的金属间相形成最小化,从而确保电阻稳定性。通过结合例如2N(99%)纯度的Pd掺杂的Au接合线对本文公开的接合焊盘系统的使用确保了例如在175℃或更高处的至少3000小时的高温稳定性。Pd添加物减少了接合焊盘和接合线之间的金属间相生长并且减少了Kirkendal空洞的形成动力学。
图1图示了具有稳健和成本有效的接合100的半导体管芯的局部截面图。半导体管芯还包括半导体衬底102。可以使用任何标准类型的半导体衬底,诸如是单元素半导体(例如,Si、Ge等)、绝缘体上硅半导体、二元半导体(例如,SiC、GaN、GaAs等)、三元半导体等,具有或不具有(一个或多个)外延层。在图1中示出的半导体衬底102的部分是主动区,在其中形成诸如晶体管、二极管等之类的一个或多个设备。根据该实施例,在半导体管芯的主动区之上形成接合焊盘100和相应的衬垫(liner)104。可以形成包括在管芯的外围或边缘终止区域(termination region)中的主动区的外部的附加的接合焊盘,为了便于说明,其在图1中未被示出。
半导体管芯还包括在半导体衬底102上方形成的一个或多个结构化的金属化层106。半导体管芯通常包括多个金属化层。为了便于说明,仅将最后(最上面的)金属化层106在图1中示出。在半导体衬底102的主动区和(一个或多个)上覆的金属化层106之间的电连接由在图1中不可见的导电通孔形成。最后金属化层106包括金属或金属合金,诸如Cu、Cu合金、AlCu或Pt,以及相应的籽晶层或衬垫108,诸如Ta、W或Ti或其合金或氮化物中的一个或多个。在一些实施例中,最后金属化层106具有在0.5微米到5微米范围中的厚度,并且最后金属化层106被布置在例如诸如SiN之类的氮化物107'和诸如SiO2之类的氧化物107''的层间电介质107中。
接合焊盘100和相应的衬垫104被布置在最后金属化层106上方。保护层110覆盖接合焊盘100的部分并且具有限定接合焊盘100的接触区114的开口112。可以将接合焊盘接触区114的大小确定成虑及预期的金属间相生长和接合公差(tolerance)。可以在接触区114处探测并且接合接合焊盘100。绝缘区域116至少在与接合焊盘100的接触区114相对应的区中将接合焊盘100与最后金属化层106分离。这样,接合焊盘100至少在接触区114的区域中通过绝缘区域116与最后金属化层106分离。绝缘区域116可以包括绝缘材料的一个或多个层。在一个实施例中,绝缘区域116包括在最后金属化层106上的诸如SiN之类的氮化物层118和在氮化物层118上的诸如SiO2之类的氧化物层120。在另一个实施例中,绝缘区域116包括AlNi或SiC。还可以将其他类型的绝缘材料用于绝缘区域116。
导电互连结构122在接合焊盘100的接触区114的外部从接合焊盘100延伸到上金属化层106,以将接合焊盘100电连接到最后金属化层106。导电互连结构122的尺寸和布局取决于预期流过接合焊盘100的电流的量。
图2图示了导电互连结构122的实施例的俯视图。根据该实施例,连接结构122是在接合焊盘100的接触区114的外部将接合焊盘100连接到上金属化层106的金属环200。
图3图示了导电互连结构122的另一个实施例的俯视图。根据该实施例,连接结构122是在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的八边形金属环300。
图4图示了导电互连结构122的又一个实施例的俯视图。根据该实施例,连接结构122包括在接合焊盘100的接触区114的外部将接合焊盘100连接到上金属化层106的多个导电通孔400。
图5图示了导电互连结构122的又一个实施例的俯视图。根据该实施例,连接结构122包括在接合焊盘100的接触区114的外部将接合焊盘100连接到上金属化层106的多个金属条500。
导电互连结构122的其他尺寸和布局处于本文中描述的接合焊盘实施例的范围之内。
如上所述,可以例如在半导体管芯和在相同的半导体晶圆上制造的其他管芯的晶圆测试期间在接触区114处探测接合焊盘100。
图6图示了探测期间的接合焊盘100。使晶圆探针600在接触区114中与接合焊盘100接触。如上所述,绝缘区域116至少在与接合焊盘100的接触区114相对应的区中将接合焊盘100与最后金属化层106分离。这样,避免了在到下面的最后金属化层106的连接区122之上的对接合焊盘100的探测。并且,在过度探测的情况下,在接触区114中将接合焊盘100与最后金属化层106分离的绝缘区域116提供了抵抗破裂形成的高稳健性。即使由于过度探测接合焊盘接触区114而将在接合焊盘衬垫104中形成破裂,绝缘分离体区域116的存在也最小化在接合焊盘100的构成金属原子和接合到接合焊盘100的电导体的构成金属原子之间的后续金属间相生长。此外,经由在接合焊盘接触区114之下的衬垫104中形成的破裂的、从最后金属化层106到接合焊盘100的顶侧的铜或其他金属迁移也通过绝缘分离体区域116的存在被最小化。
图7图示了将诸如接合线之类的电导体700接合到接合焊盘100的接触区114之后的半导体管芯。在实施例中,接合焊盘100包括AlCu并且电导体700是2N(99%纯度)Au接合线。由于Al/Au/Pd金属间相生长,所谓的钉头702可以沿着接合焊盘100的接触区114横向地形成并且扩展。金属间相生长的量是退火条件和温度应力的量的函数。可以使用其他接合焊盘和电导体材料系统,由于在电导体700的构成金属原子和接合焊盘100的构成金属原子之间的金属间相生长,这可以导致相同或类似的钉头形成。电导体700可以与诸如Pd之类的添加物掺杂,所述添加物抑制在电导体700的构成金属原子和接合焊盘100的构成金属原子之间的金属间相生长。钯(Pd)对于减缓Au-Al相生长和Kirkendal空洞的形成动力学特别有效。
图8A到8F图示了制造半导体管芯的实施例,重点在于形成接合焊盘100、接合焊盘100和最后金属化层106之间的电互连结构122以及至少在与接合焊盘100的接触区114相对应的区域中将接合焊盘100与最后金属化层106分离的绝缘区域116。
在图8A中,在半导体衬底102上方形成最后金属化层106。如上所述,在图8A中示出了一个金属化层106。然而,半导体管芯通常包括多个金属化层。最后金属化层106通过层间电介质107从下面的金属化层或半导体衬底102分离,层间电介质107在图8A中图示为在诸如SiN之类的氮化物层107'上的诸如SiO2之类的氧化物层107''。还如上提及的那样,在半导体衬底102的主动区和(一个或多个)上覆的金属化层106之间的电连接通过在图8A中不可见的导电通孔形成。在实施例中,通过在籽晶层或衬垫108上沉积Cu、Cu合金、AlCu或Pt来形成最后金属化层107。
在图8B中,在最后金属化层106上形成层间电介质800。在实施例中,形成层间电介质800包括在最后金属化层106上形成诸如SiN之类的氮化物层118以及在氮化物层118上形成诸如SiO2之类的氧化物层120。在另一个实施例中,层间电介质800包括在最后金属化层106上形成的AlNi或SiC。还可以将其他类型的标准绝缘材料用于在最后金属化层106上形成的层间电介质800。
在图8C中,在布置在最后金属化层106上的层间电介质800中形成一个或多个开口802。可以通过标准的湿法或干法化学蚀刻、等离子体蚀刻等形成(一个或多个)开口802。将一个或多个开口802用于在接合焊盘100的接触区114外部形成在最后金属化层106和接合焊盘100之间的后续电连接。如上所述,在接合焊盘100和最后金属化层106之间的互连结构122可以包括如图2和图3中所示的金属环、如图4中所示的多个导电通孔、如图5中所示的多个金属条等。因此,在层间电介质800中形成的开口802的数量和形状取决于将形成的电互连结构122的尺寸和布局。
在图8D中,将诸如Ta、W或Ti或其合金或氮化物中的一个或多个之类的衬垫材料804沉积在层间电介质800上并且将诸如AlCu、Cu等之类的接合焊盘材料806沉积在衬垫804上。衬垫材料804和接合焊盘材料806填充先前在层间电介质800中形成的每个开口802。然后例如使用标准光刻和蚀刻工艺将衬垫材料804和接合焊盘材料806图案化以形成接合焊盘100和相应的衬垫104。保持填充在层间电介质800的每个开口802中的衬垫材料804和接合焊盘材料806在接合焊盘100的接触区114外部形成在接合焊盘100和最后金属化层106之间的导电互连结构122。直接位于接合焊盘接触区114下方并且由导电互连结构122横向限制的层间电介质800的部分形成绝缘区域116,该绝缘区域116至少在与接合焊盘接触区域114相对应的区中将接合焊盘100与最后金属化层106分离。
在图8E中,在形成最后金属化层106、绝缘区域116、接合焊盘100以及在接合焊盘100和最后金属化层106之间的导电互连结构122之后,在管芯之上形成毯状保护材料110。毯状保护110可以包括在诸如SiO2之类的氧化物的层810上的诸如SiN之类的氮化物的层808。
在图8F中,例如通过标准光刻和蚀刻在毯状保护材料110中形成开口112。毯状保护材料110中的开口112限定了接合焊盘100的接触区114。毯状保护材料110中的开口112比由导电互连结构122横向限制的并且将接合焊盘100与最后金属化层106分离的绝缘区域116窄。
然后可以在如图6中所示的在例如晶圆测试期间探测接合焊盘接触区114。例如如图7中所示,可以将电导体接合到接合焊盘100的接触区114。在实施例中,接合焊盘100包括AlCu并且电导体是与Pd掺杂的2N Au接合线。电导体可以在2N Au接合线的情况下与诸如Pd之类的添加物掺杂,以便抑制电导体的构成金属原子和接合焊盘100的构成金属原子之间的金属间相生长。
诸如“第一”、“第二”以及诸如此类的术语被用于描述各种元件、区域、部分等并且不旨在限制。相同的术语贯穿说明书指代相同的元素。
如本文中所使用的术语“具有”、“包含”、“包括”、“由……组成”以及诸如此类是指示所述元素或特征的存在、但不排除附加的元素或特征的开放式术语。除非上下文另有明确指示,否则冠词“一”、“一个”和“该”旨在包括复数以及单数。
将理解:除非另有明确说明,否则本文中描述的各种实施例的特征可以互相组合。
虽然本文中已说明和描述了具体实施例,但是本领域中的普通技术人员将理解:各种替代和/或等同实现可以在不脱离本发明的范围的情况下替代所示和描述的具体实施例。本申请旨在涵盖本文中所讨论的具体实施例的任何改编或变型。因此,意图在于本发明仅由权利要求书及其等同物限制。

Claims (20)

1.一种半导体管芯,包括:
在半导体衬底上方的最后金属化层;
在最后金属化层上方的接合焊盘;
保护层,其覆盖接合焊盘的部分并且具有限定接合焊盘的接触区的开口;
绝缘区域,其至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离;以及
导电互连结构,其在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层。
2.根据权利要求1所述的半导体管芯,其中最后金属化层包括Cu、Cu合金、AlCu或Pt。
3.根据权利要求1所述的半导体管芯,其中最后金属化层具有在0.5微米到5微米的范围中的厚度。
4.根据权利要求1所述的半导体管芯,其中导电互连结构包括在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的多个导电通孔。
5.根据权利要求1所述的半导体管芯,其中导电互连结构包括在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的金属环。
6.根据权利要求1所述的半导体管芯,其中导电互连结构包括在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的多个金属条。
7.根据权利要求1所述的半导体管芯,还包括接合到接合焊盘的接触区的电导体。
8.根据权利要求7所述的半导体管芯,其中接合焊盘包括AlCu,并且其中电导体是与Pd掺杂的2N Au接合线。
9.根据权利要求7所述的半导体管芯,其中电导体包括用于抑制在电导体的构成金属原子和接合焊盘的构成金属原子之间的金属间相生长的添加物。
10.根据权利要求1所述的半导体管芯,其中绝缘区域包括在最后金属化层上的氮化物层以及在氮化物层上的氧化物层。
11.根据权利要求1所述的半导体管芯,其中绝缘区域包括AlNi或SiC。
12.一种制造半导体管芯的方法,所述方法包括:
在半导体衬底上方形成最后金属化层;
在最后金属化层上方形成接合焊盘;
利用保护层覆盖接合焊盘的部分,所述保护层具有限定接合焊盘的接触区的开口;
形成用于至少在与接合焊盘的接触区相对应的区中将接合焊盘与最后金属化层分离的绝缘区域;以及
形成在接合焊盘的接触区的外部从接合焊盘延伸到上金属化层的导电互连结构。
13.根据权利要求12所述的方法,其中形成最后金属化层包括沉积Cu、Cu合金,AlCu或Pt。
14.根据权利要求12所述的方法,其中形成导电互连结构包括形成以下之一:
在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的多个导电通孔;
在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的金属环;以及
在接合焊盘的接触区的外部将接合焊盘连接到上金属化层的多个金属条。
15.根据权利要求12所述的方法,还包括将电导体接合到接合焊盘的接触区。
16.根据权利要求15所述的方法,其中接合焊盘包括AlCu,并且其中电导体是与Pd掺杂的2N Au接合线。
17.根据权利要求15所述的方法,还包括将电导体与添加物掺杂,用于抑制在电导体的构成金属原子和接合焊盘的构成金属原子之间的金属间相生长。
18.根据权利要求12所述的方法,其中形成绝缘区域包括:
在最后金属化层上形成氮化物层;以及
在氮化物层上形成氧化物层。
19.根据权利要求12所述的方法,其中形成绝缘区域包括在最后金属化层上形成AlNi或SiC。
20.根据权利要求12所述的方法,其中利用保护层覆盖接合焊盘的部分包括:
在形成最后金属化层、绝缘区域、接合焊盘以及导电互连结构之后沉积毯状保护材料;以及
在毯状保护材料中形成限定接合焊盘的接触区的开口,毯状保护材料中的开口比如由导电互连结构限定的绝缘区域窄。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640739A (zh) * 2020-05-29 2020-09-08 青岛歌尔智能传感器有限公司 光学传感器封装结构和电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541524A (en) * 1991-08-23 1996-07-30 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US20130093061A1 (en) * 2011-10-12 2013-04-18 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
CN103426861A (zh) * 2012-05-15 2013-12-04 英飞凌科技股份有限公司 功率半导体的可靠区域接合件
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
CN104867893A (zh) * 2014-02-21 2015-08-26 英飞凌科技股份有限公司 具有电容耦合的接合焊盘的功率晶体管管芯

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426481C (zh) * 2003-04-15 2008-10-15 富士通株式会社 半导体装置及其制造方法
US8581423B2 (en) * 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
US9214385B2 (en) * 2009-12-17 2015-12-15 Globalfoundries Inc. Semiconductor device including passivation layer encapsulant
US8659170B2 (en) * 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
US8779577B2 (en) * 2012-02-13 2014-07-15 Infineon Technologies Ag Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells
US9831122B2 (en) * 2012-05-29 2017-11-28 Globalfoundries Inc. Integrated circuit including wire structure, related method and design structure
US9035395B2 (en) * 2013-04-04 2015-05-19 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
US9018757B2 (en) * 2013-07-16 2015-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming bump structures over wide metal pad
US9502343B1 (en) * 2015-09-18 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy metal with zigzagged edges

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541524A (en) * 1991-08-23 1996-07-30 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US20130093061A1 (en) * 2011-10-12 2013-04-18 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
CN103426861A (zh) * 2012-05-15 2013-12-04 英飞凌科技股份有限公司 功率半导体的可靠区域接合件
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
CN104867893A (zh) * 2014-02-21 2015-08-26 英飞凌科技股份有限公司 具有电容耦合的接合焊盘的功率晶体管管芯

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640739A (zh) * 2020-05-29 2020-09-08 青岛歌尔智能传感器有限公司 光学传感器封装结构和电子设备

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