CN109507472B - Voltage detection method of memory test module - Google Patents
Voltage detection method of memory test module Download PDFInfo
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- CN109507472B CN109507472B CN201710826559.3A CN201710826559A CN109507472B CN 109507472 B CN109507472 B CN 109507472B CN 201710826559 A CN201710826559 A CN 201710826559A CN 109507472 B CN109507472 B CN 109507472B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
Abstract
The invention provides a voltage detection method of a memory test module, which comprises the following steps: reading a preset test condition; adjusting the test input signal to meet a preset test condition; adjusting the frequency and the working period of the test input signal to each test frequency and each test working period during the scanning period; judging the maximum voltage value and the minimum voltage value of the voltage output signal of the memory test module in the scanning period; when the maximum voltage value of the voltage output signal in the scanning period is judged, testing a first frequency and a first working period corresponding to the input signal; when the minimum voltage value of the voltage output signal in the scanning period is judged, the second frequency and the second working period corresponding to the input signal are judged; and recording the first and second frequencies and the first and second duty cycles.
Description
Technical Field
The present invention relates to a voltage detection method for a memory test module, and more particularly, to a voltage detection method for a memory test module under different input signals.
Background
Generally, to ensure that the memory module on the computer device or the server device can be used normally, the memory test module is used to perform a test before the design process is developed and produced. In detail, according to the content of the test, the tester needs to input different types of test signals, such as different current magnitudes, signal frequencies, and duty cycles, to the signal input node of the memory test module in sequence, and sequentially record the changes of the output voltages of the memory test module under the different types of test signals, and finally count the output voltages during the test to determine whether the output voltages are within a normal range.
However, the types of test signals to be tested are quite large, and besides the tester needs to adjust the test signals one by one to meet the test conditions, the tester also needs to correspondingly record and retrieve the output voltage of the memory test module, which is quite time-consuming. In addition, whether the test signal meets the test condition is judged by the self-calculation of the tester, so that the detected result is not accurate enough. Therefore, a better voltage detection method for the memory test module is still needed.
Disclosure of Invention
The invention mainly aims to provide a voltage detection method of a memory test module, which has the advantages of less time consumption and high accuracy.
In order to achieve the above object, the voltage detection method of the memory test module according to the present invention is to detect a memory test module installed on a motherboard to be tested through a detection module, wherein the detection module includes a signal generator and an oscilloscope, the signal generator is configured to generate an input signal to a signal input node of the memory test module, the oscilloscope is configured to receive at least one voltage output signal of the memory test module to generate a waveform diagram, and the voltage detection method of the memory test module includes, after determining the first frequency corresponding to the input signal and the first working cycle: reading a preset test condition, wherein the preset test condition at least comprises a minimum test current value, a maximum test current value, a plurality of test working period ranges and a plurality of test frequency ranges; adjusting the valley voltage value and the peak voltage value of the input signal according to the preset test condition so that the valley current value and the peak current value of the input current of the signal input node conform to the minimum test current value and the maximum test current value; adjusting the frequency and the duty cycle of the input signal to each of the test frequencies and the test duty cycles included in the preset test condition during a scanning period; judging the maximum voltage value and the minimum voltage value of the voltage output signal in the scanning period; determining a first frequency and a first duty cycle corresponding to the input signal according to a maximum voltage value of the voltage output signal during the scanning period; determining a second frequency and a second duty cycle corresponding to the input signal according to a minimum voltage value of the voltage output signal during the scanning period; and recording the first frequency, the first duty cycle, the second frequency and the second duty cycle.
Preferably, after determining the first frequency and the first working period corresponding to the input signal, the voltage detection method of the memory test module executes the following steps through the test motherboard: adjusting the frequency and the duty cycle of the input signal to the first frequency and the first duty cycle during a first sampling period; capturing a waveform diagram and a voltage value of the voltage output signal with a predetermined sampling quantity in the first sampling period; and recording the first frequency, the first duty cycle and the waveform and voltage values captured during the first sampling period to generate a first test report. In addition, after determining the second frequency and the second working period corresponding to the input signal, the voltage detection method of the memory test module executes the following steps through the test mainboard: adjusting the frequency and duty cycle of the input signal to the second frequency and the second duty cycle during a second sampling period; capturing a waveform diagram and a voltage value of the voltage output signal with a predetermined sampling quantity in the second sampling period; and recording the second frequency, the second duty cycle and the waveform and voltage values captured during the second sampling period to generate a second test report.
Preferably, during the scanning, the test motherboard further performs the following steps: (a) adjusting the frequency of the input signal to one of the test frequencies included in the preset test condition; (b) adjusting the working period of the input signal to one of the test working periods included in the preset test condition; (c) judging the relative maximum voltage value and the relative minimum voltage value of the voltage output signal in a preset time; (d) recording the relative maximum voltage value and the relative minimum voltage value of the voltage output signal in the preset time, and correspondingly recording the frequency and the work cycle of the current input signal; (e) if the duty cycle of the input signal has not been adjusted by all of the test duty cycles, adjusting the duty cycle of the input signal to another one of the test duty cycles, and returning to step (c); and (f) if the frequency of the input signal has not been adjusted by all the test frequencies, adjusting the frequency of the input signal to another one of the test frequencies, and returning to the step (b).
Preferably, in the voltage detection method of the memory test module, the test motherboard determines the maximum voltage value and the minimum voltage value of the voltage output signal during the scan period by comparing the relative maximum voltage value and the relative minimum voltage value of the voltage output signal during each of the predetermined time periods.
Preferably, the memory test module includes a main memory test board and at least one secondary memory test board, the main memory test board is coupled to the secondary memory test board through a bus, the signal input node is disposed on the main memory test board, the main memory test board has a first detection node, and the secondary memory test board has a second detection node for outputting the voltage output signal.
Preferably, the voltage detection method of the memory test module receives a current sensing signal of the first detection node of the memory test module through the oscilloscope; and the test mainboard judges whether the trough current value and the crest current value of the input current of the signal input node accord with the minimum test current value and the maximum test current value or not according to the current sensing signal.
Preferably, the predetermined test condition includes a slew rate, and the input signal is further adjusted to meet the slew rate.
Preferably, the test module includes an electronic loader electrically connected to the memory test module, and the voltage detection method of the memory test module controls the electronic loader to perform constant current extraction on the memory test module when the minimum test current value or the maximum test current value in a preset test condition exceeds a predetermined threshold.
Preferably, the test motherboard reads the predetermined test condition by parsing the specific file, text or data field.
Compared with the prior art, the voltage detection method of the memory test module can automatically adjust the test input signal input into the memory test module according to the preset test condition, and record the output change on the memory test module under the condition of different test input signals along with the change of the parameters (such as the test frequency and the test work period) of the test input signal, so as to further judge the critical value of the output signal, greatly shorten the time for detecting and adjusting the input test signal, reduce the artificial misjudgment and enable the detection result to be more accurate.
[ description of the drawings ]
Fig. 1 is a schematic diagram illustrating a detection system according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a voltage detection method of a memory test module according to an embodiment of the invention.
[ detailed description ] embodiments
The embodiments or examples shown in the figures are expressed in a specific manner as follows. It is to be understood that the embodiment or examples are not to be construed as limiting. Any alterations and modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.
Fig. 1 is a schematic diagram illustrating a detection system 100 according to an embodiment of the invention. As shown in fig. 1, the testing system 100 includes a testing module 110, a memory testing module 120, and a motherboard 130 to be tested. The testing module 110 includes a testing motherboard 112, a signal generator 114, an Oscilloscope 116 and an electronic load 118, wherein the testing motherboard 112 is communicatively connected to the signal generator 114, the Oscilloscope 116 and the electronic load 118, for example, via a GPIB Interface (General Purpose Interface Bus). The memory test module 120 includes a main memory test board 122, a sub memory test board 124 and 126, and the main memory test board 122, the sub memory test board 124 and 126 are electrically connected to each other through a bus. The memory test module 120 is mounted on the motherboard 130 to be tested, and more specifically, the main memory test board 122, the secondary memory test boards 124 and 126 are respectively mounted in each memory slot on the motherboard 130 to be tested. It should be understood that the number of memory test boards of the memory test module 120 may vary according to the test requirements or the specification of the motherboard 130 to be tested, and the embodiment is only for illustration and is not limited thereto.
In some embodiments of the present invention, when the test motherboard 112 starts testing, the test motherboard 112 (e.g., a host computer) can automatically parse specific files, text or data fields to read predetermined test conditions or user-entered test conditions, such as a minimum test current value, a maximum test current value, a Slew Rate (Slew Rate), whether the electronic load is used or not, a number of test duty cycles (duty cycles) and a number of test frequencies, and correspondingly control the signal generator 114, the oscilloscope 116 and the electronic load 118. In other words, when performing a test, the test motherboard 112 may control the signal generator 114 to generate the input signal Stest and receive the current sensing signal VIsen and the voltage output signals Vout1, Vout2 captured by the oscilloscope 116. In some embodiments, the signal generator 114 inputs the input signal Stest to the signal input node Nin on the main memory test board 122. On the other hand, the oscilloscope 116 receives the current sensing signal VIsen at the test node NIsen on the main memory test board 122, the voltage output signal Vout1 at the test node Nout1 on the secondary memory test board 124, and the voltage output signal Vout2 at the test node Nout2 on the secondary memory test board 126. The electronic load unit 118 is electrically connected to the memory test module 120, and when the minimum test current value or the maximum test current value in the preset test condition exceeds a predetermined threshold, the test motherboard 112 may control the electronic load unit 118 to perform constant current pumping and correspondingly adjust the input signal Stest to prevent the memory test module 120 from being overloaded. It should be understood that the predetermined threshold varies with the specification of the memory test module 120 and the number of memory test boards thereof.
The following describes the operation flow of the voltage detection method of the memory test module according to the present invention with reference to fig. 2 and fig. 1. First, in step S202, the test motherboard 112 automatically reads the preset test conditions. Next, in step S204, the test motherboard 112 determines whether the preset test condition indicates to enable the electronic load device 118, and if so, continues to step S208 to enable the electronic load device 118 for performing the constant current extraction. Otherwise, the process continues directly to step S206.
In step S208, the test board 112 controls the signal generator 114 to generate a corresponding input signal Stest according to the minimum test current value, the maximum test current value, and the slew rate in the preset test condition. In detail, the test motherboard 112 generates the input signal Stest having a waveform of a square wave and conforming to the slew rate by the control signal generator 114, and adjusts the valley voltage value and the peak voltage value of the input signal Stest until the valley current value and the peak current value of the input current of the signal input node Nin on the main memory test board 122 conform to the minimum test current value and the maximum test current value of the preset test condition. In some preferred embodiments, the test motherboard 112 further detects the current sensing signal VIsen of the detection node NIsen through the oscilloscope 116, and converts the valley current value and the peak current value of the input current of the current signal input node Nin according to the valley voltage value and the peak voltage value of the detected current sensing signal VIsen, thereby determining whether there is a minimum test current value and a maximum test current value meeting the predetermined test condition. It should be appreciated that the scaling manner and value may vary with the type of output voltage to be tested (e.g., Vdd, Vtt, Vpp, etc.).
In step S210, after the test motherboard 112 selects one of a plurality of test frequencies in the preset test condition, the signal generator 114 is controlled to adjust the frequency of the input signal Stest to the selected test frequency. Next, in step S212, the test motherboard 112 selects one of a plurality of test duty cycles in the predetermined test condition, and controls the signal generator 114 to adjust the duty cycle of the input signal Stest to the selected duty cycle.
In step S214, the test board 112 determines the relative maximum voltage value and the relative minimum voltage value of the voltage output signals Vout1 and Vout2 captured by the oscilloscope 116 within a predetermined time, and records the relative maximum voltage value and the relative minimum voltage value of the voltage output signals Vout1 and Vout2, and the frequency and duty cycle of the current input signal Stest. Next, in step S216, the test main board 112 determines whether the duty cycle of the input signal Stest has been adjusted over all test duty cycles in the preset test condition and has recorded the respective relative maximum voltage values and the relative minimum voltage values of the voltage output signals Vout1 and Vout2, if yes, proceed to step S220. On the contrary, step S218 is continued, the test host board 112 selects another one of a plurality of test duty cycles in the predetermined test condition, that is, selects a test duty cycle that has not yet been tested, and controls the signal generator 114 to set the duty cycle of the input signal Stest to the selected duty cycle, and then step S214 is returned to.
In step S220, the test main board 112 determines whether the frequency of the input signal Stest has been adjusted to all the test frequencies in the preset test conditions and performs the test, and if so, continues to step S224. On the contrary, step S222 is continued, the test host board 112 selects another one of the plurality of test frequencies in the predetermined test condition, that is, selects the test frequency that has not yet been tested, and controls the signal generator 114 to set the frequency of the input signal Stest to the selected frequency, and then step S212 is returned to.
In other words, during the scanning period from step S210 to step S220, the test motherboard 112 automatically controls the signal generator 114 to adjust the frequency and duty cycle of the input signal Stest to each test frequency and each test duty cycle in the preset test condition, thereby recording the relative maximum voltage value and the relative minimum voltage value of each voltage output signal Vout1, Vout2 under different frequencies and duty cycles of the input signal Stest. Next, in step S224, the test board 112 compares the records of the relative maximum voltage values of the voltage output signals Vout1 and Vout2 to determine which frequency and which duty cycle of the input signal Stest the voltage output signals Vout1 and Vout2 have the maximum voltage values. Similarly, the tester board 112 compares the records of the minimum voltage values of the voltage output signals Vout1 and Vout2 to determine which frequency and which duty cycle of the input signal Stest the voltage output signals Vout1 and Vout2 have the minimum voltage values. In other words, in step S224, when the test main board 112 determines that the voltage output signal Vout1 has the maximum voltage value within the scan period, the input signal Stest has a corresponding set frequency and a corresponding set duty cycle (hereinafter, referred to as a first frequency and a first duty cycle). When the test board 112 determines that the voltage output signal Vout1 has the minimum voltage value during the scan period, the input signal Stest has a corresponding set frequency and a corresponding set duty cycle (hereinafter referred to as a second frequency and a second duty cycle). Similarly, when the test board 112 determines that the voltage output signal Vout2 has the maximum voltage value during the scan period, the input signal Stest has a corresponding set frequency and a corresponding set duty cycle (hereinafter referred to as a third frequency and a third duty cycle). When the test board 112 determines that the voltage output signal Vout2 has the minimum voltage value during the scan period, the frequency and the duty cycle (hereinafter referred to as the fourth frequency and the fourth duty cycle) corresponding to the input signal Stest are set.
Finally, in step S226, the test motherboard 112 records the determined first frequency and first duty cycle, second frequency and second duty cycle, third frequency and third duty cycle, and fourth frequency and fourth duty cycle and automatically generates a corresponding test report. Preferably, after the first frequency and the first duty cycle, the second frequency and the second duty cycle, the third frequency and the third duty cycle, and the fourth frequency and the fourth duty cycle are obtained, the test motherboard 112 may further perform a test on each test node under the test input signals of the frequencies and the duty cycles.
For example, when the voltage output signal Vout1 at the test node Nout1 is further detected, the test board 112 controls the signal generator 114 to adjust the frequency and duty cycle of the input signal Stest to a first frequency and a first duty cycle, and then during the sampling period, the oscillograph and voltage value of the voltage output signal Vout1 at a predetermined sampling number are captured and recorded by the oscilloscope 116 to generate a test report when the voltage output signal Vout1 has the maximum voltage value. Then, the test motherboard 112 controls the signal generator 114 to adjust the frequency and duty cycle of the input signal Stest to a second frequency and a second duty cycle, and captures and records the waveform and voltage value of the voltage output signal Vout1 at a predetermined sampling number through the oscilloscope 116 during the sampling period, so as to generate a test report when the voltage output signal Vout1 has the minimum voltage value.
Similarly, when the voltage output signal Vout2 at the test node Nout2 is further detected, the test board 112 controls the signal generator 114 to adjust the frequency and duty cycle of the input signal Stest to a third frequency and a third duty cycle, and then during the sampling period, the oscillograph and voltage value of the voltage output signal Vout2 at a predetermined sampling number are captured and recorded by the oscilloscope 116 to generate a test report when the voltage output signal Vout2 has the maximum voltage value. Then, the test motherboard 112 controls the signal generator 114 to adjust the frequency and duty cycle of the input signal Stest to a fourth frequency and a fourth duty cycle, and captures and records the waveform diagram and voltage value of the voltage output signal Vout2 at a predetermined sampling number through the oscilloscope 116 during the sampling period, so as to generate a test report when the voltage output signal Vout2 has the minimum voltage value.
In summary, the present invention can automatically adjust the test input signal inputted to the memory test module according to the preset test condition, and record the output variation of the memory test module under different test input signals as the parameters (e.g., test frequency and test duty) of the test input signal change, so as to further determine the critical value of the output signal, thereby greatly shortening the time for detecting and adjusting the input test signal, reducing the human misjudgment, and making the detection result more accurate.
The methods of the present invention, or certain aspects or portions thereof, may take the form of program code. The program code may be embodied in tangible media, such as floppy diskettes, cd-roms, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine thereby becomes an apparatus for practicing the invention. The program code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique apparatus that operates analogously to specific logic circuits.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A voltage detection method of a memory test module is characterized in that: a memory test module installed on a mainboard to be tested is detected through a detection module, the detection module comprises a signal generator and an oscilloscope, the signal generator is used for generating an input signal to a signal input node of the memory test module, the oscilloscope is used for receiving at least one voltage output signal of the memory test module and generating a waveform diagram, and the voltage detection method of the memory test module comprises the following steps executed through a test mainboard:
reading a preset test condition, wherein the preset test condition at least comprises a minimum test current value, a maximum test current value, a plurality of test working period ranges and a plurality of test frequency ranges;
adjusting the valley voltage value and the peak voltage value of the input signal according to the preset test condition so that the valley current value and the peak current value of the input current of the signal input node conform to the minimum test current value and the maximum test current value; adjusting the frequency and duty cycle of the input signal to each of the test frequencies and the test duty cycles included in the predetermined test condition during a scan period; judging the maximum voltage value and the minimum voltage value of the voltage output signal in the scanning period;
determining a first frequency and a first duty cycle corresponding to the input signal according to a maximum voltage value of the voltage output signal during the scanning period;
determining a second frequency and a second duty cycle corresponding to the input signal according to a minimum voltage value of the voltage output signal during the scanning period; and
recording the first frequency, the first duty cycle, the second frequency and the second duty cycle,
after determining the first frequency and the first working period corresponding to the input signal, the test motherboard executes the following steps:
adjusting the frequency and the duty cycle of the input signal to the first frequency and the first duty cycle during a first sampling period;
capturing a waveform diagram and a voltage value of the voltage output signal with a predetermined sampling quantity in the first sampling period; and
recording the first frequency, the first duty cycle and the waveform and voltage values captured during the first sampling period to generate a first test report;
after the second frequency and the second working period corresponding to the input signal are determined, the following steps are executed through the test mainboard:
adjusting the frequency and duty cycle of the input signal to the second frequency and the second duty cycle during a second sampling period;
capturing a waveform diagram and a voltage value of the voltage output signal with a predetermined sampling quantity in the second sampling period; and
and recording the second frequency, the second duty cycle and the waveform and voltage values captured during the second sampling period to generate a second test report.
2. The method of claim 1, wherein: during the scanning period, the test motherboard further executes the following steps:
(a) adjusting the frequency of the input signal to one of the test frequencies included in the preset test condition;
(b) adjusting the working period of the input signal to one of the test working periods included in the preset test condition;
(c) judging the relative maximum voltage value and the relative minimum voltage value of the voltage output signal in a preset time;
(d) recording the relative maximum voltage value and the relative minimum voltage value of the voltage output signal in the preset time, and correspondingly recording the frequency and the work cycle of the current input signal;
(e) if the duty cycle of the input signal has not been adjusted by all of the test duty cycles, adjusting the duty cycle of the input signal to another one of the test duty cycles, and returning to step (c);
(f) if the frequency of the input signal has not been adjusted by all the test frequencies, adjusting the frequency of the input signal to another one of the test frequencies, and returning to the step (b).
3. The method of claim 2, wherein: the test mainboard judges the maximum voltage value and the minimum voltage value of the voltage output signal in the scanning period by comparing the relative maximum voltage value and the relative minimum voltage value of the voltage output signal in each set time.
4. The method of claim 1, wherein: the memory test module comprises a main memory test board and at least one auxiliary memory test board, wherein the main memory test board is coupled to the auxiliary memory test board through a bus, the signal input node is arranged on the main memory test board, the main memory test board is provided with a first detection node, and the auxiliary memory test board is provided with a second detection node for outputting the voltage output signal.
5. The method of claim 4, wherein the step of detecting the voltage of the memory test module comprises:
receiving a current sensing signal of the first detection node of the memory test module through the oscilloscope; and the test mainboard judges whether the trough current value and the crest current value of the input current of the signal input node accord with the minimum test current value and the maximum test current value or not according to the current sensing signal.
6. The method of claim 1, wherein: the predetermined test condition further includes a slew rate, and the input signal is further adjusted to meet the slew rate.
7. The method of claim 1, wherein: the detection module further comprises an electronic loading machine electrically connected to the memory test module, and the voltage detection method of the memory test module comprises the following steps: when the minimum test current value or the maximum test current value in the preset test condition exceeds a preset threshold value, the test mainboard controls the electronic load machine to carry out constant current extraction on the memory test module.
8. The method of claim 1, wherein:
the test motherboard reads the predetermined test condition by analyzing the specific file, text or data field.
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| JPH06230043A (en) * | 1993-02-02 | 1994-08-19 | Hitachi Ltd | Voltage detecting circuit |
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| US7663418B2 (en) * | 2008-01-03 | 2010-02-16 | Nanya Technology Corp. | Driving circuit slew rate compensation method |
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