CN109507472A - The voltage detection method of memory test module - Google Patents
The voltage detection method of memory test module Download PDFInfo
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- CN109507472A CN109507472A CN201710826559.3A CN201710826559A CN109507472A CN 109507472 A CN109507472 A CN 109507472A CN 201710826559 A CN201710826559 A CN 201710826559A CN 109507472 A CN109507472 A CN 109507472A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
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Abstract
The present invention provides a kind of voltage detection method of memory test module, comprising: reads default test condition；Test input signal is adjusted to meet default test condition；During scanning, the frequency of Test input signal and duty cycle are adjusted to each test frequency and each test job period；Judge maximum voltage value and minimum amount of voltage that of the voltage output signal of memory test module during scanning；When judging maximum voltage value of the voltage output signal during scanning, first frequency corresponding to Test input signal and the first duty cycle；When judging minimum amount of voltage that of the voltage output signal during scanning, second frequency corresponding to input signal and the second duty cycle；And note down the first, second frequency and the first, second duty cycle.
Description
Technical field
The invention relates to a kind of voltage detection methods of memory test module, particularly relate in varying input signal
Under memory test module voltage detecting method.
Background technique
In general, in order to ensure the memory module on computer installation or server unit can be used normally,
R & D design process so that production before, can all be tested using memory test module.Specifically, it tests
Personnel need the content according to test, sequentially input different types of test to the signal input node of memory test module and believe
Number, for example, different size of current, signal frequency, duty cycle etc., and sequentially write down and believe in these different types of tests
The variation of output voltage in number lower memory test module arranges the output voltage during counting test again finally to judge to be
It is no to have in normal range.
However, the test signal type that need to be tested is quite a lot of, tester is in addition to needing to adjust test letter one by one
Number to meet the outer of test condition, it is also necessary to which corresponding record and the output voltage for capturing memory test module quite consume
It is time-consuming.Further, since whether test signal meets test condition and all voluntarily calculated by tester to judge, also it be easy to cause
The result that detected is not accurate enough.Therefore, it is still necessary to a kind of voltage detection method of preferable memory test module.
Summary of the invention
The main purpose of the present invention is to provide a kind of time-consuming few, the voltage detectings of the high memory test module of accuracy rate
Method.
In order to achieve the above object, the voltage detection method of memory test module of the present invention is to pacify through detection module to detect
Loaded on the memory test module on a mainboard to be measured, above-mentioned detection module includes a signal generator and an oscillograph,
And a signal input node of the above-mentioned signal generator to generate an input signal to above-mentioned memory test module, it is above-mentioned to show
Wave device is to receive an at least voltage output signal for above-mentioned memory test module to generate waveform diagram, above-mentioned memory test
The voltage detection method of module includes determining above-mentioned first frequency and above-mentioned first work corresponding to above-mentioned input signal
After making the period: reading a default test condition, and above-mentioned default test condition includes at least a minimum test current value, a maximum
Test current value, several test job periodic regimes and several test frequency ranges；According to above-mentioned default test condition
To adjust the peak voltage value of above-mentioned input signal with peak voltage value so that the wave of the input current of above-mentioned signal input node
Paddy electricity flow valuve and peak current value meet above-mentioned minimum test current value and above-mentioned full test current value；In a sweep time
Between, the frequency of above-mentioned input signal and duty cycle are adjusted to each above-mentioned test frequency included by above-mentioned default test condition
Rate and each above-mentioned test job period；Judge maximum voltage value and minimum of the above-mentioned voltage output signal during above-mentioned scanning
Voltage value；According to maximum voltage value of the above-mentioned voltage output signal during above-mentioned scanning, determine corresponding to above-mentioned input signal
A first frequency and one first duty cycle；According to minimum amount of voltage that of the above-mentioned voltage output signal during above-mentioned scanning,
Determine a second frequency corresponding to above-mentioned input signal and one second duty cycle；And it is the above-mentioned first frequency of record, above-mentioned
First duty cycle, above-mentioned second frequency and above-mentioned second duty cycle.
Preferably, the voltage detection method of memory test module determines above-mentioned corresponding to above-mentioned input signal
One frequency and after above-mentioned first duty cycle executes following steps through above-mentioned test motherboard: during one first sampling,
The frequency of above-mentioned input signal and duty cycle are adjusted to above-mentioned first frequency and above-mentioned first duty cycle；Above-mentioned first
During sampling, the waveform diagram and voltage value of the set quantity of sampling quantity of above-mentioned voltage output signal one are captured；And record above-mentioned first
The waveform diagram and voltage value captured during frequency, above-mentioned first duty cycle and above-mentioned first sampling is to generate one first survey
Examination report.In addition, the voltage detection method of memory test module, determines above-mentioned second frequency corresponding to above-mentioned input signal
Rate and after above-mentioned second duty cycle executes following steps through above-mentioned test motherboard:, will be upper during one second sampling
It states the frequency of input signal and the duty cycle adjusts to above-mentioned second frequency and above-mentioned second duty cycle；In above-mentioned second sampling
Period captures the waveform diagram and voltage value of the set quantity of sampling quantity of above-mentioned voltage output signal one；And the above-mentioned second frequency of record,
The waveform diagram and voltage value captured during above-mentioned second duty cycle and above-mentioned second sampling is reported with generating one second test
It accuses.
Preferably, during above-mentioned scanning, above-mentioned test motherboard more executes following steps: (a) by above-mentioned input signal
Frequency one of adjust to above-mentioned test frequency included by above-mentioned default test condition；(b) by the work of above-mentioned input signal
Make one of above-mentioned test job period included by period modulation to above-mentioned default test condition；(c) judge that above-mentioned voltage is defeated
Relative maximum voltage value of the signal in a given time and relatively minimal voltage value out；(d) above-mentioned voltage output signal is noted down
Relative maximum voltage value and relatively minimal voltage value in above-mentioned given time, and the current above-mentioned input signal of corresponding record
Frequency and duty cycle；It, will if (e) duty cycle of above-mentioned input signal not yet adjusted all above-mentioned test job periods
The duty cycle of above-mentioned input signal adjusts to the another one in above-mentioned test job period, and returns to step (c)；And if (f)
The frequency of above-mentioned input signal not yet adjusted all above-mentioned test frequencies, then adjusted the frequency of above-mentioned input signal to above-mentioned
The another one of frequency, and return to step (b).
Preferably, the voltage detection method of memory test module, above-mentioned test motherboard are defeated through more above-mentioned voltage
Relative maximum voltage value of the signal in each above-mentioned given time and relatively minimal voltage value are out to judge that above-mentioned voltage output is believed
Maximum voltage value and minimum amount of voltage that number during above-mentioned scanning.
Preferably, above-mentioned memory test module includes a main memory test board and at least one secondary memory test
Plate, above-mentioned main memory test board are coupled to above-mentioned secondary memory test plate through bus, and above-mentioned signal input node is set to
Above-mentioned main memory test board, and above-mentioned main memory test board has one first detection node, above-mentioned pair memory test plate
With one second detection node to export above-mentioned voltage output signal.
Preferably, the voltage detection method of memory test module receives above-mentioned memory test through above-mentioned oscillograph
One current sensing signal of above-mentioned first detection node of module；And above-mentioned test motherboard is according to above-mentioned current sensing signal
To judge whether trough current value and the peak current value of the input current of above-mentioned signal input node meet above-mentioned minimum test
Current value and above-mentioned full test current value.
Preferably, above-mentioned default test condition includes single-revolution rate, and above-mentioned input signal be more adjusted it is above-mentioned to meet
Revolution rate.
Preferably, above-mentioned detection module includes that an E-load machine is electrically connected to above-mentioned memory test module, and on
The voltage detection method for stating memory test module, when the above-mentioned minimum in default test condition tests current value or above-mentioned maximum
When testing current value more than a set threshold values, above-mentioned test motherboard control E-load machine is to above-mentioned memory test module
It carries out constant current and takes out load.
Preferably, above-mentioned test motherboard is through the specific archives of parsing, text or data field to read above-mentioned default survey
Strip part.
Compared to the prior art, the voltage detection method of memory test module of the present invention, can be according to default test-strips
Part automatically adjusts the Test input signal for being input to memory test module, and (e.g., with the parameter of Test input signal
Test frequency and test job period) change, record is in the case where different Test input signals in memory test module
Output variation, further differentiates the critical value of output signal, and detection is greatly shortened and adjusts the time of input test signal,
Reduce artificial erroneous judgement, keeps testing result more accurate.
[Detailed description of the invention]
Fig. 1 is the schematic diagram for showing detection system described in an embodiment according to the present invention.
Fig. 2 is the running stream for showing the voltage detection method of memory test module described in an embodiment according to the present invention
Journey.
[specific embodiment]
Expression in a specific way as described below is shown in embodiment or example in diagram.It will be appreciated that the embodiment or example are simultaneously
It is non-to limit.The replacement and modification of any embodiment of the present invention, and any of principle of the present invention further apply, for
There is usual operator can complete with reference to present specification in field of the present invention.
1st figure is the schematic diagram for showing detection system 100 described in an embodiment according to the present invention.As shown in Fig. 1, it examines
Examining system 100 includes detection module 110, memory test module 120 and mainboard to be measured 130.Detection module 110 includes surveying
Try motherboard 112, signal generator (function generator) 114, oscillograph (Oscilloscope) 116 and electronics
Load machine 118, test motherboard 112 and signal generator 114, oscillograph 116 and E-load machine 118 communicate to connect, example
Such as, it is connected through the interface GPIB (General Purpose Interface Bus).Memory test module 120 includes main memory
Reservoir test board 122, secondary memory test plate 124 and 126, and main memory test board 122, secondary memory test plate 124
And 126 be electrically connected to each other through bus.Memory test module 120 is installed on mainboard 130 to be measured, specifically, main
Memory test plate 122, secondary memory test plate 124 and 126 are respectively arranged in each memory bank on mainboard 130 to be measured
In.It will be understood that the quantity of 120 memory reservoir test board of memory test module can be according to test request or mainboard to be measured
130 specification and change, embodiment is only to for example, be not limited to this.
In some embodiment of the invention, when test motherboard 112 starts to be tested, test motherboard 112 is (e.g.,
Main frame) specific archives, text or data field can be parsed automatically to read default test condition or user's key
The test condition entered, e.g., minimum test current value, full test current value, revolution rate (Slew Rate), E-load machine
Using whether, several test job periods (duty cycle) and several test frequencies etc., then correspondingly control news
Number generator 114, oscillograph 116 and E-load machine 118.In other words, when testing, motherboard 112 is tested
Controllable signal generator 114 can receive the current sense letter that oscillograph 116 captures to generate input signal Stest
Number VIsen and voltage output signal Vout1, Vout2.In some embodiments, signal generator 114 is by input signal
Stest is input to the signal input node Nin on main memory test board 122.On the other hand, oscillograph 116 then receives main memory
The current sensing signal VIsen of detection node NIsen on reservoir test board 122, detection node on secondary memory test plate 124
The voltage output signal of detection node Nout2 on the voltage output signal Vout1 and pair memory test plate 126 of Nout1
Vout2.E-load machine 118 and 120 electrical connection of memory test module, when the minimum test electric current in default test condition
When value or full test current value are more than a set threshold values, test motherboard 112 can control E-load machine 118 to carry out constant current
It takes out and carries, and accordingly adjust input signal Stest, to avoid memory test module 120 from overloading.It will be understood that with storage
The difference of the specification of device test module 120 and the quantity of its memory test plate, set threshold values be not also identical.
Illustrate the fortune of the voltage detection method of memory test module of the invention with the 2nd figure and the 1st figure of cooperation below
Make process.Firstly, test motherboard 112 automatically reads default test condition in step S202.Then in step S204
In, test motherboard 112 judges whether default test condition indicates to enable E-load machine 118, if so, then continuing step S208
E-load machine 118 is enabled so that electric current is fixed and takes out load.Anti-, then continue directly to step S206.
In step S208, test motherboard 112 is according to minimum the test current value, full test in default test condition
Current value, revolution rate control signal generator 114 to generate corresponding input signal Stest.Specifically, motherboard is tested
112, which will control signal generator 114, generates wave mode as square wave and meets the input signal Stest of revolution rate, and adjusts input letter
The peak voltage value and peak voltage value of number Stest, until the input of signal input node Nin on main memory test board 122
The trough current value and peak current value of electric current meet the minimum test current value and full test electric current of default test condition
Value.In some preferred embodiments, test motherboard 112 more detects the electric current sense of detection node NIsen through oscillograph 116
Signal VIsen is surveyed, and is converted at present according to the peak voltage value of the current sensing signal VIsen detected and peak voltage value
The trough current value and peak current value of the input current of signal input node Nin, judge whether there is meet default test whereby
The minimum test current value and full test current value of condition.It will be understood that not with the output voltage type to be tested
With (for example, Vdd, Vtt or Vpp etc.), the mode and numerical value of conversion be would also vary from.
In step S210, after test motherboard 112 selects one of several test frequencies in default test condition,
Signal generator 114 is controlled again, and the frequency of input signal Stest is adjusted to selected test frequency.Then, in step S212
In, test 112 reselection of motherboard presets one of several test job periods in test condition, and controls signal generation
The duty cycle of input signal Stest is adjusted to the selected duty cycle by device 114.
In step S214, test motherboard 112 judges the voltage output that oscillograph 116 is captured in a given time
The respective relative maximum voltage value of signal Vout1, Vout2 and relatively minimal voltage value, and note down voltage output signal Vout1,
The respective relative maximum voltage value and relatively minimal voltage value of Vout2 and frequency and the work week of current input signal Stest
Phase.Then in step S216, test motherboard 112 judges that whether trained the duty cycle of input signal Stest is default
The respective relative maximum electricity in all test job periods and recorded voltage output signal Vout1, Vout2 in test condition
Pressure value and relatively minimal voltage value, if so, continuing step S220.Anti-, then continue step S218, test motherboard 112 selects
The another one in several test job periods in default test condition is selected, also that is, the test job week that selection was not tested yet
Phase, and control signal generator 114 and set the selected duty cycle for the duty cycle of input signal Stest, return step
Rapid S214.
In step S220, test motherboard 112 judges the whether trained default test of the frequency of input signal Stest
It all test frequencies in condition and is tested, if so, continuing step S224.Anti-, then continue step S222, tests
Motherboard 112 selects the another one of several test frequencies in default test condition, also that is, the test that selection was not tested yet
Frequency, and controlling signal generator 114 for the set of frequency of input signal Stest is selected frequency, returns step S212.
In other words, in step S210 to during the scanning between step S220, test motherboard 112 automatically controls news
The frequency of input signal Stest and duty cycle are adjusted into default test condition each test frequency and each by number generator 114
The test job period notes down the different frequency and work of each voltage output signal Vout1, Vout2 in input signal Stest whereby
Relative maximum voltage value and relatively minimal voltage value under period.Then in step S224, test motherboard 112 compares electricity
Press the record of each relative maximum voltage value of output signal Vout1, Vout2 to judge that voltage output signal Vout1, Vout2 exist
There is maximum voltage value duty cycle under which frequency of input signal Stest and which.Similarly, test motherboard 112 compares
The record of relatively minimal voltage value each to voltage output signal Vout1, Vout2 with judge voltage output signal Vout1,
Vout2 has minimum amount of voltage that duty cycle under which frequency of input signal Stest and which.In other words, in step
In S224, when test motherboard 112 judges that voltage output signal Vout1 has maximum voltage value during scanning, input letter
The corresponding frequency being arranged of number Stest and duty cycle (hereinafter referred to as, first frequency and the first duty cycle).Test motherboard
112 when judging that voltage output signal Vout1 has minimum amount of voltage that during scanning, the corresponding setting of input signal Stest
Frequency and duty cycle (hereinafter referred to as, second frequency and the second duty cycle).Similarly, test motherboard 112 judges electricity
When pressing output signal Vout2 that there is maximum voltage value during scanning, the corresponding frequency and work being arranged of input signal Stest
Make period (hereinafter referred to as, third frequency and third duty cycle).Test motherboard 112 judges that voltage output signal Vout2 exists
When having minimum amount of voltage that during scanning, the corresponding frequency being arranged of input signal Stest and duty cycle are (hereinafter referred to as,
4th frequency and the 4th duty cycle).
Finally in step S226, test motherboard 112 notes down judged first frequency and the first duty cycle, second
Frequency and the second duty cycle, third frequency and third duty cycle, the 4th frequency and the 4th duty cycle are simultaneously automatically generated
Corresponding test report.Preferably, test motherboard 112 is obtaining first frequency and the first duty cycle, second frequency and the
It, can be still further directed to each after two duty cycles, third frequency and third duty cycle, the 4th frequency and the 4th duty cycle
Detection node is detected under the Test input signal of those frequencies and duty cycle.
For example, when the voltage output signal Vout1 for detection node Nout1 is further detected, host is tested
Plate 112 controls signal generator 114 and the frequency of input signal Stest and duty cycle is adjusted to first frequency and the first work
Period captures through oscillograph 116 then during sampling and recording voltage output signal Vout1 is in a set quantity of sampling quantity
Waveform diagram and voltage value, test report when generating voltage output signal Vout1 with maximum voltage value.Then, it tests
Motherboard 112 controls signal generator 114 and the frequency of input signal Stest and duty cycle is adjusted to second frequency and second
Duty cycle captures through oscillograph 116 during sampling and recording voltage output signal Vout1 is in a set quantity of sampling quantity
Waveform diagram and voltage value, to generate test report of the voltage output signal Vout1 with minimum amount of voltage that when.
Similarly, when the voltage output signal Vout2 for detection node Nout2 is further detected, motherboard is tested
The frequency of input signal Stest and duty cycle are adjusted to third frequency and third work week by 112 control signal generators 114
Phase captures through oscillograph 116 then during sampling and recording voltage output signal Vout2 is in a set quantity of sampling quantity
Waveform diagram and voltage value, to generate test report of the voltage output signal Vout2 with maximum voltage value when.Then, test master
Machine plate 112 controls signal generator 114 and the frequency of input signal Stest and duty cycle is adjusted to the 4th frequency and the 4th work
Make the period, the acquisition of oscillograph 116 simultaneously wave of the recording voltage output signal Vout2 in a set quantity of sampling quantity is penetrated during sampling
Shape figure and voltage value, to generate test report of the voltage output signal Vout2 with minimum amount of voltage that when.
Memory test module is input in conclusion can automatically adjust according to default test condition through the present invention
Test input signal, and as the parameter of Test input signal (e.g., test frequency and test job period) changes, record
Output variation in the case where different Test input signals in memory test module, further differentiates the critical of output signal
Value is greatly shortened detection and adjusts the time of input test signal, decreases artificial erroneous judgement, keep testing result more smart
It is quasi-.
Method of the invention or specific kenel or its part can exist with the kenel of procedure code.Procedure code may include
In tangible media, such as floppy disk, disc, hard disk or any other machine-readable (such as computer-readable) storage media,
Or it is not limited to the computer program product of external form, wherein when procedure code is by machine, when being loaded into and execute such as computer,
This machine becomes to participate in the device of the invention.Procedure code can also penetrate some transmission media, such as electric wire or cable, light
Fine or any transmission kenel is transmitted, wherein when procedure code is by machine, when receiving, be loaded into and execute such as computer, this
Machine becomes to participate in the device of the invention.In general service processing unit implementation, procedure code combination processing unit is mentioned
The unique apparatus using particular logic circuit is similar to for an operation.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
It covers in protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of voltage detection method of memory test module, it is characterised in that: be installed on through a detection module to detect
A memory test module on one mainboard to be measured, above-mentioned detection module include a signal generator and an oscillograph, and on
State a signal input node of the signal generator to generate an input signal to above-mentioned memory test module, above-mentioned oscillograph
To receive an at least voltage output signal for above-mentioned memory test module and generate waveform diagram, above-mentioned memory test module
Voltage detection method include through one test motherboard execute following steps:
A default test condition is read, and above-mentioned default test condition includes at least minimum test a current value, a full test
Current value, several test job periodic regimes and several test frequency ranges；
The peak voltage value and peak voltage value that above-mentioned input signal is adjusted according to above-mentioned default test condition are so that above-mentioned letter
The trough current value and peak current value of the input current of number input node meet above-mentioned minimum test current value and it is above-mentioned most
Big test current value；During a scanning, the frequency of above-mentioned input signal and duty cycle are adjusted to each above-mentioned test frequency
With each above-mentioned test job period included in above-mentioned default test condition；Judge that above-mentioned voltage output signal is swept above-mentioned
Maximum voltage value and minimum amount of voltage that during retouching；
According to maximum voltage value of the above-mentioned voltage output signal during above-mentioned scanning, determine one corresponding to above-mentioned input signal
First frequency and one first duty cycle；
According to minimum amount of voltage that of the above-mentioned voltage output signal during above-mentioned scanning, determine one corresponding to above-mentioned input signal
Second frequency and one second duty cycle；And the above-mentioned first frequency of record, above-mentioned first duty cycle, above-mentioned second frequency with
And above-mentioned second duty cycle.
2. the voltage detection method of memory test module according to claim 1, it is characterised in that: determine above-mentioned input
Above-mentioned first frequency corresponding to signal and after above-mentioned first duty cycle executes following step through above-mentioned test motherboard
It is rapid:
During one first sampling, the frequency of above-mentioned input signal and duty cycle are adjusted to above-mentioned first frequency and above-mentioned the
One duty cycle；
During above-mentioned first sampling, the waveform diagram and voltage value of the set quantity of sampling quantity of above-mentioned voltage output signal one are captured；With
And the waveform diagram and voltage value captured during the above-mentioned first frequency of record, above-mentioned first duty cycle and above-mentioned first sampling
To generate one first test report.
3. the voltage detection method of memory test module according to claim 2, it is characterised in that: determine above-mentioned input
Above-mentioned second frequency corresponding to signal and after above-mentioned second duty cycle executes following step through above-mentioned test motherboard
It is rapid:
During one second sampling, the frequency of above-mentioned input signal and duty cycle are adjusted to above-mentioned second frequency and above-mentioned the
Two duty cycles；
During above-mentioned second sampling, the waveform diagram and voltage value of the set quantity of sampling quantity of above-mentioned voltage output signal one are captured；With
And the waveform diagram and voltage value captured during the above-mentioned second frequency of record, above-mentioned second duty cycle and above-mentioned second sampling
To generate one second test report.
4. the voltage detection method of memory test module according to claim 1, it is characterised in that: in above-mentioned sweep time
Between, above-mentioned test motherboard more executes following steps:
One of (a) adjust the frequency of above-mentioned input signal to above-mentioned test frequency included by above-mentioned default test condition；
(b) duty cycle of above-mentioned input signal was adjusted to the above-mentioned test job period included by above-mentioned default test condition
One of；
(c) judge relative maximum voltage value of the above-mentioned voltage output signal in a given time and relatively minimal voltage value；
(d) relative maximum voltage value and relatively minimal voltage value of the above-mentioned voltage output signal in above-mentioned given time are noted down,
And frequency and the duty cycle of the corresponding current above-mentioned input signal of record；
If (e) duty cycle of above-mentioned input signal not yet adjusted all above-mentioned test job periods, above-mentioned input is believed
Number duty cycle adjust to the another one in above-mentioned test job period, and return to step (c)；
If (f) frequency of above-mentioned input signal not yet adjusted all above-mentioned test frequencies, by the frequency of above-mentioned input signal
It adjusts to the another one of said frequencies, and returns to step (b).
5. the voltage detection method of memory test module according to claim 4, it is characterised in that: above-mentioned test host
Relative maximum voltage value and relatively minimal voltage value of the plate through more above-mentioned voltage output signal in each above-mentioned given time
To judge maximum voltage value and minimum amount of voltage that of the above-mentioned voltage output signal during above-mentioned scanning.
6. the voltage detection method of memory test module according to claim 1, it is characterised in that: above-mentioned memory is surveyed
Die trial block includes that a main memory test board and at least one secondary memory test plate, above-mentioned main memory test board penetrate bus
It is coupled to above-mentioned secondary memory test plate, above-mentioned signal input node is set to above-mentioned main memory test board, and above-mentioned main memory
Reservoir test board has one first detection node, and above-mentioned pair memory test plate has one second detection node above-mentioned to export
Voltage output signal.
7. the voltage detection method of memory test module according to claim 6, it is characterised in that:
A current sensing signal of above-mentioned first detection node of above-mentioned memory test module is received through above-mentioned oscillograph；With
And above-mentioned test motherboard judges the trough electricity of the input current of above-mentioned signal input node according to above-mentioned current sensing signal
Whether flow valuve and peak current value meet above-mentioned minimum test current value and above-mentioned full test current value.
8. the voltage detection method of memory test module according to claim 1, it is characterised in that: above-mentioned default test
Condition further includes single-revolution rate, and above-mentioned input signal is more adjusted to meet above-mentioned revolution rate.
9. the voltage detection method of memory test module according to claim 1, it is characterised in that: above-mentioned detection module
It further includes an E-load machine and is electrically connected to above-mentioned memory test module, and the voltage detecting of above-mentioned memory test module
Method includes: when the above-mentioned minimum in default test condition tests current value or above-mentioned full test current value is more than a set valve
When value, above-mentioned test motherboard control E-load machine takes out load to carry out constant current to above-mentioned memory test module.
10. the voltage detection method of memory test module according to claim 1, it is characterised in that:
Above-mentioned test motherboard is through the specific archives of parsing, text or data field to read above-mentioned default test condition.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110762794A (en) * | 2019-10-31 | 2020-02-07 | 广东美的制冷设备有限公司 | Power supply voltage determining method and device, compressor and air conditioner |
| CN113409855A (en) * | 2021-05-11 | 2021-09-17 | 珠海博雅科技有限公司 | Reference current determination method and device of nonvolatile memory unit and storage medium |
| WO2023168796A1 (en) * | 2022-03-08 | 2023-09-14 | 长鑫存储技术有限公司 | Data analysis method and apparatus, and storage medium |
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| WO2023168796A1 (en) * | 2022-03-08 | 2023-09-14 | 长鑫存储技术有限公司 | Data analysis method and apparatus, and storage medium |
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