CN109144024B - Integrated circuit chip and inspection method thereof - Google Patents
Integrated circuit chip and inspection method thereof Download PDFInfo
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- CN109144024B CN109144024B CN201710599260.9A CN201710599260A CN109144024B CN 109144024 B CN109144024 B CN 109144024B CN 201710599260 A CN201710599260 A CN 201710599260A CN 109144024 B CN109144024 B CN 109144024B
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000007689 inspection Methods 0.000 title claims description 11
- 238000001514 detection method Methods 0.000 claims abstract description 114
- 230000007704 transition Effects 0.000 claims abstract description 60
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 101100441892 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CPR7 gene Proteins 0.000 description 4
- 101100459905 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NCP1 gene Proteins 0.000 description 3
- 101150046305 cpr-1 gene Proteins 0.000 description 3
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0208—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the configuration of the monitoring system
- G05B23/0213—Modular or universal configuration of the monitoring system, e.g. monitoring system having modules that may be combined to build monitoring program; monitoring system that can be applied to legacy systems; adaptable monitoring system; using different communication protocols
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
Abstract
An integrated circuit chip and a method of inspecting the same. A target circuit of the integrated circuit chip generates a target signal. A transition detection circuit of the integrated circuit chip detects a transition of the target signal during initialization to generate a transition detection result. And judging whether the initialization of the target circuit is normal or not according to the conversion detection result.
Description
Technical Field
The present invention relates to a chip, and more particularly, to an integrated circuit chip and a method for inspecting the same.
Background
The integrated circuit chip contains a plurality of circuit modules. These circuit blocks cooperate with each other. When initialization of any of these circuit blocks fails, the integrated circuit chip is often disabled. For example, when a voltage regulator (voltage regulator) inside the integrated circuit chip is damaged and cannot supply a power voltage to other circuit modules, the circuit modules cannot operate normally. When the ic chip fails, an expensive tester is required to obtain a target signal (e.g., a power voltage outputted from a voltage regulator) of a target circuit in the ic chip by using a probe to monitor whether the target circuit is initialized properly in order to find a problematic node.
Disclosure of Invention
The invention provides an integrated circuit chip and a checking method thereof, which are used for self-monitoring the conversion of a target signal.
The embodiment of the invention provides a method for checking an integrated circuit chip. The inspection method comprises the following steps: generating a target signal by a target circuit of an integrated circuit chip; detecting, by a transition (slew) detection circuit of the integrated circuit chip, a transition of the target signal during initialization to generate a transition detection result; and judging whether the initialization of the target circuit is normal or not according to the conversion detection result.
In an embodiment of the invention, the inspection method further includes: the level of the target signal is detected by a level detection circuit of the integrated circuit chip to generate a level detection result.
In an embodiment of the invention, the inspection method further includes: when the level of the target signal does not reach the rated level in the first period and the slew rate (slew rate) of the target signal is not 0, the slew rate of the target signal is increased by the target circuit so that the level of the target signal reaches the rated level in the rated period.
In an embodiment of the invention, the inspection method further includes: recording the conversion detection result in a first register (register) within the integrated circuit chip; and a second register that records the level detection result within the integrated circuit chip.
In an embodiment of the invention, the step of determining whether the initialization of the target circuit is normal includes: when the level of the target signal reaches the rated level within the rated period, determining that the target circuit is initialized to be normal; when the level of the target signal does not reach the rated level in the rated period and the conversion rate of the target signal is not 0, judging that the target circuit is initialized to be normal; and determining that the initialization of the target circuit has failed when the level of the target signal does not reach the rated level within the rated period and the slew rate of the target signal is almost 0.
Embodiments of the invention provide an integrated circuit chip. The integrated circuit chip includes a target circuit and a transition detection circuit. The target circuit is used for generating a target signal. The transition detection circuit is coupled to the target circuit. The transition detection circuit is used for detecting the transition of the target signal during the initialization period to generate a transition detection result.
In an embodiment of the invention, the integrated circuit chip further includes a level detection circuit. The level detection circuit is coupled to the target circuit. The level detection circuit is used for detecting the level of the target signal to generate a level detection result.
In an embodiment of the invention, when the level of the target signal does not reach the rated level in the first period and the slew rate of the target signal is not 0, the target circuit increases the slew rate of the target signal so that the level of the target signal reaches the rated level in the rated period.
In an embodiment of the invention, the transition detection result is recorded in a first register of an integrated circuit chip, and the level detection result is recorded in a second register of the integrated circuit chip.
In an embodiment of the invention, the target circuit includes a power supply circuit, a feedback circuit and a voltage comparison circuit, and the transition detection circuit includes a filter. The power supply circuit provides a power supply voltage as a target signal. The feedback circuit is coupled to the power supply circuit to receive the power supply voltage, and the feedback circuit provides the feedback voltage. The voltage comparison circuit is coupled to the feedback circuit to receive the feedback voltage. The voltage comparison circuit compares the feedback voltage with a reference voltage to generate a comparison result to a feedback control end of the power supply circuit. The filter is coupled to the voltage comparison circuit to receive the comparison result. The filter filters the comparison result to obtain a conversion detection result.
Based on the above, the integrated circuit chip according to the embodiments of the present invention is configured with the transition detection circuit. During initialization, the transition detection circuit may detect a transition of a target signal of the target circuit to generate a transition detection result. That is, the integrated circuit chip may self-monitor the transition of the target signal. According to the conversion detection result, whether the initialization of the target circuit is normal can be judged without expensive test machines.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 shows a schematic circuit block diagram of an integrated circuit chip 100;
FIG. 2 shows a flow diagram of an inspection method;
FIG. 3 is a block diagram illustrating an integrated circuit chip according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method for inspecting an integrated circuit chip according to an embodiment of the invention;
FIG. 5 illustrates a signal waveform schematic diagram of the circuit of FIG. 3 in some embodiments;
FIG. 6 shows signal waveform diagrams of the circuit of FIG. 3 in further embodiments;
FIG. 7 is a block diagram illustrating the target circuit and transition detection circuit of FIG. 3 according to one embodiment of the present invention;
fig. 8 illustrates a signal waveform schematic diagram of the circuit of fig. 7 in some embodiments.
Detailed Description
The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Components/parts/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.
Fig. 1 shows a schematic block circuit diagram of an integrated circuit chip 100. The integrated circuit chip 100 includes a target circuit 110 and a voltage detection circuit 120. For convenience of illustration, it is assumed that the target circuit 110 is a power supply circuit, and therefore the target circuit 110 has a voltage regulator (voltage regulator)111, a feedback circuit 112 and a voltage comparison circuit 113. The voltage regulator 111 uses the input voltage Vin to provide the supply voltage Vout. According to the comparison result CPR1 at the feedback control terminal of the voltage regulator 111, the voltage regulator 111 can correspondingly regulate the level of the power supply voltage Vout. The voltage regulator 111 may be a conventional voltage regulator or other power supply circuit/component. The supply voltage Vout may power other circuits/components of the integrated circuit chip 100.
The feedback circuit 112 is coupled to the voltage regulator 111 to receive the power voltage Vout and provide a feedback voltage VFB1 to the voltage comparator 113. A first input terminal of the voltage comparing circuit 113 is coupled to the feedback circuit 112 for receiving the feedback voltage VFB 1. A second input of the voltage comparison circuit 113 receives a reference voltage VREF 1. The voltage comparison circuit 113 may compare the feedback voltage VFB1 with the reference voltage VREF1 to generate a comparison result CPR1 to the feedback control terminal of the voltage regulator 111. The voltage comparison circuit 113 may be a conventional voltage comparator or other level comparison circuit/component.
Fig. 2 shows a schematic flow diagram of an inspection method. Please refer to fig. 1 and fig. 2. In step S210, the target circuit 110 is activated (e.g., starts to supply the input voltage Vin to the voltage regulator 111). After the target circuit 110 is started, the target circuit 110 is initialized to enter the target circuit 110 into a normal operation mode. Ideally, the target circuit 110 may pull the supply voltage Vout from 0 volts to the nominal voltage level during the initialization period.
In step S220, the voltage detection circuit 120 may detect the level of the power supply voltage Vout. The voltage detection circuit 120 may be a conventional voltage level detector or other level detection circuit/component. When step S220 determines that the level of the target signal (the voltage level of the power supply voltage Vout) has reached the rated level, step S230 is executed. In step S230, the voltage detection circuit 120 may output the level detection result LOK to indicate "level OK". The level detection result LOK may have different processing modes according to design requirements. In some embodiments, the level detection result LOK may be transmitted to a pad (not shown) or a pin (not shown) so as to provide the level detection result LOK to a less expensive external test fixture (e.g., a voltmeter, an oscilloscope, a computer, etc., not shown). In other embodiments, the level detection result LOK may be recorded in a register (not shown) within the integrated circuit chip 100. The contents of this register (not shown) may be supplied to an external analysis platform (e.g., a computer, not shown) and/or the contents of this register (not shown) may be supplied to control circuitry (not shown) within integrated circuit chip 100, depending on the application requirements.
When it is determined in step S220 that the level of the target signal (the voltage level of the power supply voltage Vout) has not reached the rated level, step S240 is performed. Step S240 may determine whether the time for initialization has timed out. If the step S240 determines that the time has not timed out, the step S220 is executed again. If step S240 determines that the time has expired and the level of the target signal (the voltage level of the power supply voltage Vout) has not yet reached the rated level, the initialization of the target circuit 110 may be determined to be a failure (step S250).
However, in different product application environments, the power voltage Vout output by the same target circuit 110 may have different slew rates. For example, when the load circuit of the target circuit 110 is a light load, the rate at which the power supply voltage Vout is pulled from 0 volts to the rated voltage level is relatively fast, so the power supply voltage Vout can be pulled to the rated voltage level in a timely manner during the rated time, and the initialization of the target circuit 110 is determined to be successful (determination that the target circuit 110 is good). When the load circuit of the target circuit 110 is heavily loaded, the rate at which the power supply voltage Vout is pulled from 0 volts to the rated voltage level is relatively slow, and therefore the power supply voltage Vout may not be pulled to the rated voltage level in the rated time, and the initialization of the target circuit 110 is determined to be a failure (misdetermination that the target circuit 110 is bad). If there is enough time, the target circuit 110 can still pull the supply voltage Vout to the nominal voltage level. Therefore, whether the target circuit 110 is good or not is determined by detecting the voltage level, which may cause erroneous determination.
Fig. 3 is a block diagram of an integrated circuit chip 300 according to an embodiment of the invention. The integrated circuit chip 300 includes a target circuit 310 and a slew detection circuit 320. The target circuit 310 may generate a target signal 301. Target circuit 310 may be any circuit block of integrated circuit chip 300, depending on design requirements. For example, the target circuit 310 may be a power supply circuit and the target signal 301 may be a power supply voltage. In the embodiment shown in FIG. 3, a level detection circuit 330 may also be selectively configured in the integrated circuit chip 300 according to design requirements.
FIG. 4 is a flowchart illustrating a method for inspecting an integrated circuit chip according to an embodiment of the invention. Please refer to fig. 3 and fig. 4. In step S410, the target circuit 310 is activated (e.g., starts to supply the power supply voltage to the target circuit 310). After the target circuit 310 is started, the target circuit 310 is initialized to enter a normal operation mode. The target circuit 310 may generate a target signal 310. Ideally, the target circuit 310 may pull the level of the target signal 301 to the nominal level during the initialization period.
The transition detection circuit 320 is coupled to the target circuit 310. The transition detection circuit 320 may detect a transition (slew) of the target signal 301 during initialization to generate a transition detection result 302 (step S420). The level detection circuit 330 is coupled to the target circuit 310. The level detection circuit 330 may detect the level of the target signal 301 (step S430), for example, detect the voltage level, the current level, and/or the level of other physical quantities of the target signal 301. The level detection circuit 330 may generate the level detection result 303 according to the level of the target signal 301. The level detection circuit 330 may be a conventional voltage level detector or other level detection circuit/component according to design requirements. In some embodiments, the level detection circuit 330 and the level detection result 303 shown in fig. 3 can be analogized with reference to the related description of the voltage detection circuit 120 and the level detection result LOK shown in fig. 1.
The transition detection result 302 and the level detection result 303 may be processed in different manners according to design requirements. In some embodiments, the transition detection result 302 and the level detection result 303 may be transmitted to different pads (not shown) or different pins (not shown), respectively, so as to provide the transition detection result 302 and the level detection result 303 to a cheaper external test fixture (e.g., a voltmeter, an oscilloscope, a computer, etc., not shown). In other embodiments, the transition detection result 302 and the level detection result 303 may be recorded in a first register (not shown) and a second register (not shown) within the integrated circuit chip 100, respectively. The contents of these registers (not shown) may be supplied to an external analysis platform (e.g., a computer, not shown) and/or the contents of these registers (not shown) may be supplied to control circuitry (not shown) within integrated circuit chip 100, depending on the application requirements.
In step S440, an associated checking circuit (not shown), such as an external test fixture, an external analysis platform, or an internal control circuit, may determine whether the initialization of the target circuit 310 is normal according to the transition detection result 302 and/or the level detection result 303. In some embodiments, step S440 shown in fig. 4 can be analogized with reference to the related description of steps S220, S230, S240, and S250 shown in fig. 2.
Fig. 5 illustrates a signal waveform schematic diagram of the circuit of fig. 3 in some embodiments. At time t51, the target circuit 310 is enabled, so the target circuit 310 may pull the level of the target signal 301 to the nominal level during initialization period Pini. The transition detection circuit 320 may detect a transition (slew) of the target signal 301 during initialization period Pini. Since the slew rate of the target signal 301 is not 0 during the initialization period Pini, the transition detection result 302 is logic high (indicating that there is a transition in the target signal 301) during the initialization period Pini. The level detection circuit 330 may detect the level of the target signal 301 in the initialization period Pini. Since the level of the target signal 301 has not reached the rated level yet in the initialization period Pini, the level detection result 303 is low logic in the initialization period Pini.
When the level of the target signal 301 reaches the rated level, the initialization period Pini ends. Since the slew rate of the target signal 301 after the initialization period Pini ends is almost 0, the transition detection result 302 is low logic (indicating that the target signal 301 has not transitioned). Since the level of the target signal 301 after the initialization period Pini ends has reached the rated level, the level detection result 303 is high logic.
Step S440 may determine whether the initialization of the target circuit 310 is normal according to the transition detection result 302 and the level detection result 303. When the level of the target signal 301 reaches the rated level within the rated period Pra (as shown in fig. 5), an associated checking circuit (not shown), such as an external test fixture, an external analysis platform, or an internal control circuit, may determine that the initialization of the target circuit 310 is normal. Assuming that the level of the target signal 301 does not reach the nominal level within the nominal period Pra and the slew rate of the target signal 301 is not 0, i.e. the initialization period Pini is greater than the nominal period Pra, the related checking circuit (not shown), such as an external test fixture, an external analysis platform or an internal control circuit, may determine that the initialization of the target circuit 310 is normal, but the nominal period Pra needs to be increased. When the level of the target signal 301 does not reach the rated level within the rated period Pra and the slew rate of the target signal 301 is almost 0, an associated checking circuit (not shown), such as an external test fixture, an external analysis platform or an internal control circuit, may determine that the initialization of the target circuit 310 is failed, i.e., the target circuit 310 may be damaged.
Fig. 6 shows signal waveform diagrams of the circuit of fig. 3 in further embodiments. At time t61, the target circuit 310 is enabled, so the target circuit 310 may pull the level of the target signal 301 to the nominal level during initialization period Pini. The transition detection circuit 320 may detect a transition (slew) of the target signal 301 during the first period P1. When it is determined in step S440 that the level of the target signal 301 does not reach the nominal level in the first period P1 and the slew rate of the target signal 301 is not 0, the target circuit 310 may increase the slew rate of the target signal 301 in the second period P2 so as to shorten the initialization period Pini in real time. When the level of the target signal 301 reaches the rated level, the initialization period Pini ends. Since the initialization period Pini does not exceed the rated period Pra, the level of the target signal 301 may reach the rated level within the rated period Pra.
Fig. 7 is a block diagram illustrating the target circuit 310 and the transition detection circuit 320 of fig. 3 according to an embodiment of the invention. In the embodiment shown in fig. 7, the target circuit 310 includes a power supply circuit 311, a feedback circuit 312 and a voltage comparison circuit 313, and the transition detection circuit 320 includes a filter 321. The transition detection circuit 320 may also optionally configure a latch circuit 322, such as a latch, flip-flop, or other latch circuit/component, according to design requirements.
In accordance with the comparison result CPR7 of the feedback control terminal of the power supply circuit 311, the power supply circuit 311 may provide a power supply voltage as the target signal 301, wherein the power supply voltage may power other circuits/components of the integrated circuit chip 300. The power supply circuit 311 may be a voltage regulator (voltage regulator), a power conversion circuit or other power supply circuits/components according to design requirements. In some embodiments, the power supply circuit 311 may be an existing voltage regulator. The feedback circuit 312 is coupled to the power supply circuit 311 to receive the power voltage (the target signal 301) and provide the feedback voltage VFB7 to the voltage comparison circuit 313. The voltage comparator 313 is coupled to the feedback circuit 312 to receive the feedback voltage VFB 7. The voltage comparison circuit 313 may compare the feedback voltage VFB7 with the reference voltage VREF7 to generate a comparison result CPR7 to the feedback control terminal of the power supply circuit 311.
Fig. 8 illustrates a signal waveform schematic diagram of the circuit of fig. 7 in some embodiments. At time t81, the target circuit 310 is activated (e.g., starts to provide the input voltage Vin to the power supply circuit 311), so the target circuit 310 may pull the level of the target signal 301 to the nominal level during the initialization period Pini. In the initialization period Pini, since the feedback voltage VFB7 is smaller than the reference voltage VREF7, the comparison result CPR7 is a high logic. When the level of the target signal 301 reaches the rated level, the initialization period Pini ends.
The filter 321 is coupled to the voltage comparison circuit 313 to receive the comparison result CPR 7. The filter 321 may filter the comparison result CPR7 to obtain the conversion detection result 302'. The filter 321 may be a low pass filter, a band pass filter or other filtering circuits/components according to design requirements. In some embodiments, the power supply circuit 311 may be an existing low pass filter. The latch circuit 322 is coupled to the output terminal of the filter 321 to receive and latch the transition detection result 302', and output the latch result as the transition detection result 302. Therefore, the transition detection circuit 320 can detect the transition (slew) of the target signal 301 in the initialization period Pini.
Since the slew rate of the target signal 301 is not 0 during the initialization period Pini, the transition detection result 302' is logic high (indicating that the target signal 301 has a transition) during the initialization period Pini. The level detection circuit 330 may detect the level of the target signal 301 in the initialization period Pini. Since the level of the target signal 301 has not reached the rated level yet in the initialization period Pini, the level detection result 303 is low logic in the initialization period Pini. Since the slew rate of the target signal 301 after the initialization period Pini ends is almost 0, the transition detection result 302 is low logic (indicating that the target signal 301 has not transitioned). Since the level of the target signal 301 after the initialization period Pini ends has reached the rated level, the level detection result 303 is high logic.
In summary, the integrated circuit chip 300 according to the embodiments of the present invention is configured with the transition detection circuit 320. During initialization, the transition detection circuit 320 may detect a transition of the target signal 301 of the target circuit 310 to generate the transition detection result 302. That is, integrated circuit chip 300 may self-monitor transitions of target signal 301. The switch detection result 302 can determine whether the initialization of the target circuit 310 is normal without requiring an expensive testing machine.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Description of the symbols:
100: integrated circuit chip
110: target circuit
111: voltage regulator
112: feedback circuit
113: voltage comparison circuit
120: voltage detection circuit
300: integrated circuit chip
301: target signal
302. 302': converting the detection result
303: level detection result
310: target circuit
311: power supply circuit
312: feedback circuit
313: voltage comparison circuit
320: switching detection circuit
321: filter with a filter element having a plurality of filter elements
322: latch circuit
330: level detection circuit
CPR1, CPR 7: comparison results
LOK: level detection result
P1: the first period
P2: the second period
And (3) Pini: during initialization
Pra: nominal period
S210 to S250, S410 to S440: step (ii) of
t51, t61, t 81: point in time
VFB1, VFB 7: feedback voltage
Vin: input voltage
Vout: supply voltage
VREF1, VREF 7: reference voltage
Description of the drawings for P17D27860
The attached drawing of the abstract is figure 3
FIG. 1 shows a schematic view of a
120 voltage detection circuit
111 voltage regulator
FIG. 2
S210 the target circuit is started
S220 whether the level of the target signal reaches the rated level
S230 output "level OK"
Whether S240 times out
S250, judging initialization failure
FIG. 3
310 target circuit
320 conversion detection circuit
330 level detection circuit
FIG. 4
S410 the target circuit is started
S420 detecting transitions
S430 detection level
S440 judges the state of the target circuit
FIG. 7
311 power supply circuit
330 level detection circuit
321 filters
322 latch circuit
Claims (7)
1. An inspection method of an integrated circuit chip, comprising:
generating a target signal by a target circuit of the integrated circuit chip;
detecting, by a transition detection circuit of the integrated circuit chip, a transition of the target signal during an initialization period to generate a transition detection result;
detecting the level of the target signal by a level detection circuit of the integrated circuit chip to generate a level detection result; and
judging whether the initialization of the target circuit is normal or not according to the conversion detection result;
wherein the step of determining whether the initialization of the target circuit is normal comprises:
when the level of the target signal reaches a rated level within a rated period, judging that the target circuit is initialized to be normal;
when the level of the target signal does not reach the rated level within the rated period and the slew rate of the target signal is not 0, determining that the target circuit is initialized to be normal; and
when the level of the target signal does not reach the rated level within the rated period and the slew rate of the target signal is 0, it is determined that the initialization of the target circuit has failed.
2. The inspection method of an integrated circuit chip as claimed in claim 1, further comprising:
when the level of the target signal does not reach a rated level in a first period and the slew rate of the target signal is not 0, the slew rate of the target signal is increased by the target circuit so that the level of the target signal reaches the rated level in a rated period.
3. The inspection method of an integrated circuit chip as claimed in claim 1, further comprising:
recording the conversion detection result in a first register in the integrated circuit chip; and
and recording the level detection result in a second register in the integrated circuit chip.
4. An integrated circuit chip, comprising:
a target circuit for generating a target signal; and
a transition detection circuit coupled to the target circuit for detecting a transition of the target signal during an initialization period to generate a transition detection result,
wherein the conversion detection result is used for judging whether the initialization of the target circuit is normal or not, and
the target circuit comprises a power supply circuit, a feedback circuit and a voltage comparison circuit, and the conversion detection circuit comprises a filter;
the power supply circuit provides a power voltage as the target signal;
the feedback circuit is coupled to the power supply circuit to receive the power supply voltage and provide a feedback voltage;
the voltage comparison circuit is coupled to the feedback circuit to receive the feedback voltage and compares the feedback voltage with a reference voltage to generate a comparison result to a feedback control end of the power supply circuit; and
the filter is coupled to the voltage comparison circuit to receive the comparison result and to filter the comparison result to obtain the transition detection result.
5. The integrated circuit chip of claim 4, further comprising:
and the level detection circuit is coupled to the target circuit and used for detecting the level of the target signal so as to generate a level detection result.
6. The integrated circuit chip of claim 5, wherein when the level of the target signal does not reach a nominal level for a first period and the slew rate of the target signal is not 0, the target circuit increases the slew rate of the target signal such that the level of the target signal reaches the nominal level for a nominal period.
7. The integrated circuit chip of claim 5, wherein the transition detection result is recorded in a first register within the integrated circuit chip and the level detection result is recorded in a second register within the integrated circuit chip.
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| TW106121488A TWI639847B (en) | 2017-06-27 | 2017-06-27 | Integrated circuit chip and inspection method thereof |
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| CN104502883B (en) * | 2014-12-30 | 2017-07-07 | 宁波三星医疗电气股份有限公司 | The abnormality detection and solution of computation chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200422811A (en) * | 2003-04-17 | 2004-11-01 | Advanced Risc Mach Ltd | Communication interface for diagnostic circuits of an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201905480A (en) | 2019-02-01 |
| CN109144024A (en) | 2019-01-04 |
| TWI639847B (en) | 2018-11-01 |
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