CN109494260A - 一种oj芯片大功率瞬态抑制保护二极管及其制作方法 - Google Patents

一种oj芯片大功率瞬态抑制保护二极管及其制作方法 Download PDF

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CN109494260A
CN109494260A CN201811618152.2A CN201811618152A CN109494260A CN 109494260 A CN109494260 A CN 109494260A CN 201811618152 A CN201811618152 A CN 201811618152A CN 109494260 A CN109494260 A CN 109494260A
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protection diode
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崔振华
李志峰
庄明虔
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SEMI-CONDUCTOR RESEARCH INSTITUTE SHANDONG
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Abstract

本发明属于汽车电器领域，涉及网络通信用大功率浪涌保护技术，尤其涉及一种OJ芯片大功率瞬态抑制保护二极管及其制作方法；其瞬态抑制保护二极管包括方形铜座，所述方形铜座的上部设置有芯片层，所述芯片层自上至下依次包括焊片层、方形OJ双面镀镍芯片、焊片层、石墨烯层、焊片层、铜粒层、焊片层以及外接引线；所述芯片层的四周设置有白胶保护层，所述方形铜座的上部设置有设置在芯片层外侧的黑胶保护壳；其制作方法为：选材、摆料、焊接、碱煮、水洗、烘干、涂胶。本发明采用这种新工艺使芯片有效面积增加20％，其浪涌功率提高20％，芯片边缘厚度一致减少了破裂的风险，采用真空焊接气孔减少，工艺简单，良品率提高8％以上。

Description

一种OJ芯片大功率瞬态抑制保护二极管及其制作方法
技术领域
本发明属于汽车电器领域，涉及网络通信用大功率浪涌保护技术，尤其涉及一种OJ芯片大功率瞬态抑制保护二极管及其制作方法。
背景技术
瞬态二极管(Transient Voltage Suppressor)简称TVS，是一种二极管形式的高效能保护器件。当TVS二极管的两极受到反向瞬态高能量冲击时，它能以10的负12次方秒量级的速度，将其两极间的高阻抗变为低阻抗，吸收高达数千瓦的浪涌功率，使两极间的电压箝位于一个预定值，有效地保护电子线路中的精密元器件，免受各种浪涌脉冲的损坏。
随着电器功率不断增加，浪涌保护二极管功率越来越大，但gpp芯片封装的保护二极管有效面积尺寸有限。gpp芯片封装由于极性问题需要反焊，可靠性差。
发明内容
本发明针对上述的问题，提供了一种OJ芯片大功率瞬态抑制保护二极管及其制作方法。
为了达到上述目的，本发明采用的技术方案为，
一种OJ芯片大功率瞬态抑制保护二极管，包括方形铜座，所述方形铜座的上部设置有芯片层，所述芯片层自上至下依次包括焊片层、方形OJ双面镀镍芯片、焊片层、石墨烯层、焊片层、铜粒层、焊片层以及外接引线；所述芯片层的四周设置有白胶保护层，所述方形铜座的上部设置有设置在芯片层外侧的黑胶保护壳；
所述方形OJ双面镀镍芯片的厚度为310μm-980μm。
作为优选，所述白胶保护层为密封硅胶材料。
作为优选，所述黑胶保护壳为黑色环氧树脂塑封胶。
作为优选，所述黑胶保护壳的下部设置有与芯片层配合设置的方形凹槽，所述方形凹槽的一端设置有与方形凹槽连通设置的矩形凹槽，另一端设置有卡位块，所述方型凹槽的两侧设置有卡位凸柱。
作为优选，所述方形铜座的一端设置有支撑护板，另一端设置有与卡位块配合设置的卡位槽，所述方形铜座的两侧设置有与卡位凸柱配合设置的卡位凹槽。
作为优选，所述外接引线包括方形引线部分，所述方形引线板的一端设置有过渡部分，所述过渡部分远离方形引线部分的一端设置有连接部分，所述连接部分远离过渡部分的一端引线折弯部分。
一种制作OJ芯片大功率瞬态抑制保护二极管的方法，具体包括以下步骤：
I选取厚度在310μm-980μm的方形OJ双面镀镍芯片；
II按照二极管的倒装方式摆料，由下至上依次为外接引线、焊片层、铜粒层、焊片层、石墨烯层、焊片层、方形OJ双面镀镍芯片、焊片层以及方形铜座，得到初料；
III将初料放入到真空焊接炉内焊接，得到型料，其温度为420℃，时间为30-40min；
IV对型料进行高温碱煮，然后水洗，放入到烘箱内进行烘干处理，得到半成品料，其高温碱煮的温度为70-80℃，时间为20min，其水洗的温度为常温，时间为20min，烘干的温度为100℃，时间为30min；
V在半成品料中芯片层的外侧涂抹白胶，之后，再黑胶成型，得到最终产品料，即OJ芯片大功率瞬态抑制保护二极管。
作为优选，在黑胶成型之后，对外接引线中的引线折弯部分进行淬火处理，淬火处理之后，再对引线折弯部分进行折弯处理。
与现有技术相比，本发明的优点和积极效果在于，
1、本发明采用这种新工艺使芯片有效面积增加20％，其浪涌功率提高20％(oj芯片瞬态抑制保护二极管浪涌功率大于7000W，其gpp芯片瞬态抑制保护二极管浪涌功率5500-6000W)，芯片边缘厚度一致减少了破裂的风险，采用真空焊接气孔减少，工艺简单，良品率提高8％以上；
2、其中加入的铜粒层和石墨烯层则大大提高了瞬态抑制保护二极管的平稳性和反应时间，几乎解决了漏电的情况。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为OJ芯片大功率瞬态抑制保护二极管在制作过程中的三种立体结构；
图2为OJ芯片大功率瞬态抑制保护二极管的立体结构示意图；
图3为OJ芯片大功率瞬态抑制保护二极管的爆炸图；
图4为OJ芯片大功率瞬态抑制保护二极管(另一个角度)的爆炸图；
图5为图4中M的局部放大图；
图6为OJ芯片大功率瞬态抑制保护二极管(不包括黑胶保护壳)的横向中轴线剖面图；
以上各图中，
A、OJ芯片大功率瞬态抑制保护二极管(不包括黑胶保护壳)；B、OJ芯片大功率瞬态抑制保护二极管；C、OJ芯片大功率瞬态抑制保护二极管(将引线折弯部分折弯)
1、方形铜座；11、卡位槽；12、支撑护板；13、卡位槽；2、方形OJ双面镀镍芯片；3、石墨烯层；4、铜粒层；5、白胶保护层；51、方形引线部分；52、过渡部分；53连接部分；54、引线折弯部分；6、外接引线；7、黑胶保护壳；71、方形凹槽；72、矩形凹槽；73、卡位块；74、卡位凸柱；8、焊片层。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和实施例对本发明做进一步说明。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用不同于在此描述的其他方式来实施，因此，本发明并不限于下面公开说明书的具体实施例的限制。
实施例1，本发明提供了一种OJ芯片大功率瞬态抑制保护二极管以及制作方法，对于本发明来说，主要包括两部分，一部分为瞬态抑制保护二极管自身，另一部分则是制作瞬态抑制保护二极管的方法，下面分别对这两部分进行说明。
如图1-图6所示，本发明提供了一种OJ芯片大功率瞬态抑制保护二极管，包括方形铜座，该方形铜座则是该瞬态抑制保护二极管的基础座，从图3中可以看出，其方形铜座的上部设置了芯片层，该芯片层自上至下依次包括焊片层、方形OJ双面镀镍芯片、焊片层、石墨烯层、焊片层、铜粒层、焊片层以及外接引线，其方形OJ双面镀镍芯片的设置，降低了保护二极管的整体价格，其铜粒层则是为了使芯片与引线之间有个缓冲，石墨烯层的设计则是为了提高其电流的平稳性以及防漏性；发明人为了使芯片层与外接有一定的绝缘性，如图1-A和图3所示，在芯片层的四周设置在白胶保护层，该为密封硅胶材料，选用的是美国道康宁二极管专用软胶，该白胶保护层只是第一层密封保护，除此之外，发明人在方形铜座的上部设置了设置在芯片层外侧的黑胶保护壳，该黑胶保护壳选取的材料为黑色环氧树脂塑封胶；对于方形OJ双面镀镍芯片来说，其厚度也是很重要的，发明人经过大量的试验得出，其厚度为310μm-980μm是最好的，上述的设计，使用方形OJ双面镀镍芯片要比使用GPP芯片扩散结深60-100um。
发明人为了使黑胶保护壳能够更好的固定在方形铜座想，如图3和图4所示，在黑胶保护壳的下部设置了与芯片层配合设置的方形凹槽，其方形凹槽的一端设置有与方形凹槽连通设置的矩形凹槽，另一端设置有卡位块，方型凹槽的两侧设置有卡位凸柱，为了配合黑胶保护壳的设计，其方形铜座的一端设置有支撑护板，另一端设置有与卡位块配合设置的卡位槽，方形铜座的两侧设置有与卡位凸柱配合设置的卡位凹槽，这里需要对支撑护板说明一下，该支撑护板主要是为了保护外接引线的，防止其侧弯。
如图4所示，其外接引线包括方形引线部分，其方形引线板的一端设置了过渡部分，其过渡部分远离方形引线部分的一端设置了连接部分，其连接部分远离过渡部分的一端引线折弯部分，对于过渡部分来说也是为了黑胶保护壳的矩形凹槽设计的，对于引线折弯部分来说，在具体使用的时候，会如图1中C所示，该引线折弯部分则会弯折到矩形凹槽内的，其折弯的角度为180°。
一种制作OJ芯片大功率瞬态抑制保护二极管的方法，具体包括以下步骤：
I选取厚度在310μm-980μm的方形OJ双面镀镍芯片；
II按照二极管的倒装方式摆料，由下至上依次为外接引线、焊片层、铜粒层、焊片层、石墨烯层、焊片层、方形OJ双面镀镍芯片、焊片层以及方形铜座，得到初料；
III将初料放入到真空焊接炉内焊接，得到型料，其温度为420℃，时间为30-40min；
IV对型料进行高温碱煮，然后水洗，放入到烘箱内进行烘干处理，得到半成品料，其高温碱煮的温度为70-80℃，时间为20min，其水洗的温度为常温，时间为20min，烘干的温度为100℃，时间为30min；
V在半成品料中芯片层的外侧涂抹白胶，之后，再黑胶成型，得到最终产品料，即OJ芯片大功率瞬态抑制保护二极管。
需要补充一下，黑胶成型之后，对外接引线中的引线折弯部分进行淬火处理，淬火处理之后，再对引线折弯部分进行折弯处理。
以上所述，仅是本发明的较佳实施例而已，并非是对本发明作其它形式的限制，任何熟悉本专业的技术人员可能利用上述揭示的技术内容加以变更或改型为等同变化的等效实施例应用于其它领域，但是凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与改型，仍属于本发明技术方案的保护范围。

Claims (8)

1.一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，包括方形铜座，所述方形铜座的上部设置有芯片层，所述芯片层自上至下依次包括焊片层、方形OJ双面镀镍芯片、焊片层、石墨烯层、焊片层、铜粒层、焊片层以及外接引线；所述芯片层的四周设置有白胶保护层，所述方形铜座的上部设置有设置在芯片层外侧的黑胶保护壳；
所述方形OJ双面镀镍芯片的厚度为310μm-980μm。
2.根据权利要求1所述的一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，所述白胶保护层为密封硅胶材料。
3.根据权利要求2所述的一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，所述黑胶保护壳为黑色环氧树脂塑封胶。
4.根据权利要求3所述的一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，所述黑胶保护壳的下部设置有与芯片层配合设置的方形凹槽，所述方形凹槽的一端设置有与方形凹槽连通设置的矩形凹槽，另一端设置有卡位块，所述方型凹槽的两侧设置有卡位凸柱。
5.根据权利要求4所述的一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，所述方形铜座的一端设置有支撑护板，另一端设置有与卡位块配合设置的卡位槽，所述方形铜座的两侧设置有与卡位凸柱配合设置的卡位凹槽。
6.根据权利要求5所述的一种OJ芯片大功率瞬态抑制保护二极管，其特征在于，所述外接引线包括方形引线部分，所述方形引线板的一端设置有过渡部分，所述过渡部分远离方形引线部分的一端设置有连接部分，所述连接部分远离过渡部分的一端引线折弯部分。
7.一种制作权利要求1-6中任意一项的OJ芯片大功率瞬态抑制保护二极管的方法，其特征在于，具体包括以下步骤：
I选取厚度在310μm-980μm的方形OJ双面镀镍芯片；
II按照二极管的倒装方式摆料，由下至上依次为外接引线、焊片层、铜粒层、焊片层、石墨烯层、焊片层、方形OJ双面镀镍芯片、焊片层以及方形铜座，得到初料；
III将初料放入到真空焊接炉内焊接，得到型料，其温度为420℃，时间为30-40min；
IV对型料进行高温碱煮，然后水洗，放入到烘箱内进行烘干处理，得到半成品料，其高温碱煮的温度为70-80℃，时间为20min，其水洗的温度为常温，时间为20min，烘干的温度为100℃，时间为30min；
V在半成品料中芯片层的外侧涂抹白胶，之后，再黑胶成型，得到最终产品料，即OJ芯片大功率瞬态抑制保护二极管。
8.根据权利要求7所述的一种制作OJ芯片大功率瞬态抑制保护二极管的方法，其特征在于，在黑胶成型之后，对外接引线中的引线折弯部分进行淬火处理，淬火处理之后，再对引线折弯部分进行折弯处理。
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