CN109473470A - Trench schottky device - Google Patents
Trench schottky device Download PDFInfo
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- CN109473470A CN109473470A CN201811578438.2A CN201811578438A CN109473470A CN 109473470 A CN109473470 A CN 109473470A CN 201811578438 A CN201811578438 A CN 201811578438A CN 109473470 A CN109473470 A CN 109473470A
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- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 230000001154 acute effect Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 69
- 238000005530 etching Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of trench schottky devices, it is related to the technical field of semiconductor devices, the groove through metal silicide layer and through part single crystalline layer is formed including single crystalline layer and the metal silicide layer being arranged on single crystalline layer, trench schottky device, groove includes the area Kuan Jing, the area Zhai Jing and reducing district, reducing district is that the region in the area Kuan Jing is transitioned by the area Zhai Jing, the area Kuan Jing and part reducing district are located in single crystalline layer, it solves the problems, such as that barrier metal sputtering is difficult, and then dramatically alleviates leaky.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly, to a kind of trench schottky device.
Background technique
In order to optimize the pressure drop VF and electric leakage IR of Planar Schottky diode, groove type MOS structure is then produced
Trench schottky barrier diode (TMBS diode).Trench schottky barrier diode in process, for surface oxide layer
Gate oxide is inevitably carried out over etching by the process of etching, otherwise it is difficult to ensure that the oxide layer on silicon face is complete
Full removal, it is difficult in the covering of the local barrier metal of gate oxide over etching, electric leakage can be generated.
Summary of the invention
In view of this, solving asking for barrier metal sputtering difficulty the purpose of the present invention is to provide trench schottky device
Topic, and then dramatically alleviate leaky.
In a first aspect, the embodiment of the invention provides a kind of trench schottky device, including single crystalline layer and setting are described
Metal silicide layer, the trench schottky device on single crystalline layer, which are formed, runs through the metal silicide layer and through part
The groove of the single crystalline layer, the groove include the area Kuan Jing, the area Zhai Jing and reducing district, and the reducing district is by the area Zhai Jing mistake
The region to the area Kuan Jing is crossed, the area Kuan Jing and the part reducing district are located in the single crystalline layer.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein also
It is included in the gate oxide that the inner wall of the groove is formed.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein also
DOPOS doped polycrystalline silicon including being deposited on the trench interiors.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein institute
The upper surface of DOPOS doped polycrystalline silicon is stated in arc surfaced.
With reference to first aspect, the embodiment of the invention provides the 4th kind of possible embodiments of first aspect, wherein institute
The upper surface for stating single crystalline layer is higher than the minimum point of the cambered surface and is lower than the highest point of the cambered surface.
With reference to first aspect, the embodiment of the invention provides the 5th kind of possible embodiments of first aspect, wherein also
Including metal electrode layer, it is arranged on the metal silicide layer.
With reference to first aspect, the embodiment of the invention provides the 6th kind of possible embodiments of first aspect, wherein institute
The contact surface for stating metal silicide layer and the single crystalline layer is barrier region.
With reference to first aspect, the embodiment of the invention provides the 7th kind of possible embodiments of first aspect, wherein institute
It states barrier region and the angle of the gate oxide is at an acute angle.
With reference to first aspect, the embodiment of the invention provides the 8th kind of possible embodiments of first aspect, wherein institute
The width in the area Shu Kuanjing is 0.7-1.8 microns, and the width in the area Zhai Jing is 0.3-1.0 microns.
With reference to first aspect, the embodiment of the invention provides the 9th kind of possible embodiments of first aspect, wherein institute
The shape of groove is stated in convex.
The embodiment of the invention provides a kind of trench schottky devices, including single crystalline layer and the metal being arranged on single crystalline layer
Silicide layer, trench schottky device form the groove through metal silicide layer and through part single crystalline layer, and groove includes
The area Kuan Jing, the area Zhai Jing and reducing district, reducing district are that the region in the area Kuan Jing, the area Kuan Jing and part variable diameter position are transitioned by the area Zhai Jing
In in single crystalline layer, through the embodiment of the present invention in groove setting so that barrier region is resisted against on reducing district part, and/or, gesture
Building area has a lateral displacement to ditch notch direction in the horizontal direction, due to the groove shape provided in the embodiment of the present invention, no
It will cause gate oxidation overetch, and then solve the problems, such as that the covering of barrier metal sputtering is difficult, at the same time, due to potential barrier
The angle of area edge and gate oxide is at an acute angle, makes the electric field of barrier region and groove proximate region will be far below other barrier regions
Electric field, to reduce the leakage current of potential barrier area edge.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is traditional one of structural schematic diagram of trench schottky diode；
Fig. 2 is the second structural representation of traditional trench schottky diode；
Fig. 3 is a kind of trench schottky device schematic diagram provided in an embodiment of the present invention；
Fig. 4 a to 4i is a kind of process schematic of trench schottky device production method provided in an embodiment of the present invention.
Icon: 1- etching groove shelters film；2- single crystalline layer；3- gate oxide；4- DOPOS doped polycrystalline silicon；5- cavity；6- oxidation
Object；7- metal silicide layer；8- reducing district；The barrier region 9-；10- metal electrode layer；The area 11- Kuan Jing；The area 12- Zhai Jing.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Currently, then producing groove type MOS knot to optimize the pressure drop VF of Planar Schottky diode and electric leakage IR
The trench schottky barrier diode (TMBS diode) of structure.Its typical structure is as shown in Figure 1, form ditch inside single crystalline layer 2
Slot, trench wall form gate oxide 3, and trench interiors deposit DOPOS doped polycrystalline silicon 4, have oxide 6 at ditch notch gate oxide 3
Residual forms metal electrode layer 10 in single crystalline layer 2 and 4 surface of DOPOS doped polycrystalline silicon, the vertical field plate formed by trench MOS structure
The barrier region of horizontal direction is shielded, to reduce the electric leakage of barrier region, while the N under field plate effect below barrier region
Type area exhausts in advance, therefore improves the pressure resistance of vertical direction, in the case where pressure resistance is constant, can reduce the resistance of N-type region
Rate is to reduce pressure drop.Structure has carried out the excellent of performance to planar Schottky barrier diode although can largely realize
Change, but gate oxide 3 is inevitably subjected to over etching during surface oxide layer etches in technique, is otherwise difficult
Guarantee that the oxide layer on silicon face is completely removed, the local electric field that this will cause 3 over etching of gate oxide is stronger, and potential barrier gold
It is difficult to belong to covering, generates electric leakage.
In order to solve this problem, trench schottky diode shown in Figure 2, except forming groove inside single crystalline layer 2,
Trench wall forms gate oxide 3, and trench interiors deposit DOPOS doped polycrystalline silicon 4, have the residual of oxide 6 at ditch notch gate oxide 3
It stays, forms metal electrode layer 10 in single crystalline layer 2 and 4 surface of DOPOS doped polycrystalline silicon, also form high concentration impurities P+ in gate oxide 3
Area, the P+ ring (terminal of planer schottky diode) of similar planar Schottky barrier diode, to reduce electric leakage.But in this way
It does, the area of natively reduced barrier region can be further reduced, increase the pressure drop of barrier region, while also to increase height
Concentration of impurities injection, annealing operation, program are cumbersome.
Based on this, a kind of trench schottky device provided in an embodiment of the present invention, on the basis for keeping 9 area of barrier region
On, solve the problems, such as that barrier metal sputtering is difficult, and then dramatically alleviate leaky, easy to operate.
It is described in detail below by embodiment.
Fig. 3 is a kind of trench schottky device schematic diagram provided in an embodiment of the present invention.
As shown in figure 3, trench schottky device includes single crystalline layer 2 and metal silicide layer 7, run through metal silicide layer 7
Groove is formed with portion of monocrystalline layer 2, is reacted by gate oxidation, in the gate oxide 3 that the inner wall of groove is formed, in having formed grid oxygen
The trench interiors for changing layer 3 deposit DOPOS doped polycrystalline silicon 4, and the upper surface of single crystalline layer 2 is higher than the minimum point of cambered surface and is lower than cambered surface most
High point, metal silicide layer 7 are respectively overlay in the upper surface of single crystalline layer 2 and DOPOS doped polycrystalline silicon 4, set on metal silicide layer 7
It is equipped with metal electrode layer 10；Groove includes the area Kuan Jing 11, the area Zhai Jing 12 and reducing district 8, and reducing district 8 is to be transitioned by the area Zhai Jing 12
The region in the area Kuan Jing 11, the area Kuan Jing 11 and part reducing district 8 are located in single crystalline layer 2, wherein meet above-mentioned requirements groove have it is more
Kind shape, such as convex.
Wherein, the contact surface of metal silicide layer 7 and single crystalline layer 2 is barrier region 9, the angle of barrier region 9 and gate oxide 3
It is at an acute angle.
In order to make it easy to understand, the setting of middle groove through the embodiment of the present invention, so that barrier region 9 is resisted against reducing district 8
On point, and/or, there is a lateral displacement in barrier region 9 to ditch notch direction in the horizontal direction, due to providing in the embodiment of the present invention
Groove shape, not will cause gate oxide overetch, so solve the problems, such as barrier metal sputtering covering difficulty, with
This is that the electric field of barrier region 9 and groove proximate region is remote low simultaneously as the angle of barrier region 9 and gate oxide 3 is at an acute angle
Electric field other than 9 edge of barrier region, to sputter the leakage current at 9 edge of barrier region.
In the preferred embodiment of practical application, the width W2 in the area Kuan Jing 11 is 0.7-1.8 microns, such as 0.7 micron, 0.8
Micron, 0.9 micron, 1.0 microns, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns,
1.8 microns, the width W1 in the area Zhai Jing 12 is 0.3-1.0 microns, e.g., 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7
Micron, 0.8 micron, 0.9 micron, 1.0 microns；
It should be noted that single crystalline layer 2 also may be referred to epitaxial layer, including monocrystalline silicon；In the process of deposit DOPOS doped polycrystalline silicon 4
In, it is possible to it will form cavity 5；
For above-mentioned trench schottky device, the embodiment of the invention also provides a kind of production of trench schottky device
Method, in conjunction with shown in Fig. 4 a- Fig. 4 i, this method is specifically included:
S1: it in conjunction with shown in Fig. 4 a, on 2 surface of single crystalline layer, forms etching groove and shelters film 1.
Etching groove is formed in N-type single wafer surface and shelters film 1, forms etching groove window.
S2: in conjunction with shown in Fig. 4 b, on the basis of above step, groove is formed in the inside of single crystalline layer 2, groove includes width
Diameter area, the area Zhai Jing and reducing district, reducing district are that the region in the area Kuan Jing is transitioned by the area Zhai Jing.
Under the blocking of etching groove masking film 1, single crystalline layer 2 is etched, etches groove, groove includes wide diameter
Area, the area Zhai Jing and reducing district, reducing district are that the region in the area Kuan Jing is transitioned by the area Zhai Jing, and the area Kuan Jing and part reducing district are located at list
In crystal layer 2, wherein meet shape, such as convex there are many grooves of above-mentioned requirements.
S3: in conjunction with shown in Fig. 4 c, on the basis of above step, gate oxidation is formed in the inside of single crystalline layer 2 and upper surface
Layer 3.
Sacrifice oxidation processes are carried out to the trench interiors that above-mentioned steps etch, and by oxide layer together with etching groove residue
Masking film removes together, so that processed trench interiors surface is complete, then gate oxidation process is carried out, in the groove of single crystalline layer 2
Internal and upper surface forms gate oxide 3.
S4: in conjunction with shown in Fig. 4 d, on the basis of above step, DOPOS doped polycrystalline silicon 4 is deposited on gate oxide 3.
In deposition process, cavity 5 may be formed inside polysilicon.
S5: in conjunction with shown in Fig. 4 e, on the basis of above step, etching DOPOS doped polycrystalline silicon 4, so that DOPOS doped polycrystalline silicon 4
Upper surface and the upper surface of single crystalline layer 2 keep horizontal.
Etching polysilicon is carried out, polycrystal etching face is horizontal as far as possible with single crystalline layer 2, while the polysilicon on 2 surface of single crystalline layer is complete
Complete to carve only, DOPOS doped polycrystalline silicon 4 is in arc surfaced.
S6: in conjunction with shown in Fig. 4 f, on the basis of above step, the gate oxide 3 of 2 upper surface of single crystalline layer is etched.
Gate oxide 3 on single crystalline layer 2 is performed etching.
S7: in conjunction with shown in Fig. 4 g, on the basis of above step, single crystalline layer 2 is etched, so that part reducing district 8 is in monocrystalline
In layer 2.
2 upper surface of single crystalline layer is performed etching, until part reducing district in single crystalline layer 2 or the upper surface of single crystalline layer 2 position
In the reducing district of groove, at the same time, the upper surface of single crystalline layer 2 is higher than the minimum point of cambered surface and is lower than the highest point of cambered surface.
S8: in conjunction with shown in Fig. 4 h, on the basis of above step, barrier metal is sputtered, carries out silicification reaction, forms metal
Silicide layer 7.
Barrier metal is sputtered on the upper surface of single crystalline layer 2 and DOPOS doped polycrystalline silicon 4, and it is anti-to carry out silication to barrier metal
It answers, forms metal silicide layer 7, wherein barrier metal includes the metal materials such as platinum, titanium.
S9: in conjunction with shown in Fig. 4 i, on the basis of above step, removing unreacted barrier metal, deposition of electrode metal,
Form metal electrode layer 10.
The barrier metal removal of silicification reaction will not be carried out, and in the surface deposition electrode metal of metal silicide layer 7, shape
At metal electrode layer 10.
In the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " connects " connected "
Connect " it shall be understood in a broad sense, for example, it may be being fixedly connected, it may be a detachable connection, or be integrally connected；It can be machine
Tool connection, is also possible to be electrically connected；It can be directly connected, two members can also be can be indirectly connected through an intermediary
Connection inside part.For the ordinary skill in the art, above-mentioned term can be understood in the present invention with concrete condition
Concrete meaning.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.The apparatus embodiments described above are merely exemplary, for example, the division of the unit,
Only a kind of logical function partition, there may be another division manner in actual implementation, in another example, multiple units or components can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be through some communication interfaces, device or unit it is indirect
Coupling or communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of trench schottky device, which is characterized in that including single crystalline layer and the metal silication being arranged on the single crystalline layer
Nitride layer, the trench schottky device form the groove through single crystalline layer described in the metal silicide layer and through part,
The groove includes the area Kuan Jing, the area Zhai Jing and reducing district, and the reducing district is to be transitioned into the area Kuan Jing by the area Zhai Jing
Region, the area Kuan Jing and the part reducing district are located in the single crystalline layer.
2. trench schottky device according to claim 1, which is characterized in that further include being formed in the inner wall of the groove
Gate oxide.
3. trench schottky device according to claim 1, which is characterized in that further include being deposited on the trench interiors
DOPOS doped polycrystalline silicon.
4. trench schottky device according to claim 3, which is characterized in that the upper surface of the DOPOS doped polycrystalline silicon is in arc
Planar.
5. trench schottky device according to claim 4, which is characterized in that the upper surface of the single crystalline layer is higher than described
The minimum point of cambered surface and the highest point for being lower than the cambered surface.
6. trench schottky device according to claim 2, which is characterized in that further include metal electrode layer, be arranged in institute
It states on metal silicide layer.
7. trench schottky device according to claim 6, which is characterized in that the metal silicide layer and the monocrystalline
The contact surface of layer is barrier region.
8. trench schottky device according to claim 7, which is characterized in that the barrier region and the gate oxide
Angle is at an acute angle.
9. trench schottky device according to claim 1, which is characterized in that the width in the area Kuan Jing is 0.7-1.8
Micron, the width in the area Zhai Jing are 0.3-1.0 microns.
10. trench schottky device according to claim 1, which is characterized in that the shape of the groove is in convex.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811578438.2A CN109473470A (en) | 2018-12-19 | 2018-12-19 | Trench schottky device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811578438.2A CN109473470A (en) | 2018-12-19 | 2018-12-19 | Trench schottky device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109473470A true CN109473470A (en) | 2019-03-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115280517A (en) * | 2020-04-24 | 2022-11-01 | 京瓷株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060157745A1 (en) * | 2005-01-18 | 2006-07-20 | Stmicroelectronics S.A. | Vertical unipolar component with a low leakage current |
| JP2015073018A (en) * | 2013-10-03 | 2015-04-16 | 日産自動車株式会社 | Semiconductor device and manufacturing method of the same |
| KR20150072199A (en) * | 2013-12-19 | 2015-06-29 | 엘지이노텍 주식회사 | Power Semiconductor Device and Power semiconductor circuit including the device |
| CN106505099A (en) * | 2016-11-30 | 2017-03-15 | 中国科学院微电子研究所 | A kind of grooved grid power field effect transistor |
| CN108321211A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | TMBS semiconductor devices and preparation method thereof, electronic device |
| CN209016062U (en) * | 2018-12-19 | 2019-06-21 | 吉林华微电子股份有限公司 | Trench schottky device |
-
2018
- 2018-12-19 CN CN201811578438.2A patent/CN109473470A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060157745A1 (en) * | 2005-01-18 | 2006-07-20 | Stmicroelectronics S.A. | Vertical unipolar component with a low leakage current |
| JP2015073018A (en) * | 2013-10-03 | 2015-04-16 | 日産自動車株式会社 | Semiconductor device and manufacturing method of the same |
| KR20150072199A (en) * | 2013-12-19 | 2015-06-29 | 엘지이노텍 주식회사 | Power Semiconductor Device and Power semiconductor circuit including the device |
| CN106505099A (en) * | 2016-11-30 | 2017-03-15 | 中国科学院微电子研究所 | A kind of grooved grid power field effect transistor |
| CN108321211A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | TMBS semiconductor devices and preparation method thereof, electronic device |
| CN209016062U (en) * | 2018-12-19 | 2019-06-21 | 吉林华微电子股份有限公司 | Trench schottky device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115280517A (en) * | 2020-04-24 | 2022-11-01 | 京瓷株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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