CN109461412B - Organic light-emitting display panel and organic light-emitting display device - Google Patents
Organic light-emitting display panel and organic light-emitting display device Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Abstract
The embodiment of the application provides an organic light-emitting display panel, which comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a first display area and a second display area, and the number of sub-pixels in any row in the first display area is smaller than that in any row in the second display area; the non-display area is provided with a scanning driving circuit, the scanning driving circuit comprises cascaded scanning driving circuit units, and the scanning driving circuit units comprise a first scanning driving circuit unit and a second scanning driving circuit unit; the first scanning driving circuit unit is connected with the sub-pixel rows of the first display area and outputs a first scanning driving signal; the second scanning driving circuit unit is connected with the sub-pixel rows of the second display area and outputs a second scanning driving signal; the delay time of the first scan driving signal is greater than the delay time of the second scan signal. The application makes the charging time shorten by increasing the delay time, and improves the display uniformity of the organic light-emitting display panel.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of display technologies, and in particular, to an organic light emitting display panel and an organic light emitting display device.
[ background of the invention ]
With the great development of display technology, the requirements of consumers on the screen ratio of display devices are higher and higher. More and more consumers are willing to purchase full screen display devices. However, the display surface of the display device must be equipped with components such as fingerprint recognition, an earpiece, a light sensor, and a camera. One current solution is to provide a non-display area in the display area of the display panel to place these components. However, providing the non-display area in the display area results in a smaller number of sub-pixels in a pixel row that passes through the non-display area than a pixel row that does not pass through the non-display area. This results in a small load on the part of the pixels and a sufficient charging time, which results in a decrease in the luminance, and causes a non-uniform display on the whole display panel, resulting in a poor display effect.
[ summary of the invention ]
Embodiments of the present invention provide an organic light emitting display panel and an organic light emitting display device to solve the above technical problems.
In one aspect, the present application discloses an organic light emitting display panel, including a display area and a non-display area surrounding the display area, the display area including a first display area and a second display area, the number of sub-pixels in any one row of the first display area being smaller than the number of sub-pixels in any one row of the second display area; the non-display area is provided with a scanning driving circuit, the scanning driving circuit comprises cascaded scanning driving circuit units, and the scanning driving circuit units comprise a first scanning driving circuit unit and a second scanning driving circuit unit; the first scanning driving circuit unit is connected with the sub-pixel rows of the first display area and outputs a first scanning driving signal; the second scanning driving circuit unit is connected with the sub-pixel rows of the second display area and outputs a second scanning driving signal; the delay time of the first scan driving signal is greater than the delay time of the second scan signal.
In one embodiment of the present application, the first scan driving signal outputs a first high level signal from a first signal and outputs a first low level signal from a second signal; the second scanning driving signal outputs a second high-level signal from a third signal and outputs a second low-level signal from a fourth signal; the first high level signal is higher than the second high level signal and/or the first low level signal is lower than the second low level signal.
In one embodiment of the present application, the driving circuit is composed of a P-type transistor, and the first high level signal is higher than the second high level signal; the first low level signal is equal to the second low level signal.
In one embodiment of the present application, the first signal and the third signal are fixed potential signals, and the second signal and the fourth signal are low level signals of a clock signal.
In one embodiment of the present application, a first connection line and a second connection line are included; the first connecting line extends from the driving chip to the first scanning driving circuit unit and provides a first signal for the first scanning driving circuit unit; the second connecting line extends from the driving chip to a second scanning driving circuit unit and provides a third signal for the second scanning driving circuit unit; the potential of the first connecting line is higher than that of the third connecting line.
In one embodiment of the present application, a third connection line is included; the third connection line includes a first connection part extending from the driving chip to the first scan driving circuit unit, a first part supplying the first signal to the first scan driving circuit unit, and a second part supplying the third signal to the second scan driving circuit unit.
In one embodiment of the present application, a partial pressure connection portion is further provided between the first portion and the second portion.
In one embodiment of the present application, the driving chip is located on a side of the display panel close to the first driving circuit.
In one embodiment of the present application, the first driving circuit unit includes a first output transistor; the second driving unit includes a second output transistor; the width-to-length ratio of the first output transistor is smaller than the width-to-length ratio of the second output transistor.
In one embodiment of the present application, the first display region is provided with a non-display hole; the first connecting line extends from the driving chip to the middle stage of the first scanning driving circuit unit.
In one embodiment of the present application, the first display region is provided with a non-display hole; in all the first scan driving circuit units, the width-to-length ratio of the output transistors of the first scan driving circuit unit in the middle stage is the largest; and the width-to-length ratio of the output transistor of the first scan driving circuit unit decreases from the middle stage to both sides.
In one embodiment of the present application, the first display area is provided with a non-display slot; the first connecting line extends from the driving chip to a stage of the first scan driving circuit unit closest to the driving chip.
In one embodiment of the present application, the first driving circuit unit includes a first output transistor; the second driving unit includes a second output transistor; the width-to-length ratio of the first output transistor is smaller than that of the second output transistor; the non-display groove is provided with a fillet; a first scanning driving circuit unit A and a first scanning driving circuit unit B are correspondingly arranged at the round corners; the number of sub-pixels connected with the first scanning driving circuit unit is smaller than that connected with the first second driving circuit unit; the first scanning driving circuit unit comprises a first output transistor; the first second scanning driving circuit unit comprises a first second output transistor; the width-to-length ratio of the first A output transistor is smaller than that of the first B output transistor.
In one embodiment of the present application, the first display area is provided with a rounded corner; a first third scanning driving circuit unit and a first fourth scanning driving circuit unit are correspondingly arranged at the round corners; the number of sub-pixels connected with the first third scanning driving circuit unit is smaller than that connected with the first third driving circuit unit; the first third scanning driving circuit unit comprises a first third output transistor; the first D scanning driving circuit unit comprises a first D output transistor; the width-length ratio of the first third output transistor is smaller than that of the first fourth output transistor.
In another aspect, the present application discloses an organic light emitting display device including the above organic light emitting display panel.
In this application, the first display region with a small number of sub-pixel lines and the second display region with a large number of sub-pixel lines are respectively provided with the first scan driving circuit and the second scan driving circuit, so that the delay time of the first scan driving circuit is longer than that of the second scan driving circuit. Therefore, the charging time of the sub-pixels of the corresponding row of the first scanning driving circuit is shortened, the brightness of the first display area is increased and is consistent with that of the second display area, and the display uniformity of the organic light-emitting display panel is realized.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic delay time diagram of one embodiment of the present application;
FIG. 3 is a schematic delay time diagram of another embodiment of the present application;
FIG. 4A is a schematic diagram of a scan driver circuit according to an embodiment of the present application;
FIG. 4B is a schematic diagram of a scan driver circuit according to an embodiment of the present application;
FIG. 5 is a schematic view of a display panel of another embodiment of the present application;
FIG. 6 is a schematic view of a display panel of yet another embodiment of the present application;
FIG. 7 is a schematic view of a display panel of yet another embodiment of the present application;
FIG. 8 is a schematic view of a display panel of yet another embodiment of the present application;
FIG. 9 is an enlarged schematic view of FIG. 8 at the dashed box;
FIG. 10 is another enlarged schematic view of FIG. 8 at the dashed box;
FIG. 11 is a schematic view of a display panel of yet another embodiment of the present application;
FIG. 12 is an enlarged schematic view of FIG. 11 at the dashed box;
FIG. 13 is a schematic view of a display panel of yet another embodiment of the present application;
FIG. 14 is an enlarged schematic view of FIG. 13 at the dashed box;
FIG. 15 is a schematic view of a display device according to an embodiment of the present application;
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe signals in embodiments of the present invention, these signals should not be limited by these terms. These terms are only used to distinguish one signal from another. For example, a first signal may also be referred to as a second signal, and similarly, a second signal may also be referred to as a first signal, without departing from the scope of embodiments of the present invention.
In order to improve the screen occupation ratio in the prior art, a non-display area is arranged in a display area of a display panel to place the components. However, providing the non-display area in the display area results in a smaller number of sub-pixels in a pixel row that passes through the non-display area than a pixel row that does not pass through the non-display area. This results in a small load on this part of the pixels. The luminance of the sub-pixel is proportional to the current Ids ═ k (PVDD-Vdata)2Where PVDD is the fixed supply voltage and k is a transistor-dependent parameter. When Vdata rises, the current Ids decreases, resulting in a decrease in light emission luminance. Line scan driver for a small number of sub-pixels in a pixel lineThe load of the circuit is small, and the charging time is increased, so that the luminous brightness is reduced, the display of the whole display panel is not uniform, and the problem of poor display effect is caused.
In an embodiment of the present application, please refer to fig. 1, fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application; the application discloses an organic light-emitting display panel, which comprises a display area AA and a non-display area NA surrounding the display area, wherein the display area AA comprises a first display area AA1 and a second display area AA2, and the number of sub-pixels in any line of the first display area AA1 is less than that of the sub-pixels in any line of the second display area AA 2;
the non-display area NA is provided with a scan driving circuit 30 including a cascade of scan driving circuit units 300 including a first scan driving circuit unit 300a and a second scan driving circuit unit 300 b; the first scan driving circuit unit 300a is connected to the sub-pixel rows of the first display region through the first scan signal line 20a and outputs a first scan driving signal; the second scan driving circuit unit 300b is connected to the sub-pixel rows of the second display region through the second scan signal line 20b and outputs a second scan driving signal; the delay time of the first scan driving signal is greater than the delay time of the second scan signal.
Taking fig. 1 as an example, the first scan driving circuit unit 300a drives 2 sub-pixels 10, and the second scan driving circuit unit 300b drives 8 sub-pixels 10, which results in a smaller load of the first scan driving circuit 300a, a longer charging time, a higher data voltage, and a lower brightness. For example, when the same gray scale voltage is applied to all the sub-pixels of the panel, the luminance of the first display area AA1 is lower than that of the second display area AA 2. In the present application, when the delay time of the first scan driving signal is set to be greater than the delay time of the second scan driving signal, the charging time of the sub-pixels in the first display area can be reduced, so that the data voltage is reduced, the light emitting current is increased, and the brightness is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
As will be described in detail below with reference to fig. 2 and 3, fig. 2 is a schematic delay time diagram according to an embodiment of the present application; FIG. 3 is a schematic delay time diagram of another embodiment of the present application;
in this embodiment, the first scan driving signal outputs a first high level signal VGH1 from the first signal, and outputs a first low level signal VGL1 from the second signal; the second scan driving signal outputs a second high level signal VGH2 by a third signal and outputs a second low level signal VGL2 by a fourth signal; the first high level signal VGH1 is higher than the second high level signal VGH2 and/or the first low level signal VGL1 is lower than the second low level signal VGL 2.
Taking fig. 2 as an example, the first high level higher signal VGH1 is higher than the second high level signal VGH2, and the first low level signal VGL1 is equal to the second low level signal VGL 2. According to the formula V of capacitor dischargeC＝V0e-t/RCWherein, VCCapacitor voltage, V0Initial voltage of capacitor, t delay time. The larger the voltage difference between the capacitor voltage and the initial voltage, the larger the delay time. In this embodiment, the difference between the first high level signal and the first low level signal of the first driving circuit is VGH1-VGL, which is greater than the difference between the second high level signal and the second low level signal of the second driving circuit, VGH2-VGL, so the delay time of the first driving circuit unit 300a is longer. Referring to fig. 2, there is a cascade connection with the first driving circuit unit 300a and the second driving circuit unit, whose pulse width is equal, i.e., T1+ T1 is T2+ T2, and the delay time T1 of the first driving circuit unit 300a is greater than the delay time T2 of the second driving circuit unit 300b, resulting in that the actual charging time T1 of the sub-pixel 10 driven by the first driving circuit unit 300a is actually less than the charging time T2 of the sub-pixel 10 driven by the second driving circuit unit 300b, and thus, the data voltage is decreased, the light emitting current is increased, and the luminance is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
Specifically, when the driving circuit 30 of the present embodiment is composed of P-type transistors, the first high level signal VGH1 is higher than the second high level signal VGH 2; the first low level signal VGL1 is equal to the second low level signal VGL2 which are both VGL. Increasing the output level signal on the display panel requires not only redesigning the driver chip, but also redesigning the wiring on the display panel. Therefore, in the present embodiment, it is only necessary to design the first high level signal VGH1 to be greater than the second high level signal VGH2, and the first low level signal VGL1 is equal to the second ground level signal VGL 2. Therefore, only one level signal needs to be added, and the difficulty is reduced for the design of the driving chip and the wiring design of the display panel. The inventors consider that the PMOS circuit is turned on at a low level and turned off at a high level. If VGL1 < VGL2 is set, then the transistors may be turned on under the condition of VGL1 and VGL2, and the charging time T1 may not be reduced much relative to T2, and the effect is not obvious. As shown in fig. 2, setting VGH1 > VGH2 allows the charging time T1 < T2, so that the data voltage decreases, the light emission current increases, and the luminance increases. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
Also, as shown in fig. 3, when the driving circuit 30 of the present embodiment is composed of N-type transistors, the first high level signal VGH1 is equal to VGH when being higher than or equal to the second high level signal VGH 2; the first low level signal VGL1 is less than the second low level signal VGL 2. According to the formula V of capacitor dischargeC＝V0e-t/RCWherein, VCCapacitor voltage, V0Initial voltage of capacitor, t delay time. The larger the voltage difference between the capacitor voltage and the initial voltage, the larger the delay time. In this embodiment, the difference between the first high level signal and the first low level signal of the first driving circuit is VGH-VGL1, which is greater than the difference between the second high level signal and the second low level signal of the second driving circuit, VGH-VGL2, so the delay time of the first driving circuit unit 300a is longer. Referring to fig. 3, there is a cascade connection with the first driving circuit unit 300a and the second driving circuit unit, whose pulse width is equal, i.e., T3+ T3 is T4+ T4, and the delay time T3 of the first driving circuit unit 300a is greater than the delay time T4 of the second driving circuit unit 300b, resulting in an actual charging time of the sub-pixel 10 driven by the first driving circuit unit 300aT3 is less than the charging time T4 for the second driving circuit unit 300b to drive the sub-pixel 10, thus causing the data voltage to decrease and the light emitting current to increase, thereby causing the luminance to increase. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
In addition, increasing the output level signal on the display panel requires not only redesigning the driver chip but also redesigning the wiring on the display panel. Therefore, in the present embodiment, it is only necessary to design the first high level signal VGH1 equal to the second high level signal VGH2 equal to VGH, and the first low level signal VGL1 is smaller than the second ground level signal VGL 2. Therefore, only one level signal needs to be added, and the difficulty is reduced for the design of the driving chip and the wiring design of the display panel. The inventors consider that the NMOS circuit is turned on at a high level and turned off at a low level. If VGH1 > VGH2 is set, the transistors may be turned on substantially under the conditions of VGH1 and VGH2, and the charging time T3 may not be reduced much relative to T3 substantially, and the effect is not obvious. As shown in fig. 3, VGL1 < VGL2 is set such that the charging time T3 < T4 is set such that the data voltage is reduced and the light emission current is increased, thereby increasing the luminance. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
The following describes a scan driving circuit and its operation process according to an embodiment of the present application with reference to fig. 4A and 4B. FIG. 4A is a schematic diagram of a scan driver circuit according to an embodiment of the present application; FIG. 4B is a schematic diagram of a scan driver circuit according to an embodiment of the present application; the scan driving circuit of the present application includes 8 transistors and 2 capacitors, as well as clock signals CK and CKB, fixed level signals VGH and VGL, to which a signal IN has been input.
The gate of the first transistor M1 is connected to the first clock signal CK, the first stage is connected to the input signal IN, and the second stage is connected to the first stage of the fifth transistor M5;
the gate of the second transistor M2 is connected to the first clock signal CK, the first stage is connected to the low level signal VGL, and the second stage is connected to the gate of the eighth transistor M8;
the gate of the third transistor M3 is connected to the ground level signal VGL, the first stage is connected to the gate of the seventh transistor M7, and the second stage is connected to the second stage of the second transistor M1;
the gate of the fourth transistor M4 is connected to the first stage of the fifth transistor M5, the first stage is connected to the first clock signal CK, and the second stage is connected to the gate of the sixth transistor M6;
the gate of the fifth transistor M5 is connected to the second clock signal CKB, the first stage is connected to the second stage of the first transistor, and the second stage is connected to the first stage of the sixth transistor M6;
the gate of the sixth transistor M6 is connected to the gate of the eighth transistor M8, the first stage is connected to the second stage of the fifth transistor M5, and the second stage is connected to the high level signal VGH;
the gate of the seventh transistor M7 is connected to the first stage of the third transistor M3, the first stage is connected to the second clock signal CKB, and the second stage is connected to the output signal terminal OUT;
the gate of the eighth transistor M8 is connected to the gate of the sixth transistor M6, the first stage is connected to the high level signal VGH, and the second stage is connected to the output signal terminal OUT;
the first capacitor C1 is connected with the grid electrode of the seventh transistor M7 at the first stage and connected with the output signal terminal OUT at the second stage;
the second capacitor C2 has a first stage connected to the high level signal VGH and a second stage connected to the gate of the eighth transistor M8.
The operation of the scan driving circuit of the present embodiment will be described with reference to fig. 4B.
IN the first period P1, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, and the input signal IN is at a low level, at which time the valid signal is written. At this time, the scan driving circuit is to output a low level to operate the pixel circuit, and thus the active signal is at a low level. At this time, the first clock signal CK is at a low level, the first transistor M1 and the second transistor M2 are turned on, the M1 transistor of the low level signal is transmitted to the N3 node, the third transistor M3 is always turned on, so that the low level signal is transmitted to the N1 node, the seventh transistor M7 is turned on, and the second clock signal CKB is at a high level and is transmitted to the output signal terminal OUT through the M7 transistor. Meanwhile, the second transistor M2 is turned on due to the low level of the first clock signal CK, the ground level signal VGL is transmitted to the N2 node by the second transistor, the eighth transistor M8 is turned on, and the high level signal VGH is transmitted to the output signal terminal OUT by the eighth transistor M8. Therefore, a high level signal is output at this time.
IN the second period P2, the first clock signal CK becomes high level, the second clock signal CKB becomes low level, and the input signal IN becomes high level. At this time, the node N3 maintains a low level due to the existence of the capacitor C1, the fourth transistor M4 is turned on, the high level of the first clock signal CK is transmitted to the node N2 by the fourth transistor M4, and the eighth transistor M8 is turned off. At the same time, the first node N1 maintains the low level, the seventh transistor M7 is turned on, and the low level of the first clock signal CKB is transmitted to the output signal terminal OUT by the seventh transistor M7, and the ground level signal is output. Meanwhile, since the output signal terminal OUT is at a high level at the previous time, at this time, OUT becomes a low level, and the signal difference is coupled to the N1 node through the first capacitor C1, so that the gate potential of the seventh transistor M7 becomes lower, and the low level of the second clock signal CKB is completely output to the output signal terminal OUT, thereby completing the function of bootstrap. Capacitor C1 is also called the bootstrap capacitor.
IN the third period P3, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, and the input signal IN is at a high level, at which time the first transistor M1 and the second transistor M2 are turned on. The high level of the input signal IN is transmitted to the N3 node through the first transistor M1 and then to the N1 node through the third transistor M3, and at this time, the seventh transistor M7 is turned off. Meanwhile, the second transistor M2 is turned on, the low level signal VGL is transmitted to the N2 node through the second transistor M2, the eighth transistor M8 is turned on, and the high level signal VGH is transmitted to the output signal terminal OUT through the eighth transistor M8, at this time, a high level signal is output.
IN the fourth period P4, the first clock signal CK becomes high level, the second clock signal CKB becomes low level, and the input signal IN becomes high level. At this time, the first transistor M1 and the second transistor M2 are turned off. At this time, the node N1 remains high at the previous time, so that the seventh transistor M7 is turned off. The node N2 is kept at the low level by the second capacitor C2 at the previous moment, the eighth transistor M8 is turned on, and the high level signal VGH is transmitted to the output signal terminal OUT by the eighth transistor M8, and at this time, a high level signal is output.
After that, the third period P3 and the fourth period P4 are alternately performed, and the high level signal continues to be output until the next time the first clock signal CK and the input signal IN are simultaneously low level signals.
In this embodiment, the high level output from the output signal terminal OUT is output by the high level signal VGH, and the low level signal roommate is output by the low level of the second clock signal CKB. In the present specification, the scan driving circuits are cascaded, and the second clock signal CKB in the next scan driving circuit is the first clock signal CK of the present stage, so that the low level output by the output signal terminal OUT is output by the first clock signal CK and the second clock signal CKB together.
Therefore, in this embodiment, the first signal and the third signal are fixed potential signals, and the second signal and the fourth signal are low-level signals of the clock signal.
Specifically, taking the embodiment of fig. 2 as an example, the high-level signal of the first scan driving circuit unit is the first signal VGH 1; the high level signal of the second scan driving circuit unit is the third signal VGH2 bit second fixed potential signal. The second and fourth signals of the first and second scan driving circuit units are low levels of the first and second clock signals. For example: VGH1 of the first scan driving circuit unit is 10v, and VGH2 of the second scan driving circuit unit is 8 v; the low levels of CK and CKB in the first scan driving circuit unit and the second scan driving circuit unit are both-7 v, and the high levels of CK and CKB are not limited and may be the same or different.
Taking the embodiment of fig. 3 as an example, the high level signals of the first scan driving circuit unit and the second scan driving circuit unit are both VGH. The second signal and the fourth signal are low levels of the first clock signal and the second clock signal. For example: VGH of the first scan driving circuit unit and the second scan driving circuit unit is 8v, low levels of CK and CKB in the first scan driving circuit unit are both-9 v, and low levels of CK and CKB in the second scan driving circuit unit are-7 v.
Further, please refer to fig. 5, fig. 5 is a schematic view of a display panel according to another embodiment of the present application; the organic light emitting display panel includes a first connection line 401a and a second connection line 401 b; the first connection line 401a extends from the driving chip 40 to the first scan driving circuit unit 300a, and provides a first signal to the first scan driving circuit unit 300 a; the second connection line 401b extends from the driving chip to the second scan driving circuit unit 300b, and provides a third signal to the second scan driving circuit unit 300 b; the potential of the first connection line is higher than the potential of the second connection line.
The present embodiment supplies different high level signals to the first scan driving circuit unit 300a and the second scan driving circuit unit 300b based on the adjustment manner of fig. 2. The present embodiment provides a higher high level signal directly from the driving chip 40 to the first scan driving circuit unit, such that VGH1 > VGH2 makes the charging time T1 < T2, such that the data voltage is reduced, the light emitting current is increased, and the brightness is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
Also, based on the embodiment of fig. 3, the second signal may be output to the first scan driving circuit unit 300a and the fourth signal may be output to the second scan driving circuit unit 300b through the connection line 402a and the connection line 402b, and the potential of the third signal is lower than that of the fourth signal, so that VGL1 < VGL2 may make the charging time T3 < T4, so that the data voltage is decreased, the light emitting current is increased, and the luminance is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
In the above arrangement, signal lines are added to the non-display area of the display panel, so that the frame is widened. Referring to fig. 6, fig. 6 is a schematic view of a display panel according to another embodiment of the present application; the embodiment provides a narrow-frame scheme.
The embodiment comprises a third connecting line; the third connection line includes a first connection portion 4030 extended from the driving chip 40 to the first scan driving circuit unit, a first portion 4031 supplying the first signal to the first scan driving circuit unit, and a second portion 4032 supplying the third signal to the second scan driving circuit unit. According to the present embodiment, the first signal is first transmitted to the first driving circuit unit 300a through the driving chip 40, and then the first driving circuit unit 300a is transmitted to the second driving circuit unit 300b, so that the first signal generates a voltage drop and becomes the third signal. The first signal of the first driving circuit unit 300a is made higher than the third signal of the second driving circuit unit 300b without adding signal lines, so that the display panel emits light uniformly.
Further, the voltage drop of the signal line is limited, and in order to increase the voltage difference between the first signal and the third signal and improve the compensation effect, a voltage division connection 4033 is further provided between the first portion 4031 and the second portion 4032. The voltage division connection part drops a part of the voltage, so that the third signal received by the second portion 4032 further drops, and VGH1 > VGH2 makes the charging time T1 < T2, so that the data voltage decreases, the light emitting current increases, and the luminance increases. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
Further, in order to reduce the length of the third connection line and the area occupied by the third connection line on the display panel, the driving chip 40 is located on the side of the display panel close to the first driving circuit 300 a.
In addition to increasing the delay time by increasing the voltage difference between the high and low levels of the scan driver circuit output, the inventors have found that decreasing the width to length ratio of the scan driver circuit cell output transistor can also increase the delay time.
The formula of the output current of the transistor is
When the spaciousness ratio W/L of the output tube is reduced, the driving capability is reduced, so that the time delay is increased, the charging time is reduced, the luminous current is increased, and the brightness is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
Specifically, please refer to fig. 7, fig. 7 is a schematic diagram of a display panel according to another embodiment of the present application; the first driving circuit unit 300a includes a first output transistor 51; the second driving unit 300b includes a second output transistor 52; the width-to-length ratio of the first output transistor 51 is smaller than the width-to-length ratio of the second output transistor 52. Thereby increasing the delay time of the first driving circuit unit and offsetting the brightness reduction of the first display area caused by the small load. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
In both embodiments, the delay time can be increased to counteract the brightness reduction of the first display region due to the small load. So that the whole organic light-emitting display panel has uniform light-emitting brightness. However, considering that the shape of the non-display area may be gradual or abrupt, it is necessary to combine different shapes of the display area to select which compensation method achieves the best compensation effect, and if necessary, the two compensation methods can be used simultaneously. The following examples are given.
Referring to fig. 8 and 9, fig. 9 is a schematic view of a display panel according to another embodiment of the present application; FIG. 9 is an enlarged schematic view of FIG. 8 at the dashed box;
the first display area AA1 is provided with the non-display hole 22; the first connection line 401a extends from the driving chip to the middle stage first scan driving circuit unit. Since the circular or elliptical hole has the longest diameter, the shorter the chord of the edge, the smallest number of sub-pixels in the middle row, the smallest load, the most serious phenomenon of low brightness, and the less serious the surrounding, in the first display area AA1 caused by the non-display hole two. It is impossible to provide a different first connection line per row in a scheme that increases one of the high level and the low level of the first scan circuit unit 300 a. Therefore, in the present embodiment, the first signal is gradually lowered by extending from the driving chip 40 to the middle stage of the first scan driving circuit unit 300a through the first connection line 401a and then transmitting the voltage drop of the signal to both sides using the first connection line. Thus, gradual change compensation can be realized on the premise of not increasing signal lines.
Referring to fig. 8 and 10, fig. 10 is another enlarged schematic view of fig. 8 at the dashed box; for the organic light-emitting display panel with the non-display hole, a method of gradually changing the width-to-length ratios of different output transistors can be adopted for compensation. The first display area is provided with a non-display hole;
among all the first scan driving circuit units 300a, the width-to-length ratio of the output transistors of the first scan driving circuit unit 300a at the middle stage is the smallest; and the aspect ratio of the output transistor of the first scan driving circuit unit 300a increases from the middle stage to both sides. Since the circular or elliptical hole has the longest diameter, the shorter the chord of the edge, the smallest number of sub-pixels in the middle row, the smallest load, the most serious phenomenon of low brightness, and the less serious the surrounding, in the first display area AA1 caused by the non-display hole two. Therefore, the present embodiment sets the width-to-length ratio of the output transistor of the first scan driving circuit unit at the middle stage to be the smallest, and the compensation effect is the largest. And gradually changing compensation is carried out towards two sides, so that the display brightness of the whole first display area is better and uniform.
In another embodiment of the present application. Referring to fig. 11 and 12, fig. 11 is a schematic view of a display panel according to another embodiment of the present application; FIG. 12 is an enlarged schematic view of FIG. 11 at the dashed box;
in this embodiment, the first display area AA1 is provided with the non-display groove 24; as shown in fig. 5, the first connection line 401a extends from the driving chip 40 to a stage closest to the driving chip in the first scan driving circuit unit 300 a. The stage derived closest to the driving chip 40 may reduce the length of the first connection line 401 a. In addition, in the first display area AA1 of the present embodiment, the number of sub-pixels is changed abruptly with respect to the number of sub-pixels in the second display area AA 2. The gray level compensation is performed by changing the aspect ratio of the output transistor, so that the driving capability of the first scan driving circuit driving the sub-pixels of the first display region is greatly reduced, which causes other display problems.
Further, many customers require non-display slots that are not right-angled boundaries but rounded boundaries, and it is also impossible to provide a first connection line for each row with different numbers of sub-pixels, and therefore, in this embodiment,
the non-display slot 24 is provided with a rounded corner; the round corners are correspondingly provided with a first a scanning driving circuit unit 300a1 and a first b scanning driving circuit unit 300a 2; the number of sub-pixels connected to the first a-scan driving circuit unit 300a1 is smaller than the number of sub-pixels connected to the first b-scan driving circuit unit 300a 2; the first scanning driving circuit unit includes a first output transistor 51 a; the first second scan driving circuit unit 300a2 includes a first second output transistor 51 b; the width-to-length ratio of the first a output transistor 51a is smaller than that of the first b output transistor 51 b. And the first driving circuit unit includes a first output transistor; the second driving unit includes a second output transistor; the width-to-length ratio of the first output transistor is smaller than that of the second output transistor;
in this embodiment, for the rounded corner area where the number of sub-pixels gradually changes, compensation is performed in such a manner that the aspect ratio of the output transistor of the first scan driving circuit is reduced. And the width-length ratio of the output transistor of the first scanning driving circuit unit with more sub-pixels to be driven is set to be smaller, so that the compensation of the whole fillet area is consistent, and the display of the whole first display area is more uniform.
In another embodiment of the present application. Referring to fig. 13 and 14, fig. 13 is a schematic view of a display panel according to another embodiment of the present application; FIG. 14 is an enlarged schematic view of FIG. 13 at the dashed box; in this embodiment, different first connection lines are also provided for the first scan driving circuit units driving different numbers of sub-pixels.
The first display area is provided with a round angle 25; similar to the compensation manner of the gradual change of the sub-pixels in each row, the first third scanning driving circuit unit 300a3 and the first third scanning driving circuit unit 300a4 are correspondingly disposed at the corners in the present embodiment; the number of sub-pixels connected to the first third driving circuit unit 300a3 is less than the number of sub-pixels connected to the first third driving circuit unit 300a 4; the first third scanning driving circuit unit 300a3 includes a first third output transistor 51 c; the first but scan driving circuit unit 300a4 includes a first but output transistor 51 d; the width-to-length ratio of the first third output transistor 51c is smaller than that of the first third output transistor 51 d. And compensating the fillet area with gradually changed sub-pixel number in a mode of reducing the width-length ratio of the output transistor of the first scanning driving circuit. And the width-length ratio of the output transistor of the first scanning driving circuit unit with more sub-pixels to be driven is set to be smaller, so that the compensation of the whole fillet area is consistent, and the display of the whole first display area is more uniform.
The present application also discloses an organic light emitting display device. The organic light emitting display device of the present application may include the organic light emitting display panel as described above, and at least one of a light sensor, a distance sensor, a camera, a headphone, a depth sensor, and an iris recognition sensor is disposed at the non-display region. Including but not limited to a cellular phone 1000, a tablet computer, a display of a computer, a display applied to a smart wearable device, a display device applied to a vehicle such as an automobile, etc., as shown in fig. 15. The display device is considered to fall within the scope of protection of the present application as long as the display device includes the display panel included in the display device disclosed in the present application.
In this application, when the delay time of the first scan driving signal is set to be greater than the delay time of the second scan signal, the charging time of the sub-pixels of the first display region may be reduced, so that the data voltage is reduced, the light emitting current is increased, and the luminance is increased. The reduction in brightness of the first display region due to a small load is offset. So that the whole organic light-emitting display panel has uniform light-emitting brightness.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (14)
1. An organic light emitting display panel comprising a display region and a non-display region surrounding the display region,
the display area comprises a first display area and a second display area, and the number of sub-pixels in any row in the first display area is smaller than that in any row in the second display area;
the non-display area is provided with a scanning driving circuit, the scanning driving circuit comprises cascaded scanning driving circuit units, and the scanning driving circuit units comprise a first scanning driving circuit unit and a second scanning driving circuit unit;
the first scanning driving circuit unit is connected with the sub-pixel rows of the first display area and outputs a first scanning driving signal; the second scanning driving circuit unit is connected with the sub-pixel rows of the second display area and outputs a second scanning driving signal;
the delay time of the first scanning driving signal is longer than that of the second scanning signal;
the first scanning driving signal outputs a first high level signal from a first signal and outputs a first low level signal from a second signal; the second scanning driving signal outputs a second high-level signal from a third signal and outputs a second low-level signal from a fourth signal;
the first high level signal is higher than the second high level signal and/or the first low level signal is lower than the second low level signal.
2. The organic light-emitting display panel according to claim 1,
the driving circuit is composed of a P-type transistor, and the first high level signal is higher than the second high level signal; the first low level signal is equal to the second low level signal.
3. The organic light-emitting display panel according to claim 2,
the first signal and the third signal are fixed potential signals, and the second signal and the fourth signal are low level signals of a clock signal.
4. The organic light-emitting display panel according to claim 2, comprising a first connection line and a second connection line;
the first connecting line extends from the driving chip to the first scanning driving circuit unit and provides a first signal for the first scanning driving circuit unit;
the second connecting line extends from the driving chip to a second scanning driving circuit unit and provides a third signal for the second scanning driving circuit unit;
the potential of the first connecting line is higher than that of the second connecting line.
5. The organic light emitting display panel method according to claim 2, comprising a third connection line;
the third connection line includes a first connection part extending from the driving chip to the first scan driving circuit unit, a first part supplying the first signal to the first scan driving circuit unit, and a second part supplying the third signal to the second scan driving circuit unit.
6. The organic light-emitting display panel according to claim 5,
a partial pressure connecting part is also arranged between the first part and the second part.
7. The organic light-emitting display panel according to claim 5,
the driving chip is located on one side of the display panel close to the first scanning driving circuit unit.
8. The organic light-emitting display panel according to claim 1,
the first scan driving circuit unit includes a first output transistor; the second scanning driving circuit unit comprises a second output transistor;
the width-to-length ratio of the first output transistor is smaller than the width-to-length ratio of the second output transistor.
9. The organic light-emitting display panel according to claim 4,
the first display area is provided with a non-display hole;
the first connecting line extends from the driving chip to the middle stage of the first scanning driving circuit unit.
10. The organic light-emitting display panel according to claim 8,
the first display area is provided with a non-display hole;
in all the first scan driving circuit units, the width-to-length ratio of the output transistors of the first scan driving circuit unit in the middle stage is the smallest; and the width-to-length ratio of the output transistor of the first scan driving circuit unit is increased from the middle stage to two sides.
11. The organic light-emitting display panel according to claim 4,
the first display area is provided with a non-display groove;
the first connecting line extends from the driving chip to a stage of the first scan driving circuit unit closest to the driving chip.
12. The organic light-emitting display panel according to claim 11,
the first scan driving circuit unit includes a first output transistor; the second scan driving circuit unit includes a second output transistor; the width-to-length ratio of the first output transistor is smaller than that of the second output transistor;
the non-display groove is provided with a fillet;
a first scanning driving circuit unit A and a first scanning driving circuit unit B are correspondingly arranged at the round corners; the number of sub-pixels connected with the first scanning driving circuit unit is smaller than that connected with the first second driving circuit unit;
the first scanning driving circuit unit comprises a first output transistor; the first second scanning driving circuit unit comprises a first second output transistor; the width-to-length ratio of the first A output transistor is smaller than that of the first B output transistor.
13. The organic light-emitting display panel according to claim 8,
the first display area is provided with a round angle;
a first third scanning driving circuit unit and a first fourth scanning driving circuit unit are correspondingly arranged at the round corners; the number of sub-pixels connected with the first third scanning driving circuit unit is smaller than that connected with the first third driving circuit unit;
the first third scanning driving circuit unit comprises a first third output transistor; the first D scanning driving circuit unit comprises a first D output transistor; the width-length ratio of the first third output transistor is smaller than that of the first fourth output transistor.
14. An organic light emitting display device comprising the organic light emitting display panel according to any one of claims 1 to 13.
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| CN110264893B (en) * | 2019-06-18 | 2021-07-30 | 上海天马微电子有限公司 | Display panel and display device |
| CN110265448B (en) * | 2019-06-24 | 2021-11-02 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113823207A (en) * | 2020-06-18 | 2021-12-21 | 华为技术有限公司 | Drive control method and related equipment |
| CN111833813B (en) * | 2020-07-17 | 2022-03-08 | 昆山国显光电有限公司 | Pixel circuit, driving method thereof, display panel and display device |
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| CN114596807A (en) * | 2022-03-18 | 2022-06-07 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
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