CN110264893B - Display panel and display device - Google Patents
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- CN110264893B CN110264893B CN201910526279.XA CN201910526279A CN110264893B CN 110264893 B CN110264893 B CN 110264893B CN 201910526279 A CN201910526279 A CN 201910526279A CN 110264893 B CN110264893 B CN 110264893B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises: the display panel comprises a first display area and a second display area which are sequentially arranged along a first direction, wherein the width of the first display area is smaller, a first routing of the first display area comprises a first grid line extending along the first direction and a first fanout line connected with the first grid line, and a second routing of the second display area comprises a second grid line formed by extending the first grid line to the second display area along the first direction and a second fanout line connected with the second grid line; the first grid line and the second grid line are disconnected at the junction position of the first display area and the second display area; the first wire and the second wire are different in form and/or the overlapping areas of the first grid line and the second grid line with other conductive film layers are different, so that the difference between the absolute values of the optimal common voltages of the first display area and the second display area is smaller than or equal to 400mV, the problem of uniformity at the junction of the two display areas is reduced, and the display effect of the display panel is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the increasing maturity and perfection of the intelligent automobile application technology, the demand for the vehicle-mounted display screen is more and more diversified.
At present, vehicle-mounted Display screens are mainly classified into instrument Display screens (Cluster), Center information Display screens (CID), Rear Seat Entertainment Display screens (RSE), and the like, wherein the Cluster and the CID are front-loading Display screens, the Cluster is used for displaying various information, and the CID is used for displaying information such as audio, navigator, air conditioner control, and the like.
With the wide use of the large vehicular screen, automobile manufacturers require that Cluster and CID are combined in one large vehicular screen for separate display. In order to meet the requirements of automobile manufacturers, a display screen is divided into two parts for separate display, but when the size and resolution of two sub-screens (i.e. two part display areas divided for display) in the display screen are different, a homogeneous Mura risk is easy to occur at the joint of the two sub-screens.
In view of this, how to prevent the split screens with different sizes and resolutions in the same display screen from generating the Mura risk at the split screen joint is a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the problem that the joint of two screens is easy to generate uniformity risk in the same display screen in the prior art.
In a first aspect, to solve the above technical problem, an embodiment of the present invention provides a display panel, in which a first display region and a second display region are sequentially arranged along a first direction, the display panel including:
the first display area is arranged on one side of the first display area far away from the second display area, and the second display area is arranged on one side of the second display area far away from the first display area;
the first display area is provided with a first routing, the second display area is provided with a second routing, the first routing comprises a first grid line extending along a first direction and a first fanout line connected with the first grid line, and the second routing comprises a second grid line formed by extending the first grid line to the second display area along the first direction and a second fanout line connected with the second grid line; in the first direction, the width of the first display area is smaller than the width of the second display area;
the first grid line and the second grid line are disconnected at the junction of the first display area and the second display area;
the shapes of the first trace and the second trace are different and/or the overlapping areas of the first gate line and the second gate line with other conductive film layers are different, so that the difference between the absolute values of the optimal common voltage Vcom1 in the first display area and the optimal common voltage Vcom2 in the second display area is smaller than or equal to 400 mV.
In a second aspect, an embodiment of the present invention provides a display panel, in which a first display region and a second display region are sequentially arranged along a first direction, the display panel including:
the first display area is arranged on one side of the first display area far away from the second display area, and the second display area is arranged on one side of the second display area far away from the first display area;
the first display area is provided with a first routing, the second display area is provided with a second routing, the first routing comprises a first grid line extending along a first direction and a first fanout line connected with the first grid line, and the second routing comprises a second grid line formed by extending the first grid line to the second display area along the first direction and a second fanout line connected with the second grid line; in the first direction, the width of the first display area is smaller than the width of the second display area;
the first grid line and the second grid line are disconnected at the junction of the first display area and the second display area;
a common electrode covering the first display area and the second display area, and being disconnected at a junction of the first display area and the second display area; in the common electrode, the part of the common electrode positioned in the first display area is a first sub-common electrode, and the part of the common electrode positioned in the second display area is a second sub-common electrode;
the difference between the optimal common voltage Vcom1 loaded on the first sub-common electrode and the optimal common voltage Vcom2 loaded on the second sub-common electrode has a value ranging from-300 mV to 0 mV.
In a third aspect, an embodiment of the present invention provides a display device, which includes the display panel of the first aspect or the second aspect.
The invention has the following beneficial effects:
in the embodiment provided by the invention, the display panel is provided with the first display region and the second display region arranged along the first direction, the first gate line in the first display region extends into the second display region B along the first direction to form the second gate line, and the first gate line and the second gate line are disconnected at the position where the first display region and the second display region are intersected, the first gate line of the first display region is driven by a plurality of first driving circuits arranged at one side of the first display region, the second gate line of the second display region is driven by a plurality of second driving circuits arranged at one side of the second display region, so that the display panel can display in a split screen manner between the first display region and the second display region, because in the display panel, the first gate line comprising the first gate line and the first fan-out line has a different form from the second gate line comprising the second gate line and the second fan-out line, and/or the overlapping areas of the first grid line and the second grid line with other conductive film layers are different, so that the difference between the absolute values of the optimal common voltage Vcom1 of the first display area and the optimal common voltage Vcom2 of the second display area is less than or equal to 400mV, the problems of display uniformity and signal abnormity at the junction due to the difference of resolution and size of the first display area and the second display area can be effectively reduced, and the display effect of the display panel is improved.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an optimal common voltage Vcom according to an embodiment of the invention;
fig. 4 is a partial plan structure diagram of a boundary between a first display area a and a second display area B of a display panel according to an embodiment of the present invention;
fig. 5 is a partial plan structure diagram of the first display area a and the second display area B of the display panel at the fan-out line position according to the embodiment of the present invention;
FIG. 6 is a first partial plan view of the portion of FIG. 5 shown within the dashed box according to an embodiment of the present invention;
fig. 7 is a partial plan view of a portion shown in a dashed box in fig. 5 according to an embodiment of the present invention;
fig. 8 is a partial plan view of a portion shown in a dotted frame in fig. 5 according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a common electrode in a dashed area in fig. 5 according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a display panel and a display device, which are used for solving the problem that the joint of two screens is easy to generate uniformity risk in the same display screen in the prior art.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
The following describes a display panel and a display device provided in an embodiment of the present invention with reference to the accompanying drawings.
Before the scheme of the application is introduced, a simple introduction is made to the design of the vehicle-mounted large screen by the inventor so that the embodiment provided by the application can be more accurately understood.
With the development of vehicle-mounted intelligence, different functions are given to the Cluster and the CID, so that the contents required to be displayed are different, and the requirements on the screen size and the resolution are different correspondingly. At present, when the automobile system realizes the driving display of the vehicle-mounted screen, the frequency supported by the used driving interface can only support a smaller screen, so that the existing vehicle-mounted system cannot be used for driving the large vehicle-mounted screen, while the development cost of the new vehicle-mounted system is high, the development period is long, and after the cost, time and product trend are comprehensively considered, an automobile manufacturer hopes to continuously drive the Cluster and the CID of the large vehicle-mounted screen (in the same display screen) by the existing vehicle-mounted system. In order to meet the requirement of automobile manufacturers, the inventor adopts a Gate line or Vcom disconnection design at the combination of the Cluster region and the CID region of the vehicle-mounted large screen, so that the prior vehicle-mounted system respectively drives and displays the Cluster region and the CID region.
In addition, due to the fact that the sizes and the resolutions of the screens corresponding to the Cluster and the CID are different, the loads (RC loading) of the resistors and the capacitors of the screens corresponding to the Cluster and the CID are different, the uniformity of the pictures corresponding to the Cluster and the CID is poor, and the Mura risk is easy to occur at the joint of the two screens.
In view of this, the present disclosure provides a display panel for implementing split-screen driving of a large screen on a vehicle and solving the problem of poor display at a disconnected portion, as shown in fig. 1.
Referring to fig. 1, a schematic structural diagram of a display panel according to an embodiment of the present invention is shown, in which a first display area a (shown by an area covered by oblique lines in fig. 1) and a second display area B (shown by an area covered by grid lines in fig. 1) are sequentially arranged along a first direction X, and the display panel includes:
the plurality of first driving circuits 10 and the plurality of second driving circuits 20 are respectively disposed on a side of the first display area a away from the second display area B in the first direction X, and the second display area B is away from the first display area a. It should be noted that the first driving circuit 10 and the second driving circuit 20 may be driving chips, gate driving circuits, and the like, and are not limited herein, and only one first driving circuit 10 and one second driving circuit 20 are illustrated in fig. 1, or two or more first driving circuits and second driving circuits may be illustrated, and are not limited herein.
The first display region a and the second display region B together constitute a complete display region of the display panel. Please refer to fig. 2, which is another schematic structural diagram of the display panel according to the embodiment of the present invention, wherein when the display panel is an odd-shaped screen, the first display area a and the second display area B are as shown in fig. 2.
The first display area a has a first wire 11, the second display area has a second wire 21, the first wire 11 includes a first gate line 111 extending along a first direction and a first fanout line 112 connected thereto, the second wire 21 includes a second gate line 211 formed by the first gate line 111 extending to the second display area B along the first direction X, and a second fanout line 212 connected thereto; in the first direction X, the width H of the first display region A1Is smaller than the width H of the second display region B2. In fig. 1 and 2, a data line crosses the first gate line 111 and the second gate line 211, the data line is connected to the data driving circuit 40, each pixel in the first display region a is defined by the first gate line 111 crossing the data line, and the corresponding pixel is displayed or not displayed by controlling a Transistor (TFT) connected thereto to be turned on or off, and each pixel in the second display region B is defined by the second gate line 211 crossing the data line.
It should be noted that the data driving circuit 40 may be a driving chip, which is illustrated by only one data driving circuit 40 in fig. 1 and 2, or may be two or more, and is not limited herein.
At the boundary position of the first display region a and the second display region B, the first gate line 111 and the second gate line 211 are disconnected. Therefore, the same display panel can carry out split-screen display and split-screen drive.
The shapes of the first trace 11 and the second trace 21 are different and/or the overlapping areas of the first gate line 111 and the second gate line 211 with other conductive film layers are different, so that the difference between the absolute values of the optimal common voltage Vcom1 in the first display region a and the optimal common voltage Vcom2 in the second display region B is less than or equal to 400 mV.
In the display panel, the optimal common voltage Vcom is a common voltage value when the positive and negative liquid crystal voltages are the same, and is usually measured through experiments. Referring to fig. 3, a schematic diagram of a common voltage Vcom provided by the embodiment of the invention is shown in fig. 3, wherein V isdataRepresentative data voltage, VgateRepresenting the grid line voltage, Vpixel+Representing the charged voltage, V, of the pixel electrodepixel-Representing the voltage, V, after discharge of the pixel electrodelc+Is a positive polarity liquid crystal voltage, Vlc-Is a negative polarity liquid crystal voltage. Vlc+＝Vpixel+-Vcom，Vlc-＝Vcom-Vpixel-. When Vcom is adjusted to make Vlc+＝Vlc-The corresponding Vcom value is referred to as the optimum common voltage Vcom.
In the embodiment provided by the invention, the optimal common voltage Vcom1 determined in the first display region a can be obtained by adjusting after closing the second display region, and similarly, the optimal common voltage Vcom2 determined in the second display region a can be obtained by adjusting after closing the first display region, and the final optimal common voltage Vcom of the display panel can be any value between Vcom1 and Vcom2, but | Vcom1-Vcom2| should be | ≦ 400 mV. Therefore, the problem of uniformity of the boundary of the first display area A and the second display area B can be effectively prevented, and the display effect is improved.
It should be understood that the first trace 11 and the second trace 21 are shown in a straight line in fig. 1 and fig. 2, and the first trace 11 and the second trace 21 may not be straight lines in practical applications. The shape of the first trace 11 and the second trace 21 refers to the width or the length of the traces.
In the embodiment provided by the present invention, the display panel is arranged with the first display region a and the second display region B along the first direction X, the second gate line 211 is formed by extending the first gate line 111 in the first display region a into the second display region B along the first direction X, and at the position where the first display region a and the second display region B are intersected, the first gate line 111 is disconnected from the second gate line 211, the first gate line 111 of the first display region is driven by a plurality of first driving circuits disposed at one side of the first display region a, the second gate line 211 of the second display region is driven by a plurality of second driving circuits disposed at one side of the second display region B, so that the display panel can be driven and displayed separately in the first display region a and the second display region B, and since in the display panel, the first gate line 11 including the first gate line 111 and the first fan-out line 112, the resistance of the first display area a and the second display area B is changed differently from the form of the second wire 21 including the second gate line 211 and the second fanout line 212, so that the RC loading of the first display area a is increased on the original basis to reduce the Feed through voltage (Feed through), thereby increasing the voltage of the pixel electrode in the first display area a; or, the RC loading of the second display area B is reduced on the original basis to increase the Feedthrough, this can reduce the voltage of the pixel electrode in the second display region B, and finally make the difference between the absolute value of the optimal common voltage Vcom1 in the first display region a and the absolute value of the optimal common voltage Vcom2 in the second display region B less than or equal to 400mV, thereby effectively reducing the uniformity problem caused by the difference of resolution and size between the first display area A and the second display area B at the position of the broken grid line, furthermore, the display effect of the display panel is improved, and it should be noted that the RC loading of the first display area a and the RC loading of the second display area B may also be adjusted simultaneously, so that the Feed through of the first display area a is reduced, the Feed through of the second display area B is increased, the mura problem of the display panel at the grid line disconnection position is improved, and the display effect of the display panel is improved.
And/or in the display panel, the overlapping areas of the first gate line 111 and the second gate line 211 and other conductive film layers are respectively different to change the capacitance of the first display area a and the second display area B, so that the RC loading of the first display area a is increased on the original basis to reduce the feedback thereof, and thus, the voltage of the pixel electrode in the first display area a can be increased; and/or, the RC loading of the second display region B is reduced on the original basis to increase the Feedthrough thereof, so that the voltage of the pixel electrode in the second display region B can be reduced, and finally, the difference between the absolute values of the optimal common voltage Vcom1 of the first display region a and the optimal common voltage Vcom2 of the second display region B is smaller than or equal to 400mV, and when the difference between the absolute values of Vcom1 and Vcom2 is smaller than 400mV, the uniformity problem of the first display region a and the second display region B at the grid line disconnection position can not be observed by human eyes, so that the above scheme can effectively reduce the uniformity problem of the first display region a and the second display region B at the grid line disconnection position due to the difference of resolution and size, thereby improving the display effect of the display panel.
Note that the resistance of the first display region a or the second display region B can be changed by changing the form of the first gate line 111 or the form of the second gate line 211 alone, or the resistance of the first display region a and the resistance of the second display region B can be changed by changing the form of the first gate line 111 and the form of the second gate line 211 at the same time, as long as the absolute value difference between the optimum common voltage Vcom1 of the first display region a and the optimum common voltage Vcom2 of the second display region B is not more than 400 mV. Therefore, the form of the first gate line 111 or the second gate line 211 is not limited herein, and may be changed independently or simultaneously.
Similarly, the capacitance of the first display region a may be changed by separately changing the overlapping area of the first gate line 111 and another conductive film layer, or the capacitance of the second display region B may be changed by separately changing the overlapping area of the second gate line 211 and another conductive film layer; the overlapping area of the first gate line 111 and the other conductive film layer and the overlapping area of the second gate line 211 and the other conductive film layer can be changed simultaneously to change the capacitance of the first display region a and the second display region B, as long as the absolute value difference between the optimal common voltage Vcom1 of the first display region a and the optimal common voltage Vcom2 of the second display region B is smaller than or equal to 400 mV. Therefore, it is not limited herein that the overlapping area of the first gate line 111 or the second gate line 211 and the other conductive film layer is changed independently or separately.
In the embodiment provided by the present invention, the difference between the absolute values of the optimal common voltage Vcom1 in the first display area a and the optimal common voltage Vcom2 in the second display area B is less than or equal to 400mV due to the different shapes of the first trace 11 and the second trace 21 and/or the different overlapping areas of the first gate line 111 and the second gate line 211 with other conductive film layers, which can be implemented by adopting the following schemes:
fig. 4 is a partial plan structure diagram of a boundary between a first display area a and a second display area B of a display panel according to an embodiment of the present invention.
The first scheme is as follows: width W of the first gate line 1111Is smaller than the width W of the second gate line 2112。
Optionally, the width W of the first gate line 1111The value range is as follows:
wherein H1、H2The width of the first display area A and the width of the second display area B, W1、W2The widths of the first gate line 111 and the second gate line 211 respectively.
Although fig. 4 only shows the widths of the first gate line 111 and the second gate line 211 in the first display region a and the second display region B, the widths of the first gate line 111 and the second gate line 211 in the entire first display region a and the entire second display region B may be set as shown in fig. 4, or the widths of the gate lines in the two display regions may be set to be different, which is not limited herein.
In the embodiment provided by the present invention, the first gate line 111 is formed by setting the width W of the first gate line1Is set to be smaller than the width W of the second gate line 2112The resistance load in the first display area A can be improved, the RC loading of the first display area A is increased on the original basis to reduce the Feed-through voltage Feed through, so that the signal delay of the junction of the first display area A and the second display area B is the same or close to the same, the voltage of the pixel electrode in the first display area A can be increased, and finally the first display area A is enabled to be increasedThe difference between the absolute values of the optimal common voltage Vcom1 of the display area a and the optimal common voltage Vcom2 of the second display area B is less than or equal to 400mV, so that the problem of uniformity at the grid line disconnection position due to different resolutions and sizes of the first display area a and the second display area B is effectively solved, and the display effect of the display panel is improved.
Fig. 5 is a partial plan structure diagram of the first display area a and the second display area B of the display panel at the position of the fan-out line according to the embodiment of the present invention.
The second scheme is as follows: the length L of the first fanout line 1121Is longer than the length L of the second fanout line 2122。
Optionally, the length of the first fanout line has a value range of:
L2<L1<1.2L2H2/H1；
wherein H1、H2The width of the first display area A and the width of the second display area B, L1、L2The lengths of the first fanout line 112 and the second fanout line 212 are respectively.
In the third scheme: width W of the first fanout line 1123Is less than the width W of the second fanout line 2124。
Optionally, the width W of the first fanout line 1123The value range is as follows:
wherein H1、H2The width of the first display area A and the width of the second display area B, W3、W4The widths of the first fanout line 112 and the second fanout line 212 are respectively.
In the embodiment provided by the present invention, the length L of the first fanout line 112 is adjusted by1Is longer than the length L of the second fanout line 2122And/or the width W of the first fanout line 1123Is set to be smaller than the width W of the second fanout line 2124Can make the first displayThe resistance load in the display area A is improved, the RC loading of the first display area A is increased on the original basis to reduce the Feed-through voltage Feed through, so that the signal delay of the boundary of the first display area A and the second display area B is the same or close to the same, and the Feed through is the same or close to the same, the voltage of a pixel electrode in the first display area A can be increased, and finally, the difference between the absolute values of the optimal common voltage Vcom1 of the first display area A and the optimal common voltage Vcom2 of the second display area B is smaller than or equal to 400mV, the problem of uniformity at the grid line disconnection position due to different resolutions and sizes of the first display area A and the second display area B is effectively reduced, and the display effect of the display panel is improved.
Referring to fig. 6, a first partial plan view of a portion shown in a dashed box in fig. 5 according to an embodiment of the present invention is shown.
A fourth scheme, the display panel includes a first transistor 12 (shown as a filling dot and a region surrounded by a dot in an oblique scribe line in fig. 6) and a second transistor 22 (shown as a filling dot and a region surrounded by a dot in an oblique scribe line in fig. 6), the first transistor 12 being connected to the first gate line 111, the second transistor 22 being connected to the second gate line 211; and, the overlapping area a of the first gate line 111 and the source electrode 121 of the first transistor 121(shown as an area within a thick dashed line frame in fig. 6) is larger than an overlapping area a of the second gate line 211 and the source electrode 121 of the second transistor 222(shown as the area within the bold dashed box in FIG. 6).
It should be noted that the first transistor 12 and the second transistor 22 further have semiconductor layers, which are shown in fig. 6 by the areas within the thin dashed boxes of the first gate line 111 and the second gate line 211, it should be understood that in order to make the areas covered by the first gate line 111 and the second gate line 211 clearly known to those skilled in the art, the areas shown by the semiconductor layers are processed in a semi-transparent manner, and that the areas covered by the semiconductor layers shown in fig. 6 also have gate lines, but they are in different layers. The semiconductor layers in fig. 7 to 9 are also shown as in fig. 6, and the description will not be repeated.
Optionally, the overlapping area a1 of the first gate line 111 and the source 121 of the first transistor 12 has a value range as follows:
A2<A1<1.2A2H2/H1；
wherein H1、H2The width of the first display area A and the width of the second display area B, A1、A2An overlapping area of the first gate line 111 and the source electrode 121 of the first transistor 12, and an overlapping area of the second gate line 211 and the source electrode 221 of the second transistor 22, respectively.
It should be understood that, in fig. 6, the first transistor 12 and the second transistor 22 are filling points and areas surrounded by points in the diagonal scribe lines, and since the Gate electrode and the Gate line of the transistor are formed by one-step patterning when the transistors (the first transistor 111 and the second transistor 22) and the Gate line (the first Gate line 111 and the second Gate line 211) are fabricated, the Gate electrode of the transistor is also generally referred to as a Gate line (Gate line) and is not particularly distinguished from the Gate electrode of the transistor, and similarly, the Source electrode of the transistor and the scan line (Source line) are also formed by one-step patterning when the transistors are fabricated, the Source electrode of the transistor is also generally referred to as a scan line, where a is described above1、A2And may also be understood as an overlapping area of the gate line and the scan line.
Referring to fig. 7, a partial plan structure diagram ii of a portion shown in a dashed box in fig. 5 according to an embodiment of the present invention is provided.
In the fifth scheme, the overlapping area a of the first gate line 111 and the drain 122 of the first transistor 123(shown as the region within the thick dashed box in fig. 7) is smaller than the overlapping area a of the second gate line 211 and the drain 222 of the second transistor 224(shown in fig. 7 as the area within the bold dashed box).
Optionally, an overlapping area a of the first gate line and 111 the drain 122 of the first transistor 123The value range is as follows:
(5/6)A4<A3<A4；
wherein A is3、A4The overlapping area of the first gate line 111 and the drain 122 of the first transistor 12, and the overlapping area of the second gate line 211 and the second transistor 22The overlap area of the drain 222.
In the embodiment provided by the present invention, the overlapping area a of the first gate line 111 and the source electrode 121 of the first transistor 12 is defined1Is set to be smaller than an overlapping area a of the second gate line 211 and the source electrode 121 of the second transistor 222And/or an overlapping area a of the first gate line 111 and the drain electrode 122 of the first transistor 123Is smaller than the overlapping area A of the second gate line 211 and the drain electrode 222 of the second transistor 224The capacitive load in the first display area a can be improved, so that the RC loading of the first display area a is increased on the original basis to reduce the Feed through thereof, and thus the signal delay and the Feed through at the boundary between the first display area a and the second display area B are the same or nearly the same, so that the voltage of the pixel electrode in the first display area a can be increased, and further the difference between the absolute values of the optimal common voltage Vcom1 of the first display area a and the optimal common voltage Vcom2 of the second display area B is smaller than or equal to 400mV, and finally the uniformity problem at the grid line disconnection position due to the difference of resolution and size between the first display area a and the second display area B is effectively reduced, and the display effect of the display panel is improved.
Referring to fig. 8, a partial plan structure diagram of a portion shown in a dashed box in fig. 5 according to an embodiment of the present invention is shown.
In a sixth solution, the display panel further includes a common electrode 30, and the common electrode 30 covers the first display area a and the second display area B; an overlapping area a of the first gate line 111 and the common electrode 305(shown as an area within a thick dotted line frame in fig. 8) is larger than an overlapping area a of the second gate line 211 and the common electrode 306(shown as the area within the bold dashed box in FIG. 8).
Optionally, an overlapping area a of the first gate line 111 and the common electrode 305The value range is as follows:
A6<A5<1.2A4H2/H1；
wherein H1、H2Respectively the width of the first display area and the width of the second display area, A5、A6Are respectively the firstThe overlapping area of one gate line 111 and the common electrode 30, and the overlapping area of the second gate line 211 and the common electrode 30.
In the embodiment provided by the present invention, the overlapping area a of the first gate line 111 and the common electrode 30 is defined by5Is set to be larger than the overlapping area A of the second gate line 211 and the common electrode 306The capacitive load in the first display area a can be improved, so that the RC loading of the first display area a is increased on the original basis to reduce the Feed through thereof, and thus the signal delay and the Feed through at the boundary between the first display area a and the second display area B are the same or nearly the same, so that the voltage of the pixel electrode in the first display area a can be increased, and further the difference between the absolute values of the optimal common voltage Vcom1 of the first display area a and the optimal common voltage Vcom2 of the second display area B is smaller than or equal to 400mV, and finally the uniformity problem at the grid line disconnection position due to the difference of resolution and size between the first display area a and the second display area B is effectively reduced, and the display effect of the display panel is improved.
It should be understood that the above various schemes provided by the present invention can be implemented individually, or can be implemented after any combination, and finally, it is only necessary to make the difference between the absolute values of the optimal common voltage Vcom1 in the first display region a and the optimal common voltage Vcom2 in the second display region B less than or equal to 400 mV.
Based on the same inventive concept, an embodiment of the present invention provides a display panel, a schematic structural diagram of the display panel may refer to fig. 1 and fig. 2, and parts the same as those in the display panel are not repeated, specifically please refer to the above embodiment, the difference between the display panel and the structure in the above embodiment is that the first display area a and the second display area B use the same common electrode, and the first display area a and the second display area B have respective common electrodes in the embodiment, please refer to fig. 9, which is a schematic structural diagram of the common electrode in the dashed line area in fig. 5, and the display panel includes:
the plurality of first driving circuits 10 and the plurality of second driving circuits 20 are respectively disposed on a side of the first display area a away from the second display area B in the first direction X, and the second display area B is away from the first display area a.
The first display area a has a first wire 11, the second display area has a second wire 21, the first wire 11 includes a first gate line 111 extending along a first direction and a first fanout line 112 connected thereto, the second wire 21 includes a second gate line 211 formed by the first gate line 111 extending to the second display area B along the first direction X, and a second fanout line 212 connected thereto; in the first direction X, the width H of the first display region A1Is smaller than the width H of the second display region B2。
At the boundary position of the first display region a and the second display region B, the first gate line 111 and the second gate line 211 are disconnected.
The common electrode 30 covering the first display area a and the second display area B is disconnected at the boundary position between the first display area a and the second display area B; in the common electrode 30, a portion located in the first display region a is a first sub-common electrode 301, and a portion located in the second display region B is a second sub-common electrode 302.
The difference between the optimal common voltage Vcom1 applied to the first sub-common electrode 301 and the optimal common voltage Vcom2 applied to the second sub-common electrode 302 has a value in the range of-300 mV to 0 mV.
In the embodiment provided by the present invention, the display panel is arranged with the first display region a and the second display region B along the first direction X, the second gate line 211 is formed by extending the first gate line 111 in the first display region a into the second display region B along the first direction X, and the first gate line 111 is disconnected from the second gate line 211 at a position where the first display region a and the second display region B are intersected, the first gate line 111 of the first display region is driven by a plurality of first driving circuits provided at a side of the first display region a, the second gate line 211 of the second display region is driven by a plurality of second driving circuits provided at a side of the second display region B, so that the display panel can be displayed in a split screen manner in the first display region a and the second display region B, since in the display panel, the common electrode 30 covering the first display region a and the second display region B, the junction position between the first display area A and the second display area B is disconnected; dividing the common electrode 30 into a first sub-common electrode 301 located in the first display area a and a second sub-common electrode 302 located in the second display area B; therefore, the common voltages of the first display area a and the second display area B can be respectively adjusted, so that the difference between the optimal common voltage Vcom1 loaded on the first sub-common electrode 301 and the optimal common voltage Vcom2 loaded on the second sub-common electrode 302 can be in the range of-300 mV to 0mV, and when the difference between the optimal common voltage Vcom1 and the optimal common voltage Vcom2 is in the range of-300 mV to 0mV, the uniformity problem of the first display area a and the second display area B at the grid line break position can not be observed by human eyes, so that the uniformity problem of the first display area a and the second display area B at the junction position due to the difference of the resolution and the size can be effectively reduced, and the display effect of the display panel can be further improved.
Based on the same inventive concept, embodiments of the present invention provide a display device including any one of the various display panels described above.
The display device can be a liquid crystal display, a liquid crystal display screen, a liquid crystal television and other display devices, and can also be mobile equipment such as a mobile phone, a tablet personal computer, a notebook computer and the like.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A display panel, wherein a first display region and a second display region are arranged in order along a first direction, the display panel comprising:
the first display area is arranged on one side of the first display area far away from the second display area, and the second display area is arranged on one side of the second display area far away from the first display area;
the first display area is provided with a first routing, the second display area is provided with a second routing, the first routing comprises a first grid line extending along a first direction and a first fanout line connected with the first grid line, and the second routing comprises a second grid line formed by extending the first grid line to the second display area along the first direction and a second fanout line connected with the second grid line; in the first direction, the width of the first display area is smaller than the width of the second display area;
the first grid line and the second grid line are disconnected at the junction of the first display area and the second display area;
the shapes of the first trace and the second trace are different and/or the overlapping areas of the first gate line and the second gate line with other conductive film layers are different, so that the difference between the absolute values of the optimal common voltage Vcom1 in the first display area and the optimal common voltage Vcom2 in the second display area is smaller than or equal to 400 mV.
2. The display panel of claim 1,
the width of the first grid line is smaller than that of the second grid line.
3. The display panel of claim 2, wherein the width of the first gate line ranges from:
wherein H1、H2Respectively the width of the first display area, the width of the second display area, W1、W2The widths of the first grid line and the second grid line are respectively.
4. The display panel of claim 1, wherein a length of the first fanout line is greater than a length of the second fanout line.
5. The display panel of claim 4,
the length of the first fanout line has a value range as follows:
L2<L1<1.2L2H2/H1；
wherein H1、H2Respectively the width of the first display area, the width of the second display area, L1、L2The lengths of the first fan-out line and the second fan-out line are respectively.
6. The display panel of claim 1, wherein a width of the first fanout line is less than a width of the second fanout line.
7. The display panel of claim 6, wherein the width of the first fanout line has a range of values:
wherein H1、H2Respectively the width of the first display area, the width of the second display area, W3、W4The widths of the first fan-out line and the second fan-out line are respectively set.
8. The display panel according to claim 1, wherein a first transistor and a second transistor, the first transistor being connected to the first gate line, the second transistor being connected to the second gate line;
the overlapping area of the first gate line and the source electrode of the first transistor is larger than the overlapping area of the second gate line and the source electrode of the second transistor.
9. The display panel according to claim 8, wherein an overlapping area of the first gate line and the source electrode of the first transistor has a value in a range of:
A2<A1<1.2A2H2/H1；
wherein H1、H2Respectively the width of the first display area and the width of the second display area, A1、A2The overlap area of the first gate line and the source electrode of the first transistor and the overlap area of the second gate line and the source electrode of the second transistor are respectively.
10. The display panel of claim 1, wherein the display panel further comprises: a first transistor and a second transistor, the first transistor being connected to the first gate line, the second transistor being connected to the second gate line;
the overlapping area of the first grid line and the drain electrode of the first transistor is smaller than the overlapping area of the second grid line and the drain electrode of the second transistor.
11. The display panel according to claim 10, wherein an overlapping area of the first gate line and the drain of the first transistor has a value in a range of:
(5/6)A4<A3<A4；
wherein A is3、A4The overlap area of the first gate line and the drain of the first transistor and the overlap area of the second gate line and the drain of the second transistor are respectively.
12. The display panel of claim 1, wherein the display panel further comprises: a common electrode covering the first display area and the second display area;
the overlapping area of the first grid line and the common electrode is larger than that of the second grid line and the common electrode.
13. The display panel according to claim 12, wherein an overlapping area of the first gate line and the common electrode has a range of values:
A6<A5<1.2A4H2/H1；
wherein H1、H2Respectively the width of the first display area and the width of the second display area, A5、A6The first grid line and the common electrode are respectively overlapped in area, and the second grid line and the common electrode are respectively overlapped in area.
14. A display panel, wherein a first display region and a second display region are arranged in order along a first direction, the display panel comprising:
the first display area is arranged on one side of the first display area far away from the second display area, and the second display area is arranged on one side of the second display area far away from the first display area;
the first display area is provided with a first routing, the second display area is provided with a second routing, the first routing comprises a first grid line extending along a first direction and a first fanout line connected with the first grid line, and the second routing comprises a second grid line formed by extending the first grid line to the second display area along the first direction and a second fanout line connected with the second grid line; in the first direction, the width of the first display area is smaller than the width of the second display area;
the first grid line and the second grid line are disconnected at the junction of the first display area and the second display area;
a common electrode covering the first display area and the second display area, and being disconnected at a junction of the first display area and the second display area; in the common electrode, the part of the common electrode positioned in the first display area is a first sub-common electrode, and the part of the common electrode positioned in the second display area is a second sub-common electrode;
the difference between the optimal common voltage Vcom1 loaded on the first sub-common electrode and the optimal common voltage Vcom2 loaded on the second sub-common electrode has a value ranging from-300 mV to 0 mV.
15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.
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