CN109429530B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

Info

Publication number
CN109429530B
CN109429530B CN201780002329.3A CN201780002329A CN109429530B CN 109429530 B CN109429530 B CN 109429530B CN 201780002329 A CN201780002329 A CN 201780002329A CN 109429530 B CN109429530 B CN 109429530B
Authority
CN
China
Prior art keywords
conductive pattern
semiconductor switch
main electrode
electrode
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201780002329.3A
Other languages
Chinese (zh)
Other versions
CN109429530A (en
Inventor
森永雄司
久德淳志
菊地芳彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Publication of CN109429530A publication Critical patent/CN109429530A/en
Application granted granted Critical
Publication of CN109429530B publication Critical patent/CN109429530B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

To provide a semiconductor device capable of preventing a failure of a power supply circuit even when a bypass capacitor and the power supply circuit are provided. [ MEANS FOR SOLVING PROBLEMS ] A semiconductor device 1 according to an embodiment includes: an insulating substrate 2; conductive pattern portions 51, 52, 53, 54, 55 formed on the insulating substrate 2; semiconductor switching sections 10, 20; and a bypass capacitor 80, wherein the semiconductor switch section 10 is disposed on the conductive pattern section 51, the semiconductor switch section 20 is disposed on the conductive pattern section 52, the semiconductor switch section 10 has a side S1 and a side S2, the semiconductor switch section 20 has a side S3 and a side S4, and a virtual line L1 extending along the side S1 intersects a virtual line L2 extending along the side S3.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device having a power supply circuit.
Background
Conventionally, a semiconductor device having a power supply circuit that converts a power supply voltage to a desired voltage and outputs the converted voltage has been widely known. The power circuit includes an inverter (inverter), a rectifier, a DC/DC (converter) converter, and the like. Such a semiconductor device is used, for example, in a Power Conditioner (Power Conditioner) or a Server device (Server device) of a photovoltaic Power generation system. In a power supply circuit of a semiconductor device, a Half-bridge (Half-bridge) circuit or a Full-bridge (Full-bridge) circuit is used. In these circuits, a High-side switch (High-side switch) on the High voltage side and a Low-side switch (Low-side switch) on the Low voltage side are cascaded.
Patent document 1 describes a Power module (Power module) having two switching elements connected in cascade. The high-side switch and the low-side switch in the power module are arranged in parallel.
Prior art documents
Patent document 1: japanese laid-open patent publication No. 2016 & 162773
In a power supply circuit, a Bypass capacitor (Bypass capacitor) is generally used to filter out variations in a power supply voltage and various noises (Noise). And the bypass capacitor is disposed between the high voltage side terminal and the low voltage side terminal (ground terminal). In addition, it has been conventionally mounted outside the semiconductor device. Since the bypass capacitor can exert an effect even more when it is disposed in the vicinity of the switching element, it is desired in the industry to dispose the bypass capacitor inside the semiconductor device (built-in type).
In the case of the built-in type, when the high-side switch and the low-side switch are N-type, the bypass capacitor is disposed between the source electrode of the high-side switch and the drain electrode of the low-side switch. When the high-side switch and the low-side switch are P-type, the bypass capacitor is disposed between the drain electrode of the high-side switch and the source electrode of the low-side switch.
However, in a conventional layout in which the high-side switch and the low-side switch are arranged in parallel, a path from the high-side switch to the low-side switch via the bypass capacitor (hereinafter, also simply referred to as "bypass capacitor path") is too long, and thus a Parasitic inductance (Parasitic inductance) in the bypass capacitor path increases. As a result, the power supply circuit may malfunction.
In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of preventing a failure of a power supply circuit even when a bypass capacitor and the power supply circuit are provided.
Disclosure of Invention
The semiconductor device according to the present invention includes:
an insulating substrate;
a first conductive Pattern (Pattern) part formed on the insulating substrate;
a second conductive pattern part formed on the insulating substrate;
a third conductive pattern portion formed on the insulating substrate;
a fourth conductive pattern part formed on the insulating substrate;
a fifth conductive pattern part formed on the insulating substrate;
a first semiconductor switch unit having a first main electrode and a second main electrode and disposed on the first conductive pattern unit;
a second semiconductor switch unit having a third main electrode and a fourth main electrode and disposed on the second conductive pattern unit; and
a bypass capacitor having a first electrode and a second electrode,
wherein the first main electrode of the first semiconductor switch portion is electrically connected to the third conductive pattern portion, the second main electrode of the first semiconductor switch portion is electrically connected to the fourth conductive pattern portion, the third main electrode of the second semiconductor switch portion is electrically connected to the fourth conductive pattern portion, the fourth main electrode of the second semiconductor switch portion is electrically connected to the fifth conductive pattern portion, the first electrode of the bypass capacitor is electrically connected to the third conductive pattern portion, and the second electrode is electrically connected to the fifth conductive pattern portion,
the first semiconductor switch section has a first side and a second side opposite to the first side, the second semiconductor switch section has a third side and a fourth side opposite to the third side,
the first main electrode is arranged along the first side, the second main electrode is arranged along the second side, the third main electrode is arranged along the third side, and the fourth main electrode is arranged along the fourth side,
a first imaginary line extending along the first edge intersects a second imaginary line extending along the third edge.
In the semiconductor device, the semiconductor device may further include:
wherein an angle at which the first imaginary line intersects with the second imaginary line is 30 ° or more and 135 ° or less.
In the semiconductor device, the semiconductor device may further include:
wherein an angle at which the first imaginary line intersects with the second imaginary line is 45 ° or more and 90 ° or less.
In the semiconductor device, the semiconductor device may further include:
wherein the first imaginary line intersects the second imaginary line at an angle of 45 °.
In the semiconductor device, the semiconductor device may further include:
wherein the first main electrode of the first semiconductor switch portion is electrically connected to a high-voltage-side terminal via the third conductive pattern portion, and the fourth main electrode of the second semiconductor switch portion is electrically connected to a low-voltage-side terminal via the fifth conductive pattern portion.
In the semiconductor device, the semiconductor device may further include:
wherein the insulating substrate has a first substrate edge from which the high-voltage-side terminal and the low-voltage-side terminal protrude in plan view, and a second substrate edge opposite to the first substrate edge,
the first semiconductor switch portion is disposed such that the first virtual line is parallel to the first substrate side, and the second semiconductor switch portion is disposed such that the second virtual line is inclined with respect to the first substrate side.
In the semiconductor device, the semiconductor device may further include:
wherein the bypass capacitance is configured to: a third imaginary line connecting the first electrode and the second electrode intersects the first imaginary line and the second imaginary line.
In the semiconductor device, the semiconductor device may further include:
wherein the third imaginary line intersects the second imaginary line at an angle of 90 °.
In the semiconductor device, the semiconductor device may further include:
wherein the first semiconductor switch section has:
a first GaN-HEMT (high Electron Mobility transistor) disposed on the first conductive pattern part; and
a first MOS-FET disposed on the first GaN-HEMT,
the second semiconductor switch section includes:
a second GaN-HEMT disposed on the second conductive pattern section; and
a second MOS-FET disposed on the second GaN-HEMT,
the gate electrode of the first GaN-HEMT is electrically connected to the second main electrode via the fourth conductive pattern part, and the gate electrode of the second GaN-HEMT is electrically connected to the fourth main electrode via the fifth conductive pattern part.
In the semiconductor device, the semiconductor device may further include:
wherein the first and second GaN-HEMTs are Normally-on type transistors and the first and second MOS-FETs are Normally-off type transistors.
In the semiconductor device, the semiconductor device may further include:
wherein the bypass capacitor is resin-encapsulated together with the first semiconductor switch portion and the second semiconductor switch portion.
In addition, the semiconductor device may further include:
a sixth conductive pattern portion formed on the insulating substrate;
a seventh conductive pattern part formed on the insulating substrate;
an eighth conductive pattern part formed on the insulating substrate;
a ninth conductive pattern part formed on the insulating substrate;
a third semiconductor switch unit having a fifth main electrode and a sixth main electrode and disposed on the sixth conductive pattern unit; and
a fourth semiconductor switch unit having a seventh main electrode and an eighth main electrode and disposed on the seventh conductive pattern unit,
the fifth main electrode of the third semiconductor switch section is electrically connected to the eighth conductive pattern section, the sixth main electrode of the third semiconductor switch section is electrically connected to the ninth conductive pattern section, the seventh main electrode of the fourth semiconductor switch section is electrically connected to the ninth conductive pattern section, and the eighth main electrode of the fourth semiconductor switch section is electrically connected to the fifth conductive pattern section,
the first semiconductor switch portion and the third semiconductor switch portion are symmetrically disposed so as to sandwich the fifth conductive pattern portion, and the second semiconductor switch portion and the fourth semiconductor switch portion are symmetrically disposed so as to sandwich the fifth conductive pattern portion.
In addition, the semiconductor device may further include:
a further bypass capacitor having a third electrode and a fourth electrode,
the third electrode is electrically connected to the eighth conductive pattern part, the fourth electrode is electrically connected to the fifth conductive pattern part,
the bypass capacitor and the another bypass capacitor are symmetrically arranged so as to sandwich the fifth conductive pattern portion.
Effects of the invention
In the semiconductor device according to the present invention, the first semiconductor switch portion and the second semiconductor switch portion are arranged such that a first virtual line of the first semiconductor switch portion intersects a second virtual line of the second semiconductor switch portion. In this way, the bypass capacitance path can be shortened as compared with a configuration in which the first semiconductor switch portion and the second semiconductor switch portion are arranged in parallel, and parasitic inductance on the bypass capacitance path can be suppressed.
Therefore, according to the present invention, it is possible to provide a semiconductor device capable of preventing a malfunction of a power supply circuit even when a bypass capacitor and the power supply circuit are provided.
Brief description of the drawings
Fig. 1 is a plan view of an internal configuration of a semiconductor device 1 according to an embodiment of the present invention.
Fig. 2 is an appearance display diagram of the semiconductor device 1 according to the embodiment of the present invention.
Fig. 3 is a circuit diagram of the semiconductor device 1 according to the embodiment of the present invention.
Fig. 4 is an enlarged plan view for explaining imaginary lines L1 and L2.
Fig. 5 is an enlarged plan view for explaining a virtual line L3.
[ detailed description of the invention ]
Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are used to designate the same components having the same functions.
As shown in the circuit diagram of fig. 3, the semiconductor device 1 according to the embodiment of the present invention includes two half-bridge circuits. That is, the semiconductor device 1 includes: a first half-bridge circuit including the semiconductor switch unit 10 and the semiconductor switch unit 20, and a second half-bridge circuit including the semiconductor switch unit 30 and the semiconductor switch unit 40. The semiconductor switch units 10 and 30 are high-side switches, and the semiconductor switch units 20 and 40 are low-side switches. The semiconductor switch unit 10 is cascaded with the semiconductor switch unit 20, and the semiconductor switch unit 30 is cascaded with the semiconductor switch unit 40. The semiconductor device 1 functions as, for example, a DC/DC converter, a rectifier, or an inverter.
As shown in fig. 1 and 2, the semiconductor device 1 includes: an insulating substrate 2; a semiconductor switch section 10 (first semiconductor switch section); a semiconductor switch section 20 (second semiconductor switch section); a semiconductor switch section 30 (third semiconductor switch section); a semiconductor switch section 40 (fourth semiconductor switch section); conductive pattern portions 51, 52, 53, 54, 55, 56, 57, 58, 59, 61, 62, 63, 64 formed on the insulating substrate 2; bypass capacitors 80, 90; and a resin sealing portion 95.
As shown in fig. 1, the semiconductor device 1 has a bilaterally symmetrical structure, and a first half-bridge circuit is formed on one side thereof and a second half-bridge circuit is formed on the other side thereof.
The semiconductor device 1 further includes terminals T1, T2, T3, T4, T5, T6, T7, T11, T12, T13, T14, T15, and T16 for connecting external devices (an IC chip such as a driver, a power supply). These terminals are arranged to protrude from the paper surface of fig. 1 and 2 toward the viewer. The Outer leads (Outer leads) of these terminals and portions other than the rear surface of the insulating substrate 2 are encapsulated by a resin encapsulation portion 95. As shown in fig. 2, through holes H1 and H2 for inserting bolts for mounting the semiconductor device 1 to a heat sink or the like are disposed in the resin package portion 95.
The semiconductor switch section 10 has a main electrode 11 (first main electrode); main electrode 12 (second main electrode); and a control electrode 13. The semiconductor switch section 20 has a main electrode 21 (third main electrode); a main electrode 22 (fourth main electrode); and a control electrode 23. The semiconductor switch section 30 has a main electrode 31 (fifth main electrode); a main electrode 32 (sixth main electrode); and a control electrode 33. The semiconductor switch section 40 has a main electrode 41 (seventh main electrode); a main electrode 42 (eighth main electrode); and a control electrode 43.
The insulating substrate 2 is made of an insulating material, and is preferably made of a material having good heat dissipation properties, such as ceramic. As shown in fig. 1, the insulating substrate 2 has a substrate edge 2a (first substrate edge) and a substrate edge 2b (second substrate edge) opposite to the substrate edge 2 a. The substrate edges 2a, 2b are edges from which the terminals protrude when viewed in plan. That is, the terminals T1, T4, T7, T11, and T14 protrude from the substrate side 2a in plan view, and the terminals T2, T3, T5, T6, T12, T13, T15, and T16 protrude from the substrate side 2b in plan view. A conductive pattern (not shown) connected to a radiator such as a heat sink is formed on the rear surface of the insulating substrate 2.
The bypass capacitors 80 and 90 are provided to avoid variations in the power supply voltage in the semiconductor device 1 and to filter out various noises. The bypass capacitor 80 has an electrode 81 and an electrode 82. Bypass capacitor 90 has an electrode 91 and an electrode 92. The bypass capacitor 80 is provided between the terminal T1 and the terminal T7. The bypass capacitor 90 is disposed between the terminal T11 and the terminal T7. The bypass capacitors 80 and 90 are resin-sealed together with other electronic components on the insulating substrate 2 such as the semiconductor switch units 10, 20, 30, and 40 by a resin sealing unit 95. In addition, the electrostatic capacity of the bypass capacitors 80 and 90 may be set to, for example: the withstand voltage of the bypass circuit is as large as possible within a range larger than the withstand voltage of GaN HEMTs 15, 25, 35, and 45 described later.
As shown in fig. 3, the semiconductor device 1 has a path (bypass capacitance path P1) from the Node (Node) N1 to the Node N2 via the bypass capacitance 80. Specifically, the bypass capacitance path P1 is a path from the main electrode 11 of the semiconductor switch unit 10 to the main electrode 22 of the semiconductor switch unit 20 via the conductive pattern unit 53, the bypass capacitance 80, and the conductive pattern unit 55.
Similarly, the conductor device 1 also has a path (bypass capacitance path P2) from the node N3 to the node N4 via the bypass capacitance 90. Specifically, the bypass capacitance path P2 is a path from the main electrode 31 of the semiconductor switch section 30 to the main electrode 42 of the semiconductor switch section 40 via the conductive pattern section 58, the bypass capacitance 90, and the conductive pattern section 55.
Next, each terminal of the semiconductor device 1 will be explained.
The terminals T1 and T11 are terminals (high-voltage-side terminals) connected to a high-voltage side of a power supply (not shown). And the terminal T7 is a terminal (low-voltage-side terminal) connected to the low-voltage side (ground side) of the power supply. When the power supply circuit of the semiconductor device 1 functions as a rectifier, the terminals T1 and T11 are connected to a load on the output side.
The terminals T2 and T12 are terminals to which control signals are input to the high-side switches ( semiconductor switch units 10 and 30 in the present embodiment) of the half-bridge circuit. The terminals T5 and T15 are terminals to which control signals are input to the low-side switches ( semiconductor switch units 20 and 40 in the present embodiment) of the half-bridge circuit. These terminals T2, T5, T12, and T15 are electrically connected to a driver (not shown) of the drive power supply circuit.
The terminal T3 is a terminal for monitoring (Monitor) the voltage between the semiconductor switch unit 10 and the semiconductor switch unit 20. Similarly, the terminal T13 is a terminal for monitoring the voltage between the semiconductor switch unit 30 and the semiconductor switch unit 40.
The terminal T4 is a terminal for outputting the output voltage of the first half bridge circuit including the semiconductor switch units 10 and 20. Similarly, the terminal T14 is a terminal for outputting the output voltage of the second half-bridge circuit including the semiconductor switch units 30 and 40. When the power supply circuit of the semiconductor device 1 functions as a rectifier, an input-side ac power supply is connected between the terminal T4 and the terminal T14.
The terminal T6 is a terminal for monitoring the voltage between the semiconductor switch unit 20 and the terminal T7. Similarly, the terminal T16 is a terminal for monitoring the voltage between the semiconductor switch unit 40 and the terminal T7.
Next, each conductive pattern portion of the semiconductor device 1 will be described in detail with reference to fig. 1.
The conductive pattern portions 51 to 59, 61 to 64 are patterned with copper foil on the insulating substrate 2, for example. The conductive pattern portions 51, 52, 53, 54, 55, 61, 62 are conductive pattern portions for constituting a first half bridge circuit having the semiconductor switch portions 10, 20. The conductive pattern portions 55, 56, 57, 58, 59, 63, 64 are conductive pattern portions for constituting the second half-bridge circuit having the semiconductor switch portions 30, 40. The conductive pattern section 55 is shared by the first half-bridge circuit and the second half-bridge circuit.
The conductive pattern section 51 (first conductive pattern section) is a conductive pattern section for mounting the semiconductor switch section 10. Similarly, the conductive pattern section 52 (second conductive pattern section) is a conductive pattern section for mounting the semiconductor switch section 20. The conductive pattern section 56 (sixth conductive pattern section) is a conductive pattern section for mounting the semiconductor switch section 30. The conductive pattern section 57 (seventh conductive pattern section) is a conductive pattern section for mounting the semiconductor switch section 40.
In the present embodiment, the conductive pattern portions 51, 52, 56, and 57 are formed in substantially a quadrangle in plan view in accordance with the shape of the semiconductor switch portions 10, 20, 30, and 40. As shown in fig. 1, the semiconductor switch unit 10 is disposed on the conductive pattern unit 51, the semiconductor switch unit 20 is disposed on the conductive pattern unit 52, the semiconductor switch unit 30 is disposed on the conductive pattern unit 56, and the semiconductor switch unit 40 is disposed on the conductive pattern unit 57.
The conductive pattern portion 53 (third conductive pattern portion) is electrically connected to the main electrode 11 of the semiconductor switch portion 10 via a Wire (Wire)3, and is connected to the terminal T1 and the electrode 81 of the bypass capacitor 80 via solder. Similarly, the conductive pattern portion 58 (eighth conductive pattern portion) is electrically connected to the main electrode 31 of the semiconductor switch portion 30 via the metal wire 3, and is connected to the terminal T11 and the electrode 91 of the bypass capacitor 90 via solder. The metal wire 3 is an aluminum wire (Al wire) in the present embodiment, but may be made of another metal material.
The conductive pattern section 54 (fourth conductive pattern section) electrically connects the semiconductor switch section 10 and the semiconductor switch section 20. That is, the conductive pattern portion 54 is electrically connected to the main electrode 12 of the semiconductor switch portion 10 and the main electrode 21 of the semiconductor switch portion 20 via the metal wire 3. Further, the conductive pattern portion 54 is electrically connected to the terminals T3 and T4 via solder.
Similarly, the conductive pattern section 59 (ninth conductive pattern section) electrically connects the semiconductor switch section 30 and the semiconductor switch section 40. That is, the conductive pattern section 59 is electrically connected to the main electrode 32 of the semiconductor switch section 30 and the main electrode 41 of the semiconductor switch section 40 via the metal wire 3. Further, the conductive pattern section 59 is electrically connected to the terminals T13 and T14 via solder.
The conductive pattern section 55 (fifth conductive pattern section) is shared by two half-bridge circuits included in the semiconductor device 1. As shown in fig. 1, the conductive pattern part 55 is formed in a left-right symmetrical shape. The conductive pattern portion 55 is electrically connected to the electrode 82 of the bypass capacitor 80 via solder, and is also electrically connected to the main electrode 22 of the semiconductor switch portion 20 via the metal wire 3. The conductive pattern portion 55 is also electrically connected to the electrode 92 of the bypass capacitor 90 via solder, and is also electrically connected to the main electrode 42 of the semiconductor switch portion 40 via the metal wire 3.
As shown in fig. 1, the conductive pattern section 55 is also electrically connected to the gate electrode 24 of the GaN-HEMT25 and the gate electrode 44 of the GaN-HEMT45 via the metal wire 3. The conductive pattern portion 55 is also electrically connected to the terminals T6, T7, and T16 via solder.
The conductive pattern section 61 is a conductive pattern for electrically connecting the control electrode 13 of the semiconductor switching section 10 and the terminal T2. The conductive pattern portion 61 is electrically connected to the control electrode 13 via the metal wire 3 and is also electrically connected to the terminal T2 via solder. Similarly, the conductive pattern section 63 is a conductive pattern for electrically connecting the control electrode 33 of the semiconductor switch section 30 to the terminal T12. The conductive pattern portion 63 is electrically connected to the control electrode 33 via the metal wire 3, and is also electrically connected to the terminal T12 via solder.
The conductive pattern section 62 is a conductive pattern for electrically connecting the control electrode 23 of the semiconductor switch section 20 and the terminal T5. The conductive pattern portion 62 is electrically connected to the control electrode 23 via the metal wire 3 and is also electrically connected to the terminal T5 via solder. Similarly, the conductive pattern section 64 is a conductive pattern for electrically connecting the control electrode 43 of the semiconductor switch section 40 and the terminal T15. The conductive pattern portion 64 is electrically connected to the control electrode 43 via the metal wire 3 and is also electrically connected to the terminal T15 via solder.
In addition, in order to electrically connect the semiconductor switch portion and the conductive pattern, a connector made of a conductive material may be used instead of the metal wire.
Next, the detailed configuration of each semiconductor switch unit of the semiconductor device 1 will be described.
The semiconductor switching sections 10, 20, 30, 40 each have a GaN-HEMT and a MOS-FET, respectively. The method specifically comprises the following steps: the semiconductor switching section 10 has a GaN-HEMT15 disposed on the conductive pattern section 51; and a MOS-FET16 configured on the GaN-HEMT 15. Similarly, the semiconductor switching section 20 has a GaN-HEMT25 disposed on the conductive pattern section 52; and a MOS-FET26 configured on the GaN-HEMT 25. The semiconductor switch section 30 has a GaN-HEMT35 disposed on the conductive pattern section 56; and a MOS-FET36 configured on the GaN-HEMT 35. The semiconductor switch section 40 has a GaN-HEMT45 disposed on the conductive pattern section 57; and a MOS-FET46 configured on the GaN-HEMT 45.
The GaN- HEMTs 15, 25, 35, and 45 are High Electron Mobility Transistors (HEMTs) using gallium nitride (GaN) as a semiconductor material. Any one of the GaN- HEMTs 15, 25, 35, 45 is: a transistor in which a Channel (Channel) exists and current flows even when the gate voltage is 0V (i.e., a normally-on type). Any of the GaN HEMTs 15, 25, 35, and 45 is N-type. The GaN HEMTs 15, 25, 35, and 45 have a lateral structure, and have a source electrode, a drain electrode, and a gate electrode on the upper end surface.
The MOS- FETs 16, 26, 36, 46 are Field Effect transistors (Field Effect transistors) having a MOS (metallic Oxide semiconductor) structure. Any of MOS- FETs 16, 26, 36, 46 are normally-off transistors. Any of MOS- FETs 16, 26, 36, 46 is N-type. MOS- FETs 16, 26, 36, and 46 have a vertical structure, and have an active electrode and a gate electrode on an upper end surface, and a drain electrode on a lower end surface.
The source electrode disposed on the upper end surface of the GaN-HEMT15 is electrically connected to the drain electrode disposed on the lower end surface of the MOS-FET16 via solder. Similarly, the source electrode of the GaN-HEMT25 is electrically connected to the drain electrode of the MOS-FET26 via solder. The source electrode of the GaN-HEMT35 is electrically connected to the drain electrode of the MOS-FET36 via solder. The source electrode of the GaN-HEMT45 is electrically connected to the drain electrode of the MOS-FET46 via solder.
As shown in fig. 1, the gate electrode 14 of the GaN-HEMT15 is electrically connected to the main electrode 12 via the conductive pattern portion 54. The gate electrode 24 of the GaN-HEMT25 is electrically connected to the main electrode 22 via the conductive pattern part 55. The gate electrode 34 of the GaN-HEMT35 is electrically connected to the main electrode 22 via the conductive pattern section 59. The gate electrode 44 of the GaN-HEMT45 is electrically connected to the main electrode 42 via the conductive pattern part 55.
In this embodiment, main electrode 11 of semiconductor switch unit 10 is the drain electrode of GaN-HEMT15, main electrode 12 is the source electrode of MOS-FET16, and control electrode 13 is the gate electrode of MOS-FET 16. Main electrode 11 is electrically connected to conductive pattern portion 53, and main electrode 12 is electrically connected to conductive pattern portion 54. The main electrode 11 is also electrically connected to a high-voltage-side terminal (terminal T1) via the conductive pattern portion 53. The control electrode 13 is electrically connected to the conductive pattern section 61.
Main electrode 21 of semiconductor switch 20 is the drain electrode of GaN-HEMT25, main electrode 22 is the source electrode of MOS-FET26, and control electrode 23 is the gate electrode of MOS-FET 26. The main electrode 21 is electrically connected to the conductive pattern portion 54, and the main electrode 22 is electrically connected to the conductive pattern portion 55. The main electrode 11 is also electrically connected to the low-voltage-side terminal (terminal T7) via the conductive pattern portion 55. The control electrode 23 is electrically connected to the conductive pattern portion 62.
The main electrode 31 of the semiconductor switch section 30 is the drain electrode of the GaN-HEMT35, the main electrode 32 is the source electrode of the MOS-FET36, and the control electrode 33 is the gate electrode of the MOS-FET 36. The main electrode 31 is electrically connected to the conductive pattern portion 58, and the main electrode 32 is electrically connected to the conductive pattern portion 59. The main electrode 31 is also electrically connected to a high-voltage-side terminal (terminal T11) via the conductive pattern portion 58. The control electrode 33 is electrically connected to the conductive pattern section 63.
The main electrode 41 of the semiconductor switch unit 40 is the drain electrode of the GaN-HEMT45, the main electrode 42 is the source electrode of the MOS-FET46, and the control electrode 43 is the gate electrode of the MOS-FET 46. The main electrode 41 is electrically connected to the conductive pattern portion 59, and the main electrode 42 is electrically connected to the conductive pattern portion 55. The main electrode 42 is also electrically connected to the low-voltage-side terminal (terminal T7) via the conductive pattern portion 55. The control electrode 43 is electrically connected to the conductive pattern portion 64.
The semiconductor switch units 10, 20, 30, and 40 are not limited to the above configuration. For example, the semiconductor switch units 10, 20, 30, and 40 may be formed of one semiconductor switch element (normally-off GaN-HEMT or MOS-FET).
In addition, the GaN- HEMTs 15, 25, 35, 45 may be vertical structures. In this case, taking the semiconductor switch unit 10 as an example, the drain electrode disposed on the back surface of the GaN-HEMT15 is connected to the conductive pattern unit 51 via solder, and the conductive pattern unit 51 is connected to the conductive pattern unit 53, thereby constituting an integrated conductive pattern unit. The same applies to the case of the GaN-HEMT25, the drain electrode disposed on the back surface of the GaN-HEMT25 is connected to the conductive pattern section 52 via solder, and the conductive pattern section 52 is connected to the conductive pattern section 55. In addition, the same connection method as described above is also used when the semiconductor switch portion is configured by only the MOS-FET having the vertical structure.
As shown in fig. 1, the bypass capacitor 80 is disposed between the drain electrode of the GaN-HEMT15 and the source electrode of the MOS-FET 26. The bypass capacitor 90 is disposed between the drain electrode of the GaN-HEMT35 and the source electrode of the MOS-FET 46.
Next, the arrangement relationship between the high-side switch and the low-side switch in the present embodiment will be described. Here, the semiconductor switch section 10 and the semiconductor switch section 20 will be explained with reference to fig. 4.
As shown in fig. 4, the semiconductor switch units 10 and 20 are substantially rectangular in plan view. The semiconductor switch section 10 has a side S1 (first side) and a side S2 (second side) opposite to the side S1. In the present embodiment, side S1 is substantially parallel to side S2. Similarly, the semiconductor switch section 20 has a side S3 (third side) and a side S4 (fourth side) opposite to the side S3. In the present embodiment, side S3 is substantially parallel to side S4.
Main electrode 11 of semiconductor switch section 10 is disposed along side S1, and main electrode 12 is disposed along side S2. The main electrode 21 of the semiconductor switch section 20 is disposed along the side S3, and the main electrode 22 is disposed along the side S4.
In the semiconductor device 1, as shown in fig. 4, an imaginary line L1 extending along the side S1 (or the side S2) intersects an imaginary line L2 extending along the side S3 (or the side S4). In other words, the imaginary line L1 is non-parallel to the imaginary line L2. By doing so, the bypass capacitance path P1 can be shortened as compared with the case where the semiconductor switch section 10 and the semiconductor switch section 20 are arranged in parallel (i.e., the case where the virtual line L1 is parallel to the virtual line L2). Thus, the parasitic inductance in the bypass capacitance path P1 can be suppressed. Therefore, according to the present embodiment, malfunction of the power supply circuit can be prevented.
In addition, the larger the angle θ 1 at which the imaginary line L1 intersects the imaginary line L2, the shorter the length of the bypass capacitance path P1, and the more the parasitic inductance is suppressed. On the other hand, however, since the path between the semiconductor switch section 10 (specifically, the source electrode of the MOS-FET 16) and the semiconductor switch section 20 (specifically, the drain electrode of the GaN-HEMT 25) becomes longer, the parasitic inductance also becomes large, which causes a malfunction of the power supply circuit. In view of this, it is necessary not to set the angle θ 1 excessively large. Specifically, the angle θ 1 is preferably in a range of 30 ° or more and 135 ° or less, and more preferably in a range of 45 ° or more and 90 ° or less. In the present embodiment, the angle θ 1 is substantially 45 °.
As described above, in the semiconductor device 1 according to the present embodiment, the semiconductor switch section 10 and the semiconductor switch section 20 are arranged such that the virtual line L1 of the semiconductor switch section 10 intersects the virtual line L2 of the semiconductor switch section 20. Thus, the bypass capacitance path can be shortened to suppress parasitic inductance. Therefore, according to the present embodiment, it is possible to prevent the power supply circuit having the semiconductor switching units 10 and 20 from malfunctioning.
In addition, as shown in fig. 5, the bypass capacitor 80 is configured to: an imaginary line L3 connecting the electrode 81 and the electrode 82 intersects the imaginary lines L1 and L2. That is, the imaginary line L3 is not parallel to any of the imaginary line L1 and the imaginary line L2, and the bypass capacitor 80 is disposed along the bypass capacitor path P1. By so doing, the bypass capacitance path P1 becomes shorter. This further reduces the parasitic inductance in the bypass capacitance path P1. In the present embodiment, the angle θ 2 at which the imaginary line L3 intersects the imaginary line L1 is substantially 90 °.
As shown in fig. 1, the semiconductor switch section 10 as the high-side switch is arranged so that the virtual line L1 is substantially parallel to the substrate edge 2a, and the semiconductor switch section 20 as the low-side switch is arranged so that the virtual line L2 is inclined with respect to the substrate edge 2 a. The result of such a configuration is: it is easy to secure a space at the upper central region of the insulating substrate 2. Thus, for example, in the conductive pattern portion 55, the width of the region extending in the oblique direction in which the metal wire 3 connected to the main electrode 22 is connected to the conductive pattern portion 55 can be widened, and the parasitic inductance in the bypass capacitance path P1 can be further reduced.
As described above, the semiconductor device 1 has a bilaterally symmetrical structure. That is, as shown in fig. 1, the semiconductor switch unit 10 and the semiconductor switch unit 30 are symmetrically arranged with the conductive pattern unit 55 interposed therebetween, and the semiconductor switch unit 20 and the semiconductor switch unit 40 are symmetrically arranged with the conductive pattern unit 55 interposed therebetween. The bypass capacitor 80 and the bypass capacitor 90 are also symmetrically arranged with the conductive pattern part 55 interposed therebetween. The conductive pattern section 55 is shared by the two half-bridge circuits. By providing the semiconductor device 1 with a bilaterally symmetrical configuration, the width of the conductive pattern section 55 can be increased, and the parasitic inductance in the bypass capacitance paths P1 and P2 can be further reduced.
The semiconductor device according to this embodiment has been described above. The semiconductor device according to the present invention is not limited to the half-bridge circuit described above, and can be applied to a power supply circuit having another configuration such as a full-bridge circuit or a Push-pull circuit (Push-pull circuit) as long as the semiconductor device has semiconductor switching elements connected in series.
Finally, based on the above description, those skilled in the art may conceive of additional effects and various modifications of the present invention, but the form of the present invention is not limited to the above embodiments. The constituent elements of the various embodiments may be appropriately combined. And various additions, modifications, and partial deletions can be made within the scope defined in the claims and the scope of the conceptual ideas and gist of the invention indicated by their equivalents.
Description of the symbols
1 semiconductor device
2 insulating substrate
2a, 2b substrate side
3 Metal wire
10. 20, 30, 40 semiconductor switch part
11. 12, 21, 22, 31, 32, 41, 42 main electrode
13. 23, 33, 43 control electrode
15、25、35、45 GaN-HEMT
16、26、36、46 MOS-FET
51. 52, 53, 54, 55, 56, 57, 58, 59, 61, 62, 63, 64 conductive pattern part
80. 90 bypass capacitor
81. 82, 91, 92 electrode
95 resin sealing part
H1, H2 through hole
Imaginary lines of L1, L2, L3
N1, N2, N3 and N4 nodes
P1, P2 bypass capacitive path
Edges S1, S2, S3 and S4
T1, T2, T3, T4, T5, T6, T7, T11, T12, T13, T14, T15 and T16 terminals

Claims (13)

1. A semiconductor device, comprising:
an insulating substrate;
a first conductive pattern portion formed on the insulating substrate;
a second conductive pattern part formed on the insulating substrate;
a third conductive pattern portion formed on the insulating substrate;
a fourth conductive pattern part formed on the insulating substrate;
a fifth conductive pattern part formed on the insulating substrate;
a first semiconductor switch unit having a first main electrode and a second main electrode and disposed on the first conductive pattern unit;
a second semiconductor switch unit having a third main electrode and a fourth main electrode and disposed on the second conductive pattern unit; and
a bypass capacitor having a first electrode and a second electrode,
wherein the first main electrode of the first semiconductor switch portion is electrically connected to the third conductive pattern portion, the second main electrode of the first semiconductor switch portion is electrically connected to the fourth conductive pattern portion, the third main electrode of the second semiconductor switch portion is electrically connected to the fourth conductive pattern portion, the fourth main electrode of the second semiconductor switch portion is electrically connected to the fifth conductive pattern portion, the first electrode of the bypass capacitor is electrically connected to the third conductive pattern portion, and the second electrode is electrically connected to the fifth conductive pattern portion,
the first semiconductor switch section has a first side and a second side opposite to the first side, the second semiconductor switch section has a third side and a fourth side opposite to the third side,
the first main electrode is arranged along the first side, the second main electrode is arranged along the second side, the third main electrode is arranged along the third side, and the fourth main electrode is arranged along the fourth side,
a first imaginary line extending along the first edge intersects a second imaginary line extending along the third edge.
2. The semiconductor device according to claim 1, wherein:
wherein an angle at which the first imaginary line intersects with the second imaginary line is 30 ° or more and 135 ° or less.
3. The semiconductor device according to claim 1, wherein:
wherein an angle at which the first imaginary line intersects with the second imaginary line is 45 ° or more and 90 ° or less.
4. The semiconductor device according to claim 1, wherein:
wherein the first imaginary line intersects the second imaginary line at an angle of 45 °.
5. The semiconductor device according to claim 1, wherein:
wherein the first main electrode of the first semiconductor switch portion is electrically connected to a high-voltage-side terminal via the third conductive pattern portion, and the fourth main electrode of the second semiconductor switch portion is electrically connected to a low-voltage-side terminal via the fifth conductive pattern portion.
6. The semiconductor device according to claim 5, wherein:
wherein the insulating substrate has a first substrate edge from which the high-voltage-side terminal and the low-voltage-side terminal protrude in plan view, and a second substrate edge opposite to the first substrate edge,
the first semiconductor switch portion is disposed such that the first virtual line is parallel to the first substrate side, and the second semiconductor switch portion is disposed such that the second virtual line is inclined with respect to the first substrate side.
7. The semiconductor device according to claim 6, wherein:
wherein the bypass capacitance is configured to: a third imaginary line connecting the first electrode and the second electrode intersects the first imaginary line and the second imaginary line.
8. The semiconductor device according to claim 7, wherein:
wherein the third imaginary line intersects the second imaginary line at an angle of 90 °.
9. The semiconductor device according to claim 1, wherein:
wherein the first semiconductor switch section has:
a first GaN-HEMT disposed on the first conductive pattern part; and
a first MOS-FET disposed on the first GaN-HEMT,
the second semiconductor switch section includes:
a second GaN-HEMT disposed on the second conductive pattern section; and
a second MOS-FET disposed on the second GaN-HEMT,
the gate electrode of the first GaN-HEMT is electrically connected to the second main electrode via the fourth conductive pattern part, and the gate electrode of the second GaN-HEMT is electrically connected to the fourth main electrode via the fifth conductive pattern part.
10. The semiconductor device according to claim 9, wherein:
the first GaN-HEMT and the second GaN-HEMT are normally-on transistors, and the first MOS-FET and the second MOS-FET are normally-off transistors.
11. The semiconductor device according to claim 1, wherein:
wherein the bypass capacitor is resin-encapsulated together with the first semiconductor switch portion and the second semiconductor switch portion.
12. The semiconductor device according to claim 1, wherein:
wherein, further include:
a sixth conductive pattern portion formed on the insulating substrate;
a seventh conductive pattern part formed on the insulating substrate;
an eighth conductive pattern part formed on the insulating substrate;
a ninth conductive pattern part formed on the insulating substrate;
a third semiconductor switch unit having a fifth main electrode and a sixth main electrode and disposed on the sixth conductive pattern unit; and
a fourth semiconductor switch unit having a seventh main electrode and an eighth main electrode and disposed on the seventh conductive pattern unit,
the fifth main electrode of the third semiconductor switch section is electrically connected to the eighth conductive pattern section, the sixth main electrode of the third semiconductor switch section is electrically connected to the ninth conductive pattern section, the seventh main electrode of the fourth semiconductor switch section is electrically connected to the ninth conductive pattern section, and the eighth main electrode of the fourth semiconductor switch section is electrically connected to the fifth conductive pattern section,
the first semiconductor switch portion and the third semiconductor switch portion are symmetrically disposed so as to sandwich the fifth conductive pattern portion, and the second semiconductor switch portion and the fourth semiconductor switch portion are symmetrically disposed so as to sandwich the fifth conductive pattern portion.
13. The semiconductor device according to claim 12, wherein:
wherein, further include:
a further bypass capacitor having a third electrode and a fourth electrode,
the third electrode is electrically connected to the eighth conductive pattern part, the fourth electrode is electrically connected to the fifth conductive pattern part,
the bypass capacitor and the another bypass capacitor are symmetrically arranged so as to sandwich the fifth conductive pattern portion.
CN201780002329.3A 2017-06-19 2017-06-19 Semiconductor device with a plurality of semiconductor chips Active CN109429530B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/022564 WO2018235135A1 (en) 2017-06-19 2017-06-19 Semiconductor device

Publications (2)

Publication Number Publication Date
CN109429530A CN109429530A (en) 2019-03-05
CN109429530B true CN109429530B (en) 2022-03-15

Family

ID=62779942

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780002329.3A Active CN109429530B (en) 2017-06-19 2017-06-19 Semiconductor device with a plurality of semiconductor chips

Country Status (6)

Country Link
US (1) US10243477B2 (en)
EP (1) EP3644360A1 (en)
JP (1) JP6352555B1 (en)
KR (1) KR101950131B1 (en)
CN (1) CN109429530B (en)
WO (1) WO2018235135A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD920937S1 (en) * 2019-03-29 2021-06-01 Shindengen Electric Manufacturing Co., Ltd. Power module device containing semiconductor elements
JP7239380B2 (en) * 2019-04-16 2023-03-14 株式会社日立製作所 power converter
US20230056722A1 (en) * 2019-12-28 2023-02-23 Danfoss Silicon Power Gmbh Power module with improved electrical and thermal characteristics
DE102020205420A1 (en) * 2020-04-29 2021-11-04 Zf Friedrichshafen Ag Half-bridge module for an inverter of an electric drive of an electric vehicle or a hybrid vehicle and inverter for an electric drive of an electric vehicle or a hybrid vehicle
DE102021203144A1 (en) * 2021-03-29 2022-09-29 Zf Friedrichshafen Ag Power module for an electric drive of an electric vehicle or a hybrid vehicle, inverter with such a power module

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150871A (en) 1985-12-25 1987-07-04 Hitachi Ltd Semiconductor device
JP4292652B2 (en) * 1999-09-30 2009-07-08 三菱電機株式会社 Power semiconductor module
JP4009056B2 (en) 2000-05-25 2007-11-14 三菱電機株式会社 Power module
US7801793B2 (en) 2001-03-29 2010-09-21 International Business Machines Corporation User-specified time-based proxy firing in online auctions
JP4575616B2 (en) * 2001-04-26 2010-11-04 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7327024B2 (en) * 2004-11-24 2008-02-05 General Electric Company Power module, and phase leg assembly
JP2006223016A (en) * 2005-02-08 2006-08-24 Renesas Technology Corp Power supply system, multi-chip module, system-in-package, and non-isolated dc-dc converter
JP5333814B2 (en) 2007-09-12 2013-11-06 アイシン精機株式会社 Power semiconductor module, inverter device, and inverter-integrated motor
JP5353815B2 (en) * 2010-05-19 2013-11-27 三菱電機株式会社 Semiconductor module
JP6070955B2 (en) 2011-09-30 2017-02-01 ローム株式会社 Semiconductor device
DE102012217905B3 (en) * 2012-10-01 2013-11-07 Semikron Elektronik Gmbh & Co. Kg 3-level power converter half-bridge
US20140231928A1 (en) 2013-02-18 2014-08-21 Infineon Technologies Austria Ag Super Junction Semiconductor Device with an Edge Area Having a Reverse Blocking Capability
CN105191131A (en) * 2013-03-25 2015-12-23 株式会社安川电机 Power conversion apparatus
WO2015040727A1 (en) * 2013-09-20 2015-03-26 株式会社日立製作所 Semiconductor integrated circuit device
US9640471B2 (en) * 2015-02-24 2017-05-02 Navitas Semiconductor Inc. Leadless electronic packages for GaN devices
JP6594000B2 (en) 2015-02-26 2019-10-23 ローム株式会社 Semiconductor device
JP6361531B2 (en) * 2015-03-09 2018-07-25 株式会社デンソー Semiconductor device and motor control device
WO2017002390A1 (en) * 2015-06-30 2017-01-05 シャープ株式会社 Circuit module
CN107851637B (en) * 2015-07-09 2020-06-05 三菱电机株式会社 Power semiconductor module
DE102015120157A1 (en) * 2015-11-20 2017-05-24 Semikron Elektronik Gmbh & Co. Kg Power electronic switching device with a plurality of potential surfaces
CN105932016A (en) * 2016-06-12 2016-09-07 重庆大学 Dynamic and static current-sharing and multi-chip paralleled power module
US10418364B2 (en) * 2016-08-31 2019-09-17 Globalfoundries Inc. Semiconductor device structure with self-aligned capacitor device

Also Published As

Publication number Publication date
JP6352555B1 (en) 2018-07-04
CN109429530A (en) 2019-03-05
US20180367054A1 (en) 2018-12-20
US10243477B2 (en) 2019-03-26
KR101950131B1 (en) 2019-02-19
WO2018235135A1 (en) 2018-12-27
EP3644360A4 (en) 2020-04-29
EP3644360A1 (en) 2020-04-29
JPWO2018235135A1 (en) 2019-06-27

Similar Documents

Publication Publication Date Title
CN109429530B (en) Semiconductor device with a plurality of semiconductor chips
JP6909881B2 (en) Switching circuit with ferrite beads
US8796816B2 (en) Semiconductor module with electrical switching elements
TWI467712B (en) Semiconductor devices and power supply systems
WO2014185050A1 (en) Semiconductor device
US9653386B2 (en) Compact multi-die power semiconductor package
CN108511396B (en) Electronic device
JP7312604B2 (en) semiconductor equipment
EP3832862B1 (en) Power conversion device
US9780018B2 (en) Power semiconductor package having reduced form factor and increased current carrying capability
CN110226226B (en) Integrated circuit formed by two stacked chips connected in series
US9978671B2 (en) Power semiconductor device
CN109429529B (en) Semiconductor device with a plurality of semiconductor chips
US11601065B1 (en) Power converter module
US10892748B1 (en) Power module
US11749578B2 (en) Semiconductor module, power semiconductor module, and power electronic equipment using the semiconductor module or the power semiconductor module
US9704787B2 (en) Compact single-die power semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant