CN109429426A - 整合电子元件的多层线路织物材料及制造方法 - Google Patents
整合电子元件的多层线路织物材料及制造方法 Download PDFInfo
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Abstract
本发明提供一种整合电子元件的多层线路织物及制造方法,整合电子元件的多层线路织物包括:一基础层;多层的导电线路层,形成于该基础层上;至少一连接层,具有导电材料所构成的多个通孔及绝缘材料所构成的多个绝缘区域且该连接层位于上下相邻的2层导电线路层之间,经由该多个通孔电连接该上下相邻的2层导电线路层,其中该多个绝缘区域分布于连接层的除通孔以外的区域;一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上;以及一防水层,设置于该多层的导电线路层中距离基础层最远的层上。
Description
技术领域
本发明关于一种多层线路织物材料,特别是关于一种整合电子元件的多层线路织物材料及制造方法。
背景技术
结合电子产品与织物的智能穿着或配戴(smart wear),成为快速崛起的纺织制品,已逐渐受到纺织业者瞩目及研究开发。结合各种电子元件于织物的纺织制品,例如结合发光二极管的警示衣、结合运动传感器的鞋垫(insole)、结合加热线路的发热衣、结合心率感测器的运动衣等。
美国专利第8003198号揭露一种导电织物,具备纤维所构成的基础层、形成于该基础层上的导电线路层以及保护该导电线路层的绝缘层,但是该专利的构成主要在于绝缘层,以维持导电线路层在洗涤前后的电阻没有太大的变化,而且其导电线路层的宽度在10mm~20mm的范围,关于电子元件结合细微线路在具有弹性及/或可挠性的织物上短路与外观不良的问题,没有具体的解决手段。
再者,中国台湾地区专利公开第I337937号揭露一种弹性导电布的制造方法,其将发泡树脂黏着于布料表面,再形成一薄膜于发泡树脂后,对该薄膜进行电镀而使布料金属化,但是没有揭露具有图形化的导电层,也没有揭露具有电子元件的导电布。
再者,中国台湾地区专利公开第I362324号揭露一种导电布制造方法及其成品,主要利用一固定装置对于第一、第二软性基底间的导电纱,以点状间隔固定点结合三者,达到快速制造导电布的方法及成品,但是没有揭露具有电子元件的导电布。
再者,中国台湾地区专利公开第201723250号揭露一种电性连接电子元件的织物结构,使用异方性导电胶黏合可挠性电路板于薄膜(在织物结构中作为布料)上,藉由异方性导电胶电连接布料上的第一线路层与可挠性电路板的第二线路层,但是没有揭露在布料上制作多层导电线路,也没有揭露直接配置晶片或晶粒于布料上的构成,也没有提及如何解决弹性、可挠性的多种材料的匹配问题的手段。
发明内容
鉴于上述的发明背景,为了符合产业上的要求,本发明的目的之一在于提供一种整合电子元件的多层线路织物,达成在软质(多方向或任意方向的可挠性或可弯折性)薄膜或织物的布料上结合多样、多个的电子元件,提供各种功能,例如作为开关键、键盘、触控面板等。例如,传统使用可挠性电路板(FPC)的键盘,仅能沿着一个方向卷取成卷状,仍然具有相当的厚度及只具有单方向的卷取功能。再者,藉由本发明的整合电子元件的多层线路织物,可提供传统FPC无法提供的可挠性、弯折性及拉伸弹性的具备电子元件的织物。此外,使用表面涂有热塑性树脂层的立体织物作为基础层的本发明的整合电子元件的多层线路织物,可应用于医疗用途,例如骨折处的固定装置、脊椎的支持装置且提供治疗用或辅助骨细胞生长用的电脉冲波、磁脉冲波或超音波等。
再者,本发明的目的之一在于提供一种整合电子元件的多层线路织物的制造方法,解决电子元件结合细微线路在具有弹性及/或可挠性的织物上短路与外观不良的问题及使用包含FPC及晶片或晶粒的电子元件时FPC与导电线路层之间的短路问题,以及解决复杂交错的导电线路层的配置问题。
另一方面,根据本发明的整合电子元件的多层线路织物的制造方法,可制造贴纸形态的整合电子元件的多层线路织物,使用时藉由转印方式再贴合于所需要的位置。
为了达到上述目的,根据本发明一实施态样,提供一种整合电子元件的多层线路织物,包括:一基础层(base layer);多层的导电线路层,形成于该基础层上;至少一连接层,具有导电材料所构成的多个通孔及绝缘材料所构成的多个绝缘区域且该连接层位于上下相邻的2层导电线路层之间,经由该多个通孔电连接该上下相邻的2层导电线路层,其中该多个绝缘区域分布于连接层的除通孔以外的区域;一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上;以及一防水层,设置于该多层的导电线路层中距离基础层最远的层上。
再者,根据本发明另一实施态样,提供一种整合电子元件的多层线路织物的制造方法,包括:以下步骤(1)提供一基础层;(2)形成具有一第1指定图形的导电线路层于该基础层上;(3)形成一连接层于该导电线路层;(4)形成具有一第2指定图形的导电线路层于该连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上;以及(5)形成一防水层;其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4),于多个第1指定图形的情况,亦即于步骤(2)进行2 次或2次以上的情况,该多个第1指定图形可为相同,亦可为不同。
或者,又根据本发明另一实施态样,提供一种整合电子元件的多层线路织物的制造方法,包括:以下步骤(1)提供一离型纸或离型膜;(2)形成具有一第1指定图形的导电线路层于该离型纸或离型膜上;(3)形成一连接层于该导电线路层上;(4)形成具有一第2指定图形的导电线路层于该连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上;(5)形成一防水层,至少覆盖具有导电线路层、该电子元件及该连接层的区域,得到一具有电子元件的积层体;以及(6)该积层体藉由热转印至一被贴合物,得到整合电子元件的多层线路织物;其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4)。
根据本发明的整合电子元件的多层线路织物及其制造方法,可提供传统FPC无法提供的可挠性、弯折性及拉伸弹性的具备电子元件的织物,又可贴纸形态的整合电子元件的多层线路织物,使用时藉由转印方式再贴合于所需要的位置。
附图说明
图1表示关于本发明的整合电子元件的多层线路织物的一实施例的部分区域的剖面示意图。
图2表示关于本发明的整合电子元件的多层线路织物的其他实施例的部分区域的剖面示意图。
图3表示关于本发明的整合电子元件的多层线路织物的制造方法的一实施例的流程图。
图4表示关于本发明的整合电子元件的多层线路织物的制造方法的其他实施例的流程图。
图5表示关于本发明的整合电子元件的多层线路织物的制造方法的步骤(4)的热压示意图。
图6表示关于本发明的整合电子元件的多层线路织物的一实施例的平面示意图。
符号说明:
1a,1b,2a:多层线路织物
10a:热压头
10b:底座载台
50:保护膜
100:基础层
200,210,220,230:导电线路层
300,310,320,330:连接层
310a,320a,330a:通孔
310b,320b,330b:绝缘区域
400:电子元件
500:防水层
600:缓冲材料
ACF:异方性导电胶
Ad:黏着剂层
具体实施方式
有关本发明的前述及其他技术内容、特点与功效,在以下配合参考图式的一较佳实施例的详细说明中,将可清楚的呈现。以下实施例中所提到的方向用语,例如:上、下、左、右、前或后等,仅是参考附加图式的方向。因此,使用的方向用语是用来说明并非用来限制本发明。此外,“A层(或元件)设置于B层(或元件)上”的用语,并不限定为A层直接贴覆接触B层表面的态样,例如A层与B层中间尚间隔其他迭层亦为该用语所涵盖范围。图示中,相同的元件系以相同的符号表示。
同时参考图1及图2,表示关于本发明的整合电子元件的多层线路织物的实施例的部分区域的剖面示意图。如图1及图2所示,整合电子元件的多层线路织物1a,包括:基础层100、导电线路层200(包括导电线路层210、220及230)、连接层300(包括连接层310、 320及330)、电子元件400及防水层500。整合电子元件的多层线路织物1b与整合电子元件的多层线路织物1a的差异之处,在于多层线路织物1b更包括黏着剂层Ad及保护膜50,保护膜50系用以暂时保护黏着剂层Ad,具体地保护膜50例如为厚度25~200μm的聚对苯二甲酸乙二酯(PET)膜。图2所示的整合电子元件的多层线路织物2a与整合电子元件的多层线路织物1a的差异之处,在于多层线路织物2a包括更多层的导电线路层及连接层。
连接层310、320及330,具有导电材料所构成的多个通孔310a、320a及330a及绝缘材料所构成的多个绝缘区域310b、320b及330b且连接层位于上下相邻的2层导电线路层之间,经由多个通孔310a、320a及330a电连接该上下相邻的2层导电线路层,其中多个绝缘区域310b、320b及330b分布于连接层的除通孔以外的区域。
电子元件400(图式中仅显示一个电子元件,于织物的其他位置可再具有其他电子元件),藉由异方性导电胶ACF固定于导电线路层的导电线路上。
防水层500,覆盖电子元件及导电线路层所涵盖的区域,达到防水、导热、透湿的功能。构成防水层500的材料,例如为热塑性树脂、聚四氟乙烯、聚硅氧树脂等,具体地例如热塑性聚酯、热塑性聚氨酯等,较理想为热塑性聚氨酯,具体地例如热熔聚氨酯胶。
于一实施例,该电子元件元件包括可挠性电路板及设置于该可挠性电路板的晶片或晶粒。于电子元件元件包括可挠性电路板时,整合电子元件的多层线路织物可更包括补强绝缘板,设置于可挠性电路板与导电线路层之间,其中该补强绝缘板由聚酰亚胺膜所构成,例如厚度8~200μm的聚酰亚胺膜。
于一实施例,该电子元件可为任意的晶粒或晶片,可为例如发光二极管或感测器元件。
于一实施例,该基础层为单面或两面具有防水功能的梭织物、针织物、立体织物或热塑性薄膜。导电线路层200通常形成于任一具有防水功能的面上。于基础层为热塑性薄膜的情况,该热塑性薄膜通常具有防水、导热、透湿的功能,亦即两面具有防水功能的基础层。
为了确保多层线路织物上的电子元件与导电线路发挥正常的功能,例如不发生短路,构成该导电线路层的材料与构成该连接层的该绝缘材料的热膨胀系数的差的绝对值对该绝缘材料的热膨胀系数的比例为20%以下较理想,4%以下更理想,1%以下更加理想。构成该连接层的该绝缘材料与构成该连接层的该导电材料的热膨胀系数的差的绝对值对该绝缘材料的热膨胀系数的比例为20%以下,4%以下更理想,1%以下更加理想。该异方性导电胶与构成该连接层的该绝缘材料的热膨胀系数的差的绝对值对该绝缘材料的热膨胀系数的比例为20%以下,4%以下更理想,1%以下更加理想。
上述异方性导电胶具有在100~140℃的范围接着的性质,且具有快速接着的特性,例如接着时间为5~10秒的范围。例如可使用市售的异方性导电胶(ACF),具体地例如日立化学、迪睿合化学、玮锋科技公司制的低温快速接着的异方性导电胶。
于一实施例,导电线路层由导电性银胶所构成,例如具有伸缩、扭转、弯曲(伸长率≧100%)的导电银浆,例如可具有约100μΩ·cm的导电系数,可用于网版印刷,可低温干燥,此处低温指例如(120~150℃)。导电线路层的厚度,例如为12~200μm,较理想为 12~50μm。
图3及图4表示根据本发明的整合电子元件的多层线路织物的制造方法。如图3所示,本发明的制造方法包括:以下步骤(1)提供一基础层(S10);(2)形成具有一第1指定图形的导电线路层于该基础层上(S20);(3)形成一连接层于该导电线路层(S30);(4) 形成具有一第2指定图形的导电线路层于该连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上(S40);以及(5)形成一防水层(S50);其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4),于多个第 1指定图形的情况,亦即于步骤(2)进行2次或2次以上的情况,该多个第1指定图形可为相同,亦可为不同。上述基础层为单面或两面具有防水功能的梭织物、针织物、立体织物或热塑性薄膜。
如图4所示,本发明的制造方法包括:以下步骤(1)提供一离型纸或离型膜(S100);(2)形成具有一第1指定图形的导电线路层于该离型纸或离型膜上(S200);(3)形成一连接层于该导电线路层上(S300);(4)形成具有一第2指定图形的导电线路层于该连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于该导电线路层的导电线路上(S400);(5)形成一防水层,至少覆盖具有导电线路层、该电子元件及该连接层的区域,得到一具有电子元件的积层体(S500);以及(6)该积层体藉由热转印至一被贴合物,得到整合电子元件的多层线路织物(S600);其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4)。上述被贴合物为单面或两面具有防水功能的梭织物、针织物、立体织物或热塑性薄膜
于一实施例,步骤(2)形成具有一第1指定图形的导电线路层的方法(S20、S200),藉由点胶法或网版印刷法,使用银胶,形成该导电线路层。
于一实施例,步骤(3)形成该连接层的方法(S30、S300),可使用立体印表机,同时列印导电材料与绝缘材料,形成具有导电材料所构成的多个通孔及绝缘材料所构成的多个绝缘区域的该连接层,其中经由该多个通孔电连接该上下相邻的2层导电线路层,该多个绝缘区域分布于连接层的除通孔以外的区域,该导电材料为银胶或低温锡膏。
此外,于另一实施例,步骤(3)形成该连接层的方法(S30、S300),可使用喷墨法、网版印刷法、点胶法或利用遮罩的涂布法,形成绝缘材料所构成的多个绝缘区域后,再使用喷墨法、网版印刷法或点胶法形成导电材料所构成的多个通孔,该导电材料为银胶或低温锡膏。此处,银胶与上述导电银胶或银浆相同,低温锡膏的低温,指例如温度120~160℃的范围。
于一实施例,步骤(4)中(S40、S400),藉由点胶法或网版印刷法,使用银胶,形成该导电线路层,然后使用具有低温快速接着的异方性导电胶,藉由热压,将该电子元件固定于该导电线路层的导电线路上。
本发明的制造方法,该电子元件可包括可挠性电路板及设置于该可挠性电路板的晶片或晶粒,热压时该可挠性电路板与该导电线路层之间更包括一补强绝缘板。该电子元件亦可只包括晶片或晶粒,该晶片或晶粒的具体例,例如发光二极管、各种感测器等。
上述热压的条件,例如为0.5MPa~10MPa的压力,100~160℃的温度,3~30秒的时间。热压时所使用的热压头与该电子元件之间,可更具备一缓冲材料。缓冲材料例如为铁氟龙膜或硅胶膜。具体地,参考图5,表示关于本发明的整合电子元件的多层线路织物的制造方法的步骤(4)的热压示意图。图5中,10a表示热压头,10b表示底座载台,600表示缓冲材料,在热压头10a供应热源,在热压头10a与底座载台10b赋予压力。图5的(a) 表示基础层的另一侧不具有黏着剂与保护膜的多层线路织物1a,(b)表示基础层的另一侧具有黏着剂与保护膜(离型纸或离型膜)的多层线路织物1b,(c)表示具有补强绝缘板的多层线路织物。
该热转印的条件为100~200℃的温度,0.5MPa~10MPa的压力,3~30秒的时间,该离型纸或离型膜为硬质的离型纸或离型膜。
图6表示关于本发明的整合电子元件的多层线路织物的一实施例的平面示意图。该整合电子元件的多层线路织物具有多个作为电子元件的LED,可作为警示灯或各种显示用途,图6的(a)表示第一导电线路层,图6的(b)表示连接层,图6的(c)表示第二导电线路层,图6的(d)表示图6的(a)~(c)积层所得的本发明的整合电子元件的多层线路织物。
根据本发明,可提供传统FPC无法提供的可挠性、弯折性及拉伸弹性的具备电子元件的织物,又可贴纸形态的整合电子元件的多层线路织物,使用时藉由转印方式再贴合于所需要的位置。
以上虽以特定实施例说明本发明,但并不因此限定本发明的范围,只要不脱离本发明的要旨,熟悉本技艺者了解在不脱离本发明的意图及范围下可进行各种变形或变更。另外本发明的任一实施例或权利要求范围不须达成本发明所揭露的全部目的或优点或特点。此外,摘要部分和标题仅是用来辅助专利文件搜寻之用,并非用来限制本发明的权利范围。
Claims (14)
1.一种整合电子元件的多层线路织物,其特征在于,所述的整合电子元件的多层线路织物包括:
一基础层;
多层的导电线路层,形成于所述的基础层上;
至少一连接层,具有导电材料所构成的多个通孔及绝缘材料所构成的多个绝缘区域且所述的连接层位于上下相邻的2层导电线路层之间,经由所述的多个通孔电连接所述的上下相邻的2层导电线路层,其中所述的多个绝缘区域分布于连接层的除通孔以外的区域;
一个或一个以上的电子元件,藉由异方性导电胶固定于所述的导电线路层的导电线路上;以及
一防水层,设置于所述的多层的导电线路层中距离基础层最远的层上;
构成所述的导电线路层的材料与构成所述的连接层的所述的绝缘材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下,构成所述的连接层的所述的绝缘材料与构成所述的连接层的所述的导电材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下,所述的异方性导电胶与构成所述的连接层的所述的绝缘材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下。
2.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的电子元件元件包括可挠性电路板及设置于所述的可挠性电路板的晶片或晶粒。
3.如权利要求2所述的整合电子元件的多层线路织物,其特征在于,所述的整合电子元件的多层线路织物更包括:补强绝缘板,位于所述的可挠性电路板与导电线路层之间,其中所述的补强绝缘板由聚酰亚胺膜所构成。
4.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的电子元件为发光二极管或感测器。
5.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的基础层为单面或两面具有防水功能的梭织物、针织物、立体织物或热塑性薄膜。
6.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的异方性导电胶具有在100~140℃的范围接着的性质。
7.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的导电线路层由导电性银胶所构成。
8.如权利要求1所述的整合电子元件的多层线路织物,其特征在于,所述的防水层由热塑性聚氨酯所构成。
9.一种整合电子元件的多层线路织物的制造方法,其特征在于,所述的方法包括:以下步骤
(1)提供一基础层;
(2)形成具有一第1指定图形的导电线路层于所述的基础层上;
(3)形成一连接层于所述的导电线路层;
(4)形成具有一第2指定图形的导电线路层于所述的连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于所述的导电线路层的导电线路上;以及
(5)形成一防水层;
其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4),于多个第1指定图形的情况,亦即于步骤(2)进行2次或2次以上的情况,所述的多个第1指定图形可为相同,亦可为不同;
步骤(1)~(4)中构成所述的导电线路层的材料与构成所述的连接层的绝缘材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下,构成所述的连接层的所述的绝缘材料与构成所述的连接层的所述的导电材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下,所述的异方性导电胶与构成所述的连接层的所述的绝缘材料的热膨胀系数的差的绝对值对所述的绝缘材料的热膨胀系数的比例为20%以下。
10.一种整合电子元件的多层线路织物的制造方法,其特征在于,所述的方法包括:以下步骤
(1)提供一离型纸或离型膜;
(2)形成具有一第1指定图形的导电线路层于所述的离型纸或离型膜上;
(3)形成一连接层于所述的导电线路层上;
(4)形成具有一第2指定图形的导电线路层于所述的连接层上以及将一个或一个以上的电子元件,藉由异方性导电胶固定于所述的导电线路层的导电线路上;
(5)形成一防水层,至少覆盖具有导电线路层、所述的电子元件及所述的连接层的区域,得到一具有电子元件的积层体;以及
(6)所述的积层体藉由热转印至一被贴合物,得到整合电子元件的多层线路织物;
其中,步骤(2)及(3)至少进行1次,或者进行2次以上后再进行步骤(4)。
11.如权利要求9或10所述的方法,其特征在于,步骤(2)形成具有一第1指定图形的导电线路层的方法,藉由点胶法或网版印刷法,使用银胶,形成所述的导电线路层。
12.如权利要求9或10所述的方法,其特征在于,步骤(3)形成所述的连接层的方法,使用立体印表机,同时列印导电材料与绝缘材料,形成具有导电材料所构成的多个通孔及绝缘材料所构成的多个绝缘区域的所述的连接层,其中经由所述的多个通孔电连接上下相邻的2层导电线路层,所述的多个绝缘区域分布于连接层的除通孔以外的区域,所述的导电材料为银胶或低温锡膏。
13.如权利要求9或10所述的方法,其特征在于,步骤(3)形成所述的连接层的方法,是使用喷墨法、网版印刷法、点胶法或利用遮罩的涂布法,形成绝缘材料所构成的多个绝缘区域后,再使用喷墨法、网版印刷法或点胶法形成导电材料所构成的多个通孔,所述的导电材料为银胶或低温锡膏。
14.如权利要求9或10所述的方法,其特征在于,步骤(4)中,藉由点胶法或网版印刷法,使用银胶,形成所述的导电线路层,然后使用具有低温快速接着的异方性导电胶,藉由热压,将所述的电子元件固定于所述的导电线路层的导电线路上。
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US20190069407A1 (en) | 2019-02-28 |
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