CN109427797A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109427797A CN109427797A CN201710734937.5A CN201710734937A CN109427797A CN 109427797 A CN109427797 A CN 109427797A CN 201710734937 A CN201710734937 A CN 201710734937A CN 109427797 A CN109427797 A CN 109427797A
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
A kind of semiconductor structure and forming method thereof, forming method includes: offer substrate, including cell memory area and Content Addressable Memory area；Gate structure is formed on the substrate, the floating including tunnel oxide and on tunnel oxide；The first source and drain doping area is formed in the substrate of cell memory area gate structure two sides；Form the second source and drain doping area in the substrate of Content Addressable Memory area gate structure two sides, the doping concentration of the doping concentration in the second source and drain doping area less than the first source and drain doping area.By the doping concentration for reducing the second source and drain doping area, to improve the initial threshold voltage of Content Addressable Memory, accordingly floating possessed electronics in eigenstate is increased, therefore it can improve trap auxiliary tunneling effect, to improve the data retention of Content Addressable Memory；In addition, the doping concentration in the first source and drain doping area is unaffected, to keep the performance in cell memory area unaffected.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
Currently, flash memory (Flash), also known as flash memory, have become the mainstream of non-volatility memorizer.According to
Structure is different, flash memory can be divided into or non-flash (Nor Flash) and with two kinds of non-flash (NAND Flash).Flash memory it is main
Feature is to keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe
The advantages that removing and rewriteeing, thus be widely used in the multinomial field such as microcomputer, automation control.
Wherein, NAND Flash not only includes unit (Cell) memory, further includes Content Addressable Memory
(Content Addressable Memory, CAM).Content Addressable Memory is a kind of special memory, can be transported in single
Whole memory is searched in calculation, thus search application in, Content Addressable Memory than normal memory speed faster.
The fast search characteristic of Content Addressable Memory makes Content Addressable Memory especially suitable for such as network equipment, CPU
(Center Processing Unit, central processing unit), DSP (Digital Signal Processor, at digital signal
Manage device) and hard encoding and decoding of video etc. apply.
But the performance of prior art Content Addressable Memory is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves content addressable storage
The performance of device.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Substrate includes cell memory area and Content Addressable Memory area；Gate structure, the grid knot are formed on the substrate
Structure includes tunnel oxide and the floating on the tunnel oxide；In the cell memory area grid knot
The first source and drain doping area is formed in the substrate of structure two sides；Substrate in the Content Addressable Memory area gate structure two sides
The doping concentration in the second source and drain doping area of interior formation, second source and drain doping area is less than mixing for first source and drain doping area
Miscellaneous concentration.
Optionally, first source and drain doping area is formed using the first source and drain injection technology, work is injected using the second source and drain
Skill forms second source and drain doping area, and the implantation dosage of the second source and drain injection technology is injected less than first source and drain
The implantation dosage of technique.
Optionally, the step of forming the first source and drain doping area includes: the base in the Content Addressable Memory area
The first graph layer is formed on bottom, first graph layer also covers the gate structure in the Content Addressable Memory area；With institute
Stating the first graph layer is exposure mask, carries out the first source and drain injection technology to the substrate of the cell memory area gate structure two sides；
After the first source and drain injection technology, first graph layer is removed.
Optionally, it includes for P ion, As ion and Sb that the parameter of the first source and drain injection technology, which includes: injection ion,
One of ion is a variety of, Implantation Energy be 10Kev to 20Kev, implantation dosage be 7E12 atom per square centimeter extremely
1.2E13 atom per square centimeter.
Optionally, the step of forming the second source and drain doping area includes: the shape in the substrate in the cell memory area
At second graph layer, the second graph floor also covers the gate structure in the cell memory area；With the second graph layer
For exposure mask, the second source and drain injection technology is carried out to the substrate of the Content Addressable Memory area gate structure two sides；Described
After second source and drain injection technology, the second graph layer is removed.
Optionally, it includes for P ion, As ion and Sb that the parameter of the second source and drain injection technology, which includes: Doped ions,
One of ion is a variety of, and Implantation Energy is 10Kev to 20Kev, and implantation dosage is 5E12 atom per square centimeter to 1E13
Atom per square centimeter.
Optionally, the step of forming the first source and drain doping area includes: in cell memory area gate structure two
The first groove is formed in the substrate of side；It forms the first semiconductor layer in first groove, and is led forming described the first half
Auto-dope ion in situ during body layer；Alternatively, the step of forming the first source and drain doping area includes: in the unit
The first groove is formed in the substrate of memory areas gate structure two sides；The first semiconductor layer is formed in first groove；It is right
The first semiconductor layer doped ion.
Optionally, the step of forming the second source and drain doping area includes: in Content Addressable Memory area grid
The second groove is formed in the substrate of structure two sides；It forms the second semiconductor layer in second groove, and is forming described the
Auto-dope ion in situ during two semiconductor layers, the doping concentration of second semiconductor layer are less than described the first half and lead
The doping concentration of body layer；Alternatively, the step of forming the second source and drain doping area includes: in the Content Addressable Memory
The second groove is formed in the substrate of area gate structure two sides；The second semiconductor layer is formed in second groove；To described
Two semiconductor layer doped ions, the doping concentration of second semiconductor layer are less than the doping concentration of first semiconductor layer.
Optionally, the material of first semiconductor layer is Si or SiC, the Doped ions in first semiconductor layer
For N-type ion, the N-type ion includes for one of P ion, As ion and Sb ion or a variety of；First semiconductor
The material of layer is Si or SiC, and the Doped ions in first semiconductor layer are N-type ion, the N-type ion include for P from
One of son, As ion and Sb ion are a variety of.
Optionally, after forming first source and drain doping area, second source and drain doping area is formed；Alternatively, in shape
After second source and drain doping area, first source and drain doping area is formed.
Optionally, in the step of forming gate structure on the substrate, the gate structure further include: be located at described
Gate dielectric layer on floating, and the control grid layer on the gate dielectric layer.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include cell memory area
With Content Addressable Memory area；Gate structure, be located at the substrate on, the gate structure include tunnel oxide and
Floating on the tunnel oxide；First source and drain doping area is located at cell memory area gate structure two
In the substrate of side；Second source and drain doping area, in the substrate of the Content Addressable Memory area gate structure two sides, institute
The doping concentration for stating the second source and drain doping area is less than the doping concentration in first source and drain doping area.
Optionally, the Doped ions in first source and drain doping area include for one in P ion, As ion and Sb ion
Kind is a variety of.
Optionally, the Doped ions in second source and drain doping area include for one in P ion, As ion and Sb ion
Kind is a variety of.
Optionally, the gate structure further include: the gate dielectric layer on the floating, and be located at described
Control grid layer on gate dielectric layer.
Optionally, the material in first source and drain doping area is the first semiconductor material with Doped ions, described the
Two source and drain doping areas are the second semiconductor material with Doped ions.
Optionally, first semiconductor material is Si or SiC, the Doped ions packet in first semiconductor material
It includes as one of P ion, As ion and Sb ion or a variety of；Second semiconductor material be Si or SiC, described second
Doped ions in semiconductor material include for one of P ion, As ion and Sb ion or a variety of.
Compared with prior art, technical solution of the present invention has the advantage that
The first source and drain doping area is formed in the substrate of the cell memory area gate structure two sides respectively, described
The second source and drain doping area, and second source and drain doping are formed in the substrate of Content Addressable Memory area gate structure two sides
The doping concentration in area is less than the doping concentration in first source and drain doping area；With the first source and drain doping area and the second source and drain doping
The identical scheme of the doping concentration in area is compared, by reducing the doping concentration in the second source and drain doping area, to improve content addressable
The initial threshold voltage (Initial Vt) of memory accordingly makes floating (Floating Gate, FG) in eigenstate
Possessed electronics increases；Therefore it at programming (Program), for identical program voltage, is caught needed for the floating
The electronics obtained is reduced, and can accordingly reduce the trapped charge in tunnel oxide (Tunnel Oxide) caused by programming, i.e.,
Trap auxiliary tunnelling (Trap-assisted Tunneling, TAT) effect can be improved, asked so as to improve device creepage
Topic improves the threshold voltage characteristic of the Content Addressable Memory, and then improves the data of the Content Addressable Memory
(Data Retention) ability of preservation, so that the performance of the Content Addressable Memory gets a promotion；Moreover, programming
Afterwards, the electron number stored in the floating is reduced, and can also accordingly improve the floating grid as caused by other effects
Layer electronics losing issue, is conducive to the data retention for further increasing the Content Addressable Memory；In addition, passing through
It is respectively formed the first source and drain doping area and the second source and drain doping area, the doping concentration in the first source and drain doping area can be made not by shadow
It rings, to keep the performance in cell memory area unaffected.
Detailed description of the invention
Fig. 1 be content addressable storage unit corresponding to a kind of Content Addressable Memory threshold voltage with it is described interior
Hold the graph of relation of the sample size of addressing storage cell；
Fig. 2 is Content Addressable Memory shown in Fig. 1 after baking is handled, the content addressable storage unit
The graph of relation of the sample size of threshold voltage and the content addressable storage unit；
Fig. 3 is a kind of structural schematic diagram of semiconductor structure；
Fig. 4 to Fig. 7 is the corresponding schematic diagram of each step in one embodiment of forming method of semiconductor structure of the present invention；
Fig. 8 is under the conditions of Fig. 4 uses different source and drain implantation dosages to embodiment illustrated in fig. 7, and formed content addressable is deposited
Reservoir is after baking is handled, the threshold voltage of content addressable storage unit and the sample number of content addressable storage unit
The graph of relation of amount.
Specific embodiment
It can be seen from background technology that the property of Content Addressable Memory (Content Addressable Memory, CAM)
It can be to be improved.
Specifically, after baking (Bake) processing of the Content Addressable Memory by reliability test or long-term idle
(Idle) after, the Content Addressable Memory is easy to appear data and saves failure (Data Retention Fail) and threshold value
The problem of variation (Vt Shift).
It is content addressable storage unit corresponding to a kind of Content Addressable Memory in conjunction with reference Fig. 1 and Fig. 2, Fig. 1
The graph of relation of the sample size of threshold voltage and the content addressable storage unit；Fig. 2 is that content shown in Fig. 1 can be sought
Location memory is after baking is handled, the threshold voltage and content addressable storage unit of the content addressable storage unit
Sample size graph of relation.Wherein, the abscissa of Fig. 1 and Fig. 2 indicates that threshold voltage, ordinate indicate sample size.
Specifically, Fig. 2 is Content Addressable Memory described in Fig. 1 after the baking of 250 degrees Celsius, 2 hours is handled
Graph of relation, the dotted line A in Fig. 1 and Fig. 2 is the threshold voltage standard value of the content addressable storage unit, that is, is worked as
The threshold voltage of content addressable storage unit corresponding to the Content Addressable Memory is all larger than the threshold voltage standard
When value, determine that the Content Addressable Memory programs successfully.
As seen from the figure, after baking processing, the threshold voltage of the Content Addressable Memory reduces, and described
The threshold voltage shift of the left-half (i.e. Left-tail) (as shown in virtual coil in Fig. 2) of graph of relation is particularly acute.
Now in conjunction with a kind of semiconductor structure structural representation map analysis Content Addressable Memory performance decline the reason of.
With reference to Fig. 3, a kind of structural schematic diagram of semiconductor structure is shown.
The semiconductor structure includes: substrate 10, and the substrate 10 includes that cell memory area I and content addressable are deposited
Reservoir area II；Gate structure (not indicating) in the substrate 10, the gate structure includes tunnel oxide 21, position
In the floating 22 on the tunnel oxide 21, the gate dielectric layer 23 on the floating 22, and it is located at institute
State the control grid layer (Control Gate, CG) 24 on gate dielectric layer 23；Source and drain doping area 30 is located at the cell memory
In the substrates 10 of area I gate structure two sides and the substrate 10 of the Content Addressable Memory area II gate structure two sides
It is interior.
Under normal conditions, the program voltage (Program Vt) of Content Addressable Memory and reading voltage (Read Vt)
It is bigger than cell memory；Higher program voltage indicates the Content Addressable Memory after programming, the floating
The electron number stored in 22 is more, correspondingly, the trapped charge in the tunnel oxide 21 is also more, therefore is easy hair
Raw trap assists tunnelling (Trap-assisted Tunneling, TAT) effect, and the electronics in the floating 22 is easy logical
It crosses the tunnel oxide 21 that the TAT effect occurs and reveals, to be easy to cause the content addressable storage
The threshold voltage of device shifts, and then the data retention of the Content Addressable Memory is caused to decline.
In order to solve the technical problem, the present invention passes through the doping concentration for reducing the second source and drain doping area, in improving
The initial threshold voltage for holding addressable memory, increases floating possessed electronics in eigenstate；Therefore
In programming, for identical program voltage, the electronics captured needed for the floating is reduced, and can accordingly reduce programming
Caused by trapped charge in tunnel oxide, it can improve trap and assist tunneling effect, asked so as to improve device creepage
Topic improves the threshold voltage characteristic of Content Addressable Memory, and then the data for improving Content Addressable Memory save energy
Power, so that the performance of Content Addressable Memory gets a promotion；Moreover, after programming, the electricity stored in the floating
Subnumber is reduced, and can also accordingly be improved the floating electronics losing issue as caused by other effects, is conducive into one
Step improves the data retention of Content Addressable Memory；In addition, by being respectively formed the first source and drain doping area and the second source
Leak doped region, the doping concentration in the first source and drain doping area can be made unaffected, thus make the performance in cell memory area not by
It influences.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Fig. 8 is the corresponding schematic diagram of each step in one embodiment of forming method of semiconductor structure of the present invention.
With reference to Fig. 4, substrate 100 is provided, the substrate 100 includes cell memory area I and Content Addressable Memory area
II。
The substrate 100 provides technological operation basis for subsequent technique.
Specifically, the substrate 100 is used to form and non-flash (NAND Flash) device.
In the present embodiment, formed semiconductor structure is planar structure, correspondingly, the substrate 100 is planar substrate.
In other embodiments, formed semiconductor structure can also have fin structure, that is, being formed by device is fin field effect
Transistor, the substrate accordingly include substrate and discrete fin on the substrate.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
The other materials such as germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also on insulator silicon substrate or
The other kinds of substrate such as the germanium substrate on person's insulator.The material of the substrate, which can be, to be suitable for process requirement or is easy to
Integrated material.
In the present embodiment, the substrate 100 includes cell memory area I and Content Addressable Memory area II, the list
The substrate 100 of metamemory area I is used to form cell memory, and the substrate 100 of the Content Addressable Memory area II is used for
Form Content Addressable Memory.
In the present embodiment, the cell memory area I and Content Addressable Memory area II are set as non-conterminous.At it
In his embodiment, the cell memory area and Content Addressable Memory area can also be disposed adjacent.
With reference to Fig. 5, gate structure (not indicating) is formed in the substrate 100, the gate structure includes tunnel oxide
Layer (Tunnel Oxide) 210 and the floating (Floating Gate, FG) on the tunnel oxide 210
220。
It should be noted that in the step of forming gate structure in the substrate 100, the gate structure further include:
Gate dielectric layer 230 on the floating 220, and the control grid layer on the gate dielectric layer 230
(Control Gate, CG) 240.
Specifically, the step of forming the gate structure includes: the formation tunnel oxide material layer in the substrate 100；
Floating gate material layer is formed in the tunnel oxide material layer；Gate dielectric material layer is formed in the floating gate material layer；
Control gate material layer is formed in the gate dielectric material layer；Successively the graphical control gate material layer, gate dielectric material layer,
Floating gate material layer and tunnel oxide material layer, remaining tunnel oxide material layer is as tunnel oxide 210, remaining floating grid
Material layer is as floating 220, remaining gate dielectric material layer as gate dielectric layer 230, remaining control gate material layer as control
Grid layer 240 processed, and the tunnel oxide 210, floating 220, gate dielectric layer 230 and control grid layer 240 are for constituting
The gate structure.
In the present embodiment, the material of the floating 220 and the control grid layer 240 is polysilicon；The tunnelling oxygen
The material for changing layer 210 is silica；The gate dielectric layer 230 includes the first silicon oxide layer, is located on first silicon oxide layer
Silicon nitride layer and the second silicon oxide layer on the silicon nitride layer, i.e., the described gate dielectric layer 230 be ONO
(Oxide-Nitride-Oxide) structure.
The technical solution for forming the gate structure is same as the prior art, and details are not described herein for the present embodiment.
With reference to Fig. 6, the first source is formed in the substrate 100 that the cell memory area I gate structure (does not indicate) two sides
Leak doped region 315.
First source and drain doping area 315 is used for source region or drain region as formed cell memory.
In the present embodiment, first source and drain doping is formed using the first source and drain injection (CSD Implant) technique 310
Area 315.
Specifically, the step of forming first source and drain doping area 315 includes: in the Content Addressable Memory area
The first graph layer 300 is formed in the substrate 100 of II, first graph layer 300 also covers the Content Addressable Memory area
The gate structure of II；It is exposure mask with first graph layer 300, to the substrate of the cell memory area I gate structure two sides
100 carry out the first source and drain injection technology 310；After the first source and drain injection technology 310, first graph layer is removed
300。
In the present embodiment, the type of device of formed cell memory is N-type device, therefore first source and drain is injected
The injection ion of technique 310 is N-type ion, and the parameter of the first source and drain injection technology 310 according to actual process demand and
Depending on device performance requirements.
In certain embodiments, it includes for P that the parameter of the first source and drain injection technology 310, which includes: injection ion,
One of ion, As ion and Sb ion are a variety of, and Implantation Energy is 10Kev to 20Kev, and implantation dosage is 7E12 atom
It is every square centimeter to 1.2E13 atom per square centimeter.
It should be noted that in the present embodiment, it is adjacent described since the spacing of the adjacent gate structure is smaller
The first source and drain doping area 315 cell memory belonging to two gate structures between gate structure is shared.
In the present embodiment, the material of first graph layer 300 is photoresist, in the first source and drain injection technology 310
Afterwards, first graph layer 300 is removed using ashing or wet processing.
In other embodiments, in order to further increase the performance of formed cell memory, first source is being formed
It leaks and introduces extension (EPI) technology in the technical process of doped region, to improve the carrier mobility of the cell memory.
Specifically, the step of forming the first source and drain doping area includes: in cell memory area gate structure two
The first groove is formed in the substrate of side；It forms the first semiconductor layer in first groove, and is led forming described the first half
Auto-dope ion in situ during body layer；Alternatively, after forming the first semiconductor layer in first groove, to described
Semi-conductor layer Doped ions.
Correspondingly, the material of first semiconductor layer is Si or SiC, the Doped ions in first semiconductor layer
For N-type ion, the N-type ion includes for one of P ion, As ion and Sb ion or a variety of.
With reference to Fig. 7, the shape in the substrate 100 that the Content Addressable Memory area II gate structure (does not indicate) two sides
At the second source and drain doping area 415, the doping concentration in second source and drain doping area 415 is less than first source and drain doping area 315
Doping concentration.
Second source and drain doping area 415 is used for source region or drain region as formed Content Addressable Memory.
In the present embodiment, the doping concentration in second source and drain doping area 415 is less than first source and drain doping area 315
Doping concentration.
Compared with the identical scheme of doping concentration in the first source and drain doping area and the second source and drain doping area, by reducing institute
The doping concentration in the second source and drain doping area 415 is stated, to improve the initial threshold voltage of the Content Addressable Memory, accordingly
So that the floating 220 of the Content Addressable Memory possessed electronics in eigenstate increases, therefore programming
When, for identical program voltage, the electronics captured needed for the floating 220 is reduced.
And since the floating 220 captures electronics from the substrate 100, and the tunnel oxide 210 is located at
Between the floating 220 and the substrate 100, therefore subtracted by the electronics of capture needed for making the floating 220
It is few, it can accordingly reduce the trapped charge in tunnel oxide 210 caused by programming, it can improve trap and assist tunnelling
(Trap-assisted Tunneling, TAT) effect improves the content addressable so as to improve element leakage flow problem
The threshold voltage characteristic of memory avoids the problem that threshold voltage shift occurs, and then improves the number of Content Addressable Memory
According to hold capacity, so that the performance of Content Addressable Memory gets a promotion；Moreover, after programming, the floating 220
The charge number of middle storage is reduced, and can also accordingly be improved 220 electronics of the floating loss as caused by other effects and be asked
Topic, is conducive to the data retention for further increasing Content Addressable Memory.
In addition, if the initial threshold voltage of cell memory increases, although the data that cell memory can be improved are protected
Ability is deposited, but the repetitive read-write (i.e. Cycling) that accordingly will lead to cell memory is less able；Therefore first source
Leakage doped region 315 and the second source and drain doping area 415 are formed in different process, that is, are reducing by second source and drain doping area 415
Doping concentration in the case where, the doping concentration in first source and drain doping area 315 can be made unaffected, to make institute's shape
Performance at cell memory area is unaffected.
In the present embodiment, second source and drain doping area 415, and described are formed using the second source and drain injection technology 410
The implantation dosage of two source and drain injection technologies 410 is less than the implantation dosage of the first source and drain injection technology 310 (as shown in Figure 6).
Specifically, the step of forming second source and drain doping area 415 includes: the substrate in the cell memory area I
Second graph layer 400 is formed on 100, the second graph floor 400 also covers the gate structure of the cell memory area I；With
The second graph layer 400 is exposure mask, is carried out to the substrate 100 of the Content Addressable Memory area II gate structure two sides
Second source and drain injection technology 410；After the second source and drain injection technology 410, the second graph layer 400 is removed.
In the present embodiment, the type of device of formed Content Addressable Memory is N-type device, therefore second source
The injection ion for leaking injection technology 410 is N-type ion.
In certain embodiments, it includes for P that the parameter of the second source and drain injection technology 410, which includes: injection ion,
One of ion, As ion and Sb ion are a variety of, and Implantation Energy is 10Kev to 20Kev.
It should be noted that the implantation dosage of the second source and drain injection technology 410 is unsuitable too small, also should not be too large.Such as
The implantation dosage of second source and drain injection technology 410 described in fruit is too small, then is easy to cause the full of formed Content Addressable Memory
It is too small with electric current, it is too small so as to cause read current；If the implantation dosage of the second source and drain injection technology 410 is excessive, mention
The effect of the initial threshold voltage of high formed Content Addressable Memory is unobvious, and accordingly causing, which improves content addressable, deposits
The effect of reservoir performance is unobvious.For this purpose, the implantation dosage of the second source and drain injection technology 410 is 5E12 in the present embodiment
Atom per square centimeter is to 1E13 atom per square centimeter.
It should also be noted that, the implantation dosage of the second source and drain injection technology 410 be not limited only to for 5E12 atom it is every
Square centimeter is to 1E13 atom per square centimeter, in actual process, can according to actual process situation and device performance requirements into
Row adjustment.
In addition, in the present embodiment, since the spacing of the adjacent gate structure is smaller, the adjacent gate structure
Between the second source and drain doping area 415 Content Addressable Memory belonging to two gate structures share.
In the present embodiment, the material of the second graph layer 400 is photoresist, in the second source and drain injection technology 410
Afterwards, the second graph layer 400 is removed using ashing or wet processing.
In other embodiments, in order to further increase the performance of formed Content Addressable Memory, described in formation
Epitaxy technology is introduced in the technical process in the second source and drain doping area, to improve the carrier of the Content Addressable Memory
Mobility.
Specifically, the step of forming the second source and drain doping area includes: in Content Addressable Memory area grid
The second groove is formed in the substrate of structure two sides；It forms the second semiconductor layer in second groove, and is forming described the
Auto-dope ion in situ during two semiconductor layers, the doping concentration of second semiconductor layer are less than described the first half and lead
The doping concentration of body layer；Alternatively, mixing after forming the second semiconductor layer in second groove second semiconductor layer
Heteroion, the doping concentration of second semiconductor layer are less than the doping concentration of first semiconductor layer.
Correspondingly, the material of second semiconductor layer is Si or SiC, the Doped ions in second semiconductor layer
For N-type ion, the N-type ion includes for one of P ion, As ion and Sb ion or a variety of.
It should be noted that, to be initially formed first source and drain doping area 315, forming described second afterwards in the present embodiment
It is illustrated for source and drain doping area 415.In other embodiments, it can also be formed after forming the second source and drain doping area
First source and drain doping area.
In conjunction with reference Fig. 8, shows in the aforementioned embodiment, under the conditions of different source and drain implantation dosages, be formed by
Content Addressable Memory is after baking is handled, content addressable storage unit corresponding to the Content Addressable Memory
Threshold voltage and the content addressable storage unit sample size graph of relation.
Wherein, abscissa indicates that threshold voltage, ordinate indicate sample size, Content Addressable Memory shown in curve H
Used source and drain implantation dosage is the first dosage, source and drain implantation dosage used by Content Addressable Memory shown in curve G
For the second dosage, source and drain implantation dosage used by Content Addressable Memory shown in curve F be third dosage, described second
Dosage is less than first dosage and second dosage is greater than the third dosage, such as first dosage, the second dosage
It is respectively 8E12 atom per square centimeter, 6E12 atom per square centimeter and 4E12 atom per square centimeter with third dosage.
As seen from the figure, it after undergoing identical programming process, is handled by bakings in two hours, content shown in curve G can
The threshold voltage for addressing memory is greater than the threshold voltage of Content Addressable Memory shown in curve H, and content shown in curve F can
The threshold voltage for addressing memory is greater than the threshold voltage of Content Addressable Memory shown in curve G.
Therefore, by reducing the doping concentration of second source and drain doping area 415 (as shown in Figure 7), be conducive in increase
Hold addressable memory and baking treated threshold voltage, improves relations curve graph left-half (i.e. Left-tail) (such as
In Fig. 8 shown in virtual coil) threshold voltage shift problem, be conducive to improve Content Addressable Memory current leakage, from
And the data retention of Content Addressable Memory is improved, and then improve the performance of Content Addressable Memory.
Correspondingly, being previously formed method the present invention also provides a kind of use is formed by semiconductor structure.
With continued reference to Fig. 7, the structural schematic diagram of one embodiment of semiconductor structure of the present invention is shown.The semiconductor junction
Structure includes:
Substrate 100, the substrate 100 include cell memory area I and Content Addressable Memory area II；Gate structure
(not indicating), be located at the substrate 100 on, the gate structure include tunnel oxide 210 and be located at the tunnel oxide
Floating 220 on layer 210；First source and drain doping area 315, the base positioned at the cell memory area I gate structure two sides
In bottom 100；Second source and drain doping area 415, the substrate 100 positioned at the Content Addressable Memory area II gate structure two sides
Interior, the doping concentration in second source and drain doping area 415 is less than the doping concentration in first source and drain doping area 315.
In the present embodiment, the semiconductor structure is planar structure, correspondingly, the substrate 100 is planar substrate.?
In other embodiments, the semiconductor structure can also have fin structure, i.e. device is fin formula field effect transistor, described
Substrate accordingly includes substrate and discrete fin on the substrate.
Specifically, the device in the substrate 100 is and non-flash (NAND Flash) device.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
The other materials such as germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also on insulator silicon substrate or
The other kinds of substrate such as the germanium substrate on person's insulator.The material of the substrate, which can be, to be suitable for process requirement or is easy to
Integrated material.
In the present embodiment, the device of the cell memory area I is cell memory, the Content Addressable Memory
The device of area II is Content Addressable Memory.
In the present embodiment, the cell memory area I and Content Addressable Memory area II are set as non-conterminous.At it
In his embodiment, the cell memory area and Content Addressable Memory area can also be disposed adjacent.
In the present embodiment, the gate structure further include: the gate dielectric layer 230 on the floating 220, with
And the control grid layer 240 on the gate dielectric layer 230.
Specifically, the material of the floating 220 and the control grid layer 240 is polysilicon；The tunnel oxide
210 material is silica；The gate dielectric layer 230 includes the first silicon oxide layer, the nitrogen on first silicon oxide layer
SiClx layer and the second silicon oxide layer on the silicon nitride layer, i.e., the described gate dielectric layer 230 are ONO structure.
The gate structure is same as the prior art, and details are not described herein for the present embodiment.
First source and drain doping area 315 is used for source region or drain region as the cell memory.
It should be noted that in the present embodiment, it is adjacent described since the spacing of the adjacent gate structure is smaller
The first source and drain doping area 315 cell memory belonging to two gate structures between gate structure is shared.
In the present embodiment, the type of device of the cell memory is N-type device, therefore first source and drain doping area
315 Doped ions are N-type ion, and the N-type ion includes one of P ion, As ion and Sb ion or a variety of.Its
In, the doping concentration in first source and drain doping area 315 is depending on actual process demand and device performance requirements.
In other embodiments, in order to further increase the performance of formed cell memory, first source is being formed
It leaks and introduces extension (EPI) technology in the technical process of doped region, to improve the carrier mobility of the cell memory.
Correspondingly, the material in first source and drain doping area is the first semiconductor material with Doped ions.Specifically
Ground, first semiconductor material are Si or SiC, and the Doped ions in first semiconductor material include for P ion, As
One of ion and Sb ion are a variety of.
Second source and drain doping area 415 is used for source region or drain region as the Content Addressable Memory.
It should be noted that in the present embodiment, it is adjacent described since the spacing of the adjacent gate structure is smaller
The second source and drain doping area 415 Content Addressable Memory belonging to two gate structures between gate structure is shared.
In the present embodiment, the doping concentration in second source and drain doping area 415 is less than first source and drain doping area 315
Doping concentration.
Compared with the identical scheme of doping concentration in the first source and drain doping area and the second source and drain doping area, by reducing institute
The doping concentration for stating the second source and drain doping area 415 is accordingly made with improving the initial threshold voltage of Content Addressable Memory
The floating 220 of the Content Addressable Memory possessed electronics in eigenstate increases, therefore in programming, institute
The electronics captured needed for floating 220 is stated to reduce.
And since the floating 220 captures electronics from the substrate 100, and the tunnel oxide 210 is located at
Between the floating 220 and the substrate 100, therefore subtracted by the electronics of capture needed for making the floating 220
It is few, it can accordingly reduce the trapped charge in tunnel oxide 210 caused by programming, it can improve trap and assist tunnelling
(Trap-assisted Tunneling, TAT) effect improves the content addressable so as to improve element leakage flow problem
The threshold voltage characteristic of memory avoids the problem that threshold voltage shift occurs, and then improves the number of Content Addressable Memory
According to hold capacity, so that the performance of Content Addressable Memory gets a promotion；Moreover, after programming, the floating 220
The electron number of middle storage is reduced, and can also accordingly be improved 220 electronics of the floating loss as caused by other effects and be asked
Topic, is conducive to the data retention for further increasing Content Addressable Memory.
In addition, if the initial threshold voltage of cell memory increases, although the data that cell memory can be improved are protected
Ability is deposited, but the repetitive read-write (i.e. Cycling) that accordingly will lead to cell memory is less able；Therefore described in the reduction
In the case where the doping concentration in the second source and drain doping area 415, make the doping concentration in first source and drain doping area 315 not by shadow
It rings, to keep the performance in the cell memory area unaffected.
In the present embodiment, the type of device of the Content Addressable Memory is N-type device, therefore second source and drain
The Doped ions of doped region 415 are N-type ion, the N-type ion include for one of P ion, As ion and Sb ion or
It is a variety of.Wherein, the doping concentration in second source and drain doping area 415 is depending on actual process demand and device performance requirements.
In other embodiments, in order to further increase the performance of the Content Addressable Memory, described the is being formed
Epitaxy technology is introduced in the technical process in two source and drain doping areas, improves the carrier mobility of the Content Addressable Memory.
Correspondingly, second source and drain doping area is the second semiconductor material with Doped ions.Specifically, described
Second semiconductor material is Si or SiC, and the Doped ions in second semiconductor material include for P ion, As ion and Sb
One of ion is a variety of.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from
It in the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim
Subject to limited range.
Claims (17)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes cell memory area and Content Addressable Memory area；
Form gate structure on the substrate, the gate structure includes tunnel oxide and is located at the tunnel oxide
On floating；
The first source and drain doping area is formed in the substrate of the cell memory area gate structure two sides；
The second source and drain doping area, second source are formed in the substrate of the Content Addressable Memory area gate structure two sides
The doping concentration for leaking doped region is less than the doping concentration in first source and drain doping area.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that use the first source and drain injection technology shape
At first source and drain doping area, second source and drain doping area, second source and drain are formed using the second source and drain injection technology
The implantation dosage of injection technology is less than the implantation dosage of the first source and drain injection technology.
3. the forming method of semiconductor structure as claimed in claim 1 or 2, which is characterized in that form first source and drain and mix
The step of miscellaneous area includes: that the first graph layer is formed in the substrate in the Content Addressable Memory area, first graph layer
Also cover the gate structure in the Content Addressable Memory area；
Using first graph layer as exposure mask, the first source and drain note is carried out to the substrate of the cell memory area gate structure two sides
Enter technique；
After the first source and drain injection technology, first graph layer is removed.
4. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the first source and drain injection technology
Parameter include: injection ion include for one of P ion, As ion and Sb ion or a variety of, Implantation Energy be 10Kev extremely
20Kev, implantation dosage are 7E12 atom per square centimeter to 1.2E13 atom per square centimeter.
5. the forming method of semiconductor structure as claimed in claim 1 or 2, which is characterized in that form second source and drain and mix
The step of miscellaneous area includes: that second graph floor is formed in the substrate in the cell memory area, and the second graph layer also covers
The gate structure in the cell memory area；
Using the second graph layer as exposure mask, second is carried out to the substrate of the Content Addressable Memory area gate structure two sides
Source and drain injection technology；
After the second source and drain injection technology, the second graph layer is removed.
6. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the second source and drain injection technology
Parameter include: Doped ions include for one of P ion, As ion and Sb ion or a variety of, Implantation Energy be 10Kev extremely
20Kev, implantation dosage are 5E12 atom per square centimeter to 1E13 atom per square centimeter.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that form first source and drain doping area
The step of include: to form the first groove in the substrate of the cell memory area gate structure two sides；In first groove
The first semiconductor layer of middle formation, and the auto-dope ion in situ during forming first semiconductor layer；
Alternatively,
The step of forming the first source and drain doping area includes: the shape in the substrate of the cell memory area gate structure two sides
At the first groove；The first semiconductor layer is formed in first groove；To the first semiconductor layer doped ion.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that form second source and drain doping area
The step of include: to form the second groove in the substrate of the Content Addressable Memory area gate structure two sides；Described
The second semiconductor layer is formed in two grooves, and the auto-dope ion in situ during forming second semiconductor layer, it is described
The doping concentration of second semiconductor layer is less than the doping concentration of first semiconductor layer；
Alternatively,
The step of forming the second source and drain doping area includes: the base in the Content Addressable Memory area gate structure two sides
The second groove is formed in bottom；The second semiconductor layer is formed in second groove；To the second semiconductor layer doped ion,
The doping concentration of second semiconductor layer is less than the doping concentration of first semiconductor layer.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the material of first semiconductor layer
For Si or SiC, the Doped ions in first semiconductor layer are N-type ion, the N-type ion include be P ion, As ion
With one of Sb ion or a variety of；
The material of second semiconductor layer is Si or SiC, and the Doped ions in second semiconductor layer are N-type ion, institute
Stating N-type ion to include is one of P ion, As ion and Sb ion or a variety of.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that mixed forming first source and drain
After miscellaneous area, second source and drain doping area is formed；
Alternatively, forming first source and drain doping area after forming second source and drain doping area.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that form grid on the substrate
In the step of structure, the gate structure further include: the gate dielectric layer on the floating, and be located at the grid and be situated between
Control grid layer on matter layer.
12. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include cell memory area and Content Addressable Memory area；
Gate structure, be located at the substrate on, the gate structure include tunnel oxide and be located at the tunnel oxide
On floating；
First source and drain doping area, in the substrate of the cell memory area gate structure two sides；
Second source and drain doping area, in the substrate of the Content Addressable Memory area gate structure two sides, second source
The doping concentration for leaking doped region is less than the doping concentration in first source and drain doping area.
13. semiconductor structure as claimed in claim 12, which is characterized in that the Doped ions packet in first source and drain doping area
It includes as one of P ion, As ion and Sb ion or a variety of.
14. semiconductor structure as claimed in claim 12, which is characterized in that the Doped ions packet in second source and drain doping area
It includes as one of P ion, As ion and Sb ion or a variety of.
15. semiconductor structure as claimed in claim 12, which is characterized in that the gate structure further include: be located at described floating
Set the gate dielectric layer in grid layer, and the control grid layer on the gate dielectric layer.
16. semiconductor structure as claimed in claim 12, which is characterized in that the material in first source and drain doping area be with
First semiconductor material of Doped ions, second source and drain doping area are the second semiconductor material with Doped ions.
17. semiconductor structure as claimed in claim 16, which is characterized in that first semiconductor material is Si or SiC, institute
Stating the Doped ions in the first semiconductor material to include is one of P ion, As ion and Sb ion or a variety of；
Second semiconductor material is Si or SiC, and the Doped ions in second semiconductor material include for P ion, As
One of ion and Sb ion are a variety of.
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