CN106257647A - Embed the manufacture method of the CMOS of PIP capacitor - Google Patents
Embed the manufacture method of the CMOS of PIP capacitor Download PDFInfo
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- CN106257647A CN106257647A CN201510340654.3A CN201510340654A CN106257647A CN 106257647 A CN106257647 A CN 106257647A CN 201510340654 A CN201510340654 A CN 201510340654A CN 106257647 A CN106257647 A CN 106257647A
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- layer
- pip capacitor
- dielectric layer
- polysilicon
- side wall
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The present invention relates to the manufacture method of a kind of CMOS embedding PIP capacitor, including: side wall oxide layer will be deposited, side wall oxide layer is performed etching, before the process of the bottom crown both sides of PIP capacitor and grid both sides formation side wall is placed on dielectric layer and the second polysilicon layer, thus at dielectric layer and the second polysilicon layer, during dielectric layer and the second polysilicon layer are performed etching the top crown of dielectric layer and the PIP capacitor forming PIP capacitor, existence due to side wall, the side-walls avoiding the bottom crown in PIP capacitor forms dielectric layer and the residual of the second polysilicon layer, thus improve the function preventing noise emission of cmos semiconductor and prevent warbled function.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the system of a kind of CMOS embedding PIP capacitor
Make method.
Background technology
At present, hybrid-type complementary metal oxide semiconductor field effect transistor (Complementary
Metal Oxide Semiconductor, CMOS) including: N-type metal oxide semiconductcor field effect
Answer transistor (N-Mental-Oxide-Semiconductor, NMOS), P-channel metal-oxide
Semiconductor field effect transistor (Positive channel Metal Oxide Semiconductor,
PMOS).Wherein, NMOS tube is provided with polysilicondielectric layer-polysilicon capacitance
(Polysilicon-Insulator-Polysilicon, PIP), NMOS tube and PMOS pass through metal
Wires etc. connect, and form hybrid CMOS tube.
In prior art, the manufacture method of the CMOS embedding PIP capacitor includes: sequentially generate lining
The end, well region, field oxide, grid oxide layer, the bottom crown of PIP capacitor, the dielectric layer of PIP capacitor,
The top crown of PIP capacitor, N-type lightly doped drain (N type Lightly Doped Drain, NLDD),
Side wall, source-drain area, aperture layer, metal wiring layer.
But in prior art, as it is shown in figure 1, generate more than first of the bottom crown as PIP capacitor
After crystal silicon layer 5, in the surface dielectric layer 12 of whole device, deposition more than second on the dielectric layer
Crystal silicon layer, performs etching dielectric layer and the second polysilicon layer, forms the dielectric layer of PIP capacitor and upper
Pole plate 13.Owing to the bottom crown of PIP capacitor is stepped ramp type, cause dielectric layer and the second polysilicon layer
After performing etching, the side-walls at the bottom crown of PIP capacitor is coated with part of dielectric layer and part second
Polysilicon layer, as it is shown in figure 1, form dielectric layer residual 14 and residual polycrystalline silicon 15, affects CMOS
The function preventing noise emission of field-effect transistor and prevent warbled function.
Summary of the invention
The present invention provides the manufacture method of a kind of CMOS embedding PIP capacitor, is used for solving existing embedding
The function preventing noise emission of the CMOS of PIP capacitor and prevent poor the asking of warbled function
Topic.
The first aspect of the invention is to provide the making of N-type metal-oxide semiconductor (MOS) in a kind of CMOS
Method, including:
The substrate be formed with well region defines active area, in addition to the region that described active area is corresponding
Substrate surface growth field oxide, and grow grid oxide layer at the substrate surface that described active area is corresponding；
Deposit the first polysilicon layer at whole device surface, the first polysilicon layer is performed etching, reserved bit
In the field oxide the first polysilicon layer on peripheral surface, subregion and be positioned at described grid oxygen
The first polysilicon layer in layer segment region surface, to form bottom crown and the grid of PIP capacitor respectively；
By injecting ion, form the lightly doped drain of the substrate surface being positioned at described grid both sides；
Deposit side wall oxide layer at whole device surface, described side wall oxide layer is performed etching, described
Ground floor polysilicon both sides and described grid both sides form side wall；
By injecting ion, form source region and drain region；
The surface, subregion of the bottom crown of described PIP capacitor is sequentially depositing dielectric layer and the second polycrystalline
Silicon layer, to form dielectric layer and the top crown of described PIP capacitor respectively；
Carry out aperture layer making and metal line.
Further, the surface, subregion of the bottom crown of described PIP capacitor is sequentially depositing dielectric layer
With the second polysilicon layer, including:
Whole device surface is sequentially depositing dielectric layer and the second polysilicon layer；
Described dielectric layer and the second polysilicon layer are performed etching, retains the lower pole being positioned at described PIP capacitor
Dielectric layer on the surface, subregion of plate and the second polysilicon layer.
Further, described by injecting ion, formation is positioned at the substrate surface of described grid both sides
Lightly doped drain, including:
Photoresist layer it is coated with on the surface of whole device；
Described photoresist layer is carried out photoetching development, forms ion implanting window in described grid both sides；
Injecting ion to described ion implanting window, formation is positioned at the substrate surface of described grid both sides
Described lightly doped drain；
Remove remaining photoresist layer.
Further, described dielectric layer and the second polysilicon layer are performed etching, retain and be positioned at described PIP
Dielectric layer on the surface, subregion of the bottom crown of electric capacity and the second polysilicon layer, including:
It is coated with photoresist layer at whole device surface；
Described photoresist layer is carried out photoetching development, retains the part district of the bottom crown being positioned at described PIP capacitor
Photoresist layer on field surface；
Under the stop of photoresist layer, described dielectric layer and the second polysilicon layer are performed etching, be positioned to retain
Dielectric layer on the surface, subregion of the bottom crown of described PIP capacitor and the second polysilicon layer；
Remove remaining photoresist layer.
Further, the thickness of described side wall oxide layer is 1500-4000 angstrom
Further, described dielectric layer is silicon dioxide layer, silicon nitride layer or silicon dioxide and nitridation
The mixed layer of silicon.
Further, the thickness of described dielectric layer is 200-700 angstrom.
Further, the thickness of the second layer polysilicon of described PIP capacitor is 2000-5000 angstrom.
Further, described described side wall oxide layer is performed etching, including:
Described side wall oxide layer is carried out dry etching.
In the present invention, side wall oxide layer will be deposited, side wall oxide layer will be performed etching, in PIP capacitor
Bottom crown both sides and grid both sides formed the process of side wall be placed on dielectric layer and the second polysilicon layer it
Before, thus at dielectric layer and the second polysilicon layer, dielectric layer and the second polysilicon layer are performed etching
During forming the dielectric layer of PIP capacitor and the top crown of PIP capacitor, due to the existence of side wall, keep away
Exempt from the side-walls at the bottom crown of PIP capacitor and form dielectric layer and the residual of the second polysilicon layer, thus carry
The function preventing noise emission of high cmos semiconductor and prevent warbled function.
Accompanying drawing explanation
Fig. 1 is cmos fet transistor upper dielectric layer and the signal of residual polycrystalline silicon in prior art
Figure；
The flow chart of the manufacture method of the CMOS of the embedding PIP capacitor that Fig. 2 provides for the present invention；
Fig. 3 is definition active area on the substrate be formed with well region, in addition to the region that active area is corresponding
Substrate surface growth field oxide, and active area corresponding substrate surface growth grid oxide layer after embed
The schematic diagram of the CMOS of PIP capacitor；
Fig. 4 be form the bottom crown of PIP capacitor and grid after embed the signal of CMOS of PIP capacitor
Figure；
Fig. 5 is the schematic diagram forming the CMOS embedding PIP capacitor after N-type lightly doped drain NLDD；
Fig. 6 is the schematic diagram of CMOS embedding PIP capacitor after deposition side wall oxide layer；
Fig. 7 is for perform etching side wall oxide layer, in ground floor polysilicon both sides and formation side, grid both sides
The schematic diagram of the CMOS of PIP capacitor is embedded after wall；
Fig. 8 be form source region and drain region after embed the schematic diagram of CMOS of PIP capacitor；
Fig. 9 is the schematic diagram of the CMOS embedding PIP capacitor after dielectric layer；
Figure 10 is the schematic diagram that deposition the second polysilicon layer embeds the CMOS of PIP capacitor；
Figure 11, for perform etching dielectric layer and polysilicon layer, forms dielectric layer and the PIP electricity of PIP capacitor
The schematic diagram of the CMOS of PIP capacitor is embedded after the top crown held.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
The flow chart of the manufacture method of the CMOS of the embedding PIP capacitor that Fig. 2 provides for the present invention, such as figure
Shown in 2, specifically include following steps:
201, on the substrate be formed with well region, active area is defined, in addition to the region that active area is corresponding
Substrate surface growth field oxide, and grow grid oxide layer at the substrate surface that active area is corresponding.
Wherein, as it is shown on figure 3, for defining active area on the substrate 1 be formed with well region 2, except having
Substrate surface growth field oxide 3 beyond the region that source region is corresponding, and at substrate table corresponding to active area
Long grid oxide layer 4 of looking unfamiliar embeds the schematic diagram of the CMOS of PIP capacitor afterwards.
202, deposit the first polysilicon layer at whole device surface, the first polysilicon layer is performed etching, protect
Stay and be positioned at the field oxide the first polysilicon layer on peripheral surface, subregion and be positioned at grid oxygen
The first polysilicon layer in layer segment region surface, to form bottom crown 5 and the grid 6 of PIP capacitor respectively.
Wherein, the mode performed etching the first polysilicon layer is chemical wet etching.As shown in Figure 4, for shape
The schematic diagram of the CMOS of PIP capacitor is embedded after the bottom crown of one-tenth PIP capacitor and grid.
203, by injecting ion, the lightly doped drain 7 of the substrate surface being positioned at grid 6 both sides is formed.
Wherein, step 203 specifically may include that and is coated with photoresist layer on the surface of whole device；To photoresistance
Layer carries out photoetching development, forms ion implanting window in grid both sides；Ion is injected to ion implanting window,
Form the lightly doped drain of the substrate surface being positioned at grid both sides；Remove remaining photoresist layer.
Form the purpose of N-type lightly doped drain NLDD to prevent between source region or drain region and grid
Hot carrier (Hot Carrier Injection) phenomenon.As it is shown in figure 5, for forming N-type lightly doped drain
The schematic diagram of the CMOS of PIP capacitor is embedded after NLDD.
204, deposit side wall oxide layer 8 at whole device surface, side wall oxide layer is performed etching, the
One layer of polysilicon both sides and grid both sides form side wall 9.
Wherein, the thickness of side wall oxide layer is 1500-4000 angstrom.As shown in Figure 6, for deposition side wall oxygen
The schematic diagram of the CMOS of PIP capacitor is embedded after changing layer.As it is shown in fig. 7, for side wall oxide layer is carried out
Etching, embeds the CMOS's of PIP capacitor after ground floor polysilicon both sides and grid both sides form side wall
Schematic diagram.
Wherein, the mode of growth side wall oxide layer can be chemical vapour deposition technique, enters side wall oxide layer
The method of row etching can be dry etching.
205, by injecting ion, source region 10 and drain region 11 are formed.
Wherein, after ground floor polysilicon both sides and grid both sides form side wall, grid are passed through in grid both sides
Oxygen layer injects ion to well region, can retain the N-type lightly doped drain NLDD in well region under side wall.As
Shown in Fig. 8, for embedding the schematic diagram of the CMOS of PIP capacitor after forming source region and drain region.
206, on the surface, subregion of the bottom crown of PIP capacitor, dielectric layer and the second polycrystalline it are sequentially depositing
Silicon layer, to form dielectric layer 12 and the top crown 13 of PIP capacitor respectively.
Wherein, dielectric layer is the mixing of silicon dioxide layer, silicon nitride layer or silicon dioxide and silicon nitride
Layer.The thickness of dielectric layer is 200-700 angstrom.The thickness of the second polysilicon layer of PIP capacitor is 2000-5000
Angstrom.
Step 206 specifically may include that and is sequentially depositing dielectric layer and the second polycrystalline on whole device surface
Silicon layer；Dielectric layer and the second polysilicon layer are performed etching, retains the portion of the bottom crown being positioned at PIP capacitor
Dielectric layer on surface, subregion and the second polysilicon layer.
As it is shown in figure 9, the schematic diagram of the CMOS for embedding PIP capacitor after dielectric layer.Such as Figure 10
Shown in, for depositing the schematic diagram that the second polysilicon layer embeds the CMOS of PIP capacitor.As shown in figure 11,
For dielectric layer and polysilicon layer are performed etching, form dielectric layer and the upper pole of PIP capacitor of PIP capacitor
The schematic diagram of the CMOS of PIP capacitor is embedded after plate.
Wherein, the process performing etching dielectric layer and polysilicon layer is specifically as follows, at whole device table
Topcoating cloth photoresist layer；Photoresist layer is carried out photoetching development, retains the part of the bottom crown being positioned at PIP capacitor
Photoresist layer in region surface；Under the stop of photoresist layer, dielectric layer and the second polysilicon layer are performed etching,
To retain the dielectric layer on the surface, subregion of the bottom crown being positioned at PIP capacitor and the second polysilicon layer；
Remove remaining photoresist layer.
Wherein, the growth of silicon dioxide layer can use thermal oxidation technology.Process is that silicon chip is put into high temperature furnace
Guan Zhong, temperature 800～1100 degree, it is passed through oxygen, allows oxygen at high temperature react with polysilicon generation
Silicon dioxide.Chemical vapor deposition method can also be used, deposit layer of silicon dioxide layer at silicon chip surface.
The making of silicon nitride can use chemical vapor deposition method.The growth technique of polysilicon layer can be chemistry
Gas-phase deposition.
207, aperture layer making and metal line are carried out.
In the present embodiment, side wall oxide layer will be deposited, side wall oxide layer will be performed etching, in PIP capacitor
Bottom crown both sides and grid both sides formed side wall process be placed on dielectric layer and the second polysilicon layer
Before, thus at dielectric layer and the second polysilicon layer, dielectric layer and the second polysilicon layer are carved
During erosion forms the dielectric layer of PIP capacitor and the top crown of PIP capacitor, due to the existence of side wall,
Avoid forming dielectric layer and the residual of the second polysilicon layer in the side-walls of the bottom crown of PIP capacitor, thus
Improve the function preventing noise emission of cmos semiconductor and prevent warbled function.
One of ordinary skill in the art will appreciate that: realize all or part of step of above-mentioned each method embodiment
Suddenly can be completed by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer can
Read in storage medium.This program upon execution, performs to include the step of above-mentioned each method embodiment；And
Aforesaid storage medium includes: ROM, RAM, magnetic disc or CD etc. are various can store program code
Medium.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. the manufacture method of the CMOS embedding PIP capacitor, it is characterised in that including:
The substrate be formed with well region defines active area, in addition to the region that described active area is corresponding
Substrate surface growth field oxide, and grow grid oxide layer at the substrate surface that described active area is corresponding；
Deposit the first polysilicon layer at whole device surface, the first polysilicon layer is performed etching, reserved bit
In the field oxide the first polysilicon layer on peripheral surface, subregion and be positioned at described grid oxygen
The first polysilicon layer in layer segment region surface, to form bottom crown and the grid of PIP capacitor respectively；
By injecting ion, form the lightly doped drain of the substrate surface being positioned at described grid both sides；
Deposit side wall oxide layer at whole device surface, described side wall oxide layer is performed etching, described
Ground floor polysilicon both sides and described grid both sides form side wall；
By injecting ion, form source region and drain region；
The surface, subregion of the bottom crown of described PIP capacitor is sequentially depositing dielectric layer and the second polycrystalline
Silicon layer, to form dielectric layer and the top crown of described PIP capacitor respectively；
Carry out aperture layer making and metal line.
Method the most according to claim 1, it is characterised in that at the bottom crown of described PIP capacitor
Surface, subregion on be sequentially depositing dielectric layer and the second polysilicon layer, including:
Whole device surface is sequentially depositing dielectric layer and the second polysilicon layer；
Described dielectric layer and the second polysilicon layer are performed etching, retains the lower pole being positioned at described PIP capacitor
Dielectric layer on the surface, subregion of plate and the second polysilicon layer.
Method the most according to claim 1, it is characterised in that described by injecting ion, is formed
It is positioned at the lightly doped drain of the substrate surface of described grid both sides, including:
Photoresist layer it is coated with on the surface of whole device；
Described photoresist layer is carried out photoetching development, forms ion implanting window in described grid both sides；
Injecting ion to described ion implanting window, formation is positioned at the substrate surface of described grid both sides
Described lightly doped drain；
Remove remaining photoresist layer.
Method the most according to claim 2, it is characterised in that to described dielectric layer and the second polycrystalline
Silicon layer performs etching, and retains the dielectric layer on the surface, subregion of the bottom crown being positioned at described PIP capacitor
With second layer polysilicon, including:
It is coated with photoresist layer at whole device surface；
Described photoresist layer is carried out photoetching development, retains the part district of the bottom crown being positioned at described PIP capacitor
Photoresist layer on field surface；
Under the stop of photoresist layer, described dielectric layer and the second polysilicon layer are performed etching, be positioned to retain
Dielectric layer on the surface, subregion of the bottom crown of described PIP capacitor and the second polysilicon layer；
Remove remaining photoresist layer.
Method the most according to claim 1, it is characterised in that
The thickness of described side wall oxide layer is 1500-4000 angstrom.
Method the most according to claim 1 and 2, it is characterised in that
Described dielectric layer is the mixed layer of silicon dioxide layer, silicon nitride layer or silicon dioxide and silicon nitride.
Method the most according to claim 1 and 2, it is characterised in that
The thickness of described dielectric layer is 200-700 angstrom.
Method the most according to claim 1, it is characterised in that
The thickness of described second layer polysilicon is 2000-5000 angstrom.
Method the most according to claim 1, it is characterised in that described described side wall oxide layer is entered
Row etching, including:
Described side wall oxide layer is carried out dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510340654.3A CN106257647A (en) | 2015-06-18 | 2015-06-18 | Embed the manufacture method of the CMOS of PIP capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510340654.3A CN106257647A (en) | 2015-06-18 | 2015-06-18 | Embed the manufacture method of the CMOS of PIP capacitor |
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| CN106257647A true CN106257647A (en) | 2016-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510340654.3A Pending CN106257647A (en) | 2015-06-18 | 2015-06-18 | Embed the manufacture method of the CMOS of PIP capacitor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346570A (en) * | 2018-01-24 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of production method of semiconductor devices |
| CN111613725A (en) * | 2020-06-15 | 2020-09-01 | 华虹半导体(无锡)有限公司 | Method for manufacturing capacitor |
| CN114361137A (en) * | 2021-12-29 | 2022-04-15 | 广东省大湾区集成电路与系统应用研究院 | Manufacturing method of PIP capacitor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5924011A (en) * | 1997-12-15 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide process for mixed mode product |
| CN1610096A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for forming polycrystalline silicon capacitor utilizing self-aligning metal silicide producing process |
| US20070235788A1 (en) * | 2006-04-04 | 2007-10-11 | Ching-Hung Kao | Poly-Insulator-Poly Capacitor and Fabrication Method for Making the Same |
-
2015
- 2015-06-18 CN CN201510340654.3A patent/CN106257647A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5924011A (en) * | 1997-12-15 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide process for mixed mode product |
| CN1610096A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for forming polycrystalline silicon capacitor utilizing self-aligning metal silicide producing process |
| US20070235788A1 (en) * | 2006-04-04 | 2007-10-11 | Ching-Hung Kao | Poly-Insulator-Poly Capacitor and Fabrication Method for Making the Same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346570A (en) * | 2018-01-24 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of production method of semiconductor devices |
| CN108346570B (en) * | 2018-01-24 | 2020-09-04 | 中芯集成电路（宁波）有限公司 | Manufacturing method of semiconductor device |
| CN111613725A (en) * | 2020-06-15 | 2020-09-01 | 华虹半导体(无锡)有限公司 | Method for manufacturing capacitor |
| CN114361137A (en) * | 2021-12-29 | 2022-04-15 | 广东省大湾区集成电路与系统应用研究院 | Manufacturing method of PIP capacitor |
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